Solid-state imaging device and signal processing method

Abstract

This solid-state imaging device is provided with: a first light-receiving unit and a second light-receiving unit that generate electric charges in response to the incidence of light; an output unit for outputting a first signal corresponding to the charge generated by the first light receiving unit and outputting a second signal corresponding to the charge generated by the second light receiving unit; and a signal processing unit for processing the signal output from the output unit, the signal processing of the signal processing unit including: an additive signal generation process for generating an additive signal by adding the first signal and the second signal; a subtraction signal generation process for subtracting the second signal from the first signal to generate a subtraction signal; and a correction process for correcting and outputting the addition signal on the basis of the subtraction signal.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device and a signal processing method. Background Art

[0002] Patent document 1 describes an imaging device. The imaging device includes: a horizontal transfer unit that transfers charges generated by two-dimensionally arranged photoelectric conversion elements in the horizontal direction for each line and converts them into imaging signals; a transfer control gate unit that controls the supply of charges to the horizontal transfer unit; a drive unit that drives the horizontal transfer unit and the transfer control gate unit; and a signal correction unit that generates a correction signal using the imaging signal output from the horizontal transfer unit and corrects the imaging signal subsequently output from the horizontal transfer unit based on the correction signal. In addition, the drive unit performs a process of stopping the supply of charges to the horizontal transfer unit through the transfer control gate unit, and the signal correction unit generates a correction signal using the imaging signal output from the horizontal transfer unit when the supply of charges to the horizontal transfer unit is stopped. Prior art literature Patent Literature

[0003] Patent Document 1: Japanese Patent Application Publication No. 2008-005328 Summary of the invention The problem the invention is intended to solve

[0004] However, in the above-mentioned imaging device, sometimes white spots (hereinafter referred to as "WS") with a large amount of signal are generated even in a state without incident light after leaving the factory. One of the reasons for the generation of WS is believed to be that α rays from the materials of the imaging device such as packaging or neutron rays caused by cosmic rays form defects or damage the crystal structure of the semiconductor (such as silicon) of the light receiving part of the imaging device. Since α rays are emitted from materials close to the light receiving part, it is difficult to set a shield on the light receiving part, so shielding is difficult. In addition, since neutrons are not charged particles, it is also difficult to shield neutron rays flying from the outside. Therefore, it is difficult to avoid the generation of WS itself.

[0005] Therefore, when WS is generated after shipment, it is considered to correct the output signal by removing the noise caused by WS while continuing to use the camera. However, this correction is difficult in the existing camera because of concerns about the increase in WS's timeliness and the fact that the output signal changes like RTS (Random Telegraph Signal). Therefore, it is desired to correct the output signal and extend the life of the camera.

[0006] An object of the present disclosure is to provide a solid-state imaging device and a signal processing method that can achieve a longer life. Technical means of solving problems

[0007] The solid-state imaging device disclosed in the present invention is [1] "a solid-state imaging device comprising: a first light receiving unit and a second light receiving unit, which generate electric charges according to incident light; an output unit, which is used to output a first signal corresponding to the electric charges generated in the first light receiving unit, and output a second signal corresponding to the electric charges generated in the second light receiving unit; and a signal processing unit, which is used to process the signal output from the output unit, wherein the first light receiving unit has: a first pixel region, which is composed of a plurality of first pixels arranged along a first direction, or a pixel region of one first pixel, i.e., a plurality of first pixel regions arranged along a second direction intersecting the first direction; and the second light receiving unit has: a second pixel region, which is composed of a plurality of second pixels arranged along the first direction, or a pixel region of one second pixel, i.e., a plurality of The second pixel area is arranged along the second direction; the first pixel area and the second pixel area, when the first pixel area and the second pixel area are arranged along the first direction in a manner that the ends of the first pixel area and the second pixel area in the second direction are consistent, establish correspondence in a manner that each of the plurality of first pixel areas and each of the plurality of second pixel areas are arranged in parallel along the first direction; the signal processing of the signal processing unit includes: an addition signal generation process, which adds the first signal and the second signal to generate an addition signal; a subtraction signal generation process, which subtracts the second signal from the first signal to generate a subtraction signal; and a correction process, which corrects the addition signal based on the subtraction signal and outputs it.

[0008] In this solid-state imaging device, there are provided a first light receiving unit and a second light receiving unit that generate electric charge according to incident light. The first light receiving unit has a first pixel region composed of a first pixel region including one or more first pixels arranged along a second direction, and the second light receiving unit also has a second pixel region composed of a second pixel region including one or more second pixels arranged along a second direction. In the first light receiving unit and the second light receiving unit, electric charge corresponding to incident light is generated in each of the first pixel and the second pixel.

[0009] Furthermore, when the first pixel region and the second pixel region are arranged along the first direction in such a manner that the ends of the first pixel region and the second pixel region in the second direction coincide with each other (regardless of whether they are actually arranged in this manner), the first pixel region and the second pixel region are corresponding to each other in such a manner that each of the plurality of first pixel regions and each of the plurality of second pixel regions are arranged in parallel along the first direction. Therefore, in the solid-state imaging device, by causing the same or corresponding light to be incident on the first light receiving portion (first pixel region) and the second light receiving portion (second pixel region), a corresponding relationship is generated between the first signal corresponding to the charge from the first light receiving portion and the second signal corresponding to the charge from the second light receiving portion.

[0010] Therefore, by generating a subtraction signal of the first signal and the second signal by the signal processing unit, information related to the output value caused by WS that may be generated without a corresponding relationship between the first signal and the second signal (for example, the position of the pixel area that generates the output value caused by WS, or the signal itself containing the output value) can be obtained. Therefore, by correcting the addition signal of the first signal and the second signal (the output signal before correction) generated by the signal processing unit based on the subtraction signal, the output value caused by WS can be removed. Therefore, even if WS timeliness occurs, it is possible to continue to use while suppressing its influence. That is, the life of the solid-state imaging device is extended.

[0011] The solid-state imaging device disclosed in the present invention may also be, [2] "a solid-state imaging device as described in [1] above, wherein the signal processing unit generates a correction signal based on the subtraction signal in the correction processing, and corrects the addition signal by subtracting the correction signal from the addition signal, and in the correction signal, when the pixel area showing an output value lower than the negative threshold, i.e., the white point area, is confirmed to be the area, the sign of the output value of the white point area is changed to positive". In this case, by subtracting the correction signal from the addition signal, the output value caused by WS (the output value of the white point area) can be removed from the addition signal.

[0012] The solid-state imaging device disclosed in the present invention may also be, [3] "a solid-state imaging device as described in [2] above, wherein the signal processing unit generates the correction signal in all the first pixel areas and all the second pixel areas in the correction processing, and corrects the addition signal by subtracting the correction signal from the addition signal". In this case, the output value caused by WS can be removed from the addition signal without determining the position of the white spot area.

[0013] The solid-state imaging device disclosed in the present invention may also be, [4] "a solid-state imaging device as described in [1] above, wherein the signal processing unit generates a correction signal based on the subtraction signal in the correction processing, and corrects the addition signal by adding the correction signal to the addition signal, and in the correction signal, when the pixel area showing an output value exceeding the positive threshold, i.e., the white point area, is confirmed to be the pixel area, the sign of the output value of the white point area is changed to negative". In this case, by adding the correction signal to the addition signal, the output value caused by WS (the output value of the white point area) can be removed from the addition signal.

[0014] The solid-state imaging device disclosed in the present invention may also be, [5] "a solid-state imaging device as described in [4] above, wherein the signal processing unit generates the correction signal in all the first pixel regions and all the second pixel regions in the correction processing, and corrects the addition signal by adding the correction signal to the addition signal". In this case, the output value caused by WS can be removed from the addition signal without determining the position of the white spot area.

[0015] The solid-state imaging device disclosed in the present invention may also be, [6] "a solid-state imaging device as described in any one of the above [2] to [5], wherein the above-mentioned signal processing unit sets the output value of the above-mentioned pixel area that displays the output value between the positive threshold and the negative threshold in the above-mentioned correction signal to 0 in the above-mentioned correction processing". In this case, the overlapping of noise caused by the subtraction or addition operation of the correction signal is suppressed.

[0016] The solid-state imaging device disclosed in the present invention may also be, [7] "a solid-state imaging device as described in [1] above, wherein the signal processing unit, in the correction processing, replaces the output value of the white point area in the addition signal with the output value of the second pixel area at the position of the white point area of ​​the second signal set to twice the output value in the subtraction signal when the pixel area, i.e., the white point area, showing an output value below the negative threshold is detected in the subtraction signal, and replaces the output value of the white point area in the addition signal with the output value of the first pixel area at the position of the white point area of ​​the first signal set to twice the output value in the subtraction signal". In this case, when removing the output value caused by WS from the addition signal, there is no need to perform subtraction and addition operations on the correction signal.

[0017] The solid-state imaging device disclosed in the present invention may also be, [8] "a solid-state imaging device as described in any one of the above [1] to [7], wherein the above-mentioned signal processing unit performs the above-mentioned correction processing when at least one of the above-mentioned pixel area showing an output value exceeding the positive threshold, i.e., the white point area, and the above-mentioned pixel area showing an output value below the negative threshold, i.e., the white point area, is detected in the above-mentioned subtraction operation signal". In this case, when the white point area is not detected, the execution of the correction processing can be omitted.

[0018] The solid-state imaging device disclosed in the present invention may also be, [9] "a solid-state imaging device as described in any one of the above [1] to [8], comprising: a first transfer gate portion for transferring charges from each of the above-mentioned first pixel regions; a second transfer gate portion for transferring charges from each of the above-mentioned second pixel regions; a first horizontal transfer CCD portion for transferring charges transferred through the above-mentioned first transfer gate portion to the above-mentioned output portion; and a second horizontal transfer CCD portion for transferring charges transferred through the above-mentioned second transfer gate portion to the above-mentioned output portion". In this case, it is possible to achieve a longer life of the solid-state imaging device including a CCD (Charge Coupled Device).

[0019] The solid-state imaging device disclosed in the present invention may also be,

[10] "a solid-state imaging device as described in [9] above, wherein the first pixel region and the second pixel region are arranged in the first direction in such a manner that each of the first pixel regions and each of the second pixel regions are arranged in parallel along the first direction". In this case, it is easy to make the same or corresponding light incident on the first pixel region and the second pixel region.

[0020] The solid-state imaging device disclosed in the present invention may also be,

[11] "a solid-state imaging device as described in

[10] above, wherein the first pixel region, the first transfer gate portion, and the first horizontal transfer CCD portion are arranged in sequence toward one side of the first direction, and the second pixel region, the second transfer gate portion, and the second horizontal transfer CCD portion are arranged in sequence toward the opposite side of the first direction". In this case, the first horizontal transfer CCD portion, the second horizontal transfer CCD portion, the first transfer gate portion, and the second transfer gate portion may be appropriately arranged relative to the first pixel region and the second pixel region that are arranged so that the same or corresponding light is easily incident.

[0021] The solid-state imaging device disclosed in the present invention may also be,

[12] "a solid-state imaging device as described in any one of the above [1] to

[11] , wherein the above-mentioned output unit includes: a first output unit, which is used to receive the charge generated in the above-mentioned first light receiving unit and output the above-mentioned first signal; and a second output unit, which is used to receive the charge generated in the above-mentioned second light receiving unit and output the above-mentioned second signal". In this case, by providing output units corresponding to each of the first light receiving unit and the second light receiving unit, the processing speed can be improved.

[0022] The solid-state imaging device disclosed in the present invention may also be,

[13] "a solid-state imaging device as described in any one of [1] to

[12] above, wherein the first pixel region includes a plurality of first pixels arranged along the first direction, and the second pixel region includes a plurality of second pixels arranged along the first direction." In this case, pixel combination can be performed, and the SN ratio (Signal to Noise ratio) of the output signal becomes good.

[0023] The solid-state imaging device of the present disclosure may also be,

[14] "a solid-state imaging device as described in any one of [1] to

[13] above, wherein the first pixel region and the second pixel region are arranged adjacent to each other". In this case, by arranging the first pixel region and the second pixel region close to each other, the characteristics between the regions become closer, so that more appropriate correction can be performed.

[0024] The signal processing method disclosed in the present invention is

[15] "a signal processing method, which is a signal processing method having a solid-state imaging device, the solid-state imaging device having: a first light receiving unit and a second light receiving unit, which are used to generate electric charges according to the incidence of light; and an output unit, which is used to output a first signal corresponding to the electric charges generated in the above-mentioned first light receiving unit, and output a second signal corresponding to the electric charges generated in the above-mentioned second light receiving unit, the signal processing method having: an addition signal generating step, which adds the above-mentioned first signal and the above-mentioned second signal to generate an addition signal; a subtraction signal generating step, which subtracts the above-mentioned second signal from the above-mentioned first signal to generate a subtraction signal; and a correction step, which corrects the above-mentioned addition signal based on the above-mentioned subtraction signal and outputs it, the above-mentioned first light receiving unit having The invention further comprises: a first pixel region, which is composed of a plurality of first pixels arranged along a first direction, or a pixel region of one first pixel, i.e., a plurality of first pixel regions arranged along a second direction intersecting the first direction; the second light receiving portion comprises: a second pixel region, which is composed of a plurality of second pixels arranged along the first direction, or a pixel region of one second pixel, i.e., a plurality of second pixel regions arranged along the second direction; and when the first pixel region and the second pixel region are arranged along the first direction in such a manner that the ends of the first pixel region and the second pixel region in the second direction are consistent, the first pixel region and the second pixel region are corresponding to each other in such a manner that each of the plurality of first pixel regions and each of the plurality of second pixel regions are arranged in parallel along the first direction.

[0025] According to this signal processing method, the life of the solid-state imaging device can be extended for the same reason as described above. Effects of the Invention

[0026] According to the present disclosure, it is possible to provide a solid-state imaging device and a signal processing method that can achieve a longer life. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic plan view showing an example of the solid-state imaging device according to the present embodiment. Figure 2 is along Figure 1 A partial schematic cross-sectional view taken along line II-II, and a schematic diagram showing the potential in the cross-section. Figure 3 This is a schematic plan view showing another example of the solid-state imaging device according to the present embodiment. Figure 4 is along Figure 3 A partial schematic cross-sectional view along line IV-IV of FIG. 1 , and a schematic diagram showing the potential in the cross-section. Figure 5 Is a graph showing various signals. Figure 6 Is a graph showing various signals. Figure 7 This is a flowchart showing an example of the signal processing method according to the present embodiment. Figure 8 This is a flowchart showing another example of the signal processing method according to this embodiment. Fig. 9 This is a flowchart showing still another example of the signal processing method according to this embodiment. Fig.10 It is a schematic plan view showing a first modified example of the solid-state imaging device. Fig.11 is along Fig.10 A partial schematic cross-sectional view taken along line XI-XI of FIG. 1 , and a schematic diagram showing the potential in the cross-section. Fig.12 This is a schematic plan view showing another aspect of the solid-state imaging device according to the first modification. Fig.13 is along Fig.12 A partial schematic cross-sectional view taken along line XIII-XIII of , and a schematic diagram showing the potential in the cross-section. Fig.14 It is a schematic plan view showing a second modified example of the solid-state imaging device. Fig.15 It is a magnified display Fig.14 A schematic top view of a portion of. Fig.16 is along Fig.14 , 15 A partial schematic cross-sectional view taken along line XVI-XVI of , and a schematic diagram showing the potential in the cross-section. DETAILED DESCRIPTION

[0028] Hereinafter, one embodiment will be described with reference to the accompanying drawings. In addition, in the description of each figure, the same reference numerals are given to the same or corresponding parts, and repeated descriptions are omitted. In addition, in each figure, an orthogonal coordinate system including a first axis defining a first direction D1, a second axis defining a second direction D2 intersecting (orthogonal) with the first direction D1, and a third axis defining a third direction D3 intersecting (orthogonal) with the first direction D1 and the second direction D2 is shown. [Configuration of Solid-State Imaging Device]

[0029] Figure 1 It is a schematic plan view showing an example of the solid-state imaging device according to the present embodiment. Figure 2 is along Figure 1 A partial schematic cross-sectional view of the II-II line and a schematic diagram showing the potential in the cross section. Figure 2 The upper part shows a cross-sectional view along line II-II (with shadow omitted). Figure 2 The lower part shows the potential V of the cross section. Figure 1 , 2 The solid-state imaging device 1 shown is, for example, a CCD image sensor and includes a first pixel region 10 and a second pixel region 20 .

[0030] The first pixel region 10 has a plurality of first pixel areas 11 arranged along the second direction D2. The first pixel areas 11 each include a plurality of first pixels 12 arranged along the first direction D1. The first pixel 12 generates an electric charge in response to the incidence of light. Therefore, the first pixel region 10 constitutes a first light receiving portion 5 that generates an electric charge in response to the incidence of light. Here, the first light receiving portion 5 is formed into a shape that is relatively long in the second direction D2 compared to the first direction D1, according to the number of arrangement of the first pixels 12 in each of the first direction D1 and the second direction D2. That is, here, the number of arrangement of the first pixels 12 in the second direction D2 becomes larger than the number of arrangement of the first pixels 12 in the first direction D1.

[0031] The second pixel region 20 has a plurality of second pixel areas 21 arranged along the second direction D2. The second pixel areas 21 each include a plurality of second pixels 22 arranged along the first direction D1. The second pixels 22 generate charges in response to the incidence of light. Therefore, the second pixel region 20 constitutes a second light receiving portion 6 that generates charges in response to the incidence of light. Here, the second light receiving portion 6 is formed into a shape that is longer in the second direction D2 than in the first direction D1, according to the number of arrangement of the second pixels 22 in each of the first direction D1 and the second direction D2. That is, here, the number of arrangement of the second pixels 22 in the second direction D2 becomes larger than the number of arrangement of the second pixels 22 in the first direction D1.

[0032] In the present embodiment, for each of the first direction D1 and the second direction D2, the number of the first pixels 12 of the first pixel region 10 is the same as the number of the second pixels 22 of the second pixel region 20. That is, the first pixel region 10 and the second pixel region 20 have the same area. Therefore, here, the number of the first pixels 12 included in the first pixel region 11 is the same as the number of the second pixels 22 included in the second pixel region 21, and the number of the first pixel region 11 is also the same as the number of the second pixel region 21. That is, in the present embodiment, the first pixel region 10 and the second pixel region 20 have the same shape as each other in the plane including the first direction D1 and the second direction D2.

[0033] The first pixel region 11 and the second pixel region 21 are arranged in a manner that each of the plurality of first pixel regions 11 and each of the plurality of second pixel regions 21 are aligned along the first direction D1 when the first pixel region 10 and the second pixel region 20 are arranged in a manner that the ends of the first pixel region 10 and the second pixel region 20 in the second direction D2 are aligned. In the present embodiment, in fact, by arranging the first pixel region 10 and the second pixel region 20 in a manner that the ends of the first pixel region 10 and the second pixel region 20 in the second direction D2 are aligned, each of the plurality of first pixel regions 11 and each of the plurality of second pixel regions 21 (the same number as the first pixel region 11) are arranged in the first direction D1.

[0034] The above-mentioned first light receiving unit 5 (first pixel region 10) and second light receiving unit 6 (second pixel region 20) are formed on the semiconductor substrate 2. That is, the solid-state imaging device 1 includes a semiconductor substrate 2, a semiconductor layer 3 stacked on the semiconductor substrate 2, an insulating film F1 formed on the surface of the semiconductor layer 3 on the opposite side to the semiconductor substrate 2, and a plurality of transfer electrodes F2 formed on the insulating film F1. The semiconductor substrate 2 and the semiconductor layer 3 include, for example, silicon. The semiconductor substrate 2 has a first conductivity type (here, P type).

[0035] The semiconductor layer 3 includes a pair of first regions 3A and a second region 3B arranged along a first direction D1 on the semiconductor substrate 2. The first regions 3A each have a second conductivity type (here, N type) different from the first conductivity type. The second region 3B is formed between the pair of first regions 3A and has a first conductivity type (here, P type). + The first light receiving portion 5 is formed by one of the pair of first regions 3A and the region directly below the first region 3A of the semiconductor substrate 2, and the second light receiving portion 6 is formed by the other first region 3A and the region directly below the first region 3A of the semiconductor substrate 2. In addition, the individual first pixels 12 and second pixels 22 are defined by the arrangement of the transfer electrodes F2.

[0036] The second region 3B provides a potential barrier to the charge e generated by each of the first light receiving section 5 and the second light receiving section 6. Thus, an element separation section is formed between the first light receiving section 5 and the second light receiving section 6. As a result, the first light receiving section 5 (first pixel region 10) and the second light receiving section 6 (second pixel region 20) are arranged adjacent to each other in the first direction D1 via the element separation section. Figure 3 , 4 As shown, by not providing the second region 3B of the first conductivity type in the semiconductor layer 3 , the first light receiving portion 5 (first pixel region 10 ) and the second light receiving portion 6 (second pixel region 20 ) can be arranged adjacent to each other in the first direction D1 without interposing the element isolation portion therebetween.

[0037] In the case where an element separation portion is provided between the first pixel region 10 and the second pixel region 20 ( Figure 1 , 2 On the other hand, when the element separation portion is not provided between the first pixel region 10 and the second pixel region 20 and the first pixel region 10 and the second pixel region 20 are arranged closer ( Figure 3 , 4 In addition, Figure 3 This is a schematic plan view showing another example of the solid-state imaging device according to the present embodiment. Figure 4 is along Figure 3 A partial schematic cross-sectional view of the IV-IV line and a schematic diagram showing the potential in the cross section. Figure 4 The upper part of the figure shows a cross-sectional view along line IV-IV (with shadow omitted). Figure 4 The lower part shows the potential V of the cross section.

[0038] like Figure 1 , 3 As shown, the solid-state imaging device 1 further includes a first transfer gate portion 30 , a second transfer gate portion 40 , a first horizontal transfer CCD portion 50 , a second horizontal transfer CCD portion 60 , a first output portion (output portion) 70 , a second output portion (output portion) 80 , and a signal processing portion 90 .

[0039] The first transfer gate portion 30 is disposed on the side of the first pixel region 10 opposite to the second pixel region 20 in the first direction D1, and is used to transfer the charges from the first pixel region 11 along the first direction D1. The second transfer gate portion 40 is disposed on the side of the second pixel region 20 opposite to the first pixel region 10 in the first direction D1, and is used to transfer the charges from the second pixel region 21 along the first direction D1.

[0040] The first horizontal transfer CCD unit 50 is arranged on the opposite side of the first pixel region 10 in the first direction D1 with the first transfer gate unit 30 interposed therebetween. That is, the first pixel region 10, the first transfer gate unit 30, and the first horizontal transfer CCD unit 50 are sequentially arranged on one side (here, the positive side) in the first direction D1. The first horizontal transfer CCD unit 50 is used to receive the charge transferred by the first transfer gate unit 30, and transfer the charge to the first output unit 70 along the second direction D2. The second horizontal transfer CCD unit 60 is arranged on the opposite side of the first direction D1 with the second transfer gate unit 40 interposed therebetween. That is, the second pixel region 20, the second transfer gate unit 40, and the second horizontal transfer CCD unit 60 are sequentially arranged on the other side (here, the negative side) in the first direction D1. The second horizontal transfer CCD unit 60 is used to receive the charge transferred by the second transfer gate unit 40, and transfer the charge to the second output unit 80 along the second direction D2.

[0041] The first output section 70 is arranged on one end side of the first horizontal transfer CCD section 50 in the second direction D2. The first output section 70 is a first amplifier for receiving the charge generated in the first light receiving section (first pixel region 10) and transferred by the first transfer gate section 30 and the first horizontal transfer CCD section 50, converting the charge into a voltage, generating and outputting the first signal S1. The second output section 80 is arranged on one end side of the second horizontal transfer CCD section 60 in the second direction D2 (the same side as the first output section 70). The second output section 80 is a second amplifier for receiving the charge generated in the second light receiving section (second pixel region 20) and transferred by the second transfer gate section 40 and the second horizontal transfer CCD section 60, converting the charge into a voltage, generating and outputting the second signal S2.

[0042] The signal processing unit 90 receives an input of the first signal S1 from the first output unit 70 and receives an input of the second signal S2 from the second output unit 80. The signal processing unit 90 appropriately processes the first signal S1 and the second signal S2, generates an output signal So, and outputs it. In the solid-state imaging device 1, the first transfer gate unit 30, the second transfer gate unit 40, the first horizontal transfer CCD unit 50, the second horizontal transfer CCD unit 60, the first output unit 70, the second output unit 80, and the signal processing unit 90 may be configured on the semiconductor substrate 2, and a part of them may be configured outside the semiconductor substrate 2. In addition, in the solid-state imaging device 1, the first light receiving unit 5 and the second light receiving unit 6 may be formed on different semiconductor substrates and arranged in parallel as described above. [Specific example of signal processing]

[0043] Next, specific signal processing that can be performed by the signal processing unit 90 will be described. Figure 5 and Figure 6The horizontal axis of each graph shows the position of the first pixel region 11 or the second pixel region 21 in the second direction D2, and the vertical axis of each graph shows the output value (voltage value).

[0044] In the following, it is assumed that light is equally incident on the first pixel region 10 and the second pixel region 20. Making light equally incident on the first pixel region 10 and the second pixel region 20 can be achieved, for example, by positioning the expansion center of the incident light at the boundary between the first pixel region 10 and the second pixel region 20. The boundary between the first pixel region 10 and the second pixel region 20, for example Figure 1 , 2 When the element isolation portion (second region 3B) is disposed between the first pixel region 10 and the second pixel region 20, the center of the element isolation portion in the first direction D1 is shown. Figure 3 , 4 As shown, when the first pixel region 10 and the second pixel region 20 are directly connected, it is the actual boundary between the first pixel region 10 and the second pixel region 20 .

[0045] Figure 5 (a) shows the first signal S1 input to the signal processing unit 90, Figure 5 (b) shows the second signal S2 input to the signal processing unit 90. Here, in the first signal S1, WS is generated in one of the plurality of first pixel regions 11, and a relatively high output value V1 is generated. The first pixel region 11 that displays the output value V1 is set as a WS region (white dot region) 11a. In addition, in the second signal S2, WS is generated in one of the plurality of second pixel regions 21, and a relatively high output value V2 is generated. The second pixel region 21 that displays the output value V2 is set as a WS region 21a. The position of the WS region 11a in the second direction D2 is different from the position of the WS region 21a in the second direction D2.

[0046] like Figure 5As shown in (c), the signal processing of the signal processing unit 90 includes an addition signal generation process of adding the first signal S1 and the second signal S2 to generate an addition signal S3. The addition signal S3 includes an output value V1a corresponding to the output value V1 of the WS region 11a of the first signal S1 and the output value V2a corresponding to the output value V2 of the WS region 21a of the second signal S2, which are increased by adding each peak value of the output values ​​of the first signal S1 and the second signal S2 corresponding to the incident light images to the first pixel region 10 and the second pixel region 20 to each other (for example, twice). The output value V1a corresponding to the output value V1 is a value obtained by adding the output value V1 of the second pixel region 21 of the second signal S2 corresponding to the WS region 11a of the first signal S1. The output value V2a corresponding to the output value V2 is a value obtained by adding the output value of the first pixel area 11 of the first signal S1 corresponding to the WS area 21a of the second signal S2 to the output value V2.

[0047] like Figure 6 As shown in (a), the signal processing of the signal processing unit 90 includes a subtraction signal generation process of generating a subtraction signal S4 by subtracting the second signal S2 from the first signal S1. In the subtraction signal S4, the peak values ​​of the output values ​​of the first signal S1 and the second signal S2 corresponding to the incident light images to the first pixel region 10 and the second pixel region 20 are subtracted from each other and removed. On the other hand, since the output value V1b corresponding to the output value V1 of the WS region 11a of the first signal S1 and the output value V2b corresponding to the output value V2 of the WS region 21a of the second signal S2 are generated at positions that have no corresponding relationship with each other, they are not removed and remain. The output value V1b corresponding to the output value V1 is a value obtained by subtracting the output value of the second pixel region 21 of the second signal S2 corresponding to the WS region 11a of the first signal S1 from the output value V1. The output value V2b corresponding to the output value V2 is a value obtained by subtracting the output value V2 from the output value of the first pixel area 11 of the first signal S1 corresponding to the WS area 21a of the second signal S2, and is a negative value.

[0048] like Figure 6As shown in (b), the signal processing of the signal processing unit 90 includes a correction signal generation process of converting the sign of the output value V2b of the WS area 21a in the subtraction signal S4 to positive and setting it as the output value V2c to generate the correction signal S5. In addition, in the signal processing of the signal processing unit 90, the sign of the output value V1b of the WS area 11a in the subtraction signal S4 may be converted to negative to generate the correction signal S5. The signal processing unit 90 may further perform a noise removal process of setting the output value of the pixel area (the first pixel area 11 and the second pixel area 21) showing the output value between the positive threshold value Tp and the negative threshold value Tn in the correction signal S5 to 0. The timing of the noise removal process is arbitrary, and the noise removal process may be performed before the process of inverting the sign of the output value V2b (or the output value V1b), or after the process of inverting the sign of the output value V2b (or the output value V1b), or simultaneously.

[0049] Thus, in the correction signal S5, noise other than the noise caused by WS is removed, and only the output values ​​V1b and V2c caused by WS (or the output value V1b with a negative sign and the output value V2b) remain. The threshold value Tp and the threshold value Tn may be the same or different, and may be set to any value that can remove noise.

[0050] like Figure 6 As shown in (c), the signal processing of the signal processing unit 90 includes a correction process of correcting the addition signal S3 and generating the output signal So by subtracting the correction signal S5 generated by the subtraction signal S4 from the addition signal S3. As a result, in the output signal So, only the output values ​​V1a and V2a are removed from the addition signal S3. In this way, in the correction process of the signal processing unit 90, the addition signal S3 is corrected based on the subtraction signal S4 and output. In addition, in the case where the signal processing unit 90 converts the sign of the output value V1b of the WS area 11a in the subtraction signal S4 into a negative sign to generate the correction signal S5, the signal processing unit 90 may also correct the addition signal S3 and generate the output signal So by adding the correction signal S5 to the addition signal S3. As a result, only the output values ​​V1a and V2a are removed from the addition signal S3. [An example of a signal processing method]

[0051] Next, an example of a signal processing method of the solid-state imaging device 1 by the signal processing unit 90 will be described. Figure 7 FIG. 4 is a flowchart showing an example of a signal processing method according to the present embodiment. Figure 7As shown, in the signal processing method of this embodiment, first, shooting is performed (step S101). In step S101, shooting is performed by making light equally incident on the first pixel region 10 and the second pixel region 20 (making the same light incident). In step S101, a first signal S1 and a second signal S2 corresponding to the charges generated in the first pixel region 10 and the second pixel region 20 are generated and input to the signal processing unit 90.

[0052] Next, the signal processing unit 90 performs image addition (step S102: addition signal generation processing, addition signal generation step). More specifically, in step S102, the signal processing unit 90 adds the first signal S1 (the image captured in the first pixel region 10) and the second signal S2 (the image captured in the second pixel region 20) to generate an addition signal S3.

[0053] At the same time, in the subsequent step S103, the signal processing unit 90 performs image subtraction (step S103: subtraction signal generation processing, subtraction signal generation step). More specifically, in step S103, the signal processing unit 90 subtracts the second signal S2 from the first signal S1 to generate a subtraction signal S4. In addition, the order of step S102 and step S103 is irrelevant.

[0054] Next, the signal processing unit 90 determines whether there is WS based on the subtraction signal S4 (step S104). More specifically, in step S104, the signal processing unit 90 sets a positive threshold value Tp and a negative threshold value Tn for the subtraction signal S4, and determines whether there is a pixel area (first pixel area 11) whose output value exceeds the positive threshold value Tp, and whether there is a pixel area (second pixel area 21) whose output value is lower than the negative threshold value Tn in the subtraction signal S4.

[0055] If the result of determination in step S104 is that WS is not detected in the subtraction signal S4 (step S104: No), the signal processing unit 90 outputs the addition signal S3 (image) as the output signal So (step S108), and the processing ends. That is, if there is no WS in the subtraction signal S4, the signal processing unit 90 does not perform the correction processing.

[0056] On the other hand, when the judgment result of step S104 is that WS is detected in the subtraction signal S4 (step S104: Yes), that is, when at least one of the pixel area, i.e., the WS area 11a, which displays an output value V1 exceeding the positive threshold Tp, and the pixel area, i.e., the WS area 21a, which displays an output value V2 lower than the negative threshold Tn, is detected in the subtraction signal S4, the signal processing unit 90 performs image processing (step S105: correction processing, correction step).

[0057] More specifically, in step S105, when the signal processing unit 90 identifies the pixel area showing the output value V2b lower than the negative threshold value Tn, that is, the WS area 21a in the subtraction signal S4, the signal processing unit 90 changes the sign of the output value V2b of the WS area 21a in the subtraction signal S4 to positive, and generates the correction signal S5. At this time, the signal processing unit 90 can set the output value of the pixel area showing the output value between the positive threshold value Tp and the negative threshold value Tn in the correction signal S5 to 0.

[0058] Next, the signal processing unit 90 corrects the addition signal S3 by subtracting the correction signal S5 from the addition signal S3 and generates the output signal So (step S106: correction processing, correction step). As a result, the output values ​​V1a and V2a caused by WS are removed from the addition signal S3. In this way, in steps S105 and S106, the signal processing unit 90 corrects the addition signal S3 based on the subtraction signal S4. In addition, in step S106, the signal processing unit 90 can correct the addition signal S3 by generating the correction signal S5 in all the first pixel areas 11 and all the second pixel areas 21 and subtracting it from the addition signal S3.

[0059] After the above, the signal processing unit 90 outputs the correction signal S5 as the output signal So (image) (step S107), and the processing ends.

[0060] Furthermore, in step S105, when the signal processing unit 90 identifies the WS region 11a as a pixel region showing an output value V1b exceeding the positive threshold value Tp in the subtraction signal S4, the signal processing unit 90 may change the sign of the output value V1b of the WS region 11a in the subtraction signal S4 to negative, thereby generating the correction signal S5. In this case, the signal processing unit 90 may also set the output value of the pixel region showing an output value between the positive threshold value Tp and the negative threshold value Tn in the correction signal S5 to 0.

[0061] Furthermore, in this case, in step S106, the signal processing unit 90 can correct the addition signal S3 by adding the correction signal S5 to the addition signal S3 and generate the output signal So. Thus, the output values ​​V1a and V2a caused by WS are removed from the addition signal S3. Furthermore, in this case, in step S106, the signal processing unit 90 can also correct the addition signal S3 by generating the correction signal S5 in all the first pixel regions 11 and all the second pixel regions 21 and adding the addition signal S3. [Another example of signal processing method]

[0062] Next, another example of the signal processing method of the solid-state imaging device 1 by the signal processing unit 90 will be described. Figure 8FIG. 4 is a flowchart showing another example of the signal processing method of this embodiment. Figure 8 As shown, the signal processing method of this example is compared with Figure 7 The signal processing method of the example is different only in that step S106 of determining whether or not a WS is present is not performed.

[0063] That is, here, after the signal processing unit 90 generates the addition signal S3 and the subtraction signal S4 in steps S102 and S103, it performs the image processing in step S105 and the image subtraction (or addition) in step S106 regardless of whether there is WS in the subtraction signal S4. Therefore, there is no need for processing for determining whether there is WS. [Another example of signal processing method]

[0064] Next, another example of the signal processing method of the solid-state imaging device 1 by the signal processing unit 90 will be described. Fig. 9 FIG. 4 is a flowchart showing another example of the signal processing method of this embodiment. Fig. 9 As shown, in the signal processing method of this example, Figure 7 Similarly to the signal processing method of the example, steps S101, S102, and S103 are implemented to generate the addition signal S3 and the subtraction signal S4, and step S104 is implemented to determine whether the subtraction signal S4 contains WS. In addition, the subtraction signal S4 is generated by subtracting the second signal S2 from the first signal S1, so when the pixel area showing the output value V1b exceeding the positive threshold value Tp, i.e., the WS area 11a, is detected in the subtraction signal S4, the state is that the first signal S1 contains the output value V1 corresponding to WS, and when the pixel area showing the output value V2b below the negative threshold value Tn, i.e., the WS area 21a, is detected in the subtraction signal S4, the state is that the second signal S2 contains the output value V2 corresponding to WS.

[0065] Subsequently, when the judgment result of step S104 is that WS is detected in the subtraction signal S4 (step S104: yes), that is, in the subtraction signal S4, when at least one of the pixel area, i.e., the WS area 11a, which displays an output value V1b exceeding the positive threshold Tp, and the pixel area, i.e., the WS area 21a, which displays an output value V2b lower than the negative threshold Tn, is detected, the signal processing unit 90 extracts the position of the detected WS area 11a and / or WS area 21a in the second direction D2 (step S205).

[0066] Next, the signal processing unit 90 performs image processing of the addition signal S3 based on the information about the position of the WS extracted in step S205 (step S206: correction processing, correction step). More specifically, in step S206, when the WS area 11a is detected, the signal processing unit 90 replaces the output value V1a of the WS area 11a in the addition signal S3 with an output value obtained by doubling the output value of the second pixel area 21 at the position of the WS area 11a of the second signal S2.

[0067] Alternatively, in step S206, when the WS region 21a is detected, the signal processing unit 90 replaces the output value V2a of the WS region 21a in the addition signal S3 with an output value obtained by doubling the output value of the first pixel region 11 at the position of the WS region 21a of the first signal S1. Thus, the output value V1a caused by WS included in the addition signal S3 is corrected to a normal value corresponding to the output value of the second signal S2, and the output value V2a caused by WS included in the addition signal S3 can be corrected to a normal value corresponding to the output value of the first signal S1.

[0068] Thus, in step S206, when the signal processing unit 90 detects a pixel area, i.e., WS area 11a, showing an output value V1b exceeding the positive threshold value Tp in the subtraction signal S4, the output value V1a of the WS area 11a in the addition signal S3 is replaced by an output value obtained by doubling the output value of the second pixel area 21 at the position of the WS area 11a of the second signal S2, and when the signal processing unit 90 detects a pixel area, i.e., WS area 21a, showing an output value lower than the negative threshold value Tn in the subtraction signal S4, the output value V2a of the WS area 21a in the addition signal S3 is replaced by an output value obtained by doubling the output value of the first pixel area 11 at the position of the WS area 21a of the first signal S1. Thus, the output values ​​V1a and V2a caused by WS are removed from the addition signal S3. Subsequent processing is the same as Figure 7 The same example.

[0069] In addition, in step S206, when the output value V1a and the output value V2a of the addition signal S3 are replaced with the output value of the first signal S1 or the output value of the second signal S2, it is also possible to determine whether the output value used for the replacement is appropriate. As an example of this case, the signal processing unit 90 may also use a specified positive threshold value Tpa set to be greater than the maximum value of the output value of the pixel area where WS is not generated and less than the output value overlapped with WS relative to the output value (noise) in the case of no light incidence, to determine whether the output value used for the replacement is a value between 0 and the threshold value Tpa. And, if the result of this judgment is that the output value used for the replacement is a value between 0 and the threshold value Tpat, the replacement can be performed.

[0070] That is, in step S206, when the signal processing unit 90 detects a pixel area, namely, the WS area 11a, which displays an output value V1b exceeding the positive threshold value Tp in the subtraction signal S4, and the output value of the second pixel area 21 at the position of the WS area 11a of the second signal S2 is a value between 0 and the threshold value Tpa, the output value V1a of the WS area 11a in the addition signal S3 can be replaced by an output value obtained by doubling the output value of the second pixel area 21 at the position of the WS area 11a of the second signal S2.

[0071] In addition, in step S206, when the signal processing unit 90 detects the pixel area, i.e., the WS area 21a, which shows an output value lower than the negative threshold value Tn in the subtraction signal S4, and the output value of the first pixel area 11 at the position of the WS area 21a of the first signal S1 is between 0 and the threshold value Tpa, the output value V2a of the WS area 21a in the addition signal S3 can be replaced by the output value obtained by doubling the output value of the first pixel area 11 at the position of the WS area 21a of the first signal S1. In addition, the positive threshold value Tpa used here can be a value different from the positive threshold value Tp used in step S104 to determine whether the subtraction signal S4 has WS. [Function, Effect]

[0072] As described above, the solid-state imaging device 1 of the present embodiment includes the first light receiving unit 5 and the second light receiving unit 6 that generate electric charge in response to incident light. The first light receiving unit 5 includes the first pixel region 10 in which the first pixel region 11 including the plurality of first pixels 12 is arranged along the second direction D2, and the second light receiving unit 6 also includes the second pixel region 20 in which the second pixel region 21 including the plurality of second pixels 22 is arranged along the second direction D2. In the first light receiving unit 5 and the second light receiving unit 6, electric charge corresponding to the incident light is generated in each of the first pixel 12 and the second pixel 22.

[0073] Furthermore, when the first pixel region 10 and the second pixel region 20 are arranged along the first direction D1 in such a manner that the ends of the first pixel region 10 and the second pixel region 20 in the second direction D2 coincide with each other (which is actually arranged in this embodiment), the first pixel region 11 and the second pixel region 21 are corresponding to each other in parallel along the first direction D1. Therefore, in the solid-state imaging device 1, by causing the same or corresponding light to be incident on the first light receiving portion 5 (first pixel region 10) and the second light receiving portion 6 (second pixel region 20), a corresponding relationship is generated between the first signal S1 corresponding to the charge from the first light receiving portion 5 and the second signal S2 corresponding to the charge from the second light receiving portion 6.

[0074] Therefore, by generating the subtraction signal S4 of the first signal S1 and the second signal S2 by the signal processing unit 90, information related to the output values ​​V1 and V2 caused by WS that may be generated without a corresponding relationship between the first signal S1 and the second signal S2 (for example, information related to the position of the pixel area where the output values ​​V1 and V2 caused by WS are generated, or the signal itself of the output values ​​V1 and V2) can be obtained. Therefore, by correcting the addition signal S3 (the output signal So before correction) of the first signal S1 and the second signal S2 generated by the signal processing unit 90 based on the subtraction signal S4, the output values ​​V1a and V2a caused by WS can be removed. Therefore, even if WS is generated over time, its influence can be suppressed and it can be used continuously. That is, the life of the solid-state imaging device 1 is prolonged.

[0075] In addition, in the solid-state imaging device 1 of the present embodiment, in the correction process, the signal processing unit 90 generates a correction signal S5 based on the subtraction signal S4, and can correct the addition signal S3 by subtracting the correction signal S5 from the addition signal S3. At this time, in the correction signal S5, when it is confirmed that the pixel area showing the output value V2b lower than the negative threshold value Tn, that is, the WS area 21a, the sign of the output value V2b of the WS area 21a is changed to positive. Therefore, by subtracting the correction signal S5 from the addition signal S3, the output values ​​V1a and V2a caused by WS can be removed from the addition signal S3 to generate the output signal So.

[0076] In the solid-state imaging device 1 of the present embodiment, in the correction process, the signal processing unit 90 can set the output value of the pixel area showing the output value between the positive threshold value Tp and the negative threshold value Tn in the correction signal S5 to 0. Therefore, superposition of noise caused by subtraction of the correction signal S5 is suppressed.

[0077] In addition, in the solid-state imaging device 1 of the present embodiment, in the correction process, the signal processing unit 90 can generate the correction signal S5 in all the first pixel regions 11 and all the second pixel regions 21, and can correct the addition signal S3 by subtracting the correction signal S5 from the addition signal S3. Therefore, the output values ​​V1a and V2a caused by WS can be removed from the addition signal S3 without determining the position of the WS region.

[0078] In addition, in the solid-state imaging device 1 of the present embodiment, the signal processing unit 90 may generate a correction signal S5 based on the subtraction signal S4 in the correction process, and correct the addition signal S3 by adding the correction signal S5 to the addition signal S3. At this time, in the correction signal S5, when it is confirmed that the pixel area showing the output value V1b exceeding the positive threshold value Tp, that is, the WS area 11a, the sign of the output value V1b of the WS area 11a may be changed to negative. In this case, by adding the correction signal S5 to the addition signal S3, the output values ​​V1a and V2a caused by WS can be removed from the addition signal S3.

[0079] In this case, the signal processing unit 90 may generate a correction signal S5 in all the first pixel regions 11 and all the second pixel regions 21 during the correction process, and correct the addition signal S3 by adding the correction signal S5 to the addition signal S3. In this case, the position of the WS region may be not determined, and the output values ​​V1a and V2a caused by WS may be removed from the addition signal S3.

[0080] In addition, in the solid-state imaging device 1 of the present embodiment, in the correction process, when the signal processing unit 90 detects at least one of the WS area 11a showing an output value V1b exceeding the positive threshold value Tp and the WS area 21a showing an output value V2b below the negative threshold value Tn in the subtraction signal S4, the output values ​​V1a and V2a of the WS areas 11a and 21a in the addition signal S3 are replaced by output values ​​obtained by doubling the output values ​​of the pixel areas whose output values ​​are between the positive threshold value Tpa and 0 in the first pixel area 11 at the position of the WS areas 11a and 21a of the first signal S1 and the second pixel area 21 at the position of the WS areas 11a and 21a of the second signal S2. Therefore, when the output values ​​V1a and V2a due to WS are removed from the addition signal S3, the subtraction and addition of the correction signal S5 are unnecessary.

[0081] In addition, in the solid-state imaging device 1 of the present embodiment, the signal processing unit 90 can execute the correction process when at least one of the WS region 11a showing the output value V1b exceeding the positive threshold value Tp and the WS region 21a showing the output value V2b below the negative threshold value Tn is detected in the subtraction signal S4. Therefore, when the WS region is not detected, the execution of the correction process can be omitted.

[0082] In addition, the solid-state imaging device 1 of the present embodiment includes: a first transfer gate portion 30 for transferring charges from each of the first pixel region 11; a second transfer gate portion 40 for transferring charges from each of the second pixel region 21; a first horizontal transfer CCD portion 50 for transferring the charges transferred via the first transfer gate portion 30 to the first output portion 70; and a second horizontal transfer CCD portion 60 for transferring the charges transferred via the second transfer gate portion 40 to the second output portion 80. Therefore, the life of the solid-state imaging device 1 including the CCD can be extended.

[0083] In the solid-state imaging device 1 of the present embodiment, the first pixel region 10 and the second pixel region 20 are arranged in the first direction D1 in such a manner that each of the first pixel regions 11 and each of the second pixel regions 21 are arranged in parallel in the first direction D1. Therefore, it is easy to make the same or corresponding light incident on the first pixel region 10 and the second pixel region 20.

[0084] In the solid-state imaging device 1 of the present embodiment, the first pixel region 10, the first transfer gate portion 30, and the first horizontal transfer CCD portion 50 are arranged in this order toward one side in the first direction D1, and the second pixel region 20, the second transfer gate portion 40, and the second horizontal transfer CCD portion 60 are arranged in this order toward the opposite side in the first direction D1. Therefore, the first horizontal transfer CCD portion 50, the second horizontal transfer CCD portion 60, the first transfer gate portion 30, and the second transfer gate portion 40 can be appropriately arranged with respect to the first pixel region 10 and the second pixel region 20 arranged so that the same or corresponding light can be easily incident.

[0085] In addition, the solid-state imaging device 1 of the present embodiment includes: a first output unit 70 for receiving the charge generated in the first light receiving unit 5 and outputting the first signal S1; and a second output unit 80 for receiving the charge generated in the second light receiving unit 6 and outputting the second signal S2. In this way, by providing the output units corresponding to the first light receiving unit 5 and the second light receiving unit 6, the processing speed can be improved.

[0086] In the solid-state imaging device 1 of this embodiment, the first pixel region 11 includes a plurality of first pixels 12 arranged along the first direction D1, and the second pixel region 21 includes a plurality of second pixels 22 arranged along the first direction D1. Therefore, pixel combination is possible, and the SN ratio of the output signal So becomes good.

[0087] In the solid-state imaging device 1 of the present embodiment, the first pixel region 10 and the second pixel region 20 are arranged adjacent to each other (sometimes with an element separation portion interposed therebetween). Therefore, by arranging the first pixel region 10 and the second pixel region 20 close to each other, the characteristics between the regions become closer, and thus more appropriate correction can be performed.

[0088] Furthermore, according to the signal processing method of the present embodiment, the life of the solid-state imaging device 1 can be prolonged for the same reason as described above.

[0089] The above embodiment is one mode for explaining the present invention. Therefore, the present invention is not limited to the above embodiment, and the mode shown in the above embodiment can be arbitrarily modified. Next, a modification example will be described. [First Modification]

[0090] Fig.10 It is a schematic plan view showing a first modified example of the solid-state imaging device. Fig.11 is along Fig.10 A partial schematic cross-sectional view of the line XI-XI of FIG. 1 and a schematic diagram showing the potential in the cross section. Fig.11 The upper part shows a cross-sectional view along line XI-XI (with shadow omitted). Fig.11 The lower part of shows the potential V in the cross section.

[0091] Fig.10 , 11 The solid-state imaging device 1A shown is different in that it is a resistor gate CCD, whereas the solid-state imaging device 1 of the embodiment is a pixel-binned CCD. Specifically, the solid-state imaging device 1A is different from the solid-state imaging device 1 in that it includes a first pixel region 10A instead of the first pixel region 10 and includes a second pixel region 20A instead of the second pixel region 20.

[0092] The first pixel region 10A has a plurality of first pixel regions 11A arranged along the second direction D2. Each of the first pixel regions 11A includes a first pixel 12A extending along the first direction D1. The first pixel 12A generates charge in response to incident light. Therefore, the first pixel region 10A constitutes the first light receiving portion 5 that generates charge in response to incident light.

[0093] The second pixel region 20A has a plurality of second pixel regions 21A arranged along the second direction D2. Each of the second pixel regions 21A includes a second pixel 22A extending along the first direction D1. The second pixel 22A generates charge in response to incident light. Therefore, the second pixel region 20A constitutes the second light receiving portion 6 that generates charge in response to incident light.

[0094] Here, by configuring the first pixel region 10A and the second pixel region 20A so that their ends in the second direction D2 coincide with each other, each of the plurality of first pixel regions 11A and each of the plurality of second pixel regions 21A (the same number as the first pixel regions 11A) are arranged in the first direction D1.

[0095] As a cross-sectional structure of the solid-state imaging device 1A, it has a semiconductor substrate 2 and a semiconductor layer 3 similar to the solid-state imaging device 1, and on the other hand, a high resistance electrode F2A constituting a resistance gate structure is provided on the insulating film F1. The high resistance electrode F2A is provided on a pair of first regions 3A of the semiconductor layer 3, respectively, to define individual first pixels 12A (first pixel area 11A) and second pixels 22A (second pixel area 21A). In the solid-state imaging device 1A, by applying different voltages to both ends of the high resistance electrode F2A, a potential gradient is formed, and the charge e is transferred. As a result, high-speed transfer can be performed, and even in the case of a large pixel height, reading with less unread can be performed.

[0096] In addition, Fig.10 , 11 In the example of FIG. 3 , the element separation portion of the second region 3B is disposed between the first light receiving portion 5 (the first pixel region 10A) and the second light receiving portion 6 (the second pixel region 20A). Fig.12 , 13 As shown, by not providing the second region 3B of the first conductivity type in the semiconductor layer 3 , the first light receiving portion 5 (first pixel region 10A) and the second light receiving portion 6 (second pixel region 20A) can be arranged adjacent to each other in the first direction D1 without interposing the element isolation portion therebetween.

[0097] also, Fig.12 This is a schematic plan view showing another example of the solid-state imaging device according to the modified example. Fig.13 is along Fig.12 A partial schematic cross-sectional view of the XIII-XIII line and a schematic diagram showing the potential in the cross section. Fig.13 The upper part of the figure shows a cross-sectional view along the line XIII-XIII (with shadow omitted). Fig.13 The lower part shows the potential V of the cross section. [Second Modification]

[0098] Fig.14 It is a schematic plan view showing a second modified example of the solid-state imaging device. Fig.15 It is a magnified display Fig.14 A schematic top view of a portion of. Fig.16 is along Fig.14 , 15 A partial schematic cross-sectional view of the XVI-XVI line and a schematic diagram showing the potential in the cross section. Fig.16 The upper part shows a cross-sectional view along the XVI-XVI line (with shading omitted). Fig.16 The lower part shows the potential V of the cross section.

[0099] Fig.14 , 16The solid-state imaging device 1B shown is different in that it is an embedded PD (Photodiode) type CCD, whereas the solid-state imaging device 1 of the embodiment is a pixel-binned CCD. Specifically, the solid-state imaging device 1B is different from the solid-state imaging device 1 in that it includes a first pixel region 10B instead of the first pixel region 10 and includes a second pixel region 20B instead of the second pixel region 20.

[0100] The first pixel region 10B has a plurality of first pixel regions 11B arranged along the second direction D2. Each of the first pixel regions 11B includes a first pixel 12B extending along the first direction D1. The first pixel 12B generates charge in response to incident light. Therefore, the first pixel region 10B constitutes the first light receiving portion 5 that generates charge in response to incident light.

[0101] The second pixel region 20B has a plurality of second pixel regions 21B arranged along the second direction D2. Each of the second pixel regions 21B includes a second pixel 22B extending along the first direction D1. The second pixel 22B generates charges in response to incident light. Therefore, the second pixel region 20B constitutes a second light receiving portion 6 that generates charges in response to incident light.

[0102] Here, by configuring the first pixel region 10B and the second pixel region 20B so that their ends in the second direction D2 coincide with each other, each of the plurality of first pixel regions 11B and each of the plurality of second pixel regions 21B (the same number as the first pixel regions 11B) are arranged in the first direction D1.

[0103] The cross-sectional structure of the solid-state imaging device 1B includes a semiconductor substrate 2 and a semiconductor layer 3 similarly to the solid-state imaging device 1. On the other hand, a first conductivity type (here, P) is provided between the semiconductor layer 3 and the insulating film F1. + Thus, a P is provided on the surface side of the first light receiving portion 5 and the second light receiving portion 6. + The P of the diffusion layer (semiconductor layer 4) + N + P structure.

[0104] The semiconductor layer 3 includes, in a region corresponding to the first region 3A of the semiconductor layer 3 of the solid-state imaging device 1, a channel portion 3Ab of the second conductivity type (here, N type), and a second conductivity type (here, N type) having an impurity concentration higher than that of the channel portion 3Ab. + The channel additional injection portion 3Aa of the surface incident type is formed. The channel additional injection portion 3Aa is formed so as to expand toward each of the first transfer gate portion 30 and the second transfer gate portion 40. Thus, a potential gradient is formed and the charge e is transferred. According to this structure, a transfer electrode is not formed, and a high quantum efficiency is achieved even in the surface incident type. [Other Modifications]

[0105] The above solid-state imaging device 1 (and solid-state imaging devices 1A and 1B (hereinafter the same)) is configured as a CCD image sensor having a transfer gate and a horizontal transfer gate CCD portion, but may be configured as a CMOS (Complementary Metal Oxide Semiconductor) image sensor instead of a CCD image sensor.

[0106] In addition, in the solid-state imaging device 1, the first pixel region 10 and the second pixel region 20 are arranged in such a manner that their ends in the second direction D2 coincide with each other, so that each of the plurality of first pixel regions 11 and each of the plurality of second pixel regions 21 (the same number as the first pixel region 11) are arranged in the first direction D1. The first pixel region 11 and the second pixel region 21 may be arranged in such a manner that each of the plurality of first pixel regions 11 and each of the plurality of second pixel regions 21 are arranged in parallel in the first direction D1 when the first pixel region 10 and the second pixel region 20 are arranged in such a manner that their ends in the second direction D2 coincide with each other.

[0107] That is, the first pixel region 10 and the second pixel region 20 may be arranged along the first direction D1 with their ends in the second direction D2 offset from each other (moved in the second direction D2). In this case, the first pixel region 11 which is a part of the first pixel region 10 and the second pixel region 21 which is a part of the second pixel region 20 are arranged in a manner that repeats in the first direction. Alternatively, the first pixel region 10 and the second pixel region 20 may not have a portion that repeats in the first direction D1, but may be arranged along the second direction D2.

[0108] In addition, the positional relationship between the first pixel region 10 and the second pixel region 20, the first transfer gate portion 30 and the second transfer gate portion 40, the first horizontal transfer CCD portion 50 and the second horizontal transfer CCD portion 60 is not limited to the above-mentioned form, and can be arbitrarily modified. For example, the respective portions may be arranged in the order of the second pixel region 20, the second transfer gate portion 40, the second horizontal transfer CCD portion 60, the first pixel region 10, the first transfer gate portion 30, and the first horizontal transfer CCD portion 50 from one side toward the other side in the first direction D1.

[0109] In addition, in the solid-state imaging device 1, although the first output section 70 and the second output section 80 may be provided as the output section, only one output section may be provided. Furthermore, a gap other than the element separation section may be formed between the first pixel region 10 and the second pixel region 20, and the first pixel region 10 and the second pixel region 20 may be separated from each other.

[0110] In addition, in the solid-state imaging device 1, the pixel regions are two, namely the first pixel region 10 and the second pixel region 20, but the number of pixel regions is not limited to two, and may be any n. When the number of pixel regions is three or more, the correction for removing the output value caused by WS can be performed more reliably than when the number of pixel regions is two. That is, when the number of pixel regions is three or more, even if WS is generated in the pixel regions at the same position corresponding to each other in two of the pixel regions, the same correction as described above can be performed using the signal from the remaining pixel region.

[0111] In the case where there are more than 2 pixel areas, first, 2 pixel areas are selected from the n pixel areas, and the correction signal S5 is generated or the position of the WS area is extracted in the same manner as described above. Then, the above processing is performed on the combination of all pixel areas. Then, the correction signal S5 or the position information of the WS area obtained from all combinations is combined to complete the correction signal S5 or the position information. In addition, the addition signal S3 of the signals from all pixel areas is replaced with the output value corresponding to the subtraction operation of the correction signal S5 or the position information obtained, and the output signal So is generated.

[0112] Furthermore, the first pixel region 10 and the second pixel region 20 are not limited to the case where the light is incident equally, and light having a known correspondence relationship may be incident separately. As an example, when a beam of light is split and incident on the first pixel region 10 and the second pixel region 20, the light intensity in the first pixel region 10 and the second pixel region 20 becomes a known ratio. Industrial Applicability

[0113] According to the present disclosure, it is possible to provide a solid-state imaging device and a signal processing method that can achieve a longer life.

Explanation of symbols

[0114] 1, 1A, 1B…solid-state imaging device, 5…first light receiving unit, 6…second light receiving unit, 10, 10A, 10B…first pixel region, 11, 11A, 11B…first pixel area, 12, 12A, 12B…first pixel, 20, 20A, 20B…second pixel region, 21, 21A, 21B…second pixel area, 22, 22A, 22B…second pixel, 30…first transfer gate unit, 40…second transfer gate unit, 50…first horizontal transfer CCD unit, 60…second horizontal transfer CCD unit, 70…first output unit (output unit), 80…second output unit, 90…signal processing unit, S1…first signal, S2…second signal, S3…addition signal, S4…subtraction signal, S5…correction signal, So…output signal.

Claims

1. A solid-state imaging device, wherein, comprising: a first light-receiving unit and a second light-receiving unit that generate charges according to the incidence of light; an output unit that outputs a first signal corresponding to the charges generated in the first light-receiving unit and outputs a second signal corresponding to the charges generated in the second light-receiving unit; and a signal processing unit that processes the signals output from the output unit, the first light-receiving unit having: a first pixel region formed by arranging a plurality of first pixel regions, each of which is a pixel region including a plurality of first pixels arranged along a first direction or one first pixel, along a second direction intersecting the first direction; the second light-receiving unit having: a second pixel region formed by arranging a plurality of second pixel regions, each of which is a pixel region including a plurality of second pixels arranged along the first direction or one second pixel, along the second direction; when the first pixel region and the second pixel region are arranged along the first direction such that the ends of the first pixel region and the second pixel region in the second direction coincide, the respective ones of the plurality of first pixel regions are corresponding to the respective ones of the plurality of second pixel regions in a side-by-side manner along the first direction; the signal processing of the signal processing unit includes: an addition operation signal generation process that adds the first signal and the second signal to generate an addition operation signal; a subtraction operation signal generation process that subtracts the second signal from the first signal to generate a subtraction operation signal; and a correction process that corrects and outputs the addition operation signal based on the subtraction operation signal.

2. The solid-state imaging device according to claim 1, wherein, in the correction process, the signal processing unit generates a correction signal based on the subtraction operation signal, and corrects the addition operation signal by subtracting the correction signal from the addition operation signal, in the correction signal, when it is confirmed that a white point region of the pixel region with an output value indicating less than a negative threshold is present, the sign of the output value of the white point region is changed to positive.

3. The solid-state imaging device according to claim 2, wherein, in the correction process, the signal processing unit generates the correction signal in all of the first pixel regions and all of the second pixel regions, and corrects the addition operation signal by subtracting the correction signal from the addition operation signal.

4. The solid-state imaging device according to claim 1, wherein, in the correction process, the signal processing unit generates a correction signal based on the subtraction operation signal, and corrects the addition operation signal by adding the correction signal to the addition operation signal, in the correction signal, when it is confirmed that a white point region of the pixel region with an output value indicating more than a positive threshold is present, the sign of the output value of the white point region is changed to negative.

5. The solid-state imaging device according to claim 4, wherein, in the correction process, the signal processing unit generates the correction signal in all of the first pixel regions and all of the second pixel regions, and corrects the addition operation signal by adding the correction signal to the addition operation signal.

6. The solid-state imaging device according to any one of claims 2 to 5, wherein, in the correction process, the signal processing unit sets the output value of the pixel region that displays the output value between the positive threshold and the negative threshold in the correction signal to 0.

7. The solid-state imaging device according to claim 1, wherein, in the correction process, in the subtraction operation signal, when a white point region of the pixel region that displays an output value exceeding the positive threshold is detected, the output value of the white point region in the addition operation signal is replaced with an output value obtained by doubling the output value of the second pixel region at the position of the white point region of the second signal, and in the subtraction operation signal, when a white point region of the pixel region that displays an output value lower than the negative threshold is detected, the output value of the white point region in the addition operation signal is replaced with an output value obtained by doubling the output value of the first pixel region at the position of the white point region of the first signal.

8. The solid-state imaging device according to any one of claims 1 to 7, wherein, in the subtraction operation signal, when at least one of a white point region of the pixel region that displays an output value exceeding the positive threshold and a white point region of the pixel region that displays an output value lower than the negative threshold is detected, the signal processing unit performs the correction process.

9. The solid-state imaging device according to any one of claims 1 to 8, wherein, it includes: a first transfer gate unit for transferring charges from each of the first pixel regions; a second transfer gate unit for transferring charges from each of the second pixel regions; a first horizontal transfer CCD unit for transferring the charges transferred through the first transfer gate unit to the output unit; and a second horizontal transfer CCD unit for transferring the charges transferred through the second transfer gate unit to the output unit.

10. The solid-state imaging device according to claim 9, wherein, the first pixel region and the second pixel region are arranged in the first direction such that each of the first pixel regions and each of the second pixel regions are arranged side by side along the first direction.

11. The solid-state imaging device according to claim 10, wherein, the first pixel region, the first transfer gate unit, and the first horizontal transfer CCD unit are arranged in sequence on one side facing the first direction, the second pixel region, the second transfer gate unit, and the second horizontal transfer CCD unit are arranged in sequence on the opposite side facing the first direction.

12. The solid-state imaging device according to any one of claims 1 to 11, wherein, the output unit includes: a first output unit for receiving the charges generated in the first light-receiving unit and outputting the first signal; and a second output unit for receiving the charges generated in the second light-receiving unit and outputting the second signal.

13. The solid-state imaging device according to any one of claims 1 to 12, wherein, the first pixel region includes a plurality of first pixels arranged along the first direction, the second pixel region includes a plurality of second pixels arranged along the first direction.

14. The solid-state imaging device according to any one of claims 1 to 13, wherein, the first pixel region and the second pixel region are arranged adjacent to each other.

15. A signal processing method, wherein, it is a signal processing method for a solid-state imaging device, the solid-state imaging device including: a first light-receiving portion and a second light-receiving portion that generate charges according to the incidence of light; and an output portion that outputs a first signal corresponding to the charges generated in the first light-receiving portion and outputs a second signal corresponding to the charges generated in the second light-receiving portion, the signal processing method includes: an addition operation signal generation step of adding the first signal and the second signal to generate an addition operation signal; a subtraction operation signal generation step of subtracting the second signal from the first signal to generate a subtraction operation signal; and a correction step of correcting and outputting the addition operation signal based on the subtraction operation signal, the first light-receiving portion has: a first pixel region formed by arranging a plurality of first pixel regions each of which is a pixel region including a plurality of first pixels arranged along a first direction or one first pixel along a second direction intersecting the first direction; the second light-receiving portion has: a second pixel region formed by arranging a plurality of second pixel regions each of which is a pixel region including a plurality of second pixels arranged along the first direction or one second pixel along the second direction; when the first pixel region and the second pixel region are arranged along the first direction such that the ends in the second direction of the first pixel region and the second pixel region coincide, the respective ones of the plurality of first pixel regions and the respective ones of the plurality of second pixel regions are made to correspond in a manner of being juxtaposed along the first direction.

Images