Scribing method of sapphire substrate and article
Cutting the sapphire substrate by double-light laser beams solves the problem of cutting channels collapse during laser scribing, improves the preparation yield of the light emitting diodes, and achieves more efficient cutting efficiency and flatter cutting channels.
Patent Information
- Application Number
- CN202510144023.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-10
- Publication Date
- 2025-06-13
AI Technical Summary
When preparing light emitting diodes, laser scribing of sapphire substrates is prone to cut-out collapse, resulting in a low yield of the light emitting diodes.
The sapphire substrate is cut using a double-point laser beam. The two light spots are located on the same straight line perpendicular to the substrate. The laser beam is controlled to cut in different directions to form a cutting path with parallel spaces.
Through dual-point laser beam cutting, it is easier to cut the sapphire substrate and the side walls are flattered, which improves cutting efficiency and yield and avoids the increase in cutting defect rate.
Smart Images
Figure CN120133747A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of optoelectronic manufacturing, and particularly to a scribing method and a product of a sapphire substrate. Background Art
[0002] As a highly influential new product in the optoelectronic industry, a light emitting diode (LED for short) has the characteristics of small size, long service life, rich and colorful colors, low energy consumption, etc., and is widely used in fields such as lighting, display screens, signal lights, backlights, toys, etc.
[0003] In the related art, when manufacturing a light emitting diode, an epitaxial layer is first formed on a sapphire substrate. Then, scribing and die separation operations are performed on the sapphire substrate, so as to divide the sapphire substrate together with the epitaxial layer into multiple LED die chips.
[0004] However, when laser scribing the sapphire substrate, the cutting channels are often prone to chipping, resulting in a low yield of the manufactured light emitting diodes. Summary of the Invention
[0005] Embodiments of the present disclosure provide a scribing method and a product of a sapphire substrate, which can improve the problem of chipping of the cutting channels during scribing and improve the manufacturing yield of light emitting diodes. The technical solutions are as follows:
[0006] On the one hand, embodiments of the present disclosure provide a scribing method of a sapphire substrate. The scribing method includes: providing a product, where the product includes a sapphire substrate and an epitaxial layer located on the sapphire substrate; cutting the sapphire substrate by a double-spot laser beam, and two spots of the double-spot laser beam are located on the same straight line perpendicular to the sapphire substrate.
[0007] Optionally, the focal lengths of the two spots of the double-spot laser beam are 25 μm ± 2 μm.
[0008] Optionally, cutting the sapphire substrate by a double-spot laser beam includes: controlling the double-spot laser beam to cut the sapphire substrate along a first direction to form a plurality of parallel and spaced first cutting channels on the sapphire substrate; controlling the double-spot laser beam to cut the sapphire substrate along a second direction to form a plurality of parallel and spaced second cutting channels on the sapphire substrate, and the first direction is perpendicular to the second direction.
[0009] Optionally, the first direction is parallel to the flat edge of the sapphire substrate; when cutting the sapphire substrate along the first direction, the scribing speed of the double-spot laser beam is controlled to be 400 mm / s to 500 mm / s; when cutting the sapphire substrate along the second direction, the scribing speed of the double-spot laser beam is controlled to be 650 mm / s to 750 mm / s.
[0010] Optionally, the ratio of the cutting depth of the double-spot laser beam to the thickness of the product is less than or equal to 0.6.
[0011] An embodiment of the present disclosure provides a product, which is scribed by using the scribing method of the sapphire substrate as described above. The product includes: a sapphire substrate and an epitaxial layer, and the epitaxial layer is located on the surface of the sapphire substrate.
[0012] Optionally, the product further includes a passivation layer, the passivation layer is located on the surface of the sapphire substrate and covers the epitaxial layer. The surface of the passivation layer away from the sapphire substrate has a scribing groove, and the scribing groove is opposite to the first cutting channel or the second cutting channel formed on the surface of the sapphire substrate by the scribing method.
[0013] Optionally, the thickness of the passivation layer is 2.5 μm to 2.7 μm.
[0014] Optionally, the scribing groove exposes the sapphire substrate.
[0015] Optionally, the epitaxial layer includes: a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer. The first semiconductor layer, the multi-quantum well layer, and the second semiconductor layer are sequentially stacked on the sapphire substrate. The second semiconductor layer has a groove exposing the first semiconductor layer; the product further includes: a current blocking layer, a transparent conductive layer, a first electrode, a second electrode, a first pad, and a second pad. The current blocking layer and the transparent conductive layer are both located on the surface of the second semiconductor layer away from the sapphire substrate, and the transparent conductive layer covers the current blocking layer; the first electrode is located in the groove, the second electrode is located on the surface of the transparent conductive layer, the passivation layer covers the epitaxial layer, the transparent conductive layer, the first electrode, and the second electrode, the passivation layer has through holes exposing the first electrode and the second electrode, the first pad and the second pad are both located on the surface of the passivation layer away from the sapphire substrate, and the first pad is connected to the first electrode through a through hole, and the second pad is connected to the second electrode through a through hole.
[0016] The beneficial effects brought by the technical solution provided by the embodiment of the present disclosure at least include:
[0017] The dicing method of the sapphire substrate provided by the embodiments of the present disclosure uses a double-spot laser beam to cut the sapphire substrate. Among them, the two spots of the double-spot laser beam are located on the same straight line perpendicular to the sapphire substrate. When cutting the sapphire substrate with the double-spot laser beam in this way, the two laser beams irradiate vertically downward from the front of the sapphire substrate at the same position of the sapphire substrate. By using the two laser beams to cut the same position simultaneously, it is easier to cut through the sapphire substrate, and the cut sidewalls are smoother. Since the focal points of the two laser beams are different, one of the laser beams can cut to a deeper position on the sapphire substrate. In this way, using the double-laser beam cutting can not only ensure the cutting speed and the flatness of the cut, but also cut out deeper cutting channels as much as possible, which is beneficial to subsequent chip separation.
[0018] Compared with single-spot cutting, double-laser beam cutting can improve the cutting efficiency and reduce the cutting defect rate. Even when the thickness of the product is relatively thick, there will be no problem of slow cutting speed and cutting defects caused by the small energy of a single laser beam. Compared with multi-spot cutting, double-laser beam cutting can reasonably control the depth of the cutting channel, avoiding problems such as appearance defects such as scribing cracks due to excessive depth of the cutting channel. Description of the Drawings
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0020] Figure 1 is a flowchart of a dicing method for a sapphire substrate provided by an embodiment of the present disclosure;
[0021] Figure 2 is a schematic structural diagram of a product provided by an embodiment of the present disclosure;
[0022] Figure 3 is a schematic diagram of cutting a sapphire substrate with a double-spot laser beam provided by an embodiment of the present disclosure;
[0023] Figure 4 is a schematic diagram of the cutting direction of a product provided by an embodiment of the present disclosure.
[0024] The descriptions of the marks in the figure are as follows:
[0025] 10. Sapphire substrate; 11. First cutting channel; 12. Second cutting channel; 13. Flat edge; 1a. First direction; 1b. Second direction;
[0026] 20. Epitaxial layer; 21. First semiconductor layer; 22. Multi-quantum well layer; 23. Second semiconductor layer; 26. Isolation groove;
[0027] 30. Passivation layer; 31. Dicing groove;
[0028] 41. First electrode; 42. Second electrode;
[0029] 51. First pad; 52. Second pad;
[0030] 61. Current blocking layer; 62. Transparent conductive layer. Detailed implementation manners
[0031] To make the objectives, technical solutions, and advantages of the present disclosure clearer, the following will further describe the embodiments of the present disclosure in detail with reference to the accompanying drawings.
[0032] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", "third", and similar terms used in the specification and claims of the present patent application do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, terms such as "a" or "one" do not denote a quantity limitation, but mean that there is at least one. The terms "include" or "comprise" and similar terms mean that the elements or items appearing before "include" or "comprise" cover the elements or items listed after "include" or "comprise" and their equivalents, and do not exclude other elements or items. The terms "connect" or "couple" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", "top", "bottom", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationships may also change accordingly.
[0033] Figure 1 is a flowchart of a dicing method for a sapphire substrate provided by an embodiment of the present disclosure. As Figure 1 shown, the dicing method includes:
[0034] Step S11: Provide an article.
[0035] Figure 2 is a schematic structural diagram of an article provided by an embodiment of the present disclosure. As Figure 2 shown, the article includes a sapphire substrate 10 and an epitaxial layer 20 located on the sapphire substrate 10.
[0036] As Figure 2As shown, the epitaxial layer 20 includes: a first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23. The first semiconductor layer 21, the multi-quantum well layer 22, and the second semiconductor layer 23 are sequentially stacked on the sapphire substrate 10, and the second semiconductor layer 23 has a groove exposing the first semiconductor layer 21.
[0037] Optionally, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.
[0038] Exemplarily, the first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.
[0039] Optionally, the first semiconductor layer 21 is an n-type GaN layer doped with silicon. The thickness of the n-type GaN layer can be 0.5 μm to 3 μm.
[0040] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. Among them, the multi-quantum well layer 22 can include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.
[0041] As an example, in the embodiments of the present disclosure, the multi-quantum well layer 22 includes 5 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.
[0042] Optionally, the thickness of the multi-quantum well layer 22 can be 150 nm to 200 nm.
[0043] Optionally, the second semiconductor layer 23 is a p-type GaN layer doped with magnesium. The thickness of the p-type GaN layer can be 0.5 μm to 3 μm.
[0044] Optionally, as Figure 2 shown, the article may further include: a current blocking layer 61, a transparent conductive layer 62, and a passivation layer 30. The current blocking layer 61 and the transparent conductive layer 62 are both located on the surface of the second semiconductor layer 23 away from the sapphire substrate 10, and the transparent conductive layer 62 covers the current blocking layer 61.
[0045] Exemplarily, the current blocking layer 61 can be a silicon oxide layer. Silicon oxide has good insulation and can effectively block the current in the electrode from vertically downwardly transmitting to the epitaxial layer.
[0046] Exemplarily, the transparent conductive layer 62 can be an indium tin oxide (ITO) layer or an indium zinc oxide (IZO) layer.
[0047] Both the ITO layer and the IZO layer have good transmittance and low resistivity. Using the ITO layer or the IZO layer as the transparent conductive layer 62 allows more light to transmit through the transparent conductive layer 62, thus ensuring the light output effect. At the same time, due to the low resistivity, it is also convenient for carrier conduction and improves the injection efficiency.
[0048] As an example, the thickness of the transparent conductive layer 62 can be from 1000 angstroms to 5000 angstroms. For example, the thickness of the transparent conductive layer 62 is 2000 angstroms.
[0049] As Figure 2 shown, the article further includes a first electrode 41, a second electrode 42, a first pad 51 and a second pad 52. The first electrode 41 is located in the groove, the second electrode 42 is located on the surface of the transparent conductive layer 62, the passivation layer 30 covers the epitaxial layer, the transparent conductive layer 62, the first electrode 41 and the second electrode 42. The passivation layer 30 has through holes exposing the first electrode 41 and the second electrode 42. The first pad 51 and the second pad 52 are both located on the surface of the passivation layer 30 away from the sapphire substrate 10. The first pad 51 is connected to the first electrode 41 through a through hole, and the second pad 52 is connected to the second electrode 42 through a through hole.
[0050] Among them, the first pad 51 and the second pad 52 are used to connect to an external power supply so that current can be transmitted to the electrodes through the pads and then transmitted to different semiconductor layers through different electrodes.
[0051] Exemplarily, the passivation layer 30 can be a Distributed Bragg Reflection (DBR layer for short). The DBR layer includes multiple periodically alternating stacked SiO 2 layers and TiO 2 layers. And the number of periods of the DBR layer can be between 20 and 50. For example, the number of periods of the DBR layer is 32.
[0052] Among them, the thickness of the SiO 2 layer in the DBR layer can be 800 angstroms to 1200 angstroms, and the thickness of the TiO 2 layer can be 500 angstroms to 900 angstroms.
[0053] In addition to the passivation function, the DBR layer is also used to reflect the light emitted from the multi-quantum well layer 22 to the sapphire substrate 10 to improve the light output effect.
[0054] Optionally, the process of preparing the article may include the following steps:
[0055] First step, pre-treat the sapphire substrate 10. Place the sapphire substrate 10 in an MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and bake the sapphire substrate 10 for 12 to 18 minutes.
[0056] As an example, in the embodiments of the present disclosure, the sapphire substrate 10 is baked for 15 minutes.
[0057] Specifically, the baking temperature can be 1000°C to 1200°C, and the pressure in the MOCVD reaction chamber during baking can be 100 mbar to 200 mbar.
[0058] Second step, sequentially form a first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23 on the sapphire substrate 10 through MOCVD technology.
[0059] Exemplarily, the first semiconductor layer 21 is an n-type GaN layer, and the second semiconductor layer 23 is a p-type GaN layer.
[0060] Optionally, the thickness of the n-type GaN layer can be 0.5 μm to 3 μm.
[0061] The growth temperature of the n-type GaN layer can be 1000°C to 1100°C, and the growth pressure of the n-type GaN layer can be 100 torr to 300 torr.
[0062] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. Among them, the multi-quantum well layer 22 can include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.
[0063] When growing the multi-quantum well layer 22, the pressure in the MOCVD reaction chamber is controlled at 200 torr. When growing the InGaN quantum well layer, the reaction chamber temperature is 760°C to 780°C. When growing the GaN quantum barrier layer, the reaction chamber temperature is 860°C to 890°C.
[0064] As an example, in the embodiments of the present disclosure, the multi-quantum well layer 22 includes 5 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.
[0065] Optionally, the thickness of the multi-quantum well layer 22 can be 150 nm to 200 nm.
[0066] Optionally, the thickness of the p-type GaN layer can be 0.5 μm to 3 μm.
[0067] When growing the p-type GaN layer, the growth pressure of the p-type GaN layer can be from 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer can be from 800 °C to 1000 °C.
[0068] In the third step, the second semiconductor layer 23 is etched to form a groove on the surface of the second semiconductor layer 23 away from the sapphire substrate 10.
[0069] Among them, the groove etching can be achieved by dry etching, or by lithography combined with wet etching, such as H 3 PO 4 / H 2 SO 4 etching with a mixed solution, or by laser front scribing.
[0070] In the fourth step, the second semiconductor layer 23 is etched to form isolation grooves 26 exposing the sapphire substrate 10, and the isolation grooves 26 divide the epitaxial layer into multiple spaced-apart light-emitting structures.
[0071] Among them, the isolation grooves can be etched by dry etching, or by lithography combined with wet etching, such as H 3 PO 4 / H 2 SO 4 etching with a mixed solution, or by laser front scribing.
[0072] In the embodiments of the present disclosure, in the subsequent die separation process, the product needs to be split along the position where the isolation grooves are located to form multiple die chips. Therefore, the isolation grooves are provided to avoid damaging the light-emitting structures of the die chips when splitting the product.
[0073] At the same time, in the subsequent process, the position where the isolation grooves are located is opposite to the scribe lines formed in the scribing process, which can also avoid damage to the epitaxial layer caused by laser irradiation during the scribing process.
[0074] In the fifth step, a current blocking layer 61 is formed on the surface of the second semiconductor layer 23, and a transparent conductive layer 62 is formed on the surface of the second semiconductor layer 23 and the surface of the current blocking layer 61.
[0075] Exemplarily, the current blocking layer 61 is a silicon oxide layer. Silicon oxide has good insulation properties and can effectively block the vertical downward transmission of current in the electrode to the epitaxial layer.
[0076] Exemplarily, the transparent conductive layer 62 is an indium tin oxide layer or an indium zinc oxide layer.
[0077] Exemplarily, the thickness of the transparent conductive layer 62 can be from 1000 Å to 5000 Å. For example, the thickness of the transparent conductive layer 62 is 2000 Å.
[0078] Step 6: Fabricate the first electrode 41 in the groove such that the first electrode 41 is connected to the first semiconductor layer 21. Fabricate the second electrode 42 on the surface of the transparent conductive layer 62 such that the second electrode 42 is connected to the transparent conductive layer 62.
[0079] Step 7: Form a passivation layer 30 on the surface of the second semiconductor layer 23, on the surface of the transparent conductive layer 62, on the surface of the first electrode 41, on the surface of the second electrode 42, and in the groove.
[0080] Among them, the passivation layer 30 can be a DBR layer, and the DBR layer includes a plurality of periodically alternating stacked SiO 2 layers and TiO 2 layers. And the number of periods of the DBR layer can be between 20 and 50. For example, the number of periods of the DBR layer is 32.
[0081] Among them, the thickness of the SiO 2 layer in the DBR layer can be 800 Å to 1200 Å, and the thickness of the TiO 2 layer can be 500 Å to 900 Å.
[0082] After forming the passivation layer 30, two through holes need to be etched on the surface of the passivation layer 30.
[0083] One of the through holes exposes the first electrode 41, and the other through hole exposes the second electrode 42.
[0084] Step 8: Fabricate the first pad 51 and the second pad 52 on the surface of the passivation layer 30.
[0085] Among them, the first pad 51 is connected to the first electrode 41 through one through hole, and the second pad 52 is connected to the second electrode 42 through the other through hole.
[0086] Exemplarily, both the first pad 51 and the second pad 52 can be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked in sequence.
[0087] In the embodiments of the present disclosure, after fabricating the pads, the fabrication method may further include: fabricating a protective layer on the surface of the passivation layer 30.
[0088] Exemplarily, in the embodiments of the present disclosure, the protective layer can be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 Å.
[0089] It should be noted that after growing the protective layer on the surface of the passivation layer 30, photolithography technology can be used to etch through holes exposing the pads on the surface of the protective layer for convenient electrical connection.
[0090] Step S12: Cut the sapphire substrate 10 by a two-spot laser beam.
[0091] Figure 3 It is a schematic diagram of a double-spot laser beam for cutting a sapphire substrate 10 provided by an embodiment of the present disclosure. As Figure 3 shown, the two spots (X, Y) of the double-spot laser beam are located on the same straight line perpendicular to the sapphire substrate 10.
[0092] Optionally, as Figure 3 shown, the focal lengths L of the two spots X and Y of the double-spot laser beam are 25 μm ± 2 μm.
[0093] By controlling the focal lengths of the two spots of the double-spot laser beam within the above range, the depth of the cutting track is controlled within a suitable range, which can avoid the cutting track being too deep, resulting in the focus of the laser beam being too close to the surface where the pad is located and losing the electrical yield of the product; and it can also avoid the cutting track being too shallow and the situation where the product cannot be cut.
[0094] Exemplarily, the focal lengths of the two spots of the double-spot laser beam are 25 μm.
[0095] Step S12 may specifically include the following steps:
[0096] First, control the double-spot laser beam to cut the sapphire substrate 10 along the first direction 1a, and form a plurality of parallel and spaced first cutting tracks 11 on the sapphire substrate 10.
[0097] Figure 4 It is a schematic diagram of the cutting direction of a product provided by an embodiment of the present disclosure. As Figure 4 shown, the sapphire substrate 10 is non-circular, and a part of the side of the sapphire substrate 10 is a flat edge 13, so as to facilitate positioning when the manipulator grabs the product, and make the flat edges 13 of each product face the same side.
[0098] Among them, the cross-section parallel to the flat edge 13 on the sapphire substrate 10 is a non-inclined fracture surface, and the cross-section with an angle to the direction of the flat edge 13 on the sapphire substrate 10 is an inclined fracture surface.
[0099] Optionally, as Figure 4 shown, the first direction 1a is parallel to the flat edge 13 of the sapphire substrate 10.
[0100] Optionally, when cutting the sapphire substrate 10 along the first direction 1a, control the scribing speed of the double-spot laser beam to be 400 mm / s to 500 mm / s.
[0101] Exemplarily, when cutting the sapphire substrate 10 along the first direction 1a, control the scribing speed of the double-spot laser beam to be 440 mm / s.
[0102] Since the difficulty of cutting non-oblique cleavage planes is higher than that of oblique cleavage planes, when controlling the double-spot laser beam to cut the sapphire substrate 10 along the first direction 1a, the double-spot laser beam should be controlled to scribe at a slower speed to ensure the cutting quality.
[0103] Then, control the double-spot laser beam to cut the sapphire substrate 10 along the second direction 1b to form a plurality of parallel and spaced second cutting channels 12 on the sapphire substrate 10.
[0104] As Figure 4 shown, the first direction 1a is perpendicular to the second direction 1b.
[0105] Optionally, when cutting the sapphire substrate 10 along the second direction 1b, control the scribing speed of the double-spot laser beam to be 650 mm / s to 750 mm / s.
[0106] Exemplarily, when cutting the sapphire substrate 10 along the second direction 1b, control the scribing speed of the double-spot laser beam to be 700 mm / s.
[0107] Since the difficulty of cutting oblique cleavage planes is lower than that of non-oblique cleavage planes, when controlling the double-spot laser beam to cut the sapphire substrate 10 along the second direction 1b, the double-spot laser beam can be controlled to scribe at a faster speed to improve the efficiency of cutting the sapphire substrate 10.
[0108] Optionally, as Figure 3 shown, the ratio of the cutting depth H of the double-spot laser beam to the thickness of the product is less than or equal to 0.6.
[0109] Exemplarily, the thickness of the product is 120 μm to 140 μm.
[0110] As an example, as Figure 3 shown, when the ratio of the cutting depth of the double-spot laser beam to the thickness of the product is 0.5, and the focal length of the double-spot laser beam is 25 μm and the thickness of the product is 120 μm, the cutting depth h of the laser beam with the closest focus to the surface of the sapphire substrate 10 in the double-spot laser beam can be determined to be 120×0.5 - 25 = 35 μm.
[0111] By controlling the ratio of the cutting depth of the double-spot laser beam to the thickness of the product within the above range, the depth of the cutting channel is controlled within a suitable range, which can avoid the cutting channel being too deep and causing the focus of the laser beam to be too close to the surface where the pad is located, resulting in loss of the electrical yield of the product; and it can also avoid the cutting channel being too shallow and the situation where the product cannot be scribed.
[0112] Finally, operations such as cleaving the sapphire substrate 10, AOI back inspection, and reverse film and film expansion can be performed to obtain light-emitting diodes.
[0113] The dicing method of the sapphire substrate 10 provided by the embodiments of the present disclosure uses a double-spot laser beam to cut the sapphire substrate 10. Among them, the two spots of the double-spot laser beam are located on the same straight line perpendicular to the sapphire substrate 10. In this way, when using the double-spot laser beam to cut the sapphire substrate 10, the two laser beams irradiate vertically downward from the front of the sapphire substrate 10 at the same position of the sapphire substrate 10, and the two laser beams are used to cut the same position simultaneously, which can more easily cut the sapphire substrate 10, and the cut side wall is smoother. Since the focal points of the two laser beams are different, one of the laser beams can cut to a deeper position on the sapphire substrate 10. In this way, using the double-laser beam cutting can not only ensure the cutting speed and the flatness of the cut, but also cut out deeper cutting channels as much as possible, which is beneficial to subsequent chip separation.
[0114] Compared with single-spot cutting, double-laser beam cutting can improve the cutting efficiency and reduce the cutting defect rate. Even when the thickness of the product is relatively thick, there will be no problem of slow cutting speed and cutting defects caused by the small energy of a single laser beam. Compared with multi-spot cutting, double-laser beam cutting can reasonably control the depth of the cutting channel, avoid the problem of excessive cutting channel depth and appearance defects such as scribe cracking.
[0115] In the sapphire substrate 10 cut by the above dicing method, three chips are taken from each of the five points of the upper, middle, lower, left, and right of the product to observe the chip chipping situation, and through AOI inspection and electrical testing, the influence of the introduction of the double-spot process on the product appearance and electrical yield is verified.
[0116] According to the comparison, before using the dicing method provided by the present disclosure, the chipping phenomenon at the chip scribe was serious, showing a serrated and club-shaped abnormality; after using the dicing method provided by the present disclosure, the chip appearance was good, without club-shaped and serrated chipping, and by comparing the appearance and electrical yield of the wafer sources after the two processes were processed, it was found that the introduction of the double-spot process significantly improved the appearance yield of the chips and had no obvious influence on their electrical properties.
[0117] The embodiments of the present disclosure provide a product. The product is diced by using the dicing method of the sapphire substrate 10 as described above. As Figure 2 shown, the product includes: a sapphire substrate 10 and an epitaxial layer 20, and the epitaxial layer 20 is located on the surface of the sapphire substrate 10.
[0118] Optionally, as Figure 2 shown, the product further includes a passivation layer 30. The passivation layer 30 is located on the surface of the sapphire substrate 10, and the passivation layer 30 covers the epitaxial layer 20. The surface of the passivation layer 30 away from the sapphire substrate 10 has a dicing groove 31, and the dicing groove 31 is opposite to the first cutting channel 11 or the second cutting channel 12 formed on the surface of the sapphire substrate 10 by the dicing method.
[0119] Exemplarily, the passivation layer 30 may be a DBR layer, and the DBR layer includes a plurality of periodically alternating stacked SiO 2 layers and TiO 2 layers. And the number of periods of the DBR layer may be between 20 and 50. For example, the number of periods of the DBR layer is 32.
[0120] Among them, the thickness of the SiO 2 layer in the DBR layer may be 800 Å to 1200 Å, and the thickness of the TiO 2 layer may be 500 Å to 900 Å.
[0121] In addition to having a passivation effect, the DBR layer is also used to reflect the light emitted from the multiple quantum well layer 22 to the sapphire substrate 10, improving the light extraction effect.
[0122] Since the DBR layer has many layers and a relatively thick thickness, it is difficult to cut with a laser. Therefore, a dicing groove 31 is provided to thin the thickness of the DBR layer, so as to quickly cut the product and improve the dicing efficiency.
[0123] Optionally, the dicing groove 31 exposes the epitaxial layer 20. In this way, the DBR layer is completely etched away by the dicing groove 31 at the corresponding place of the cutting channel, avoiding laser cutting of the DBR layer, reducing the laser cutting difficulty, and being beneficial to improving the dicing speed.
[0124] Optionally, as Figure 2 shown, the epitaxial layer 20 includes: a first semiconductor layer 21, a multiple quantum well layer 22, and a second semiconductor layer 23. The first semiconductor layer 21, the multiple quantum well layer 22, and the second semiconductor layer 23 are sequentially stacked on the sapphire substrate 10, and the second semiconductor layer 23 has a groove exposing the first semiconductor layer 21.
[0125] Optionally, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.
[0126] Exemplarily, the first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.
[0127] Optionally, the first semiconductor layer 21 is an n-type GaN layer doped with silicon. The thickness of the n-type GaN layer may be 0.5 μm to 3 μm.
[0128] Optionally, the multiple quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. Among them, the multiple quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.
[0129] As an example, in the embodiments of the present disclosure, the multi-quantum well layer 22 includes 5 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.
[0130] Optionally, the thickness of the multi-quantum well layer 22 can be 150 nm to 200 nm.
[0131] Optionally, the second semiconductor layer 23 is a p-type GaN layer doped with magnesium. The thickness of the p-type GaN layer can be 0.5 μm to 3 μm.
[0132] As Figure 2 shown, the article further includes a current blocking layer 61 and a transparent conductive layer 62. Both the current blocking layer 61 and the transparent conductive layer 62 are located on the surface of the second semiconductor layer 23 away from the sapphire substrate 10, and the transparent conductive layer 62 covers the current blocking layer 61.
[0133] Exemplarily, the current blocking layer 61 can be a silicon oxide layer. Silicon oxide has good insulation and can effectively block the vertical downward transfer of current in the electrode to the epitaxial layer.
[0134] Exemplarily, the transparent conductive layer 62 can be an ITO layer or an IZO layer.
[0135] As an example, the thickness of the transparent conductive layer 62 can be 1000 Å to 5000 Å. For example, the thickness of the transparent conductive layer 62 is 2000 Å.
[0136] As Figure 2 shown, the article further includes a first electrode 41, a second electrode 42, a first pad 51 and a second pad 52. The first electrode 41 is located in the groove, the second electrode 42 is located on the surface of the transparent conductive layer 62, the passivation layer 30 covers the epitaxial layer, the transparent conductive layer 62, the first electrode 41 and the second electrode 42. The passivation layer 30 has through holes exposing the first electrode 41 and the second electrode 42. Both the first pad 51 and the second pad 52 are located on the surface of the passivation layer 30 away from the sapphire substrate 10. The first pad 51 is connected to the first electrode 41 through a through hole, and the second pad 52 is connected to the second electrode 42 through a through hole.
[0137] Among them, the first pad 51 and the second pad 52 are used to connect to an external power supply so that current can be transmitted to the electrodes through the pads and then transmitted to different semiconductor layers through different electrodes.
[0138] Exemplarily, both the first electrode 41 and the second electrode 42 can include multiple stacked metal layers. The metal layers include a Ti layer, an Al layer, a Pt layer, a Ni layer and an Au layer.
[0139] Among them, setting the metal Ti in the electrode can improve the strength of the electrode; setting the metals Al and Pt in the electrode can improve the corrosion resistance of the electrode; setting the metal Ni in the electrode can increase the melting point of the electrode; setting the metal Au in the electrode can make the electrode better resistant to erosion.
[0140] Exemplarily, the electrode includes a Ti layer, an Al layer, a Pt layer, a Ni layer, and an Au layer stacked in sequence.
[0141] Optionally, the thickness of the electrode is 0.1 μm to 3 μm.
[0142] Exemplarily, the thickness of the Ti layer is 2 μm; the thickness of the Al layer is 1 μm; the thickness of the Pt layer is 0.5 μm; the thickness of the Ni layer is 1.2 μm; the thickness of the Au layer is 1.5 μm.
[0143] Exemplarily, both the first pad 51 and the second pad 52 can be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked in sequence.
[0144] The above are only optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.
Claims
1. A sapphire substrate scribing method, characterized in that: The dicing method comprises: A product is provided, the product comprising a sapphire substrate (10) and an epitaxial layer (20) located on the sapphire substrate (10); The sapphire substrate (10) is cut by a double-spot laser beam, wherein two light spots of the double-spot laser beam are located on the same straight line perpendicular to the sapphire substrate (10).
2. The dicing method according to claim 1, characterized in that: The focal lengths of the two spots of the dual-spot laser beam are 25 μm±2 μm.
3. The dicing method according to claim 1 or 2, characterized in that: Cutting the sapphire substrate (10) by a dual-spot laser beam comprises: Controlling the dual-spot laser beam to cut the sapphire substrate (10) along a first direction (1a), thereby forming a plurality of parallel and spaced first cutting paths (11) on the sapphire substrate (10); The dual-spot laser beam is controlled to cut the sapphire substrate (10) along a second direction (1b) to form a plurality of parallel and spaced second cutting paths (12) on the sapphire substrate (10), wherein the first direction (1a) is perpendicular to the second direction (1b).
4. The dicing method according to claim 3, characterized in that: The first direction (1a) is parallel to the flat edge (13) of the sapphire substrate (10); When cutting the sapphire substrate (10) along the first direction (1a), controlling the scribing speed of the double-spot laser beam to be 400 mm / s to 500 mm / s; When the sapphire substrate (10) is cut along the second direction (1b), the scribing speed of the dual-spot laser beam is controlled to be 650 mm / s to 750 mm / s.
5. The dicing method according to claim 1 or 2, characterized in that: The ratio of the cutting depth of the dual-spot laser beam to the thickness of the product is less than or equal to 0.
6.
6. A product, characterized in that: The product is diced using the sapphire substrate dicing method according to any one of claims 1 to 5, and comprises: a sapphire substrate (10) and an epitaxial layer (20), wherein the epitaxial layer (20) is located on the surface of the sapphire substrate (10).
7. The product according to claim 6, characterized in that The product also includes a passivation layer (30), which is located on the surface of the sapphire substrate (10) and covers the epitaxial layer (20), and the surface of the passivation layer (30) away from the sapphire substrate (10) has a scribe groove (31), and the scribe groove (31) is opposite to the first cutting path (11) or the second cutting path (12) formed on the surface of the sapphire substrate (10) by the scribe method.
8. The product according to claim 7, characterized in that The thickness of the passivation layer (30) is 2.5 μm to 2.7 μm.
9. The product according to claim 7, characterized in that The scribe line (31) exposes the sapphire substrate (10).
10. The product according to claim 7, characterized in that The epitaxial layer (20) comprises: a first semiconductor layer (21), a multi-quantum well layer (22) and a second semiconductor layer (23), wherein the first semiconductor layer (21), the multi-quantum well layer (22) and the second semiconductor layer (23) are sequentially stacked on the sapphire substrate (10), and the second semiconductor layer (23) has a groove exposing the first semiconductor layer (21); The product further comprises: a current blocking layer (61), a transparent conductive layer (62), a first electrode (41), a second electrode (42), a first pad (51), and a second pad (52), wherein the current blocking layer (61) and the transparent conductive layer (62) are both located on a surface of the second semiconductor layer (23) away from the sapphire substrate (10), and the transparent conductive layer (62) covers the current blocking layer (61); The first electrode (41) is located in the groove, the second electrode (42) is located on the surface of the transparent conductive layer (62), the passivation layer (30) covers the epitaxial layer (20), the transparent conductive layer (62), the first electrode (41) and the second electrode (42), the passivation layer (30) has a through hole exposing the first electrode (41) and the second electrode (42), the first pad (51) and the second pad (52) are both located on the surface of the passivation layer (30) away from the sapphire substrate (10), the first pad (51) is connected to the first electrode (41) through the through hole, and the second pad (52) is connected to the second electrode (42) through the through hole.