Circuit board quality detection method, device, equipment and medium

Abstract

The invention relates to a circuit board quality detection method and device, equipment and a medium, and the method comprises the steps: obtaining a detection task, and determining a corresponding to-be-determined detection node according to the detection task; acquiring circuit board detection information, splitting the circuit board detection information into a plurality of pieces of detection sub-information, and storing each piece of detection sub-information into a distributed file system; based on a task scheduling system, determining a corresponding target detection node; calling each piece of detection sub-information from the distributed file system, respectively distributing the detection sub-information to a corresponding target detection node for processing so as to generate a corresponding node detection result, summarizing each node detection result to the distributed file system, and sending a corresponding summarized packet to a central processing node through the distributed file system; the distributed system ensures that each subtask can be processed in parallel on different nodes, so that the reduction of detection precision caused by overweight load of a single node is avoided, and the accuracy and reliability of overall detection are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board quality inspection, and particularly to a circuit board quality inspection method, device, equipment and medium. Background Art

[0002] At present, traditional circuit board quality inspection methods mainly rely on AOI (Automated Optical Inspection) and AXI (Automated X-ray Inspection) technologies to detect external and internal defects of circuit boards respectively. AOI captures images through a camera to identify solder joints and surface defects, while AXI uses X-ray fluoroscopy imaging to detect internal welding conditions. Although these methods can meet the basic quality inspection requirements, with the rapid development of the electronic manufacturing industry, these inspection technologies are facing problems such as low efficiency, incomplete inspection, and increased system complexity. Especially when facing complex multi-layer boards and small components, the existing inspection methods are difficult to ensure inspection accuracy. Summary of the Invention

[0003] In order to solve the problems of low efficiency, incomplete inspection, and increased system complexity in traditional circuit board quality inspection methods, the present application provides a circuit board quality inspection method, device, equipment and medium.

[0004] The first invention object of the present application is achieved through the following technical solutions: A circuit board quality inspection method, the circuit board quality inspection method includes: Obtain an inspection task, and determine corresponding to-be-determined inspection nodes according to the inspection task; Obtain circuit board inspection information at least based on AOI inspection technology and / or AXI inspection technology, where the circuit board inspection information at least includes external image information and internal sensing information; Split the circuit board inspection information to generate multiple inspection sub-information, and store each inspection sub-information in a distributed file system; Based on a task scheduling system, determine a first balance value of each to-be-determined inspection node, and determine a corresponding target inspection node according to the first balance value; Call out each inspection sub-information from the distributed file system, and respectively allocate them to corresponding target inspection nodes for processing to generate corresponding node inspection results, summarize each node inspection result in the distributed file system, and send a corresponding summary packet to a central processing node through the distributed file system; The central processing node integrates each node inspection result to generate a final inspection report, and performs visual push display based on a visualization tool.

[0005] By adopting the above technical solutions, the combination of high-resolution AOI detection technology and in-depth structure AXI detection technology can perform detailed quality inspections on tiny components and multi-layer structures, greatly improving the detection accuracy and ensuring the comprehensiveness of the detection. Moreover, the detection information is split into sub-information and processed distributively, enabling the system to specifically process a part of the defect information for each detection node, thereby covering the defect types in different regions and layers on the circuit board and further enhancing the comprehensiveness of the detection. Through the task scheduling system and the equilibrium value calculation, the system can automatically manage and allocate the tasks of each detection node, avoiding human intervention and operational complexity. The system automatically selects the optimal node to perform the detection task, reducing the operational complexity among multiple devices and multiple systems. The distributed system ensures that each sub-task can be processed in parallel on different nodes, preventing the decline in detection accuracy caused by overloading a single node. Each node focuses on a specific task, improving the overall detection accuracy and reliability.

[0006] In a preferred example of the present application, it can be further configured that: the step of determining the corresponding to-be-determined detection node according to the detection task includes: Decompose the detection task to generate corresponding sub-tasks; Determine the detection area of the circuit board according to the sub-tasks; Extract the key features of the detection area; Match the corresponding to-be-determined detection node according to the key features, where different to-be-determined detection nodes correspond to different computing resources, and the computing resources include AOI computing resources for processing different external defects on the circuit board and AXI computing resources for processing different internal defects on the circuit board.

[0007] By adopting the above technical solutions, decomposing the detection task into sub-tasks and determining the detection area of the circuit board according to these sub-tasks can perform refined inspections on different regions, thereby improving the pertinence and accuracy of the detection. Extracting the key features of the detection area and matching the to-be-determined detection nodes based on these key features can allocate different detection resources according to the specific requirements of the detection area, thereby optimizing the utilization of computing resources. By distinguishing the AOI computing resources for processing external defects and the AXI computing resources for processing internal defects, various detection technologies can be utilized more effectively to process different types of defects respectively, further improving the detection accuracy and efficiency.

[0008] In a preferred example of the present application, it can be further configured that: the step of determining the first equilibrium value of each to-be-determined detection node based on the task scheduling system includes: Obtain the thread tasks and resource running statuses of each to-be-determined detection node, where the resource running status is generated according to the feedback information of the verification task, and the resource running status includes a normal status, a pending status, and an abnormal status; Determine the current availability weight coefficient of each detection node according to the resource running status, where the availability weight coefficient of the normal status is the highest, the availability weight coefficient of the pending status is medium, and the availability weight coefficient of the abnormal status is the lowest; Determine the task load coefficient of each detection node according to the thread task, where the task load coefficient is generated based on the load metrics generated from the execution quantity, task complexity, and completion rate of the thread task; Calculate the first balance value corresponding to each detection node according to the resource availability coefficient and the task load coefficient.

[0009] By adopting the above technical solution, obtaining the thread tasks and resource running statuses of the to-be-determined detection nodes can accurately understand the actual running situation of each node, thereby optimizing the distribution of detection tasks. Generating the availability weight coefficient according to the resource running status can flexibly adjust the task distribution according to the health status of the nodes, improving the adaptability and stability of the system. Generating the task load coefficient according to the thread task can evaluate the workload of each node in real time, ensure the balance of task distribution, and avoid overloading or resource waste. Finally, by calculating the resource availability coefficient and the task load coefficient to generate the first balance value, the task distribution of the nodes can be comprehensively optimized, further improving the overall performance and response speed of the system.

[0010] In a preferred example of the present application, it can be further configured as follows: In the step of calling out each detection sub-information from the distributed file system, respectively allocating it to the corresponding target detection node for processing to generate the corresponding node detection result, summarizing each node detection result to the distributed file system, and sending the corresponding summary packet to the central processing node through the distributed file system, it includes: Based on the task scheduling system, obtain the storage identifier of the distributed file system; According to the storage identifier, match the corresponding target detection node, and call the detection sub-information corresponding to the storage identifier to the target detection node; Mark the start time of the detection cycle. When the target detection node generates the node detection result and returns it to the distributed file system, mark the end time of the detection cycle. According to the start time and the end time of the detection cycle, determine the thread task of the target detection node to be used to determine the second balance value of the target detection node; Determine the preset number of tags for the summary package. When the actual number of tags at the end time of the detection cycle is greater than the preset number of tags, send the corresponding summary package to the central processing node through the distributed file system.

[0011] By adopting the above technical solution, calling the detection sub-information from the distributed file system and allocating it to the corresponding target detection nodes can realize the automatic allocation of data and the dynamic adjustment of tasks, thereby improving the flexibility of task processing and the efficiency of data transmission. By storing the identification to match the target detection node, it can ensure that the detection sub-information is accurately allocated to the appropriate node and optimize the utilization rate of computing resources. Marking the start and end times of the detection cycle can accurately calculate the execution efficiency of each detection node, evaluate its performance, and ensure that the system monitors in real time and dynamically adjusts the node load. Calculating the thread tasks according to the detection cycle and determining the second balance value can optimize the task allocation among nodes and further improve the overall detection efficiency of the system.

[0012] In a preferred example of the present application, it can be further configured as follows: After the step of determining the preset number of tags for the summary package and sending the corresponding summary package to the central processing node through the distributed file system when the actual number of tags at the end time of the detection cycle is greater than the preset number of tags, it further includes: When new circuit board detection information is obtained, based on the task scheduling system, compare the first balance value and the second balance value to determine a new target detection node.

[0013] By adopting the above technical solution, when new circuit board detection information is obtained, comparing the first balance value and the second balance value based on the task scheduling system can flexibly adjust the new task allocation scheme by comparing the historical task load and the current node status, thereby improving the self-adaptability and real-time response ability of the system. By dynamically adjusting the new target detection node, it can ensure that the system can still operate efficiently under changing task requirements, further optimize the execution efficiency of the detection task, and avoid situations such as node overload or insufficient resource utilization.

[0014] In a preferred example of the present application, it can be further configured as follows: In the step of allocating it to the corresponding target detection node for processing to generate the corresponding node detection result, it includes: Judge whether the actual calculation amount of the detection sub-information is greater than the determined preset calculation amount; If not, then based on the trained key detection sub-algorithm model, generate the corresponding node detection result according to the detection sub-information; If so, determine the trained key detection sub-algorithm model, based on the distributed mode of the deep learning framework, disassemble the calculation task of the detection sub-information, and allocate the calculation task to the trained redundant detection sub-algorithm model; Summarize all the partial calculation results generated based on the trained redundant detection sub - algorithm models to the trained key detection sub - algorithm model, and generate corresponding node detection results according to the trained key detection sub - algorithm model.

[0015] By adopting the above - mentioned technical solution, it is possible to determine whether the actual calculation amount of the detection sub - information is greater than the pre - designed calculation amount, dynamically adjust the complexity of the calculation task according to the actual calculation requirements, and ensure the rationality of resource allocation and the accuracy of the detection task. If the calculation amount of the detection sub - information is small, the node detection results can be directly generated based on the trained key detection sub - algorithm model, which can simplify the calculation process and improve the processing efficiency. If the calculation amount of the detection sub - information is large, the calculation task is disassembled through the distributed mode of the deep - learning framework and allocated to the redundant detection sub - algorithm models, which can make full use of the advantages of distributed computing, balance the task loads of different nodes, and ensure the efficient execution of complex calculation tasks. Finally, summarizing the partial calculation results and generating the node detection results can improve the processing efficiency of large - scale calculation tasks and ensure the accuracy and comprehensiveness of the detection results.

[0016] The second invention object of the present application is achieved through the following technical solutions: The first acquisition module is used to acquire a detection task and determine corresponding detection nodes to be determined according to the detection task; The second acquisition module is used to acquire circuit board detection information at least based on AOI detection technology and / or AXI detection technology, and the circuit board detection information at least includes external image information and internal sensing information; The splitting module is used to split the circuit board detection information into multiple detection sub - information and store each detection sub - information in a distributed file system; The determination module is used to determine the first balance value of each detection node to be determined based on a task scheduling system, and determine the corresponding target detection node according to the first balance value; The first generation module is used to call out each detection sub - information from the distributed file system, respectively allocate it to the corresponding target detection nodes for processing to generate corresponding node detection results, summarize each node detection result to the distributed file system, and send a corresponding summary packet to the central processing node through the distributed file system; The second generation module is used for the central processing node to integrate each node detection result, generate a final detection report, and perform visual push display based on a visualization tool.

[0017] The third object of the present application is achieved through the following technical solutions: A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the above-mentioned method for detecting the quality of a circuit board are implemented.

[0018] The above-mentioned fourth object of the present application is achieved by the following technical solutions: A computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the steps of the above-mentioned method for detecting the quality of a circuit board are implemented.

[0019] In summary, the present application includes at least one of the following beneficial technical effects: Through the combination of high-resolution AOI detection technology and in-depth structure AXI detection technology, the present application can perform detailed quality detection on micro-components and multi-layer structures, greatly improving the detection accuracy and ensuring the comprehensiveness of detection. Moreover, the detection information is split into sub-information and processed distributively, enabling the system to specifically process a certain part of the defect information for each detection node, thereby covering the defect types in different regions and layers of the circuit board and further improving the comprehensiveness of detection. Through the task scheduling system and equilibrium value calculation, the system can automatically manage and allocate tasks for each detection node, avoiding human intervention and operation complexity. The system automatically selects the best node to perform the detection task, reducing the operation complexity between multiple devices and multiple systems. The distributed system ensures that each subtask can be processed in parallel on different nodes, avoiding a decrease in detection accuracy caused by overloading a single node. Each node focuses on a specific task, improving the overall detection accuracy and reliability. Description of the Drawings

[0020] Figure 1 is a flowchart of a method for detecting the quality of a circuit board in an embodiment of the present application.

[0021] Figure 2 is a flowchart for implementing step S10 in a method for detecting the quality of a circuit board in an embodiment of the present application; Figure 3 is a flowchart for implementing step S40 in a method for detecting the quality of a circuit board in an embodiment of the present application; Figure 4 is a flowchart for implementing step S50 in a method for detecting the quality of a circuit board in an embodiment of the present application; Figure 5 is another flowchart for implementing step S50 in a method for detecting the quality of a circuit board in an embodiment of the present application; Figure 6 is other flowcharts for implementing step S50 in a method for detecting the quality of a circuit board in an embodiment of the present application; Figure 7 It is a principle block diagram of a circuit board quality detection device in an embodiment of the present application; Figure 8 It is a schematic diagram of the device in an embodiment of the present application. Specific implementation manners

[0022] The present application will be further described in detail below with reference to the accompanying drawings.

[0023] In one embodiment, as Figure 1 shown, the present application discloses a circuit board quality detection method, which specifically includes the following steps: S10. Obtain a detection task and determine the corresponding to-be-determined detection node according to the detection task; in this embodiment, obtaining a detection task is the starting point of the entire quality detection process. The system will automatically generate a detection task according to the requirements input by the production line or the user. This task may include detecting certain specific areas or certain specific types of defects on the circuit board. The system will identify and match the corresponding to-be-determined detection node according to different requirements of the task. The to-be-determined detection node can be a detection unit with different functions. For example, the AOI detection node is used for detecting external defects, while the AXI detection node is used for detecting internal structures. In this way, the system can reasonably allocate nodes according to the requirements of the task at the initial stage, ensure that each task is processed by appropriate resources, and improve the efficiency and accuracy of task execution.

[0024] Preferably, in the step of extracting key features, the system first preprocesses the detection area of the circuit board, mainly including image preprocessing (such as denoising, binarization, etc.) and data filtering. Next, key physical features such as the component layout, solder joint position, solder joint shape, component size, and soldering angle of each detection area are extracted. The specific implementation methods include: First, the system uses AOI detection technology to collect high-resolution images of the external area, and extracts the appearance information of components and the geometric parameters of solder joints, such as the size, shape, and position deviation of solder joints, through feature recognition algorithms. For the internal area, AXI detection technology will deeply detect the internal soldering conditions of the circuit board through X-ray imaging technology, and extract the internal connection features of solder joints, such as internal voids in solder joints and the thickness of soldering materials. The extracted key features will affect the selection of subsequent nodes. For example, if the extracted key features are the installation errors of surface components or surface defects of solder joints, the system will preferentially select the AOI detection node for external detection; while if the extracted features involve internal connection problems of multi-layer boards or internal voids of solder joints, the system will select the AXI detection node for further processing. In addition, the system will decide whether to call a single detection node or multiple detection nodes to work together according to the complexity and size of components in the detection area, so as to ensure that key features can be detected comprehensively and accurately. This node selection logic based on key features can significantly improve the detection accuracy and efficiency and avoid resource waste.

[0025] S20. Obtain circuit board detection information based on at least AOI detection technology and / or AXI detection technology. The circuit board detection information includes at least external image information and internal sensing information. In this embodiment, based on AOI detection technology and / or AXI detection technology, the system will collect multi-dimensional information of the circuit board. AOI (Automated Optical Inspection) technology captures the external image of the circuit board through a high-resolution camera to detect external solder joints, component installation errors, etc.; while AXI (Automated X-ray Inspection) technology obtains the internal structure information of the circuit board through X-ray imaging for detecting internal defects of solder joints. This step ensures that the system can obtain both external and internal information of the circuit board, thus achieving a comprehensive detection of the circuit board. Through this multi-dimensional data collection, the system can accurately locate external and internal defects, especially when dealing with multi-layer boards and complex circuit boards, which can significantly improve the detection depth and accuracy.

[0026] S30. Split the circuit board detection information into multiple detection sub-information, and store each detection sub-information in a distributed file system. In this embodiment, the obtained circuit board detection information is relatively large, so these information need to be split into multiple detection sub-information. Each sub-information represents the detection data of a certain area or a certain level of the circuit board. The purpose of splitting is to facilitate parallel processing and storage. Storing these sub-information in a distributed file system can make full use of the advantages of distributed computing, support the storage and efficient invocation of large-scale data. The distributed file system can flexibly allocate storage space according to task requirements to ensure the security and efficient transmission of data. This method enables the system to maintain high processing capacity even when facing large-scale detection tasks, avoiding the bottleneck problem of data processing.

[0027] S40. Based on the task scheduling system, determine the first balance value of each detection node to be determined, and determine the corresponding target detection node according to the first balance value. In this embodiment, the task scheduling system will calculate the first balance value according to the current state of each detection node to be determined. The calculation of the first balance value comprehensively considers factors such as the task load and resource availability of the node to ensure that the system can reasonably allocate tasks. The system will automatically select the target detection node most suitable for processing the current detection task according to the calculated balance value, avoiding performance degradation caused by overloading of some nodes. Through this dynamic adjustment and optimization, the system can maintain balance in resource allocation, thereby improving the efficiency and stability of the entire detection process. This scheduling method is especially suitable for multi-task concurrent environments to avoid nodes affecting the detection accuracy due to overload.

[0028] Preferably, when determining computing resources, the system will intelligently schedule AOI (Automated Optical Inspection) and AXI (Automated X-ray Inspection) detection nodes to work together according to the complexity of the task and detection requirements, especially when certain tasks require simultaneous external and internal inspections. The specific implementation is as follows: When the inspection task involves both the external solder joint quality and the internal soldering state of the circuit board, the system first decomposes the task through the task scheduling system and divides the inspection task into two subtasks: AOI and AXI. The system will first allocate the AOI node to be responsible for the inspection of external components and solder joints, mainly obtaining high-resolution image data for identifying external defects, such as irregular solder joint shapes, poor surface soldering, etc.; at the same time, the system will allocate the AXI node in parallel to detect the quality of internal solder joints through X-ray scanning and analyze internal defects such as voids, cracks, or insufficient solder inside the solder joints. To ensure the effective coordination of the two inspection methods, the system will introduce a task synchronization mechanism and a data sharing mechanism. Specifically, when the AOI and AXI nodes are performing inspections, they first complete their respective inspection tasks and generate preliminary inspection data. The system stores this data from two different sources uniformly through a distributed file system and aligns the data according to the ID and timestamp of the inspection area. In this way, the system can ensure that the external inspection data and the internal inspection data are synchronously processed for the same inspection area within the same time period. The task scheduling system will continuously monitor the execution progress of the AOI and AXI nodes to ensure that there is no waste of resources for the other party after one party has completed the inspection. For example, when the AOI inspection node has completed the inspection of surface components and found defects, the system will immediately mark the area and preferentially transmit the internal solder joint information of this area to the AXI node for further in-depth analysis, and vice versa. This collaborative inspection mode of AOI and AXI can play an important role in the inspection of complex multi-layer boards. By parallelizing the processing of external and internal defects, it effectively shortens the overall inspection time and ensures the comprehensiveness and accuracy of the inspection results.

[0029] S50. Call out each detection sub - information from the distributed file system, and respectively allocate it to the corresponding target detection nodes for processing to generate corresponding node detection results. Then, summarize all the node detection results to the distributed file system, and send the corresponding summary packet to the central processing node through the distributed file system. In this embodiment, the system calls out each detection sub - information from the distributed file system and distributes these sub - information to the corresponding nodes according to the characteristics of each target detection node. Each detection node processes according to the allocated sub - information to generate corresponding node detection results. Different nodes independently process different sub - information. This parallel processing method can significantly improve the speed of the overall detection task. After processing, the node detection results are summarized to the distributed file system again. The system generates a summary packet through this file system and sends it to the central processing node for integration. In this way, the system can ensure smooth data flow between each node, and the summarization of node detection results can guarantee the efficiency of data processing.

[0030] S60. The central processing node integrates all the node detection results to generate a final detection report, and performs visual push display based on a visualization tool. In this embodiment, the central processing node integrates the detection results returned by each node to generate a final detection report. This report will contain the detailed results of all detection areas and detection sub - information. To facilitate user understanding and analysis, the system will generate corresponding charts or report pages based on the visualization tool. Through visualization display technology, the detection results can be intuitively presented, making it convenient for users to timely understand the quality status of the circuit board. This method not only improves the readability of data, but also simplifies the user's decision - making process, enabling the detection report to be fed back to the production link faster, avoiding complex manual analysis steps, and further improving the response speed and efficiency of the system.

[0031] In summary, the combination of high - resolution AOI detection technology and in - depth structure AXI detection technology can conduct detailed quality inspections on tiny components and multi - layer structures, greatly improving the detection accuracy and ensuring the comprehensiveness of detection. Moreover, by splitting the detection information into sub - information and performing distributed processing, the system can specifically process a certain part of the defect information for each detection node, thus covering the defect types in different areas and layers of the circuit board, further improving the comprehensiveness of detection. Through the task scheduling system and equilibrium value calculation, the system can automatically manage and allocate tasks for each detection node, avoiding human intervention and operation complexity. The system automatically selects the best node for the detection task, reducing the operation complexity among multiple devices and multiple systems. The distributed system ensures that each sub - task can be processed in parallel on different nodes, avoiding a decline in detection accuracy caused by over - loading of a single node. Each node focuses on a specific task, improving the overall detection accuracy and reliability.

[0032] In one embodiment, as Figure 2 shown, in step S10, the step of determining the corresponding detection node to be determined according to the detection task includes: S101. Decompose the detection task to generate corresponding subtasks; in this embodiment, decomposing the detection task is to divide the entire detection process into several small subtasks, and each subtask focuses on detecting a specific part of the circuit board or a specific type of defect. This decomposition method enables the system to process multiple subtasks in parallel, improving the efficiency and flexibility of detection. The decomposed subtasks can be classified and allocated according to the detection objectives (such as solder joints, component installation, internal circuit structure, etc.) to ensure that each task is assigned to the most suitable detection node. This subtask division can also be adjusted according to the complexity of the circuit board. Especially for multi-layer boards or highly integrated circuits, the decomposition of subtasks can help the system manage and process the detection process more efficiently.

[0033] S102. Determine the detection area of the circuit board according to the subtasks; in this embodiment, determining the detection area of the circuit board according to the subtasks is to further refine each subtask to a specific area. For example, a certain subtask may require detecting specific solder joints or capacitor components on the circuit board, and these targets will correspond to specific detection areas. By determining the detection area, the system can optimize the configuration of the detection nodes, ensure that the detection task only processes specific areas, avoid unnecessary full-board detection, and thus improve the detection speed and resource utilization rate. Especially for large circuit boards or complex multi-layer boards, this method of allocating detection tasks by area can significantly reduce the detection time and avoid waste of resources.

[0034] S103. Extract the key features of the detection area; in this embodiment, extracting the key features of the detection area is to help the system more accurately identify the detection targets and tasks. The key features may include the geometric shape of the circuit board, the position of the solder joints, the type of components, the wiring density, etc. By extracting these features, the system can accurately locate the area to be detected. These features can help the detection nodes more efficiently judge the type of defects and provide effective detection data. Taking solder joint detection as an example, the geometric shape and position of the solder joints are its key features. By identifying these features, AOI or AXI detection equipment can more accurately detect welding quality problems and avoid omissions or misdetections.

[0035] S104. Match the corresponding detection nodes to be determined according to the key features, where different detection nodes to be determined correspond to different computing resources. The computing resources include AOI computing resources for processing different external defects of the circuit board and AXI computing resources for processing different internal defects of the circuit board. In this embodiment, the corresponding detection nodes to be determined are matched according to the key features, and these detection nodes will select appropriate computing resources according to the task requirements. Different detection nodes to be determined will be matched according to their proficient detection types. For example, AOI computing resources mainly process the detection of external defects, such as solder joint defects, component installation errors, etc.; while AXI computing resources focus on the detection of internal defects, such as internal soldering problems, hidden defects in multi-layer boards, etc. Through this reasonable matching of resources, the system can dynamically allocate computing resources according to the specific requirements of the task to ensure that each subtask can be completed efficiently. For example, when it is necessary to detect both the external and internal parts of the circuit board simultaneously, the system can call AOI and AXI resources in parallel to process external and internal defects respectively, so as to achieve fast and comprehensive detection.

[0036] In summary, decomposing the detection task into subtasks and determining the detection areas of the circuit board according to these subtasks can perform refined detection on different areas, thereby improving the pertinence and accuracy of detection. Extracting the key features of the detection areas and matching the detection nodes to be determined based on these key features can allocate different detection resources according to the specific requirements of the detection areas, thereby optimizing the utilization of computing resources. By distinguishing AOI computing resources for processing external defects and AXI computing resources for processing internal defects, various detection technologies can be used more effectively to process different types of defects respectively, further improving the accuracy and efficiency of detection.

[0037] In one embodiment, as Figure 3 shown, in step S40, that is, the step of determining the first balance value of each detection node to be determined based on the task scheduling system includes: S401. Obtain the thread tasks and resource running statuses of each detection node to be determined. Among them, the resource running status is generated based on the feedback information of the verification task, and the resource running status includes normal status, pending status, and abnormal status. In this embodiment, obtaining the thread tasks and resource running statuses of each detection node to be determined is a crucial step. The system evaluates the availability of each detection node by monitoring and collecting the current execution task situation and resource usage of each detection node. The resource running status is generated based on the feedback information of the previously executed verification task. For example, the performance of a certain node may show an abnormal status in the previous task, resulting in the task not being completed as expected. The system will update the status of each node in real time according to this feedback information, including normal status (the node works well and resources are available), pending status (the node resources may be about to be exhausted or there is a risk of task delay), and abnormal status (the node cannot execute the task normally or the task fails). By obtaining this information, the system can evaluate the status of each node and ensure that the most suitable node for the current task is selected in subsequent task allocation.

[0038] Preferably, when generating the "feedback information of the verification task", the system will automatically record the task execution situation of each detection node and generate feedback information through a series of real-time monitoring and data analysis steps. The specific implementation method is as follows: When the detection node receives the detection task and starts to execute, the system will start the real-time monitoring module to track key parameters such as the resource usage, task progress, and detection accuracy of the node. First, the system will collect the resource usage status of the detection node through built-in performance monitoring tools (such as CPU, memory, and GPU usage rates), and these data will be reported to the central task scheduling system regularly. Secondly, the system will compare the expected completion time of the node with the actual execution time and record whether the task is completed within the expected time to judge the execution efficiency of the node. The system will also conduct a preliminary verification of the detection results output by the node through a data verification mechanism, including the integrity of the results, the correctness of the data format, and a preliminary evaluation of the detection accuracy. If it is found that the result data is missing, incorrect, or abnormal, the system will immediately record this situation. In addition, the system will also extract information from the execution records of historical tasks to comprehensively evaluate the status of the current node. For example, if a certain node has repeatedly experienced delays or result deviations in several recent detection tasks, the system will mark this node as "pending status" or "abnormal status" and feedback this information to the central system. In this way, the feedback information of the verification task can reflect the running status, resource availability, and task execution quality of the node. The system generates a detailed node performance report based on this feedback information to help the task scheduling system make a more reasonable choice in subsequent task allocation and ensure the smooth completion of the detection task.

[0039] S402. Determine the current availability weight coefficients of each detection node according to the resource running status, where the availability weight coefficient in the normal state is the highest, the availability weight coefficient in the pending state is medium, and the availability weight coefficient in the abnormal state is the lowest. In this embodiment, determining the current availability weight coefficients of each detection node according to the resource running status is to further quantify the status of each node, so as to provide a basis for task allocation. The system will assign a weight coefficient to each node according to its resource running status. Among them, the node in the normal state has the highest availability, so the weight coefficient is the largest. The node in the pending state has a medium weight coefficient because there may be risks of resource shortage or task delay. The node in the abnormal state cannot run reliably, so its weight coefficient is the lowest and may even be excluded from the selection of task allocation. Through this division of weight coefficients, the system can preferentially select the nodes in the normal state and with sufficient resources for task allocation, thereby improving the reliability and efficiency of task execution.

[0040] S403. Determine the task load coefficients of each detection node according to the thread task, where the task load coefficient is generated based on the load indicators generated by the execution quantity, task complexity, and completion rate of the thread task. In this embodiment, determining the task load coefficients of each detection node according to the thread task is calculated by analyzing the number of tasks currently being executed by the node, the complexity of the tasks, and the task completion rate. The task load coefficient reflects the current working pressure of the node. If a node is executing a large number of high-complexity tasks, its load coefficient will be relatively high, indicating that the node is in a loaded state and may not be able to process new tasks efficiently. On the contrary, if a node has a small number of tasks, low complexity, or most tasks are nearly completed, its load coefficient is relatively low, indicating that the node has more computing resources available for new tasks. Through this calculation of the load coefficient, the system can balance the task volume of different nodes and avoid performance degradation caused by individual nodes being overloaded.

[0041] Preferably, when generating the task load factor, the system comprehensively considers the complexity of the task, the execution progress, and the resource occupancy of the nodes, and uses a unified quantitative index to evaluate the load of each detection node. The specific implementation method is as follows: First, the measurement of task complexity is evaluated through pre-set standardized parameters. The system will assign a complexity coefficient according to the different types of circuit boards involved in the detection task, the size of the detection area, the component density, and the detection type (such as AOI, AXI). The calculation of the complexity coefficient is based on the statistical results of historical data. For example, an internal solder joint detection task involving multi-layer circuit boards has a higher complexity and may be assigned a higher complexity coefficient (such as a value between 1 and 10, with 10 being the highest complexity). Second, the measurement of task completion rate is calculated in real time through the execution progress of the detection task. When the task is being executed, the system determines the current completion ratio of the task by comparing the amount of data already processed by the node with the total task amount. The completion rate is expressed as a percentage. For example, if a node has completed 50% of the task, its completion rate is 50%. To more accurately reflect the task load situation, the system also considers the resource utilization rate of the node, including the occupancy of CPU, memory, and GPU. The resource utilization rate, together with the task complexity and completion rate, are the three main factors for the comprehensive load. The system combines them into a unified task load factor through weighted averaging. For example, the calculation formula for the task load factor can be: task load factor = (0.5 × complexity coefficient) + (0.3 × resource utilization rate) + (0.2 × completion rate), and the weights are adjusted according to the importance of the task and the resource status of the node. In this way, the system can generate the load index of each detection node in real time, which is used by the scheduling system to evaluate the current task pressure of the node, so as to ensure that subsequent tasks can be reasonably allocated to nodes with lower load and optimize the execution efficiency of the overall detection task.

[0042] S404. Calculate the first balance value corresponding to each detection node according to the resource availability coefficient and the task load factor. In this embodiment, the system combines these two coefficients to comprehensively evaluate the task processing ability of each node by calculating the first balance value corresponding to each detection node according to the resource availability coefficient and the task load factor. The first balance value is a key indicator for the task scheduling system to allocate tasks. It not only considers the resource availability of the node but also combines the current task load situation to ensure that tasks can be reasonably allocated to the most suitable nodes. In this way, the system can avoid continuing to allocate tasks to some nodes that have sufficient resources but are overloaded, and can also preferentially allocate tasks to nodes with available resources and low load, thereby achieving load balancing and optimal resource utilization of the entire detection task.

[0043] In summary, by obtaining the thread tasks and resource running states of the detection nodes to be determined, the actual running conditions of each node can be accurately understood, thereby optimizing the allocation of detection tasks. Generating the availability weight coefficient according to the resource running state can flexibly adjust the task allocation according to the health state of the nodes, improving the adaptability and stability of the system. Generating the task load coefficient according to the thread tasks can evaluate the workload of each node in real time, ensure the balance of task allocation, and avoid overload or resource waste. Finally, by calculating the resource availability coefficient and the task load coefficient to generate the first balance value, the task allocation of the nodes can be comprehensively optimized, further improving the overall performance and response speed of the system.

[0044] In one embodiment, as Figure 4 shown, in step S50, that is, calling out each detection sub-information from the distributed file system and respectively allocating it to the corresponding target detection nodes for processing to generate the corresponding node detection results, and summarizing the node detection results to the distributed file system, and sending the corresponding summary packet to the central processing node through the distributed file system, includes: S5011. Based on the task scheduling system, obtain the storage identifier of the distributed file system; in this embodiment, based on the task scheduling system, obtaining the storage identifier of the distributed file system is to ensure that the system can efficiently and accurately locate and call the required detection sub-information. The storage identifier is similar to the unique identification code of a file, which guides the system to find the location where the specific detection sub-information is located in the distributed file system. The distributed file system indexes and manages the detection data through the storage identifier, so that the system can quickly retrieve the corresponding file from the massive data. During the task scheduling process, the system will automatically call the relevant storage identifier according to the detection task to ensure that the required detection data can be correctly accessed and processed. This process simplifies the file management of complex detection tasks, avoids the complexity of manually querying the file location, and improves the overall efficiency of the detection tasks.

[0045] S5012. Match the corresponding target detection node according to the storage identifier, and call the detection sub-information corresponding to the storage identifier to the target detection node; in this embodiment, matching the corresponding target detection node according to the storage identifier and calling the detection sub-information corresponding to the storage identifier to the target detection node is to associate the located detection sub-information with the best detection node. The system will find the detection sub-information stored in the distributed file system based on the previously obtained storage identifier, and then match the target detection node most suitable for processing this sub-information through the task scheduling system. These detection sub-informations will be sent to the corresponding detection nodes for further processing. The matching process involves the task scheduling system automatically selecting the most suitable node according to the availability and task load of the nodes, which can ensure that each detection task is assigned to the node with the best computing resources, thereby improving the processing efficiency of the detection task. For example, when the system needs to detect the internal structure of a circuit board, the task scheduling system will preferentially select the detection node with AXI computing resources for processing.

[0046] S5013. Mark the start time of the detection cycle. When the target detection node generates the node detection result and returns it to the distributed file system, mark the end time of the detection cycle. Determine the thread task of the target detection node according to the start time and end time of the detection cycle, so as to determine the second balance value of the target detection node; in this embodiment, marking the start time of the detection cycle is to accurately record the time starting point of each detection node executing the task and ensure the tracking and management of the detection task. The start time of the detection cycle indicates the moment when the detection node receives the task and starts processing, and when the target detection node generates the node detection result and returns it to the distributed file system, mark the end time of the detection cycle. The purpose of this process is to track the task execution time of each detection node, so as to evaluate the execution efficiency of the node. The system can evaluate the processing speed and task completion status of each detection node by calculating the duration of the detection cycle, and determine the thread task of the target detection node according to this information. This step provides a basis for the system to generate the second balance value, ensuring that subsequent tasks can be reasonably allocated and avoiding performance degradation of the node due to task overload.

[0047] S5014. Determine the preset number of marks for the summary package. When the actual number of marks at the end time of the detection period is greater than the preset number of marks, send the corresponding summary package to the central processing node through the distributed file system. In this embodiment, determining the preset number of marks for the summary package is to ensure the integrity of task processing and the accuracy of data aggregation. After each detection task is completed, the system will judge whether the task has been completed according to the preset number of marks. If the actual number of marks at the end time of the detection period is greater than the preset number of marks, it means that all tasks have been successfully completed. At this time, the system will send the corresponding summary package to the central processing node through the distributed file system. The summary package contains the detection results of all target detection nodes, and the central processing node integrates the final detection report by receiving these summary packages. Through this marking and summarization mechanism, the system can ensure that the results of each detection task are transmitted to the central node completely and accurately, thus avoiding data loss or omission and improving the reliability of the detection system and the accuracy of the results.

[0048] In summary, calling the detection sub-information from the distributed file system and allocating it to the corresponding target detection nodes can achieve automatic data allocation and dynamic task adjustment, thereby improving the flexibility of task processing and the efficiency of data transmission. By storing the identification to match the target detection node, it can ensure that the detection sub-information is accurately allocated to the appropriate node and optimize the utilization rate of computing resources. Marking the start and end times of the detection period can accurately calculate the execution efficiency of each detection node, evaluate its performance, and ensure that the system monitors in real time and dynamically adjusts the node load. Calculating the thread tasks according to the detection period and determining the second balance value can optimize the task allocation between nodes and further improve the overall detection efficiency of the system.

[0049] In one embodiment, as Figure 5 shown, after step S5014, that is, after the step of determining the preset number of marks for the summary package and sending the corresponding summary package to the central processing node through the distributed file system when the actual number of marks at the end time of the detection period is greater than the preset number of marks, the following steps are further included: S5015. When new circuit board detection information is obtained, based on the task scheduling system, compare the first equilibrium value and the second equilibrium value to determine the new target detection node. In this embodiment, when new circuit board detection information is obtained, the system will first evaluate the current detection environment through the task scheduling system. The acquisition of new detection information means that the current node resources and loads need to be reallocated. The system will compare the first equilibrium value and the second equilibrium value of each detection node. The first equilibrium value reflects the previous resource availability and task load of the node, while the second equilibrium value is the actual load after executing part of the tasks. By comparing these two equilibrium values, the system can determine whether the current state of certain nodes is suitable for continuing to undertake new detection tasks, or whether new tasks need to be assigned to other nodes with lighter loads. This comparison can not only dynamically adjust the task allocation of nodes, but also optimize the overall resource utilization rate of the system. For example, if the second equilibrium value of a certain node is higher than the first equilibrium value, it means that the node may be overloaded during the task execution and is no longer suitable for receiving new tasks; while nodes with lighter loads and relatively lower equilibrium values are more suitable for new task allocation. Through this mechanism, the system can continuously optimize the task distribution of each node in a complex multi-task detection environment, avoid overloading or resource waste of certain nodes, and ensure the efficiency and stability of the detection process. Finally, based on the dynamic adjustment of the equilibrium value, the system will determine the new target detection node and allocate the new circuit board detection task to the most suitable node for processing, thereby improving the overall response speed of the system and the execution efficiency of the detection task. This process ensures that even in a high-concurrency task environment, the system can flexibly allocate resources, maintain high processing performance and detection accuracy.

[0050] In summary, when new circuit board detection information is obtained, by comparing the first equilibrium value and the second equilibrium value based on the task scheduling system, it is possible to flexibly adjust the new task allocation plan by comparing the historical task load and the current node state, thereby improving the self-adaptability and real-time response ability of the system. By dynamically adjusting the new target detection node, it can ensure that the system can still operate efficiently under changing task requirements, further optimize the execution efficiency of the detection task, and avoid the situation of node overload or insufficient resource utilization.

[0051] In one embodiment, as Figure 6 shown, in step S50, that is, the step of allocating to the corresponding target detection node for processing to generate the corresponding node detection result, includes: S5021. Determine whether the actual computation amount of the detected sub - information is greater than the determined pre - set computation amount. In this embodiment, determining whether the actual computation amount of the detected sub - information is greater than the determined pre - set computation amount is an important operation before the system processes the detection task. The computation amount of the detected sub - information depends on the complexity of the information and the required computing resources. The pre - set computation amount is a threshold value pre - set by the system according to historical tasks and the computing power of the model, and is used to determine whether the current task is simple or complex. For example, for the detection of some circuit boards, the detection of surface defects may have a relatively small computation amount, lower than the pre - set amount, while for the analysis of the soldering state of multi - layer circuit boards, the computation amount may far exceed the pre - set value. At this step, the system will determine whether the actual computation amount exceeds this pre - set value to decide the subsequent processing method.

[0052] S5022. If not, then based on the trained key detected - sub - algorithm model, generate the corresponding node detection result according to the detected sub - information. In this embodiment, if not, then based on the trained key detected - sub - algorithm model, generate the corresponding node detection result according to the detected sub - information. This means that if the actual computation amount of the detected sub - information is small, the system will directly call the trained key detected - sub - algorithm model to process. This model is trained based on a large amount of data and previous detection tasks and can efficiently process regular detected - sub - tasks. For example, when detecting standard components or common solder - joint defects on a circuit board, since the computation amount of these tasks is low and the system model has been fully trained, there is no need to call complex computing resources, and the key detected - sub - algorithm model can quickly generate the node detection result, thus improving the processing speed and efficiency of the system.

[0053] S5023. If so, then determine the trained key detected - sub - algorithm model, based on the distributed mode of the deep - learning framework, disassemble the computing task of the detected sub - information, and allocate the computing task to the trained redundant detected - sub - algorithm models. In this embodiment, if so, then determine the trained key detected - sub - algorithm model, based on the distributed mode of the deep - learning framework, disassemble the computing task of the detected sub - information, and allocate the computing task to the trained redundant detected - sub - algorithm models. This means that when the computation amount of the detected sub - information is large and exceeds the pre - set computation amount, the system will adopt a more complex distributed computing mode. At this time, the system will first split the detection task into multiple sub - tasks and allocate these sub - tasks to multiple redundant detected - sub - algorithm models based on the deep - learning framework. These redundant models are also trained and can process different parts of complex detection tasks respectively. For example, when processing the detection of complex multi - layer circuit boards, the system may need to analyze the connections and solder - joint states between different layers. The redundant models can effectively accelerate the completion speed of the detection task through parallel processing.

[0054] Preferably, in the collaborative working mechanism between the "key detection sub-algorithm model" and the "redundant detection sub-algorithm model", the system will automatically determine whether to use the redundant detection sub-algorithm model for parallel processing according to the complexity, computational volume, and execution time limit of the task. The specific implementation method is as follows: First, before executing the detection task, the system uses the key detection sub-algorithm model to perform preliminary calculations on the detection task. When the system determines that the computational volume of the task exceeds a preset threshold (for example, the computational volume reaches a certain size or the task execution time is expected to exceed the set time limit), the parallel processing mechanism of the redundant detection sub-algorithm model will be triggered. At this time, the system splits the task into multiple smaller subtasks, and each subtask corresponds to a different detection area or detection dimension. For example, when detecting the multi-layer structure of a circuit board, the system can split the detection task of each layer into independent subtasks to separately process internal defects such as solder joints and connectivity of different layers. After the task is split, the system assigns these subtasks to multiple redundant detection sub-algorithm models for parallel processing. The redundant detection sub-algorithm model is a specially trained algorithm model with high parallel processing capabilities and can process multiple subtasks simultaneously, thus greatly improving the detection speed. Each redundant model independently processes its assigned subtask, generates partial detection results, and aggregates the results into a distributed file system. At the same time, the system monitors the execution progress of each redundant model in real time through the task scheduling system to ensure that the task is completed on time. If a certain redundant model experiences a delay or anomaly, the system can dynamically adjust the task assignment and increase the computational tasks of other redundant models to ensure that the progress of the overall detection task is not affected. Finally, when all the subtasks of the redundant models are completed, the system aggregates the partial calculation results of each subtask into the key detection sub-algorithm model. The key detection sub-algorithm model is responsible for uniformly analyzing and fusing all the sub-results to ensure the accuracy of the final detection result. The parallel processing mechanism of the redundant model is particularly suitable for the detection of complex multi-layer boards or circuit boards with dense components. In this case, assigning the task to multiple redundant models can significantly improve the overall detection efficiency and ensure the rapid and accurate completion of the detection task.

[0055] S5024. Aggregate all the partial calculation results generated based on the trained redundant detection sub-algorithm models to the trained key detection sub-algorithm model, and generate corresponding node detection results according to the trained key detection sub-algorithm model. In this embodiment, all the partial calculation results generated based on the trained redundant detection sub-algorithm models are aggregated to the trained key detection sub-algorithm model, and corresponding node detection results are generated according to the trained key detection sub-algorithm model. In the distributed mode, the redundant detection sub-algorithm models will process different parts of the task separately to generate partial detection results. Subsequently, the system will aggregate these scattered results into the key detection sub-algorithm model, and the key model will conduct unified analysis and judgment. Finally, the key detection sub-algorithm model generates a complete node detection result. This process ensures that even in the face of complex and large-scale detection tasks, the system can still effectively complete the detection tasks through the distributed processing and aggregation mechanism. For example, when processing the solder joint detection of multiple regions on a circuit board, the redundant models can simultaneously process the detection results of multiple solder joints and finally aggregate them to the key model to form a complete detection report. This method not only improves the processing efficiency but also ensures the accuracy and consistency of the detection results.

[0056] Preferably, in a distributed environment, the deep learning framework performs task splitting and distribution mainly through two methods: data parallelism and model parallelism. The specific implementation is as follows: The system first determines which parallelism method to adopt based on the type and scale of the detection task. When the task involves large-scale data processing, the system will preferentially adopt the data parallelism method, which means that the same deep learning model is replicated to different computing nodes, and each node processes different parts of the detection data. For example, for the multi-region detection task of a circuit board, the system will split the detection data by region or level, and distribute the data of each sub-region to different nodes for parallel processing. Each node independently runs the same model, processes the data assigned to it, and finally generates its own detection results. In the case of model parallelism, the system will split the deep learning model itself according to the complexity and resource requirements of the model, and distribute different layers or modules of the model to different computing nodes for parallel processing. This method is particularly suitable for processing very large deep learning models, such as multi-layer neural networks or convolutional neural networks (CNNs) that require a large amount of computing resources. For example, the system can assign the convolutional layer of the model to one node for processing, and the fully connected layer to another node for calculation. The advantage of model parallelism is that it can maximize the use of the system's computing resources. Especially when a single node cannot carry the entire model, model parallelism can effectively solve the computing bottleneck problem. For task splitting and distribution, the system will use a task scheduling system for coordination. The scheduling system will dynamically allocate tasks based on information such as the resource usage of nodes and task loads to ensure that the resource utilization rate of each node is optimized during operation. At the same time, the system will use the distributed computing library in the deep learning framework (such as TensorFlow's DistributedStrategy or PyTorch's DistributedDataParallel) to manage data synchronization and model updates between nodes to ensure data consistency between nodes. When summarizing the partial calculation results generated by redundant detection models, the system will synchronize and coordinate the data through a distributed file system. The specific process is as follows: After each redundant detection model finishes processing the sub-task assigned to it, it will upload the generated detection result to the distributed file system and mark its completion status. The system tracks the progress of each sub-task through the unique task identifier (such as task ID and timestamp) of the distributed file system to ensure that the results of all sub-tasks can be summarized on the central processing node. The summarization process uses a data synchronization mechanism, such as an event-driven callback function. When all sub-tasks of all nodes are completed, the system will automatically trigger the summarization operation to integrate all scattered sub-task results.

[0057] To ensure the consistency and synchronization of results, the system uses a distributed lock mechanism to prevent data write conflicts during task aggregation. When all subtasks are completed, the central node will perform weighted or comprehensive processing on the results of all subtasks to ensure the consistency of the final detection results. The system will also perform integrity verification on each sub-result to ensure that all detection results are correct and prevent the final results from being affected by task failures or data loss at some nodes. This synchronization and coordination mechanism ensures the accuracy and efficiency of the distributed deep learning system in processing complex tasks, enabling it to adapt to large-scale detection tasks and provide highly reliable detection results.

[0058] In summary, by determining whether the actual computational amount of the detection sub-information is greater than the pre-designed computational amount, it is possible to dynamically adjust the complexity of the computational task according to the actual computational requirements, ensuring the rationality of resource allocation and the accuracy of the detection task. If the computational amount of the detection sub-information is small, the node detection result can be directly generated based on the trained key detection sub-algorithm model, which can simplify the computational process and improve the processing efficiency. If the computational amount of the detection sub-information is large, the computational task can be disassembled through the distributed mode of the deep learning framework and allocated to the redundant detection sub-algorithm model, which can make full use of the advantages of distributed computing, balance the task load of different nodes, and ensure the efficient execution of complex computational tasks. Finally, summarizing the sub-computation results and generating the node detection result can improve the processing efficiency of large-scale computational tasks and ensure the accuracy and comprehensiveness of the detection results.

[0059] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not imply the order of execution. The execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0060] In one embodiment, a circuit board quality detection device is provided. This circuit board quality detection device corresponds one-to-one with the circuit board quality detection method in the above embodiment. As Figure 7 shown, this circuit board quality detection device includes a first acquisition module, a second acquisition module, a splitting module, a determination module, a first generation module, and a second generation module. The detailed description of each functional module is as follows: The circuit board quality detection device includes: a first acquisition module, configured to acquire a detection task and determine corresponding detection nodes to be determined according to the detection task; A second acquisition module, configured to acquire circuit board detection information at least based on AOI detection technology and / or AXI detection technology, where the circuit board detection information at least includes external image information and internal sensing information; A splitting module, configured to split the circuit board detection information into multiple detection sub-informations and store each of the detection sub-informations in a distributed file system; A determination module, configured to determine a first balance value of each of the to-be-determined detection nodes based on a task scheduling system, and determine corresponding target detection nodes according to the first balance value; A first generation module, configured to call out each of the detection sub-information from the distributed file system, and respectively allocate them to corresponding target detection nodes for processing to generate corresponding node detection results, aggregate each of the node detection results to the distributed file system, and send a corresponding summary packet to a central processing node through the distributed file system; A second generation module, configured to integrate each of the node detection results by the central processing node to generate a final detection report, and perform visual push display based on a visualization tool.

[0061] Optionally, the first acquisition module includes: A first generation unit, configured to decompose the detection task to generate corresponding subtasks; A first determination unit, configured to determine a detection area of the circuit board according to the subtasks; An extraction unit, configured to extract key features of the detection area; A first matching unit, configured to match corresponding to-be-determined detection nodes according to the key features, where different to-be-determined detection nodes correspond to different computing resources, and the computing resources include AOI computing resources for processing different external defects of the circuit board and AXI computing resources for processing different internal defects of the circuit board; Optionally, the determination module includes: A first acquisition unit, configured to acquire thread tasks and resource operation states of each of the to-be-determined detection nodes, where the resource operation state is generated according to feedback information of a verification task, and the resource operation state includes a normal state, a pending state, and an abnormal state; A second determination unit, configured to determine a current availability weight coefficient of each detection node according to the resource operation state, where the availability weight coefficient of the normal state is the highest, the availability weight coefficient of the pending state is medium, and the availability weight coefficient of the abnormal state is the lowest; A third determination unit, configured to determine a task load coefficient of each detection node according to the thread tasks, where the task load coefficient is generated by generating a load index according to the execution quantity, task complexity, and completion rate of the thread tasks; A calculation unit, configured to calculate a first balance value corresponding to each detection node according to the resource availability coefficient and the task load coefficient; Optionally, the first generation module includes: A second acquisition unit, configured to acquire a storage identifier of the distributed file system based on a task scheduling system; A second matching unit, configured to match a corresponding target detection node according to the storage identifier, and call the detection sub-information corresponding to the storage identifier to the target detection node; A marking unit, configured to mark the start time of the detection cycle. When the target detection node generates a node detection result and returns it to the distributed file system, mark the end time of the detection cycle, and determine the thread task of the target detection node according to the start time and the end time of the detection cycle, so as to determine the second balance value of the target detection node; A fourth determination unit, configured to determine a preset marking quantity of the summary packet. When the actual marking quantity at the end time of the detection cycle is greater than the preset marking quantity, send the corresponding summary packet to the central processing node through the distributed file system; Optionally, the first generation module further includes: A comparison unit, configured to, when obtaining new circuit board detection information, compare the first balance value and the second balance value based on the task scheduling system to determine a new target detection node; Optionally, the first generation module further includes: A judgment unit, configured to judge whether the actual calculation amount of the detection sub-information is greater than a determined preset calculation amount; A second generation unit, configured to, if not, generate a corresponding node detection result according to the detection sub-information based on a trained key detection sub-algorithm model; A disassembling unit, configured to, if so, determine a trained key detection sub-algorithm model, disassemble the calculation task of the detection sub-information based on the distributed mode of the deep learning framework, and allocate the calculation task to a trained redundant detection sub-algorithm model; A third generation unit, configured to summarize all sub-calculation results generated based on the trained redundant detection sub-algorithm model to the trained key detection sub-algorithm model, and generate a corresponding node detection result according to the trained key detection sub-algorithm model.

[0062] For the specific limitations of a circuit board quality detection device, reference may be made to the limitations of a circuit board quality detection method in the foregoing text, which will not be elaborated herein. Each module in the foregoing circuit board quality detection device may be implemented in whole or in part by software, hardware, and their combination. The foregoing modules may be embedded in the processor in the computer device in hardware form or independent thereof, or stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to the foregoing modules.

[0063] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as Figure 8As shown. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it implements a circuit board quality detection method.

[0064] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the following steps are implemented: S10. Obtain a detection task, and determine a corresponding to-be-determined detection node according to the detection task; S20. At least based on the AOI detection technology and / or the AXI detection technology, obtain circuit board detection information, where the circuit board detection information at least includes external image information and internal sensing information; S30. Split the circuit board detection information into multiple detection sub-information, and store each detection sub-information in a distributed file system; S40. Based on a task scheduling system, determine a first balance value of each to-be-determined detection node, and determine a corresponding target detection node according to the first balance value; S50. Call out each detection sub-information from the distributed file system, and respectively allocate them to the corresponding target detection nodes for processing to generate corresponding node detection results, summarize each node detection result in the distributed file system, and send a corresponding summary packet to a central processing node through the distributed file system; S60. The central processing node integrates each node detection result to generate a final detection report, and performs visual push display based on a visualization tool.

[0065] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: S10. Obtain a detection task, and determine a corresponding to-be-determined detection node according to the detection task; S20. At least based on the AOI detection technology and / or the AXI detection technology, obtain circuit board detection information, where the circuit board detection information at least includes external image information and internal sensing information; S30. Split the circuit board detection information into multiple detection sub-information, and store each detection sub-information in a distributed file system; S40, determining a first balance value of each to-be-determined detection node based on the task scheduling system, and determining a corresponding target detection node according to the first balance value; S50, calling each detection sub-information from the distributed file system, and respectively distributing them to the corresponding target detection nodes for processing to generate corresponding node detection results, aggregating the detection results of each node into the distributed file system, and sending the corresponding summary package to the central processing node through the distributed file system; S60: The central processing node integrates the detection results of each node, generates a final detection report, and performs visual push display based on a visualization tool.

[0066] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0067] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0068] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included within the protection scope of the present application.

Claims

1. A circuit board quality detection method, characterized in that: The circuit board quality detection method comprises: Obtaining a detection task, and determining a corresponding to-be-determined detection node according to the detection task; At least based on the AOI detection technology and / or the AXI detection technology, obtaining circuit board detection information, wherein the circuit board detection information at least includes external image information and internal sensor information; Splitting the circuit board detection information into a plurality of detection sub-information, and storing each of the detection sub-information in a distributed file system; Based on the task scheduling system, determining a first balance value of each of the to-be-determined detection nodes, and determining a corresponding target detection node according to the first balance value; Retrieving each of the detection sub-information from the distributed file system, and respectively distributing them to corresponding target detection nodes for processing to generate corresponding node detection results, aggregating each of the node detection results into the distributed file system, and sending corresponding summary packages to the central processing node through the distributed file system; The central processing node integrates the detection results of each node, generates a final detection report, and performs visual push and display based on a visualization tool.

2. A circuit board quality inspection method according to claim 1, characterized in that: The step of determining the corresponding to-be-determined detection node according to the detection task comprises: Decomposing the detection task to generate corresponding subtasks; According to the subtask, determining the inspection area of ​​the circuit board; Extracting key features of the detection area; According to the key features, corresponding detection nodes to be determined are matched, wherein different detection nodes to be determined correspond to different computing resources, and the computing resources include AOI computing resources for processing different external defects of circuit boards, and AXI computing resources for processing different internal defects of circuit boards.

3. A circuit board quality detection method according to claim 2, characterized in that: The step of determining the first equilibrium value of each of the to-be-determined detection nodes based on the task scheduling system comprises: Obtaining the thread tasks and resource running status of each of the to-be-determined detection nodes, wherein the resource running status is generated according to the feedback information of the verification task, and the resource running status includes a normal state, a pending state, and an abnormal state; According to the resource operation status, determine the current availability weight coefficient of each detection node, wherein the availability weight coefficient of the normal state is the highest, the availability weight coefficient of the pending state is medium, and the availability weight coefficient of the abnormal state is the lowest; Determine the task load coefficient of each detection node according to the thread task, wherein the task load coefficient is generated by generating a load index according to the number of thread tasks executed, task complexity, and completion rate; A first balancing value corresponding to each detection node is calculated according to the resource availability coefficient and the task load coefficient.

4. A circuit board quality inspection method according to claim 1, characterized in that: The steps of calling out each of the detection sub-information from the distributed file system and distributing them to corresponding target detection nodes for processing to generate corresponding node detection results, aggregating each of the node detection results to the distributed file system, and sending the corresponding summary package to the central processing node through the distributed file system include: Based on the task scheduling system, obtaining a storage identifier of the distributed file system; According to the storage identifier, a corresponding target detection node is matched, and the detection sub-information corresponding to the storage identifier is called to the target detection node; Marking the detection cycle start time, when the target detection node generates the node detection result and returns it to the distributed file system, marking the detection cycle end time, and determining the thread task of the target detection node according to the detection cycle start time and the detection cycle end time, so as to determine the second balance value of the target detection node; Determine a preset number of marks for the summary package, and when the actual number of marks at the end of the detection cycle is greater than the preset number of marks, send the corresponding summary package to the central processing node through the distributed file system.

5. A circuit board quality inspection method according to claim 4, characterized in that: After the step of determining the preset number of marks of the summary package, and when the actual number of marks at the end of the detection period is greater than the preset number of marks, sending the corresponding summary package to the central processing node through the distributed file system, the method further includes: When new circuit board detection information is obtained, the first balance value and the second balance value are compared based on the task scheduling system to determine a new target detection node.

6. A circuit board quality inspection method according to claim 1, characterized in that: The step of allocating to the corresponding target detection node for processing to generate the corresponding node detection result includes: Determining whether the actual calculation amount of the detection sub-information is greater than the determined preset calculation amount; If not, then based on the trained key detection sub-algorithm model, generate the corresponding node detection result according to the detection sub-information; If yes, determine the trained key detection sub-algorithm model, disassemble the calculation tasks of the detection sub-information based on the distributed mode of the deep learning framework, and assign the calculation tasks to the trained redundant detection sub-algorithm model; All sub-calculation results generated based on the trained redundant detection sub-algorithm model are aggregated into the trained key detection sub-algorithm model, and corresponding node detection results are generated according to the trained key detection sub-algorithm model.

7. A circuit board quality inspection device, characterized in that: The circuit board quality inspection device comprises: a first acquisition module, which is used to acquire an inspection task and determine a corresponding to-be-determined inspection node according to the inspection task; A second acquisition module is used to acquire circuit board detection information based at least on the AOI detection technology and / or the AXI detection technology, where the circuit board detection information includes at least external image information and internal sensor information; A splitting module, used for splitting the circuit board detection information into multiple detection sub-information, and storing each of the detection sub-information in a distributed file system; A determination module, configured to determine, based on a task scheduling system, a first balance value of each of the to-be-determined detection nodes, and determine a corresponding target detection node according to the first balance value; A first generating module is used to call out each of the detection sub-information from the distributed file system, and respectively distribute them to corresponding target detection nodes for processing to generate corresponding node detection results, summarize each of the node detection results into the distributed file system, and send the corresponding summary package to the central processing node through the distributed file system; The second generation module is used for the central processing node to integrate the detection results of each node, generate a final detection report, and perform visual push and display based on a visualization tool.

8. A circuit board quality inspection device according to claim 7, characterized in that: The first acquisition module includes: A first generating unit, used to decompose the detection task and generate corresponding subtasks; A first determining unit, configured to determine a detection area of ​​the circuit board according to the subtask; An extraction unit, used to extract key features of the detection area; A first matching unit is used to match the corresponding detection nodes to be determined according to the key features, wherein different detection nodes to be determined correspond to different computing resources, and the computing resources include AOI computing resources for processing different external defects of the circuit board, and AXI computing resources for processing different internal defects of the circuit board; The determination module comprises: A first acquisition unit is used to acquire the thread task and resource running state of each of the to-be-determined detection nodes, wherein the resource running state is generated according to the feedback information of the verification task, and the resource running state includes a normal state, a to-be-determined state and an abnormal state; A second determining unit is used to determine the current availability weight coefficient of each detection node according to the resource operation state, wherein the availability weight coefficient of the normal state is the highest, the availability weight coefficient of the pending state is medium, and the availability weight coefficient of the abnormal state is the lowest; A third determining unit is used to determine a task load coefficient of each detection node according to the thread task, wherein the task load coefficient is generated by generating a load index according to the number of executions of the thread task, the task complexity and the completion rate; A calculation unit, configured to calculate a first balance value corresponding to each detection node according to the resource availability coefficient and the task load coefficient; The first generation module comprises: A second acquisition unit, configured to acquire a storage identifier of the distributed file system based on a task scheduling system; A second matching unit is used to match a corresponding target detection node according to the storage identifier, and call the detection sub-information corresponding to the storage identifier to the target detection node; a marking unit, used to mark the start time of a detection cycle, and when the target detection node generates a node detection result and returns it to the distributed file system, mark the end time of the detection cycle, and determine the thread task of the target detection node according to the start time of the detection cycle and the end time of the detection cycle, so as to determine the second balance value of the target detection node; a fourth determining unit, configured to determine a preset number of marks of the summary package, and when the actual number of marks at the end time of the detection cycle is greater than the preset number of marks, send the corresponding summary package to the central processing node through the distributed file system; The first generation module also includes: A comparison unit, configured to compare the first balance value and the second balance value based on the task scheduling system when new circuit board detection information is acquired, so as to determine a new target detection node; The first generation module also includes: A judging unit, used to judge whether the actual calculation amount of the detection sub-information is greater than a determined preset calculation amount; A second generating unit is used to generate a corresponding node detection result according to the detection sub-information based on the trained key detection sub-algorithm model if no; A disassembling unit, for, if yes, determining a trained key detection sub-algorithm model, disassembling the computing tasks of the detection sub-information based on a distributed mode of a deep learning framework, and allocating the computing tasks to the trained redundant detection sub-algorithm model; The third generation unit is used to aggregate all sub-calculation results generated based on the trained redundant detection sub-algorithm model into the trained key detection sub-algorithm model, and generate corresponding node detection results according to the trained key detection sub-algorithm model.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the circuit board quality detection method as claimed in any one of claims 1 to 6 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of a circuit board quality detection method as claimed in any one of claims 1 to 6 are implemented.

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