Chip testing device, chip testing system and preparation method of chip testing device

Abstract

The embodiment of the invention provides a chip testing device, a chip testing system and a preparation method of the chip testing device, relates to the technical field of chip detection, and aims to solve the problem that the service life of a probe card structure is short. The chip testing device comprises a ceramic substrate, a first detection circuit, an interconnection part and a plurality of detection contacts. The ceramic substrate comprises a substrate main body and a supporting part, the supporting part is arranged on one surface of the substrate main body, and the first detection circuit is arranged in the substrate main body; the interconnection part is located on the surface, provided with the supporting part, of the substrate body, and at least part of the side face of the interconnection part is connected to the supporting part; and the plurality of detection contacts are located at one side, deviating from the substrate main body, of the interconnection part and are electrically connected with the first detection circuit through the interconnection part. The chip testing device is used for detecting the chip.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a chip testing device, a chip testing system, and a method for preparing the chip testing device. Background Art

[0002] The probe card structure is a very important technology in the chip manufacturing process. Before the chip is packaged, the probe on the probe card structure contacts the chip's pad or bump, and cooperates with test equipment such as a probe station to achieve automated measurement and screen known good die (KGD). Currently, the existing probe card structure has the problem of a short service life. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a chip testing device, a chip testing system and a method for preparing a chip testing device, so as to improve the problem of a short service life of a probe card structure.

[0004] To achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0005] On the one hand, a chip testing device is provided. The chip testing device includes: a ceramic substrate, a first detection circuit, an interconnection part and a plurality of detection contacts. The ceramic substrate includes a substrate body and a support part, the support part is arranged on a surface of the substrate body, and the first detection circuit is arranged in the substrate body. The interconnection part is located on the surface of the substrate body where the support part is arranged, and at least part of the side surface of the interconnection part is connected to the support part. A plurality of detection contacts, the plurality of detection contacts are located on a side of the interconnection part away from the substrate body, and are electrically connected to the first detection circuit through the interconnection part.

[0006] In the above-mentioned chip testing device, the chip testing device can be a probe card structure. A plurality of detection contacts can contact the pads of the chip, and then the first detection circuit can be electrically connected to the chip through the interconnection part and the detection contact. Among them, the interconnection part and the support part can be arranged on the same surface of the substrate body, and the substrate body and the interconnection part can both support the interconnection part, so as to improve the support strength of the ceramic substrate to the interconnection part. When the pad of the chip to be tested contacts the detection contact, the interconnection part is not easily damaged, thereby improving the service life of the chip testing device.

[0007] In some embodiments, the support portion is disposed around the interconnection portion.

[0008] The supporting portion may be arranged around the interconnecting portion, thereby increasing the connection area between the supporting portion and the interconnecting portion, and thereby improving the supporting strength of the supporting portion to the interconnecting portion.

[0009] In some embodiments, the number of interconnections is plural.

[0010] Among them, by arranging multiple interconnection parts in the chip testing device, the chip testing device can test multiple chips.

[0011] In some embodiments, the support portion further includes a first support portion and a second support portion, the first support portion is arranged along the edge of the substrate body, the second support portion is arranged in the first area and divides the first area into a plurality of second areas. An interconnection portion is arranged in one second area.

[0012] The number of the second supporting parts may be one or more, and the second supporting parts may separate the first area into a plurality of second areas, so as to accommodate a plurality of interconnecting parts.

[0013] In some embodiments, a first gap is formed between the interconnection portion and the support portion. The chip testing device further includes: a first filling portion, which is disposed in the first gap.

[0014] Among them, the shape of the interconnection part can be designed according to actual needs. At this time, the side surface of the interconnection part can be spaced apart from the supporting part. By setting a first filling part in the first gap between the interconnection part and the supporting part, the supporting part can be connected to the side surface of the interconnection part through the first filling part, so that the supporting part can provide support to the interconnection part through the first filling part.

[0015] In some embodiments, the interconnection portion includes an interconnection line and a dielectric material film layer, the dielectric material film layer is arranged on one side of the substrate body, the interconnection line is arranged in the dielectric material film layer, the detection contact piece is arranged on the side of the dielectric material film layer away from the substrate body, and is electrically connected to the first detection circuit through the interconnection line, wherein the side of the dielectric material film layer is connected to the support portion.

[0016] The interconnection part can be directly formed on the substrate body, thereby simplifying the preparation process of the chip testing device.

[0017] In some embodiments, the interconnection part includes an interconnection line and a dielectric material film layer, the dielectric material film layer is arranged on one side of the substrate body, the interconnection line is arranged in the dielectric material film layer, and the detection contact is electrically connected to the interconnection line. The interconnection part also includes: a filling layer and an electrical transfer part, the electrical transfer part is arranged in the filling layer, the filling layer is located between the dielectric material film layer and the substrate body, and at least part of the side surface of the filling layer is connected to the support part; wherein the interconnection line is electrically connected to the first detection circuit through the electrical transfer part.

[0018] Among them, due to the provision of the electrical transfer portion, the dielectric material film layer and the interconnection lines disposed within the dielectric material film layer can be formed independently of the ceramic substrate. For the convenience of description, the structure composed of the dielectric material film layer and the interconnection lines disposed within the dielectric material film layer is defined as the intermediate portion. Subsequently, the formed intermediate portion can be connected to the first detection circuit within the ceramic substrate through the electrical transfer portion. Thus, compared with directly forming the intermediate portion above the ceramic substrate by means of photolithography, development, and electroplating, the line width and line pitch of the interconnection lines in the intermediate portion can be set narrower and the density can be greater. Further, when a detection contact member is disposed on the side of the intermediate portion facing away from the ceramic substrate, the setting range of the detection contact member can be larger. For example, the detection contact member can include a plurality of probes arranged at intervals, and both the setting range and the density of the probes can be increased. Thus, when the chip detection device is used as a probe card structure, the detection efficiency of the chip can be improved, and since the probe pitch can better match the pad pitch of the chip, it is also beneficial to improve the reliability during detection. In addition, a filling layer is filled between the ceramic substrate and the intermediate portion and surrounds the electrical transfer portion. In this embodiment, by providing the filling layer, the electrical transfer portion can be protected, for example, to prevent water vapor erosion, etc., so the connection stability between the intermediate portion and the ceramic substrate can be enhanced.

[0019] In some embodiments, a second gap is formed between the dielectric material film layer and the support portion. The filling layer includes a first portion and a second portion. The first portion is located between the dielectric material film layer and the substrate body, and the second portion is located in the second gap, wherein the electrical transfer portion is disposed within the first portion.

[0020] Among them, the second portion is located in the second gap between the dielectric material film layer and the support portion. Thus, the support portion can support the dielectric material film layer through the second portion, thereby improving the support strength of the support portion for the interconnection portion.

[0021] In some embodiments, the chip testing device further includes: alignment marks. The alignment marks are disposed on the surface of the support portion facing away from the substrate body.

[0022] Among them, the detection contact member can be pre-formed and then transferred to the surface of the interconnection portion facing away from the substrate body. At this time, alignment marks are required to ensure that the detection contact member can be transferred to the designated position. During the process of transferring the detection contact member to the designated position, alignment marks are used for positioning. In the embodiment of the present application, by disposing the alignment marks on the support portion, the position of the support portion does not change, and thus the position of the alignment marks does not change, thereby improving the transfer accuracy of the detection contact member.

[0023] In some embodiments, an alignment mark is disposed on each side of the interconnection portion in a first direction, wherein the first direction is parallel to the substrate body.

[0024] Among them, two alignment marks are configured for each interconnection part, so as to improve the transfer accuracy of detecting the contact parts.

[0025] In some embodiments, the chip testing device further includes a printed circuit board, which is disposed on the surface of the substrate body facing away from the supporting part. The printed circuit board includes a second detection circuit, and the second detection circuit is electrically connected to the first detection circuit.

[0026] On the other hand, a chip testing system is provided, which includes a probe station and a probe card structure connected to each other. The probe card structure includes the chip testing device provided in some of the above embodiments.

[0027] Among them, the chip testing system may include the chip testing device provided in some of the above embodiments. Therefore, the chip testing system has all the beneficial effects of the chip testing device provided in some of the above embodiments, which will not be elaborated here.

[0028] On yet another aspect, a preparation method of a chip testing device is provided. The preparation method includes: forming a ceramic substrate and a first detection circuit, wherein the ceramic substrate includes a substrate body and a supporting part, the supporting part is disposed on one surface of the substrate body, and the first detection circuit is disposed within the substrate body; forming an interconnection part, the interconnection part is located on the surface of the substrate body where the supporting part is disposed, and at least part of the side surface of the interconnection part is connected to the supporting part; forming a plurality of detection contact parts, the plurality of detection contact parts are located on the side of the interconnection part facing away from the substrate body, and are electrically connected to the first detection circuit through the interconnection part.

[0029] Among them, the preparation method of the chip testing device can be used to prepare the chip testing device provided in some of the above embodiments. Therefore, the preparation method of the chip testing device has all the beneficial effects of the chip testing device provided in some of the above embodiments, which will not be elaborated here.

[0030] In some embodiments, forming the ceramic substrate and the first detection circuit includes: forming a ceramic plate and the first detection circuit, the first detection circuit is disposed within the ceramic plate; removing a part of the ceramic plate to form the ceramic substrate.

[0031] Among them, after removing a part of the ceramic base layer, the substrate body and the supporting part are formed, and the substrate body and the supporting part can constitute the ceramic substrate.

[0032] In some embodiments, a first gap is formed between the interconnection part and the supporting part. The preparation method further includes: forming a first filling part within the first gap.

[0033] Among them, the shape of the interconnection part can be designed according to actual needs. At this time, the side surface of the interconnection part can be spaced apart from the supporting part. By setting a first filling part in the first gap between the interconnection part and the supporting part, the supporting part can be connected to the side surface of the interconnection part through the first filling part, so that the supporting part can provide support to the interconnection part through the first filling part.

[0034] In some embodiments, forming the interconnection portion includes: forming an interconnection line and a dielectric material film layer, the dielectric material film layer is arranged on one side of the substrate body, and the interconnection line is arranged in the dielectric material film layer, wherein the interconnection line is electrically connected between the detection contact piece and the first detection circuit.

[0035] The interconnection part can be directly formed on the substrate body, thereby simplifying the preparation process of the chip testing device.

[0036] In some embodiments, forming the interconnection portion includes: forming an interconnection line and a dielectric material film layer on a carrier, wherein the interconnection line is disposed in the dielectric material film layer. Forming an electrical transfer portion on one side of the dielectric material film layer, wherein the electrical transfer portion is electrically connected to the interconnection line. Transferring the interconnection line and the dielectric material film layer on the carrier to one side of the substrate body, and connecting the interconnection line to the first detection circuit through the electrical transfer portion. Forming a filling layer between the dielectric material film layer and the substrate body.

[0037] Wherein, by forming interconnection lines and dielectric material film layers on the carrier. Wherein, for the convenience of description, the structure composed of the dielectric material film layer and the interconnection lines arranged in the dielectric material film layer is defined as an intermediary part. Afterwards, the formed intermediary part can be connected to the ceramic substrate through the electrical transfer part, and the interconnection lines can be electrically connected to the first detection circuit through the electrical transfer part. In this way, compared with the formation of the intermediary part directly on the ceramic substrate by light forming, developing, and electroplating methods, the line width and line spacing of the interconnection lines in the intermediary part can be set narrower and denser. Further, when the detection contact piece is set on the side of the intermediary part away from the ceramic substrate, the setting range of the detection contact piece can be larger, for example, the detection contact piece can include a plurality of probes arranged at intervals, and the setting range and density of the probes can be increased. In this way, when the chip detection device is used as a probe card structure, the detection efficiency of the chip can be improved, and because the probe spacing can be better matched with the chip pad spacing, it is also beneficial to improve the reliability during detection. In addition, the filling layer is filled between the ceramic substrate and the intermediary part and surrounds the electrical transfer part. In this embodiment, the filling layer is provided to protect the electrical transfer portion, for example, to prevent water vapor erosion, etc., thereby improving the connection stability between the intermediary portion and the ceramic substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] To more clearly illustrate the technical solutions in this application, the following will briefly introduce the accompanying drawings required for use in some embodiments of this application. Obviously, the accompanying drawings in the following description are only the accompanying drawings of some embodiments of this application. For those of ordinary skill in the art, other accompanying drawings can also be obtained based on these drawings. In addition, the accompanying drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual dimensions of the products involved in the embodiments of this application, the actual processes of the methods, the actual timings of the signals, etc.

[0039] Figure 1 Structural diagram of a chip testing device for some embodiments of this application;

[0040] Figure 2 Another structural diagram of a chip testing device for some embodiments of this application;

[0041] Figure 3 Another structural diagram of a chip testing device according to some embodiments;

[0042] Figure 4 Another structural diagram of a chip testing device according to some embodiments;

[0043] Figure 5 Another structural diagram of a chip testing device according to some embodiments;

[0044] Figure 6 Flowchart of a preparation method of a chip testing device according to some embodiments;

[0045] Figure 7 Another flowchart of a preparation method of a chip testing device according to some embodiments;

[0046] Figure 8 Another flowchart of a preparation method of a chip testing device according to some embodiments;

[0047] Figure 9 Another flowchart of a preparation method of a chip testing device according to some embodiments;

[0048] Figure 10 Another flowchart of a preparation method of a chip testing device according to some embodiments;

[0049] Figure 11 Structural block diagram of a chip testing system provided by the embodiments of this application. Detailed implementation manners

[0050] Next, in conjunction with the accompanying drawings, the technical solutions in some embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art shall fall within the protection scope of the present disclosure.

[0051] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular form "comprises" and the present participle form "comprising", are interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example", or "some examples", etc., are intended to indicate that the specific features, structures, materials, or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0052] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality" is two or more.

[0053] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or integrated; it may be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical contact or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0054] As used herein, "parallel" and "perpendicular" include the described situations as well as situations similar to the described situations, where the range of the similar situations is within an acceptable deviation range, and the acceptable deviation range is determined by those of ordinary skill in the art considering the measurements being discussed and the errors associated with the measurements of specific quantities (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism can be, for example, within a deviation of 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, within a deviation of 5°.

[0055] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0056] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of the regions are enlarged for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Therefore, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but include shape deviations caused, for example, by manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0057] During the chip manufacturing process, at least one corresponding probe card structure is required for each type of chip for testing. The purpose of the test is to ensure that after the wafer is diced, the good products will enter the next packaging process, avoiding waste caused by continued processing of defective products. As the chip integration density has increased significantly, the distance between the pads of the chip has been greatly reduced. Therefore, it is necessary to synchronously reduce the line width and line pitch of the probe card structure to reduce the distance (pitch) between the probes. In addition, in order to improve the test efficiency, the area of the probe card structure is getting larger and the number of needles required to be implanted on the probe card structure is increasing. When the probe card structure tests the chip, the probes of the probe card structure can contact the pads of the chip to be tested. At this time, the chip will exert a large pressure on the probe card structure, which will affect the service life of the probe card structure.

[0058] Based on this, an embodiment of the present application provides a chip testing device.

[0059] Figure 1 It is a structural diagram of a chip testing device 1000 according to some embodiments of the present application.

[0060] Please refer toFigure 1 The chip testing device 1000 may include a ceramic substrate 110, a first detection circuit 120, an interconnecting part 200, and a plurality of detection contacts 300. Among them, the ceramic substrate 110 includes a substrate body 111 and a support part 112. The support part 112 is disposed on one surface of the substrate body 111, and the first detection circuit 120 is disposed within the substrate body 111. The interconnecting part 200 is located on the surface of the substrate body 111 where the support part 112 is disposed, and at least a part of the side surface 201 of the interconnecting part 200 is connected to the support part 112. The plurality of detection contacts 300 are located on the side of the interconnecting part 200 away from the substrate body 111, and the plurality of detection contacts 300 are electrically connected to the first detection circuit 120 through an interconnecting line 210.

[0061] Exemplarily, the chip testing device 1000 may be a probe card structure.

[0062] The chip testing device 1000 may include a detection circuit. Exemplarily, the detection circuit may be the first detection circuit 120.

[0063] Among them, the support part 112 may be disposed on the first surface 1111 of the substrate body 111.

[0064] The interconnecting part 200 and the support part 112 may be disposed on the same surface of the substrate body 111. Exemplarily, both the interconnecting part 200 and the support part 112 may be disposed on the first surface 1111 of the substrate body 111. Among them, the substrate body 111 may support the interconnecting part 200.

[0065] The detection contact 300 may include a probe 310. Exemplarily, the probe 310 may be welded to the interconnecting line 210 of the interconnecting part 200, for example, by laser-assisted bonding (LAB) (high-temperature solder melting point (m.p.) > 260 °C).

[0066] When testing the chip, the plurality of probes 310 may contact the pads of the chip to be tested, and then the first detection circuit 120 may be electrically connected to the chip to be tested through the interconnecting part 200 and the probes 310.

[0067] The support part 112 may extend along at least a part of the edge of the interconnecting part 200. At this time, at least a part of the side surface 201 of the interconnecting part 200 faces the support part 112 and is connected to the support part 112. Among them, the above at least a part of the side surface 201 may be directly in contact with and connected to the support part 112, or the above at least a part of the side surface 201 may be indirectly connected to the support part 112. At this time, the above at least a part of the side surface 201 may be connected to the support part 112 through other structures.

[0068] Since the support part 112 can be connected to the interconnection part 200, the support part 112 can provide support for the interconnection part 200, thereby improving the support strength of the ceramic substrate 110 for the interconnection part 200. When it is detected that the contact part 300 contacts the pad of the chip to be tested, the interconnection part 200 is impacted and is not easily damaged, and thus the service life of the chip testing device 1000 can be prolonged.

[0069] In some embodiments, the support part 112 is arranged around the interconnection part 200 for one week, thereby increasing the connection area between the support part 112 and the interconnection part 200, and increasing the support strength of the support part 112 for the interconnection part 200.

[0070] Exemplarily, the support part 112 includes a first support part 1121. The first support part 1121 is arranged along the edge of the substrate main body 111 for one week, and the interconnection part 200 is arranged in the first area surrounded by the first support part 1121. At this time, the first support part 1121 and the substrate main body 111 can form a receiving groove, and the interconnection part 200 can be arranged in the receiving groove.

[0071] Of course, when the support part 112 is arranged along a part of the edge of the interconnection part 200, the support part 112 can extend along a part of the edge of the substrate main body 111.

[0072] Figure 2 Another structural diagram of the chip testing device 1000 according to some embodiments of the present application.

[0073] Please refer to Figure 2 , in some embodiments, the number of the interconnection parts 200 is multiple.

[0074] Among them, by arranging multiple interconnection parts 200 in the chip testing device 1000, the chip testing device 1000 can test multiple chips.

[0075] In some examples, multiple interconnection parts 200 can be arranged in the first area surrounded by the first support part 1121. At this time, multiple interconnection parts 200 can be connected to the first support part 1121.

[0076] Among them, a gap can be arranged between two adjacent interconnection parts 200, that is, two adjacent interconnection parts 200 are arranged at intervals.

[0077] In some embodiments, the support part 112 further includes a second support part 1122. The second support part 1122 is arranged in the first area and divides the first area into multiple second areas; one interconnection part 200 is arranged in one second area.

[0078] Among them, the number of the second support parts 1122 can be one or more. Exemplarily, when the number of the second support parts 1122 is one, one second support part 1122 can divide the first area into two second areas. The number of the interconnection parts 200 is two, and the two interconnection parts 200 are respectively arranged in the two second areas.

[0079] When the number of the second support parts 1122 is multiple, the multiple second support parts 1122 can extend along the same direction and be arranged side by side in the first area, thereby dividing the first area into multiple second areas.

[0080] In addition, when the number of the second support parts 1122 is multiple, some of the second support parts 1122 can extend along the first direction, and the rest of the second support parts 1122 can extend along the second direction, wherein the first direction and the second direction intersect and are both parallel to the substrate main body 111. Among them, the second support parts 1122 extending along the first direction and the second support parts 1122 extending along the second direction can intersect, thereby dividing the first area into multiple second areas.

[0081] Figure 3 It is another structural diagram of the chip testing device 1000 according to some embodiments.

[0082] Please refer to Figure 3 , in some embodiments, a first gap is formed between the interconnection part 200 and the support part 112. The chip testing device 1000 may further include: a first filling part 700, and the first filling part 700 is arranged in the first gap.

[0083] At this time, the side surface 201 of the interconnection part 200 can be connected to the support part 112 through the first filling part 700. At this time, the support part 112 can provide support for the interconnection part 200 through the first filling part 700.

[0084] Among them, the shape of the interconnection part 200 can be designed according to actual needs. At this time, the side surface 201 of the interconnection part 200 can be arranged at an interval from the support part 112. By arranging the first filling part 700 in the first gap between the interconnection part 200 and the support part 112, the support part 112 can be connected to the side surface of the interconnection part 200 through the first filling part 700, so that the support part 112 can provide support for the interconnection part 200 through the first filling part 700.

[0085] Such as Figures 1 to 3As shown, in some embodiments, the interconnecting portion 200 includes an interconnecting line 210 and a dielectric material film layer 220. The dielectric material film layer 220 is disposed on one side of the substrate body 111, and the interconnecting line 210 is disposed within the dielectric material film layer 220. The detection contact 300 is disposed on the side of the dielectric material film layer 220 facing away from the substrate body 111 and is electrically connected to the first detection circuit through the interconnecting line 210.

[0086] Wherein, the dielectric material film layer 220 of the interconnecting portion 200 may include a third surface 221, a fourth surface 222 and side surfaces which are disposed opposite to each other. Among them, the third surface 221 faces the substrate body 111, while the fourth surface 222 faces away from the substrate body 111, and the side surfaces are connected between the third surface 221 and the fourth surface 222. In Figure 1 the provided example, the third surface 221 may be attached to the first surface 1111 of the substrate body 111.

[0087] Wherein, a part of the interconnecting line 210 may be exposed on the fourth surface 222 of the dielectric material film layer 220, and the detection contact 300 may be electrically connected to the part of the interconnecting line 210 exposed on the fourth surface 222.

[0088] In some examples, the interconnecting line 210 may include an interconnecting wire 211 and a connecting portion 212. Among them, the interconnecting wire 211 is disposed within the dielectric material film layer 220, while the connecting portion 212 is disposed on the fourth surface 222 of the dielectric material film layer 220 and is electrically connected to the interconnecting wire. The interconnecting wire is also electrically connected to the first detection circuit. Among them, the detection contact 300 may be connected to the connecting portion 212. Thus, the detection contact 300 can be electrically connected to the first detection circuit through the connecting portion 212 and the interconnecting wire 211.

[0089] Wherein, the interconnecting portion 200 may be directly formed on the substrate body 111, thereby simplifying the preparation process of the chip testing device.

[0090] In some examples, the side surface 201 of the interconnecting portion 200 includes the side surface of the dielectric material film layer 220, and the side surface of the dielectric material film layer 220 is connected to the support portion 112.

[0091] For example, as Figure 1 and Figure 2 shown, the side surface of the dielectric material film layer 220 of the interconnecting portion 200 may be directly connected to the support portion 112.

[0092] For example, as Figure 3As shown, the side surface of the dielectric material film layer 220 of the interconnection part 200 can be indirectly connected to the support part 112. At this time, the dielectric material film layer 220 can be connected to the support part 112 through other structures. For example, the dielectric material film layer 220 can be connected to the support part 112 through the first filling part 700.

[0093] Please refer to Figures 1 to 3 , in some examples, when the interconnection part 200 includes a dielectric material film layer 220 and an interconnection line 210, the height H1 of the support part 112 in the third direction F3 is greater than or equal to the height H2 of the dielectric material film layer 220 in the third direction F3.

[0094] Among them, the part of the side surface of the dielectric material film layer 220 facing the support part 112 is connected to the support part 112 along the third direction F3, so as to improve the support strength of the support part 112 for the dielectric material film layer 220, that is, to improve the support strength of the support part 112 for the interconnection part 200.

[0095] Among them, when the support part 112 includes the first support part 1121, the height H1 of the support part 112 in the third direction F3 is the height of the first support part 1121 in the third direction F3.

[0096] When the support part 112 includes the first support part 1121 and the second support part 1122, the height of the first support part 1121 in the third direction F3 can be equal to the height of the second support part 1122 in the third direction F3.

[0097] Of course, in some other examples, the height H1 of the support part 112 in the third direction F3 can also be less than the height H2 of the dielectric material film layer 220 in the third direction F3.

[0098] Please refer to Figure 3 , the height of the first filling part 700 in the third direction F3 can be less than or equal to the height H1 of the support part 112 in the third direction F3. For example, the height of the first filling part 700 in the third direction F3 is equal to the height H1 of the support part 112 in the third direction F3.

[0099] Among them, the height of the first filling part 700 in the third direction F3 can be less than or equal to the height H2 of the dielectric material film layer 220 in the third direction F3.

[0100] Figure 4 It is another structural diagram of the chip testing device 1000 according to some embodiments. Figure 5 It is another structural diagram of the chip testing device 1000 according to some embodiments. Among them, Figure 4 the chip testing device 1000 in Figure 5The chip testing device 1000 in the embodiment includes a plurality of interconnection parts 200 .

[0101] See also Figure 4 and Figure 5 In some embodiments, the interconnection part 200 further includes: a filling layer 230 and an electrical transfer part 240, wherein the electrical transfer part 240 is disposed in the filling layer 230, the filling layer 230 is located between the dielectric material film layer 220 and the substrate body 111, and at least part of the side surface of the filling layer 230 is connected to the support part 112. The interconnection line 210 is electrically connected to the first detection circuit through the electrical transfer part 240.

[0102] The electrical adapter 240 is electrically connected between the interconnection line 210 and the first detection circuit. Therefore, the detection contact member 300 can be electrically connected to the first detection circuit through the interconnection line 210 and the electrical adapter 240 .

[0103] The side of the interconnection part 200 may include the side of the filling layer 230 . In some embodiments, the side of the filling layer 230 is connected to the support part 112 , and the support part 112 can support the interconnection part 200 , thereby improving the supporting strength of the ceramic substrate 110 for the interconnection part 200 .

[0104] The chip detection device 1000 provided in the embodiment of the present application is provided with an electrical transfer part 240, so that the dielectric material film layer 220 and the interconnection line 210 provided in the dielectric material film layer 220 can be formed independently of the ceramic substrate 110. Among them, for the convenience of description, the structure composed of the dielectric material film layer 220 and the interconnection line 210 provided in the dielectric material film layer 220 is defined as an intermediary part. Afterwards, the formed intermediary part can be connected to the first detection circuit 120 in the ceramic substrate 110 through the electrical transfer part 240. In this way, compared with directly forming the intermediary part on the ceramic substrate 110 by photoforming, developing, and electroplating methods, the line width and line spacing of the interconnection line 210 in the intermediary part can be set narrower and denser. Furthermore, when the detection contact member 300 is arranged on the side of the intermediary portion away from the ceramic substrate 110, the setting range of the detection contact member 300 can be larger. For example, the detection contact member 300 can include a plurality of probes 310 arranged at intervals, and the setting range and density of the probes 310 can be increased. In this way, when the chip detection device 1000 is used as a probe card structure, the detection efficiency of the chip can be improved, and because the probe spacing can be better matched with the chip pad spacing, it is also beneficial to improve the reliability of the detection.

[0105] Among them, the filling layer 230 is filled between the ceramic substrate 110 and the intermediate part, and surrounds the electrical transfer part 240. In this embodiment, by providing the filling layer 230, the electrical transfer part 240 can be protected, for example, to prevent moisture erosion, etc., so the connection stability between the intermediate part and the ceramic substrate 110 can be improved.

[0106] Please continue to refer to Figure 4 and Figure 5 , in some embodiments, the electrical transfer part 240 includes a plurality of solder joints 241 arranged at intervals. With such an arrangement, a plurality of solder joints 241 can be used to be soldered to the first detection circuit provided in the ceramic substrate 110, and thus the reliability after connection is high.

[0107] Please continue to refer to Figure 4 and Figure 5 , in some embodiments, a second gap is formed between the dielectric material film layer 220 and the support part 112. The filling layer 230 includes a first part 231 and a second part 232. The first part 231 is located between the dielectric material film layer 220 and the substrate main body 111, and the second part 232 is located in the second gap, wherein the electrical transfer part 240 is arranged in the first part.

[0108] Among them, the second part 232 is located in the second gap between the dielectric material film layer 220 and the support part 112. Furthermore, the support part 112 can support the dielectric material film layer 220 through the second part 232, thereby improving the support strength of the support part 112 for the interconnecting part 200.

[0109] Please continue to refer to Figure 4 and Figure 5 , in some examples, the thickness H3 of the filling layer 230 in the third direction F3 can be less than or equal to the thickness H1 of the support part 112 in the third direction F3. Among them, in the case where the filling layer 230 includes a first part 231 and a second part 232, the thickness H3 of the filling layer 230 in the third direction F3 can be equal to the sum of the thickness of the first part 231 in the third direction F3 and the thickness of the second part 232 in the third direction F3.

[0110] For example, the thickness H3 of the filling layer 230 in the third direction F3 is equal to the thickness H1 of the support part 112 in the third direction F3. With such an arrangement, the support strength provided by the support part 112 to the dielectric material film layer 220 through the second part 232 can be ensured, and thus the support strength of the ceramic substrate 110 for the interconnecting part 200 can be improved.

[0111] Of course, in some other examples, the thickness H3 of the filling layer 230 in the third direction F3 can also be greater than the thickness H1 of the support part 112 in the third direction F3.

[0112] In some examples, the thickness H3 of the filling layer 230 in the third direction F3 may be less than or equal to the thickness H1 of the support portion 112 in the third direction F3, and the thickness of the dielectric material film layer 220 in the third direction F3 may be less than or equal to the thickness of the second portion 232 in the third direction F3. With such a setting, the support strength provided by the support portion 112 to the dielectric material film layer 220 through the second portion 232 can be ensured, and thus the support strength of the ceramic substrate 110 for the interconnect portion 200 can be improved.

[0113] Of course, in some other examples, the thickness of the dielectric material film layer 220 in the third direction F3 may be greater than the thickness of the second portion 232 in the third direction F3.

[0114] In some embodiments, the chip testing device 1000 further includes: alignment marks 600. The alignment marks 600 are disposed on the surface of the support portion 112 facing away from the substrate body 111.

[0115] Among them, the detection contact 300 can be pre-formed and then transferred to the surface of the interconnect portion 200 facing away from the substrate body 111. At this time, the alignment marks 600 are required to ensure that the detection contact 300 can be transferred to the designated position.

[0116] In the related art, the alignment marks 600 are disposed on the dielectric material film layer 220, and the dielectric material film layer 220 will shrink, resulting in a change in the position of the alignment marks 600, and further resulting in an offset in the position of the detection contact 300.

[0117] In the embodiments of the present application, by disposing the alignment marks 600 on the support portion 112, the position of the support portion 112 will not change, and thus the position of the alignment marks 600 will not change, thereby improving the transfer accuracy of the detection contact 300.

[0118] Please refer to Figures 1 to 5 , in some embodiments, an alignment mark 600 is disposed on each side of the interconnect portion 200 in the first direction.

[0119] Exemplarily, two alignment marks 600 are configured for one interconnect portion 200. Among them, the two alignment marks 600 corresponding to one interconnect portion 200 can be respectively located on both sides of the interconnect portion 200 in the first direction, as Figure 1 and Figure 2 shown, and the direction indicated by the arrow F1 is the first direction F1.

[0120] Such as Figure 1 , Figure 3 and Figure 4As shown, when the support part 112 includes the first support part 1121, the alignment mark 600 can be set on a surface of the first support part 1121 facing away from the substrate body 111.

[0121] As Figure 2 and Figure 5 shown, when the support part 112 includes the first support part 1121 and the second support part 1122, part of the alignment marks 600 can be set on the first support part 1121, and the remaining part of the alignment marks 600 can be set on the second support part 1122.

[0122] In Figure 2 one of the two alignment marks 600 corresponding to one interconnect part 200 is located on the first support part 1121, and the other is located on the second support part 1122.

[0123] In Figure 5 one of the two alignment marks 600 corresponding to part of the interconnect parts 200 is located on the first support part 1121, and the other is located on the second support part 1122, and the two alignment marks 600 corresponding to the remaining part of the interconnect parts 200 are both located on the second support part 1122.

[0124] Among them, two alignment marks 600 are configured for each interconnect part 200, so as to improve the transfer accuracy of the detection contact 300.

[0125] Please refer to Figures 1 to 5 , in some embodiments, the detection circuit can include a first detection circuit 120 and a second detection circuit, and the chip testing device 1000 can also include a printed circuit board 400, and the printed circuit board 400 is arranged on the surface of the substrate body 111 facing away from the support part 112. For example, the substrate body 111 can include a first surface 1111 and a second surface 1112 arranged opposite to each other, wherein the support part 112 can be arranged on the first surface 1111, and the printed circuit board 400 can be located on the second surface 1112 of the substrate body 111.

[0126] The printed circuit board 400 can include a printed board body and a second detection circuit, wherein the second detection circuit can be arranged in the printed board body, and at this time, the second detection circuit is electrically connected to the first detection circuit 120.

[0127] For example, the first detection circuit 120 can include a connection circuit 121, and the connection circuit 121 can be arranged in the substrate body 111.

[0128] In addition, in order to facilitate the movement of the chip testing device 1000, a mounting frame 500 can also be arranged on the side of the printed circuit board 400 facing away from the ceramic substrate 110, and the structure of the mounting frame 500 can be as Figure 1As shown, the mounting bracket 500 can be connected only to a part of the surface on the side of the printed circuit board 400 facing away from the ceramic substrate 110. In this way, it is beneficial to reduce the use of materials, save costs, and can stably and reliably move the chip testing device 1000 through the mounting bracket 500. Exemplarily, a boss 510 can be formed on the side of the mounting bracket 500 facing away from the printed circuit board 400, which is convenient for the manipulator to grasp. In this way, when the chip testing device 1000 is a probe card structure, it is convenient to apply it to a chip detection system composed of testing equipment such as a probe station. Of course, in some other examples, a notch 520 convenient for grasping (the notch 520 can expose the printed circuit board 400 to facilitate better heat dissipation of the printed circuit board 400) and other structures can also be formed on the side of the mounting bracket 500 facing away from the printed circuit board 400. The present application does not limit this.

[0129] The embodiment of the present application also provides a preparation method for a chip testing device.

[0130] Figure 6 It is a flowchart of a preparation method for a chip testing device according to some embodiments.

[0131] Please refer to Figure 6 , and this preparation method includes the following steps S1 to S3.

[0132] S1. Form a ceramic substrate and a first detection circuit. Among them, the ceramic substrate includes a substrate body and a support portion. The support portion is provided on one surface of the substrate body, and the first detection circuit is provided in the substrate body.

[0133] S2. Form an interconnecting portion. The interconnecting portion is located on the surface of the substrate body where the support portion is provided, and at least part of the side surface of the interconnecting portion is connected to the support portion.

[0134] S3. Form a plurality of detection contacts. The plurality of detection contacts are located on the side of the interconnecting portion facing away from the substrate body and are electrically connected to the first detection circuit through the interconnecting portion.

[0135] Among them, the preparation method provided by some embodiments can be used to prepare the chip testing device 1000 provided by some of the above embodiments. Therefore, the preparation method of the chip testing device includes all the beneficial effects of the chip testing device 1000 provided by some of the above embodiments, which will not be elaborated here.

[0136] Figure 7 It is another flowchart of a preparation method for a chip testing device according to some embodiments.

[0137] Please refer to Figure 7 , in some embodiments, step S1 may further include the following steps S11 and S12.

[0138] S11. Form a ceramic plate and a first detection circuit, and the first detection circuit is disposed within the ceramic plate.

[0139] S12. Remove a portion of the ceramic plate to form a ceramic substrate.

[0140] Wherein, after step S12, after removing a portion of the ceramic base layer, a substrate body 111 and a support portion 112 are formed, and the substrate body 111 and the support portion 112 can constitute the ceramic substrate 110.

[0141] Exemplarily, in step S12, a portion of the ceramic base layer can be removed by an etching process.

[0142] Exemplarily, in the case where the support portion includes a first support portion 1121, after step S12, the first support portion 1121 and the substrate body 111 can be formed, wherein the first support portion 1121 can be disposed around the edge of the substrate body 111 for one week.

[0143] Exemplarily, in the case where the support portion includes a first support portion 1121 and a second support portion 1122, after step S12, the first support portion 1121, the second support portion 1122 and the substrate body 111 can be formed.

[0144] Figure 8 It is another flowchart of a preparation method of a chip testing device according to some embodiments.

[0145] Please refer to Figure 8 , and at the same time in combination with Figure 3 , in some embodiments, the chip testing device 1000 may further include a first filling portion 700, and a first gap is formed between the interconnection portion and the support portion. At this time, the preparation method further includes: S4. Form a first filling portion in the first gap.

[0146] Wherein, the shape of the interconnection portion 200 can be designed according to actual requirements. At this time, the side surface 201 of the interconnection portion 200 can be spaced apart from the support portion 112. By providing the first filling portion 700 in the first gap between the interconnection portion 200 and the support portion 112, the support portion 112 can be connected to the side surface of the interconnection portion 200 through the first filling portion 700, so that the support portion 112 can provide support for the interconnection portion 200 through the first filling portion 700.

[0147] Figure 9 It is yet another flowchart of a preparation method of a chip testing device according to some embodiments.

[0148] Please refer to Figure 9 , and at the same time in combination with Figures 1 to 3In some embodiments, the interconnection part 200 may include an interconnection line 210 and a dielectric material film layer 220. At this time, S2, forming the interconnection part includes: S21, forming an interconnection line and a dielectric material film layer, the dielectric material film layer is arranged on one side of the substrate body, and the interconnection line is arranged in the dielectric material film layer, wherein the interconnection line is electrically connected between the detection contact element and the first detection circuit.

[0149] See you later Figures 1 to 3 , wherein the interconnection portion 200 can be directly formed on the substrate body 111, thereby simplifying the preparation process of the chip testing device.

[0150] Figure 10 FIG. 4 is another flow chart of a method for preparing a chip testing device according to some embodiments.

[0151] See also Figure 10 , while combining Figure 4 and Figure 5 In some embodiments, the interconnection part 200 may include an interconnection line 210, a dielectric material film layer 220, a filling layer 230 and an electrical transfer part 240. At this time, S2, forming the interconnection part includes: the following steps S22 to S25.

[0152] S22, forming interconnection circuits and a dielectric material film layer on the carrier board, wherein the interconnection circuits are arranged in the dielectric material film layer.

[0153] S23, forming an electrical transfer portion on one surface of the dielectric material film layer, wherein the electrical transfer portion is electrically connected to the interconnection line.

[0154] S24, transferring the interconnection circuit and the dielectric material film layer on the carrier to one side of the substrate body, and connecting the interconnection circuit to the first detection circuit through the electrical transfer part.

[0155] S25, forming a filling layer between the dielectric material film layer and the substrate body.

[0156] See you later Figure 4 and Figure 5 In this embodiment, the line width and line spacing of the interconnection line 210 can be set to be narrower and denser.

[0157] The embodiment of the present application also provides a chip testing system.

[0158] Figure 11 This is a structural block diagram of the chip testing system provided in an embodiment of the present application.

[0159] See also Figure 11, based on the chip testing device 1000 provided by some of the above embodiments, an embodiment of the present application provides a chip testing system 2000. The chip detection system 2000 includes: a probe station 1001 and a probe card structure 1002 connected to each other, and the probe card structure 1002 includes the chip testing device 1000 provided by some of the above embodiments.

[0160] This embodiment provides a chip detection system 2000. Since it includes the chip testing device 1000 provided by some of the above embodiments, therefore, the chip detection system 2000 has all the beneficial effects of the chip testing device 1000 provided by some of the above embodiments, which will not be elaborated here.

[0161] As described above, only the specific implementation manners of the present application are provided, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application, who thinks of changes or substitutions, should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip testing device, It is characterized in that include: A ceramic substrate and a first detection circuit, wherein the ceramic substrate comprises a substrate body and a support portion, the support portion is arranged on one surface of the substrate body, and the first detection circuit is arranged in the substrate body; An interconnection portion, located on a surface of the substrate body on which the support portion is disposed, and at least part of a side surface of the interconnection portion is connected to the support portion; A plurality of detection contact members are located on a side of the interconnection portion away from the substrate body and are electrically connected to the first detection circuit through the interconnection portion.

2. The chip testing device according to claim 1, It is characterized in that The supporting portion is arranged around the interconnecting portion.

3. The chip testing device according to claim 1, It is characterized in that The number of the interconnection parts is plural.

4. The chip testing device according to claim 3, It is characterized in that The support portion includes a first support portion and a second support portion, wherein the first support portion is arranged along the edge of the substrate body, and the second support portion is arranged in a first area and divides the first area into a plurality of second areas; One of the interconnecting parts is arranged in one of the second regions.

5. The chip testing device according to any one of claims 1 to 4, It is characterized in that A first gap is formed between the interconnection portion and the support portion; The chip testing device further includes: a first filling portion, wherein the first filling portion is disposed in the first gap.

6. The chip testing device according to any one of claims 1 to 5, It is characterized in that The interconnection portion includes an interconnection circuit and a dielectric material film layer, the dielectric material film layer is arranged on one side of the substrate body, the interconnection circuit is arranged in the dielectric material film layer, the detection contact piece is arranged on the side of the dielectric material film layer away from the substrate body, and is electrically connected to the first detection circuit through the interconnection circuit, wherein the side surface of the dielectric material film layer is connected to the support portion.

7. The chip testing device according to any one of claims 1 to 4, It is characterized in that The interconnection part includes an interconnection line and a dielectric material film layer, the dielectric material film layer is arranged on one side of the substrate body, the interconnection line is arranged in the dielectric material film layer, and the detection contact element is electrically connected to the interconnection line; The interconnection part also includes: a filling layer and an electrical transfer part, the electrical transfer part is arranged in the filling layer, the filling layer is located between the dielectric material film layer and the substrate body, and at least part of the side surface of the filling layer is connected to the supporting part; wherein the interconnection line is electrically connected to the first detection circuit through the electrical transfer part.

8. The chip testing device according to claim 6, It is characterized in that A second gap is formed between the dielectric material film layer and the supporting portion; The filling layer includes a first part and a second part, the first part is located between the dielectric material film layer and the substrate body, the second part is located in the second gap, and the electrical switching portion is arranged in the first part.

9. The chip testing device according to any one of claims 1-8, characterized in that, further comprising: alignment marks; The alignment marks are disposed on the surface of the support portion facing away from the substrate body.

10. The chip testing device according to claim 9, characterized in that, One alignment mark is provided on each of the two sides of the interconnect portion in a first direction, wherein the first direction is parallel to the substrate body.

11. The chip testing device according to any one of claims 1-10, characterized in that, further comprising: a printed circuit board, the printed circuit board is disposed on the surface of the substrate body facing away from the support portion, the printed circuit board includes a second detection circuit, and the second detection circuit is electrically connected to the first detection circuit.

12. A chip testing system, characterized in that, comprising: A probe station and a probe card structure connected to each other, the probe card structure includes the chip testing device according to any one of claims 1-11.

13. A method for manufacturing a chip testing device, characterized in that, forming a ceramic substrate and a first detection circuit, wherein the ceramic substrate includes a substrate body and a support portion, the support portion is disposed on one surface of the substrate body, and the first detection circuit is disposed within the substrate body; forming an interconnect portion, the interconnect portion is located on the surface of the substrate body where the support portion is disposed, and at least a part of the side surface of the interconnect portion is connected to the support portion; forming a plurality of detection contacts, the plurality of detection contacts are located on the side of the interconnect portion facing away from the substrate body, and are electrically connected to the first detection circuit through the interconnect portion.

14. The manufacturing method according to claim 13, characterized in that, The forming of the ceramic substrate and the first detection circuit includes: forming a ceramic plate and the first detection circuit, the first detection circuit is disposed within the ceramic plate; removing a part of the ceramic plate to form the ceramic substrate.

15. The manufacturing method according to claim 13 or 14, characterized in that, a first gap is formed between the interconnect portion and the support portion; The manufacturing method further includes: forming a first filling portion within the first gap.

16. The manufacturing method according to any one of claims 13-15, characterized in that, The forming of the interconnect portion includes: forming an interconnect line and a dielectric material film layer, the dielectric material film layer is disposed on one side of the substrate body, the interconnect line is disposed within the dielectric material film layer, wherein the interconnect line is electrically connected between the detection contact and the first detection circuit.

17. The manufacturing method according to claim 13 or 14, characterized in that, The forming of the interconnect portion includes: forming an interconnect line and a dielectric material film layer on a carrier plate, the interconnect line is disposed within the dielectric material film layer; forming an electrical transfer portion on one surface of the dielectric material film layer, the electrical transfer portion is electrically connected to the interconnect line; transferring the interconnect line and the dielectric material film layer on the carrier plate to one side of the substrate body, and connecting the interconnect line to the first detection circuit through the electrical transfer portion; A filling layer is formed between the dielectric material film layer and the substrate body.

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