Control circuit for realizing low power consumption of hardware of motor controller of automobile electronic part

Abstract

The invention relates to a control circuit for realizing low hardware power consumption of a motor controller of an automobile electronic part. The control circuit comprises an external power supply input Vm and a main chip power supply Vs, the triode Q9 is used for controlling the on-off of a chip power supply Vs so as to realize low power consumption of hardware; the IGN signal input circuit comprises a filter circuit and an MOS (Metal Oxide Semiconductor) tube Q10 and is used for controlling the conduction of the MOS tube Q10 through an IGN signal so as to control the conduction of a triode Q9 and realize hardware low-power-consumption wakeup of the IGN signal; the PWM signal input circuit / LIN signal input circuit controls the conduction of an MOS tube Q8 through the falling edge of a PWM signal / LIN signal, generates a PWMCtrl signal, further controls the conduction of an MOS tube Q10 and a triode Q9, achieves the hardware low-power wakeup of the PWM signal / LIN signal, is additionally provided with a triode Q12 for controlling the sleep time, and enables the MOS tube Q10 to be closed through the conduction of the triode Q12. The circuit not only can be compatible with a hardware low-power-consumption capacitor for realizing IGN, LIN or PWM wake-up modes, but also can realize a latch function and rapid dormancy.

Description

Technical Field

[0001] The present invention relates to the technical field of automotive electronic components, and specifically to a control circuit for realizing hardware low power consumption of a motor controller of an automotive electronic component. Background Art

[0002] As the requirements for low power consumption of automotive components by vehicle manufacturers are becoming increasingly strict, starting from the initial low power consumption current requirement of less than 1 mA, to the current requirement of less than 100 μA, and in the future, the low power consumption current requirement for motor controller components may be less than 50 μA. Under the increasingly strict low power consumption requirements, it is becoming increasingly difficult to achieve low power consumption through software, and the low power consumption current of the chip is required to be lower and lower. Implementing low power consumption through software is relatively complex.

[0003] Considering the increasingly high requirements for low power consumption, hardware low power consumption can well solve this problem. The way to achieve hardware low power consumption is to directly power off the chip and supply power to the chip through a specific wake-up signal. However, the existing hardware low power consumption scheme uses a KEY button to wake up, which is not suitable for the wake-up method of automotive components, and the existing technology scheme lacks flexibility. Summary of the Invention

[0004] Due to the very small low power consumption requirement value, the sleep current is required to be less than <30 μA, and it is required to be able to be woken up separately by the IGN signal or the PWM signal. When the IGN signal is absent, the PWM signal can independently control the motor operation. When the PWM signal is absent, the IGN signal can control the motor to run at full speed. Therefore, in view of the above problems, the present invention provides a control circuit for realizing hardware low power consumption of a motor controller of an automotive electronic component that can be compatible with and implement three wake-up methods: IGN, LIN, or PWM, and is very flexible to use.

[0005] The technical solution adopted by the present invention to solve the above technical problems is: a control circuit for realizing hardware low power consumption of a motor controller of an automotive electronic component,

[0006] It includes an external power input Vm and a main chip power supply Vs, and the main chip power supply Vs is used to supply power to the main chip; the external power input Vm is connected in parallel with two filter capacitors C41 and C42 after passing through a current-limiting resistor R39 and then flows out in two paths. One path is connected to the E pole of a triode Q9, and the triode Q9 is used to control the on-off of the chip power supply Vs to achieve hardware low power consumption. The other path flows into the C pole of a triode Q11 and the D pole of a MOS tube Q10 respectively through series-connected current-limiting resistors R41 and R42. At the same time, the D pole of the MOS tube Q10 and the C pole of the triode Q11 are connected in parallel to one end of the current-limiting resistor R42, the other end of the current-limiting resistor R42 is connected to the B pole of the triode Q9, and the S pole of the MOS tube Q10 and the E pole of the triode Q11 are both grounded. The B pole of the triode Q11 is connected in parallel with a current-limiting resistor R50 and a pull-down resistor R52, and one end of the current-limiting resistor R52 and the E pole of the triode Q11 are both grounded;

[0007] The IGN signal input circuit includes a filter circuit and a MOS tube Q10, and is used to control the conduction of the MOS tube Q10 through the IGN signal, and further control the conduction of the triode Q9 to achieve the hardware low power consumption wake-up of the IGN signal;

[0008] The PWM signal input circuit includes voltage-dividing resistors R38, R40 and a MOS tube Q8, and is used to control the conduction of the MOS tube Q8 through the falling edge of the PWM signal to generate a high-level PWM_Ctrl signal, and further control the conduction of the MOS tube Q10 and the triode Q9 to achieve the hardware low power consumption wake-up of the PWM signal;

[0009] The LIN signal input circuit is used to control the conduction of the MOS tube Q8 through the falling edge of the LIN signal by adjusting the resistance values of the voltage-dividing resistors R38, R40 to generate a high-level PWM_Ctrl signal, and further control the conduction of the MOS tube Q10 and the triode Q9 to achieve the hardware low power consumption wake-up of the LIN signal;

[0010] The MOS tubes Q8, Q10 are voltage control devices and are turned on through a very small current to ensure the low power consumption of the wake-up source.

[0011] Preferably, the IGN_Ctrl signal reaches the G pole of the MOS transistor Q10 along the transmission path successively through the series-connected current-limiting resistor R43, diode D15, and current-limiting resistor R48. The PWM_Ctrl signal reaches the G pole of the MOS transistor Q10 along the transmission path successively through the series-connected current-limiting resistor R49, diode D16, and current-limiting resistor R48. The diode D15 and the diode D16 are connected in parallel to one end where the signal of the current-limiting resistor R48 is input. At the same time, a pull-down resistor R51 and a filter capacitor C43 are connected in parallel to one end where the signal of the current-limiting resistor R48 is input. The output end of the current-limiting resistor R48 is connected in parallel to the G pole of the MOS transistor Q10 with a protection zener diode D17. The filter capacitor C43 can eliminate the noise of the IGN_Ctrl signal and the PWM_Ctrl signal, ensuring the stable input of these two signals.

[0012] Preferably, the D pole of the MOS transistor Q8 is connected to the voltage-dividing resistor R38, and the G pole of the MOS transistor Q8 is connected to the voltage-dividing resistor R40. The PWM signal reaches the G pole of the MOS transistor Q8 through the voltage-dividing resistor R40 and reaches the power supply signal VBAT from the voltage-dividing resistor R38, turning on the MOS transistor Q8 to achieve level conversion, making PWM_Ctrl a high level. The resistance values of the voltage-dividing resistors R38 and R40 can be adjusted according to actual application requirements to achieve different wake-up level thresholds.

[0013] Preferably, the falling-edge wake-up circuit of the PWM signal input circuit or the LIN signal input circuit further includes pull-up resistors R44 and R45. The pull-up resistors R44 and R45 are connected in parallel to the diode D13. Among them, the parallel value of the pull-up resistors R44 and R45 in the LIN signal input circuit is changed to 30K. At the same time, the other ends of the pull-up resistors R44 and R45 are connected to a magnetic bead. The power supply signal VBAT reaches the pull-up resistors R44 and R45 through the diode D13, and then pulls the PWM signal or the LIN signal to the VBAT high level through the magnetic bead, making the MOS transistor Q8 non-conductive and the PWM_Ctrl signal low level, thereby controlling the non-conduction of the triode Q9 to achieve sleep.

[0014] Preferably, a latch circuit is further included, which is used to generate an IG_LOCK signal through the main chip to turn on the triode Q11 after waking up, so that one end of the current-limiting resistor R42 is pulled to GND, and the triode Q9 is turned on, thereby latching the chip power supply Vs.

[0015] Preferably, it further includes a fast sleep electronic lock. A triode Q12 is included in the fast sleep circuit. The C pole of the triode Q12 is connected to one ends of diodes D15 and D16. The E pole of the triode Q12 is grounded. The B pole of the triode Q12 is shunted with a current-limiting resistor R55 and a pull-down resistor R56. Meanwhile, the end of the pull-down resistor R56 away from the triode Q12 is grounded. During sleep, the main chip generates an Unlock signal which is introduced into the triode Q12 through the shunted current-limiting resistor R55 and pull-down resistor R56 to control the conduction of the triode Q12, turn off the MOS tube Q10, and disconnect the chip power supply Vs to achieve fast sleep.

[0016] Preferably, the IGN signal becomes an IGN_Ctrl signal through a bead FB3.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] The present invention can be compatible with and implement hardware low-power capacitors for three wake-up modes of IGN, LIN or PWM, and is very flexible in use. The specific features are as follows:

[0019] 1. It has a latching function and can flexibly control the sleep time after the absence of a wake-up source according to customer requirements. After waking up, the main chip can control the IG_LOCK signal, reach the test point through the current-limiting resistor R50, shunt the pull-down resistor R52, turn on the triode Q11, pull one end of the current-limiting R42 to GND, turn on the triode Q9, and latch the chip power supply Vs. When going to sleep, a fast sleep path of the triode Q12 is added. The Unlock signal generated by the main chip reaches the test point through the current-limiting resistor R55 and is connected to the pull-down resistor R56, making the triode Q12 conduct, thereby turning off the MOS tube Q10 and unlocking the IG_LOCK signal to achieve fast sleep;

[0020] 2. The requirement for the holding time of the wake-up source is very short, only 10 us at the fastest. The switching tube on the wake-up source side is a MOS tube. This MOS tube is a voltage control device and only needs to consume an extremely small current (in the ua level) to turn on. And anti-backflow diodes D15 and D16 are added, enabling the wake-up source to achieve wake-up only in an extremely short time (in the us level). At the same time, since the wake-up signals IGN_Ctrl and PWM_Ctrl cannot have current backflow, they can always wake up when a normal control signal is given. Theoretically, the software does not need to control the latching pin IG_LOCK;

[0021] 3. The wake-up level can be flexibly configured through resistors. Assuming that the turn-on voltage of MOS transistor Q8 is Gth, the turn-on level V of the wake-up signal is V = VBAT - (Gth / R38) * (R38 + R40). Therefore, the resistance values of the two voltage-dividing resistors R38 and R40 can be adjusted according to actual application requirements to achieve different wake-up level thresholds. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic diagram of the control circuit in the present invention;

[0023] Figure 2 is a schematic diagram of the ING signal acquisition circuit;

[0024] Figure 3 is a schematic diagram of the PWM and LIN signal acquisition circuits;

[0025] Figure 4 is a schematic diagram of the level inversion circuit for wake-up at the falling edge of PWM and LIN communications. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] The following will be combined with Figures 1-4 to describe the present invention in detail. Here, the schematic embodiments of the present invention and the descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0027] A control circuit for realizing hardware low power consumption of a motor controller of an automotive electronic component, which includes an external power input Vm and a main chip power supply Vs, and the main chip power supply Vs is used to supply power to the main chip;

[0028] The external power input Vm is connected in parallel with two filter capacitors C41 and C42 after passing through a current-limiting resistor R39 and then flows out in two paths. One path is connected to the E pole of a triode Q9, and the triode Q9 is used to control the on and off of the chip power supply Vs to achieve hardware low power consumption. One path flows into the C pole of a triode Q11 and the D pole of a MOS transistor Q10 respectively through series current-limiting resistors R41 and R42. At the same time, the D pole of the MOS transistor Q10 and the C pole of the triode Q11 are connected in parallel to one end of the current-limiting resistor R42. The other end of the current-limiting resistor R42 is connected to the B pole of the triode Q9, and the S pole of the MOS transistor Q10 and the E pole of the triode Q11 are both grounded. The B pole of the triode Q11 is connected in parallel with a current-limiting resistor R50 and a pull-down resistor R52, and one end of the pull-down resistor R52 and the E pole of the triode Q11 are both grounded;

[0029] The IGN signal input circuit includes a filter circuit and a MOS transistor Q10, and is used to control the conduction of the MOS transistor Q10 through the IGN signal, and further control the conduction of the triode Q9 to achieve hardware low power consumption wake-up of the IGN signal, wherein the IGN signal becomes an IGN_Ctrl signal through a bead FB3;

[0030] The PWM signal input circuit includes voltage-dividing resistors R38, R40 and MOS transistor Q8, and is used to control the conduction of MOS transistor Q8 through the falling edge of the PWM signal, generate a high-level PWM_Ctrl signal, and further control the conduction of MOS transistor Q10 and triode Q9 to achieve hardware low-power wake-up of the PWM signal.

[0031] The LIN signal input circuit is used to control the conduction of MOS transistor Q8 through the falling edge of the LIN signal by adjusting the resistance values of the voltage-dividing resistors R38, R40, generate a high-level PWM_Ctrl signal, and further control the conduction of MOS transistor Q10 and triode Q9 to achieve hardware low-power wake-up of the LIN signal.

[0032] The D pole of MOS transistor Q8 is connected to the voltage-dividing resistor R38, the G pole of MOS transistor Q8 is connected to the voltage-dividing resistor R40, the PWM signal passes through the voltage-dividing resistor R40 to the G pole of MOS transistor Q8, and from the voltage-dividing resistor R38 to the power supply signal VBAT, the MOS transistor Q8 is turned on to achieve level conversion, making PWM_Ctrl at a high level.

[0033] The falling-edge wake-up circuit of the PWM signal input circuit or the LIN signal input circuit further includes pull-up resistors R44, R45. The pull-up resistors R44, R45 are connected in parallel to diode D13. The parallel value of the pull-up resistors R44, R45 in the LIN signal input circuit is changed to 30K. At the same time, the other ends of the pull-up resistors R44, R45 are connected to a bead. The power supply signal VBAT reaches the pull-up resistors R44, R45 through diode D13, and then pulls the PWM signal or the LIN signal to the VBAT high level through the bead, making MOS transistor Q8 non-conductive and the PWM_Ctrl signal at a low level, and further controlling triode Q9 not to conduct to achieve sleep.

[0034] Specifically, the IGN_Ctrl signal travels along the transmission path and sequentially passes through the series-connected current-limiting resistor R43, diode D15, and current-limiting resistor R48 to reach the G pole of MOS transistor Q10. The PWM_Ctrl signal travels along the transmission path and sequentially passes through the series-connected current-limiting resistor R49, diode D16, and current-limiting resistor R48 to reach the G pole of MOS transistor Q10. Diode D15 and diode D16 are connected in parallel to one end of the current-limiting resistor R48 where the signal is input. At the same time, a pull-down resistor R51 and a filter capacitor C43 are connected in parallel to one end of the current-limiting resistor R48 where the signal is input. The other end of the current-limiting resistor R48 where the signal is output is connected in parallel to the protection zener diode D17 to the G pole of MOS transistor Q10.

[0035] Specifically, it further includes a latch circuit, which is used to turn on triode Q11 through the main chip to generate an IG_LOCK signal after wake-up, so that one end of the current-limiting resistor R42 is pulled to GND, and triode Q9 is turned on, thereby latching the chip power supply Vs.

[0036] It also includes a fast sleep circuit. The fast sleep circuit includes a triode Q12. The C pole of the triode Q12 is connected to one end of diodes D15 and D16. The E pole of the triode Q12 is grounded. The B pole of the triode Q12 is connected in parallel with a current-limiting resistor R55 and a pull-down resistor R56. At the same time, the end of the pull-down resistor R56 far from the triode Q12 is grounded. During sleep, the main chip generates an Unlock signal, which is introduced into the triode Q12 through the parallel-connected current-limiting resistor R55 and pull-down resistor R56, used to control the conduction of the triode Q12, turn off the MOS tube Q10, and disconnect the chip power supply Vs to achieve fast sleep.

[0037] During the implementation process, as Figures 1-4 shown, Figure 1 In it, Vm is the external power supply input. After passing through the current-limiting resistor R39, two filter capacitors C41 and C42 are connected in parallel to the test point TP46. It is divided into two paths. One path is connected to the E pole of the triode Q9, and the other path passes through the current-limiting resistor R41 to the test point TP50, and then through the current-limiting resistor R42 to the C pole of the triode Q11 and the D pole of the MOS tube Q10. When giving the IGN signal, the IGN_Ctrl signal passes through the current-limiting resistor R43 and the diode D15 to the test point TP55, is connected in parallel with the pull-down resistor R51 and the filter capacitor C43, passes through the current-limiting resistor R48 to the test point TP58, is connected in parallel with the protective voltage-regulating diode D17, and reaches one end G pole of the MOS tube Q10, making the MOS tube Q10 conduct, pulling TP51 to the ground, making the E and C poles of Q9 conduct, and supplying power to the main chip power supply Vs, thereby realizing the hardware low-power wake-up of the IGN signal.

[0038] PWM communication: During sleep, VBAT passes through the diode D13 to IP, then through the pull-up resistors R44 and R45 to TP1, and through the bead FB1 to TP53, pulling the PWM signal to VBAT, making Figure 1 the triode Q9 non-conductive, achieving hardware low power consumption. When the first falling edge of the PWM communication occurs, through Figure 4 the circuit, the PWM signal passes through the voltage-dividing resistor R40 to the G pole of the MOS tube Q8, from the voltage-dividing resistor R38 to VBAT, making the MOS tube Q8 conduct, making PWM_Ctrl high (if the PWM is a rising-edge wake-up, the Figure 4 circuit is not required. As Figure 3 shown in the circuit, the PWM signal can be directly used as the wake-up source. Figure 4The circuit can be blank-mounted), generating a control signal PWM_Ctrl and transmitting it to the control circuit. The PWM_Ctrl signal passes through the current-limiting resistor R49 to the test point TP56, through the diode D16 to the test point TP55, in parallel with the pull-down resistor R51 and the filter capacitor C43, through the current-limiting resistor R48 to the test point TP58 in parallel with the protective zener diode D17, and reaches the G pole of the MOS transistor Q10, causing the MOS transistor Q10 to conduct, pulling TP51 to the ground, causing the E pole and C pole of the transistor Q9 to conduct, supplying the power of Vs, and thus waking up.

[0039] LIN communication: One of the pull-up resistors R44 and R45 needs to be changed to 30K, and the other is not mounted. When LIN communication is idle, it is pulled to a high level, causing Figure 1 the transistor Q9 not to conduct. During communication, when the first falling edge occurs, through Figure 4 the circuit, the PWM signal passes through the voltage-dividing resistor R40 to the G pole of the MOS transistor Q8, from the voltage-dividing resistor R38 to VBAT, turning on the MOS transistor Q8, making PWM_Ctrl at a high level (if PWM wakes up on the rising edge, this circuit is not needed Figure 4 circuit, and the PWM signal can be directly used as the wake-up source, as Figure 3 shown), the PWM_Ctrl signal passes through the current-limiting R49 to TP56, through the diode D16 to the test point TP55, in parallel with the pull-down resistor R51 and the filter capacitor C43, through the current-limiting resistor R48 to the test point TP58 in parallel with the protective zener diode D17, and reaches the G pole of the MOS transistor Q10, causing the MOS transistor Q10 to turn on, pulling the test point TP51 to the ground, causing the E pole and C pole of the transistor Q9 to conduct, supplying the power of Vs, and thus waking up.

[0040] The wake-up level threshold can be configured by the resistance values of the voltage-dividing resistors R38 and R40. The turn-on level V of the wake-up signal = VBAT - (Gth / R38) * (R38 + R40), where Gth is the turn-on voltage of the MOS transistor Q8. Since the PWM and LIN signals generally wake up at a low level, Figure 4 the circuit needs to perform an inversion process. After the PWM or LIN signal is input, it passes through the voltage-dividing resistor R40 to the MOS transistor Q8, and through the MOS transistor Q8, a signal PWM_Ctrl at a high level is generated for level inversion to control the control circuit.

[0041] The present invention has a latching function and can flexibly control the sleep time after the absence of a wake-up source according to customer requirements. After wake-up, the main chip can control the IG_LOCK signal, which reaches the test point TP57 through the current-limiting resistor R50 and is shunted with the pull-down resistor R52 to turn on the triode Q11, causing one end of the current-limiting resistor R42 to be pulled to GND, turning on the triode Q9, and latching the chip power supply Vs. When going to sleep, the Unlock signal generated by the main chip reaches the test point through the current-limiting resistor R55 and is connected in parallel with the pull-down resistor R56, turning on the triode Q12, pulling the test point TP55 to GND, thereby turning off the MOS transistor Q10 and unlocking the IG_LOCK signal, enabling fast sleep;

[0042] In addition, the holding time requirement for the wake-up source is very short, only 10 us at the fastest. The switching transistor on the wake-up source side is a MOS transistor. This MOS transistor is a voltage-controlled device and only needs to consume an extremely small current (in the ua level) to turn on. And the anti-conduction diodes D15 and D16 are added, enabling the wake-up source to achieve wake-up in only an extremely short time (in the us level). At the same time, since the currents of the wake-up signals IGN_Ctrl and PWM_Ctrl cannot flow back, it can be continuously woken up when the control signal is normally given. Theoretically, the software does not need to control the latching pin IG_LOCK.

[0043] The technical solutions provided by the embodiments of the present invention have been introduced in detail above. Specific examples are used in this article to elaborate on the principles and implementation manners of the embodiments of the present invention. The descriptions of the above embodiments are only applicable to help understand the principles of the embodiments of the present invention; at the same time, for those of ordinary skill in the art, according to the embodiments of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A control circuit for realizing hardware low power consumption of a motor controller of an automotive electronic component, characterized in that: It includes an external power input Vm and a main chip power supply Vs, wherein the main chip power supply Vs is used to supply power to the main chip; The external power input Vm passes through the current limiting resistor R39 and is connected in parallel with two filter capacitors C41 and C42 and then flows out in two ways, one of which is connected to the E pole of the transistor Q9. The transistor Q9 is used to control the on and off of the chip power supply Vs to achieve low power consumption of the hardware, and the other flows into the C pole of the transistor Q11 and the D pole of the MOS transistor Q10 through the series-connected current limiting resistors R41 and R42, and at the same time, the D pole of the MOS transistor Q10 and the C pole of the transistor Q11 are connected in parallel to one end of the current limiting resistor R42, and the other end of the current limiting resistor R42 is connected to the B pole of the transistor Q9, and the S pole of the MOS transistor Q10 and the E pole of the transistor Q11 are both connected to the ground, and the B pole of the transistor Q11 is connected in parallel with the current limiting resistor R50 and the pull-down resistor R52, and one end of the current limiting resistor R52 and the E pole of the transistor Q11 are both grounded; The IGN signal input circuit includes a filter circuit and a MOS tube Q10, which is used to control the conduction of the MOS tube Q10 through the IGN signal, and then control the conduction of the triode Q9 to achieve hardware low-power wake-up of the IGN signal; The PWM signal input circuit includes voltage-dividing resistors R38 and R40 and MOS tube Q8, which is used to control the conduction of MOS tube Q8 through the falling edge of the PWM signal, generate a high-level PWM_Ctrl signal, and then control the conduction of MOS tube Q10 and transistor Q9 to achieve hardware low-power wake-up of the PWM signal; The LIN signal input circuit controls the conduction of the MOS tube Q8 through the falling edge of the LIN signal by adjusting the resistance values ​​of the voltage-dividing resistors R38 and R40, generates a high-level PWM_Ctrl signal, and then controls the conduction of the MOS tube Q10 and the transistor Q9, thereby realizing the hardware low-power wake-up of the LIN signal.

2. The motor controller of the automotive electronic component according to claim 1 realizes a control circuit of hardware low power consumption, characterized in that: The IGN_Ctrl signal passes through the series-connected current limiting resistor R43, the diode D15, and the current limiting resistor R48 in sequence along the transmission path to reach the G pole of the MOS tube Q10. The PWM_Ctrl signal passes through the series-connected current limiting resistor R49, the diode D16, and the current limiting resistor R48 in sequence along the transmission path to reach the G pole of the MOS tube Q10. The diode D15 and the diode D16 are connected in parallel to one end of the current limiting resistor R48 signal input. At the same time, a pull-down resistor R51 and a filter capacitor C43 are connected in parallel to one end of the current limiting resistor R48 signal input. The signal output end of the current limiting resistor R48 is connected in parallel with the protection voltage regulator tube D17 to the G pole of the MOS tube Q10.

3. The motor controller of the automotive electronic component according to claim 1 realizes the control circuit of hardware low power consumption, characterized in that: The D-pole of the MOS tube Q8 is connected to the voltage-dividing resistor R38, and the G-pole of the MOS tube Q8 is connected to the voltage-dividing resistor R40. The PWM signal passes through the voltage-dividing resistor R40 to the G-pole of the MOS tube Q8, and from the voltage-dividing resistor R38 to the power supply signal VBAT, turning on the MOS tube Q8 to realize level conversion, so that PWM_Ctrl is a high level.

4. The motor controller of the automotive electronic component according to claim 1 realizes the control circuit of hardware low power consumption, characterized in that: The falling edge wake-up circuit of the PWM signal input circuit or the LIN signal input circuit also includes pull-up resistors R44 and R45, which are connected in parallel to the diode D13, wherein the parallel value of the pull-up resistors R44 and R45 in the LIN signal input circuit is changed to 30K, and the other ends of the pull-up resistors R44 and R45 are connected to magnetic beads, and the power supply signal VBAT reaches the pull-up resistors R44 and R45 through the diode D13, and then the PWM signal or LIN signal is pulled to the VBAT high level through the magnetic beads, so that the MOS tube Q8 is not turned on, and the PWM_Ctrl signal is at a low level, thereby controlling the transistor Q9 to be turned off to achieve sleep.

5. The motor controller of the automotive electronic component according to claim 1 realizes the control circuit of hardware low power consumption, characterized in that: It also includes a latch circuit, which is used to generate an IG_LOCK signal through the main chip to turn on the transistor Q11 after waking up, so that one end of the current limiting resistor R42 is pulled to GND, and the transistor Q9 is turned on, thereby latching the chip power supply Vs.

6. The control circuit for realizing hardware low power consumption of the motor controller of the automotive electronic component according to claim 1, characterized in that: It also includes a fast sleep circuit, which includes a transistor Q12, a C pole of the transistor Q12 is connected to one end of the diodes D15 and D16, an E pole of the transistor Q12 is grounded, a B pole of the transistor Q12 is connected in parallel with a current limiting resistor R55 and a pull-down resistor R56, and at the same time, an end of the pull-down resistor R56 away from the transistor Q12 is grounded. When in sleep mode, the main chip generates an Unlock signal, which is transmitted to the transistor Q12 through the parallel current limiting resistor R55 and the pull-down resistor R56, and is used to control the conduction of the transistor Q12, turn off the MOS tube Q10, and disconnect the chip power supply Vs to achieve fast sleep.

7. The control circuit for realizing hardware low power consumption of the motor controller of the automotive electronic component according to claim 1, characterized in that: The IGN signal is converted into an IGN_Ctrl signal through the magnetic bead FB3.

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