Combined reset device, display system and combined reset method

Abstract

The invention relates to the technical field of digital system reset, and discloses a combined reset device, a display system and a combined reset method.The combined reset device comprises a watchdog chip and a first AND logic gate chip; the input end of the watchdog chip is connected with a pulse width modulation output pin of the microprocessor, and the output end of the watchdog chip is connected with the first input end of the first AND logic gate chip; the second input end of the first AND logic gate chip is connected with a hardware reset signal output pin, the output end of the first AND logic gate chip is connected with a reset pin of the microprocessor, and the hardware reset signal output pin is further connected with a reset pin of the field programmable gate array chip. And the first AND logic gate chip is used for outputting a third reset signal when receiving the first reset signal and / or the second reset signal so as to indicate the microprocessor to perform reset operation. According to the invention, the microprocessor not only has a function of simultaneously resetting external hardware with the FPGA, but also has a watchdog function.

Description

Technical Field

[0001] The present invention relates to the technical field of digital system reset, and in particular, to a combined reset device, a display system and a combined reset method. Background Art

[0002] A digital system refers to a system that processes, transmits, stores, and controls information through digital signals. In the design of digital systems, an architecture combining a Field Programmable Gate Array (FPGA) and a microprocessor has been increasingly widely used. The FPGA is mainly used to implement high-speed data processing, and the microprocessor mainly implements functions such as system process control, human-computer interaction, external communication, and FPGA control.

[0003] Currently, when a digital system fails, the FPGA and the microprocessor are reset separately. For example, the FPGA is reset by an automatic reset restart circuit, and the microprocessor with an ARM architecture is reset by an externally connected watchdog chip. However, the existing external hardware reset and watchdog reset each have limitations and are difficult to well meet the requirements of the digital system for reset and fault monitoring and recovery. Summary of the Invention

[0004] In view of this, the present invention provides a combined reset device, a display system and a combined reset method to improve the problem that the existing external hardware reset and watchdog reset each have limitations and are difficult to well meet the requirements of the digital system for reset and fault monitoring and recovery.

[0005] In a first aspect, the present invention provides a combined reset device. The combined reset device includes a watchdog chip and a first AND logic gate chip. The input end of the watchdog chip is connected to the pulse width modulation output pin of the microprocessor, and the output end of the watchdog chip is connected to the first input end of the first AND logic gate chip. Among them, the watchdog chip outputs a first reset signal when detecting an abnormality of the microprocessor. The second input end of the first AND logic gate chip is connected to the hardware reset signal output pin, and the output end of the first AND logic gate chip is connected to the reset pin of the microprocessor. Among them, the hardware reset signal output pin is also connected to the reset pin of the field programmable gate array chip. The hardware reset signal output pin outputs a second reset signal when an external hardware is abnormal. The first AND logic gate chip is used to output a third reset signal when receiving the first reset signal and / or the second reset signal to instruct the microprocessor to perform a reset operation.

[0006] The combined reset device provided in this embodiment, through the mutual cooperation of the first AND logic gate chip and the watchdog chip, enables the microprocessor to not only have the external hardware reset function simultaneously with the FPGA, but also have the watchdog function, thereby improving the convenience of resetting the digital system (such as a display system), facilitating multiple reset options for the digital system, and enhancing security.

[0007] In an alternative embodiment, the watchdog chip includes a watchdog process detector, a watchdog timer, a resistor, and a reset generator; the input terminal of the watchdog process detector forms the input terminal of the watchdog chip, the output terminal of the watchdog process detector is connected to the input terminal of the watchdog timer, the output terminal of the watchdog timer is connected to the first input terminal of the reset generator in series with the resistor, and the output terminal of the reset generator forms the output terminal of the watchdog chip; the watchdog process detector is configured to output a reset signal when receiving a watchdog feeding signal output from the pulse width modulation output pin to reset the count value of the watchdog timer, the watchdog timer is configured to output an overflow signal when not receiving the watchdog feeding signal within a first preset duration, and the reset generator is configured to convert the overflow signal into a first reset signal.

[0008] In an alternative embodiment, the watchdog chip further includes a comparator and a second AND logic gate chip; the output terminal of the watchdog timer is connected to the first input terminal of the second AND logic gate chip, and the output terminal of the second AND logic gate chip is connected to the first input terminal of the reset generator in series with the resistor; the first input terminal of the comparator is connected to the power supply voltage terminal of the microprocessor, the second input terminal of the comparator is connected to the reference potential terminal and then grounded, and the output terminal of the comparator is connected to the second input terminal of the reset generator and the second input terminal of the second AND logic gate chip.

[0009] In this embodiment, in addition to the basic timing reset function, the watchdog chip also monitors the power supply voltage of the microprocessor. When the power supply voltage is lower than the normal operating range, the watchdog chip will also trigger a reset operation to protect the microprocessor from abnormal environmental conditions.

[0010] In an alternative embodiment, the first AND logic gate chip includes a NOT logic gate, a NAND logic gate, a first buffer, a second buffer, and a third buffer; the input terminal of the first buffer forms the first input terminal of the first AND logic gate chip, and the output terminal of the first buffer is connected to the first input terminal of the NAND logic gate; the input terminal of the second buffer forms the second input terminal of the first AND logic gate chip, and the output terminal of the second buffer is connected to the second input terminal of the NAND logic gate; the output terminal of the NAND logic gate is connected to the input terminal of the third buffer, the output terminal of the third buffer is connected to the input terminal of the NOT logic gate, and the output terminal of the NOT logic gate forms the output terminal of the first AND logic gate chip.

[0011] In this embodiment, a first AND logic chip is constituted by a NOT logic gate, a NAND logic gate, a first buffer, a second buffer, and a third buffer, which can enhance the driving ability, optimize the signal, and improve the stability of the first AND logic chip in processing signals.

[0012] In a second aspect, the present invention provides a display system, which includes a microprocessor, a field programmable gate array chip, a display screen, and the combined reset device according to the first aspect or any corresponding embodiment thereof; the microprocessor and the field programmable gate array chip are electrically connected, the field programmable gate array chip and the display screen are electrically connected, the microprocessor performs a reset operation when receiving a third reset signal, and the field programmable gate array chip performs a reset operation when receiving a second reset signal.

[0013] In this embodiment, the display system adopts an architecture combining a microprocessor and a field programmable gate array chip. When processing complex image and video tasks, the field programmable gate array chip can share the work of the microprocessor, can quickly process the input data and output it to the display screen, has extremely low latency, and can improve the refresh rate of the display screen.

[0014] In an optional embodiment, the microprocessor is further configured to receive first display data from an electronic device, perform format conversion and encoding processing on the first display data to obtain second display data, and transmit the second display data to the field programmable gate array chip.

[0015] In an optional embodiment, the field programmable gate array chip is further configured to receive the second display data from the microprocessor and process the second display data to meet the driving requirements of the display screen.

[0016] In an optional embodiment, the microprocessor is a microprocessor with a reduced instruction set computer architecture.

[0017] In an optional embodiment, the display screen is an organic light emitting diode display screen.

[0018] In a third aspect, the present invention provides a combined reset method, which is applied to the microprocessor of the display system according to the second aspect or any corresponding embodiment thereof. The combined reset method includes: sending a dog feeding signal to the watchdog chip every second preset duration; performing a reset operation when receiving a third reset signal sent by the first AND logic gate chip, where the first AND logic gate chip generates the third reset signal when receiving a first reset signal output by the watchdog chip and / or a second reset signal output by the hardware reset signal output pin. Description of the Drawings

[0019] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the related art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 is a schematic structural diagram of a combined reset device according to an embodiment of the present invention;

[0021] Figure 2 is a schematic structural diagram of another combined reset device according to an embodiment of the present invention;

[0022] Figure 3 is a schematic structural diagram of yet another combined reset device according to an embodiment of the present invention;

[0023] Figure 4 is a schematic structural diagram of still another combined reset device according to an embodiment of the present invention;

[0024] Figure 5 is a schematic structural diagram of a display system according to an embodiment of the present invention;

[0025] Figure 6 is a schematic flowchart of a combined reset method according to an embodiment of the present invention.

[0026] Reference numerals: 100, combined reset device; 110, watchdog chip; 111, watchdog process detector; 112, watchdog timer; 113, resistor; 114, reset generator; 115, comparator; 116, second AND logic gate chip; 117, reference potential terminal; 120, first AND logic gate chip; 121, NOT logic gate; 122, NAND logic gate; 123, first buffer; 124, second buffer; 125, third buffer; 200, microprocessor; 210, pulse width modulation output pin; 220, first reset pin; 300, field programmable gate array chip; 310, second reset pin; 410, hardware reset signal output pin; 500, display screen; 1000, display system. Detailed Embodiments

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0028] At present, in a digital system (such as a display system) combined with a microprocessor and an FPGA, the microprocessor generally externally connects a watchdog chip for reset, and the FPGA uses an automatic reset and restart circuit for reset. The reset of the watchdog chip is relatively passive and will only act after detecting system anomalies, lacking initiative and operational portability. The automatic reset and restart circuit only forces the states of chips such as the FPGA to be restored to the initial state under specific external conditions, and cannot detect errors that may occur inside the chip in real time and issue a restart signal in a timely manner.

[0029] In view of this, the present invention provides a combined reset device, which enables the microprocessor to not only have the function of external hardware reset simultaneously with the FPGA, but also have the watchdog function, improving the reliability of the digital system.

[0030] The following will describe in detail the structure of the combined reset device provided by the present invention with reference to the accompanying drawings.

[0031] As Figure 1 shown, the combined reset device 100 provided by the present invention includes a watchdog chip 110 and a first AND logic gate chip 120.

[0032] Among them, the input terminal (Watch-Dog Input, WDI) of the watchdog chip 110 is connected to the pulse width modulation (Pulse Width Modulation, PWM) output pin 210 of the microprocessor 200, the output terminal (Watch-Dog Output, WDO) of the watchdog chip 110 is connected to the first input terminal of the first AND logic gate chip 120, the second input terminal of the first AND logic gate chip 120 is connected to the hardware reset signal output pin 410, the output terminal of the first AND logic gate chip 120 is connected to the reset pin of the microprocessor 200, and the hardware reset signal output pin 410 is also connected to the reset pin of the field programmable gate array chip 300. For the convenience of distinction, the reset pin of the microprocessor 200 is denoted as the first reset pin 220, and the reset pin of the field programmable gate array chip 300 is denoted as the second reset pin 310.

[0033] It should be understood that PWM is a method of digitally encoding the level of an analog signal, and by adjusting the pulse width (i.e., the duty cycle) of the output square wave, it equivalently controls the average voltage or current of the output signal, thereby realizing the control of various physical quantities such as the brightness of a light. The PWM output pin 210 is a hardware interface for outputting the modulated pulse signal. There are usually dedicated pins marked as PWM on different microcontrollers, microprocessors, or other integrated circuit chips for connecting external devices or circuits that require PWM control.

[0034] Specifically, when the watchdog chip 110 detects an abnormality of the microprocessor 200, it outputs a first reset signal, and when there is an abnormality in the external hardware, the hardware reset signal output pin 410 outputs a second reset signal. The first AND logic gate chip 120 is used to output a third reset signal when receiving the first reset signal and / or the second reset signal to instruct the microprocessor 200 to perform a reset operation. Among them, in Figure 1 Hardware_RES represents the second reset signal, #RESET represents the first reset signal, and MCU_RES represents the third reset signal.

[0035] In this embodiment, the reset signal (i.e., the first reset signal, the second reset signal, and the third reset signal) can be a low-level signal. During the operation of the microprocessor 200 and the field programmable gate array chip 300, if the hardware reset signal output pin 410 outputs a low-level signal, the field programmable gate array chip 300 performs a reset operation to return the hardware and software of the field programmable gate array chip 300 to the initial state; if the hardware reset signal output pin 410 outputs a high-level signal, the field programmable gate array chip 300 does not perform a reset operation and continues to run.

[0036] If either one or both of the output terminals of the hardware reset signal output pin 410 and the watchdog chip 110 output a low-level signal, the first AND logic gate chip 120 outputs a low-level signal to trigger the microprocessor 200 to perform a reset operation to return the hardware and software of the microprocessor 200 to the initial state. If the output terminals of the hardware reset signal output pin 410 and the watchdog chip 110 are both high-level signals at the same time, the first AND logic gate chip 120 outputs a high-level signal. At this time, the microprocessor 200 does not perform a reset operation and continues to run.

[0037] Exemplarily, the external hardware can be an input device (such as a keyboard, a mouse, or a microphone, etc.), an output device (such as a display or a speaker, etc.), or a storage device, etc. The hardware reset signal output pin 410 can be a pin on a central processing unit (CPU) or other controller. The central processing unit or other controller can generate the second reset signal when the user presses a physical reset button, or can also trigger and generate the second reset signal after the external power management circuit detects an abnormality.

[0038] The combined reset device provided in this embodiment, through the mutual cooperation of the first AND logic gate chip and the watchdog chip, can enable the microprocessor to not only have the function of externally resetting the hardware with the FPGA at the same time, but also have the watchdog function, thereby improving the convenience of resetting the digital system (such as a display system), being beneficial to the digital system to perform multiple reset selections, and improving the security.

[0039] In some embodiments, such as Figure 2 shown, the watchdog chip 110 includes a watchdog process detector 111, a watchdog timer 112, a resistor 113, and a reset generator 114.

[0040] Among them, the input end of the watchdog process detector 111 constitutes the input end of the watchdog chip 110. The output end of the watchdog process detector 111 is connected to the input end of the watchdog timer 112. The output end of the watchdog timer 112 is connected to the first input end of the reset generator 114 after being connected in series with the resistor 113. The output end of the reset generator 114 constitutes the output end of the watchdog chip 110.

[0041] The watchdog process detector 111 is configured to output a reset signal when receiving the watchdog signal output from the pulse width modulation output pin 210, so as to reset the count value of the watchdog timer 112. The watchdog timer 112 is configured to output an overflow signal when not receiving the watchdog signal within a first preset duration. The reset generator 114 is configured to convert the overflow signal into a first reset signal.

[0042] The first preset duration can be configured by designers according to the actual operating conditions and requirements of the microprocessor. The setting of the first preset duration needs to ensure that during the normal operation of the microprocessor, the watchdog timer 112 will not overflow during normal task execution, and at the same time can be triggered in time when the microprocessor has an abnormality. For example, the first preset duration can be 30s, 1min, 2min, etc.

[0043] Exemplarily, the watchdog timer 112 can be a hardware timer or a timer function implemented based on software. The hardware timer can be provided with a clock signal by a dedicated clock source to ensure the accuracy and stability of its timing. The software timer relies on mechanisms such as the clock interrupt of the display system to implement the timing function.

[0044] Specifically, during the normal operation of the microprocessor, the "watchdog feeding" operation will be regularly performed before the watchdog timer 112 overflows. The "watchdog feeding" operation refers to writing specific data or executing specific instructions (the watchdog signal in this embodiment) to the relevant register of the watchdog timer 112 to reset the count value of the watchdog timer 112 and make it start timing again. In this way, as long as the microprocessor is operating normally, the watchdog feeding operation will be performed on time, and the watchdog timer 112 will not generate an overflow signal.

[0045] If the microprocessor experiences an exception for some reason, such as a runaway program, entering an infinite loop, or a hardware failure, and cannot output a watchdog signal, the watchdog process detector 111 cannot output a reset signal, and the watchdog timer 112 will generate an overflow signal after the set time interval (i.e., the first preset duration) arrives. After receiving the overflow signal generated by the watchdog timer 112, the reset generator 114 generates a first reset signal to trigger the microprocessor 200 to perform a reset operation.

[0046] In this embodiment, through the watchdog process detector 111, the watchdog timer 112, the resistor 113, and the reset generator 114, the operating state of the microprocessor can be monitored, and the microprocessor 200 can be triggered to reset in an abnormal state, which can prevent the microprocessor from continuing to run in an abnormal state, resulting in data loss, device damage, or other more serious problems.

[0047] Furthermore, as Figure 3 shown, the watchdog chip 110 further includes a comparator 115 and a second AND logic gate chip 116.

[0048] Among them, the output end of the watchdog timer 112 is connected to the first input end of the second AND logic gate chip 116, and the output end of the second AND logic gate chip 116 is connected to the first input end of the reset generator 114 in series with the resistor 113. The first input end of the comparator 115 is connected to the power supply voltage terminal VCC of the microprocessor 200, the second input end of the comparator 115 is connected to the reference potential terminal 117 and then grounded, and the output end of the comparator 115 is connected to the second input end of the reset generator 114 and the second input end of the second AND logic gate chip 116. The voltage of the reference potential terminal 117 can be configured by the designer according to actual requirements.

[0049] Specifically, the comparator continuously monitors the power supply voltage of the microprocessor 200. When the power supply voltage is lower than the voltage of the reference potential terminal 117, it will also trigger the reset generator 114 to generate a first reset signal, causing the microprocessor 200 to enter the reset state.

[0050] In this embodiment, in addition to the basic timing reset function, the watchdog chip 110 also monitors the power supply voltage of the microprocessor 200. When the power supply voltage is lower than the normal operating range, the watchdog chip 110 will also trigger a reset operation to protect the microprocessor 200 from the influence of abnormal environmental conditions.

[0051] In some embodiments, the first AND logic gate chip 120 can be directly composed of AND logic gates.

[0052] In other embodiments, as Figure 4As shown, the first AND logic gate chip 120 may also include a NOT logic gate 121, a NAND logic gate 122, a first buffer 123, a second buffer 124, and a third buffer 125.

[0053] Among them, the input end of the first buffer 123 constitutes the first input end of the first AND logic gate chip 120, and the output end of the first buffer 123 is connected to the first input end of the NAND logic gate 122. The input end of the second buffer 124 constitutes the second input end of the first AND logic gate chip 120, and the output end of the second buffer 124 is connected to the second input end of the NAND logic gate 122. The output end of the NAND logic gate 122 is connected to the input end of the third buffer 125, the output end of the third buffer 125 is connected to the input end of the NOT logic gate 121, and the output end of the NOT logic gate 121 constitutes the output end of the first AND logic gate chip 120.

[0054] Specifically, the buffer can enhance the driving ability of the signal, isolate the front and rear stage circuits, and reduce the mutual influence between the front and rear stage circuits. At the same time, the buffer has a shaping effect on the signal, and can shape the irregular signal into a standard logic level signal. When the signal is distorted during transmission, it can recover clear high and low levels after passing through the buffer, enabling the NOT logic gate 121 and the NAND logic gate 122 to accurately identify the signal.

[0055] In this embodiment, the first AND logic gate chip 120 is constituted by the NOT logic gate 121, the NAND logic gate 122, the first buffer 123, the second buffer 124, and the third buffer 125, which can enhance the driving ability and optimize the signal, and improve the stability of the first AND logic gate chip 120 in processing signals.

[0056] The present invention also provides a display system, as Figure 5 shown, the display system 1000 includes a microprocessor 200, a field programmable gate array chip 300, a display screen 500, and the combined reset device 100 provided in any of the above embodiments.

[0057] Among them, the microprocessor 200 and the field programmable gate array chip 300 are electrically connected, the field programmable gate array chip 300 and the display screen 500 are electrically connected, the microprocessor 200 performs a reset operation when receiving a third reset signal, and the field programmable gate array chip 300 performs a reset operation when receiving a second reset signal.

[0058] Specifically, the field programmable gate array (FPGA) chip 300 is a programmable logic device, which contains a large number of configurable logic units and rich wiring resources inside, and can realize various different logic functions through programming.

[0059] Exemplarily, the microprocessor 200 can be a microprocessor of the Advanced RISC Machines (ARM) architecture. The microprocessor of the ARM architecture features low power consumption, low cost, and high performance. It has a complete instruction set and rich peripheral interfaces, enabling convenient connection to various external devices. It can be responsible for running the operating system, implementing various complex control algorithms, performing data processing and transmission, etc.

[0060] Exemplarily, the display screen 500 can be an Organic Light-Emitting Diode (OLED) display screen.

[0061] Based on the principle of electroluminescence, the OLED display screen uses indium tin oxide (ITO) transparent electrodes and metal electrodes as the anode and cathode respectively, with organic thin films such as an electron transport layer, a hole transport layer, and a light-emitting layer in between. Under the drive of a certain voltage, electrons are injected from the cathode and holes are injected from the anode into the corresponding transport layers respectively, and then migrate to the light-emitting layer to meet and combine to form excitons. The excitons radiatively transition and release energy to generate visible light. Simply put, when an electric current passes through the organic material coating, the organic material emits light to display an image.

[0062] The OLED display screen has the characteristics of self-luminescence, does not require a backlight, can achieve independent pixel light control, has a fast response speed, has no smear when displaying moving images, can be manufactured on different substrate materials, can be made into a flexible and bendable display, has low energy consumption, and higher luminous efficiency.

[0063] Exemplarily, the microprocessor 200 is also used to receive the first display data from the electronic device, and to perform format conversion and encoding processing on the first display data to obtain the second display data, and then transmit the second display data to the field programmable gate array chip 300. The field programmable gate array chip 300 is also used to receive the second display data from the microprocessor 200, and to process the second display data to meet the driving requirements of the display screen 500.

[0064] Specifically, the microprocessor 200 can collect the data to be displayed (i.e., the first display data) from an electronic device (such as a mobile phone or a computer) through various interfaces, such as a Universal Serial Bus (USB) interface, an Ethernet interface, a Serial Peripheral Interface (SPI), etc. The first display data can be in various forms, such as images, texts, video streams, etc. After obtaining the first display data, the microprocessor 200 is further configured to perform format conversion and encoding processing on the first display data for subsequent transmission and display. For example, converting image data in the Red Green Blue (RGB) format into a specific format recognizable by an OLED display screen, or performing decoding operations on a video stream. Among them, the first display data after format conversion and encoding processing is the second display data.

[0065] After obtaining the second display data, the microprocessor 200 can generate corresponding display instructions according to the content and effect to be displayed, such as instructions for setting the display position, font size, color, etc. And transmit the display instructions together with the second display data to the field programmable gate array chip 300. The microprocessor 200 and the field programmable gate array chip 300 can use a high-speed communication interface for data transmission, such as a high-speed parallel bus, SPI, Inter-Integrated Circuit (I2C), or USB.

[0066] After receiving the display instructions and the second display data, in order to improve the display effect, the field programmable gate array chip 300 can perform some enhancement and optimization processing on the second display data, such as contrast adjustment, brightness adjustment, color correction, etc. The field programmable gate array chip 300 is also configured to generate the pixel data required by the display screen according to the display instructions and the preprocessed second display data, and generate accurate timing signals through a clock module for controlling operations such as the refresh frequency, row scanning, and column scanning of the display screen.

[0067] In this embodiment, the display system adopts an architecture combining the microprocessor 200 and the field programmable gate array chip 300. When processing complex image and video tasks, the field programmable gate array chip 300 can share the work of the microprocessor, can quickly process the input data and output it to the display screen, has extremely low latency, and can improve the refresh frequency of the display screen.

[0068] In this embodiment, a combined reset method is provided, which can be used for the microprocessor of the above display system. Figure 6 It is a schematic flowchart of a combined reset method according to an embodiment of the present invention. As Figure 6 shown, the method includes the following steps:

[0069] Step S601: Send a watchdog feeding signal to the watchdog chip every second preset duration.

[0070] Among them, the second preset duration can be configured by the designer based on the actual operating conditions and requirements of the microprocessor, and the second preset duration can be less than or equal to the first preset duration.

[0071] Step S602: Perform a reset operation when receiving the third reset signal sent by the first AND logic gate chip.

[0072] Among them, the first AND logic gate chip generates a third reset signal when receiving the first reset signal output by the watchdog chip and / or the second reset signal output by the hardware reset signal output pin.

[0073] Specifically, when the second reset signal is output by the hardware reset signal output pin 410 and / or the first reset signal is output by the watchdog chip, it will trigger the microprocessor to perform a reset operation.

[0074] For the combined reset method provided in this embodiment, the microprocessor not only has the function of external hardware reset simultaneously with the FPGA, but also has the watchdog function, which can improve the reliability of the display system.

[0075] In the present invention, unless otherwise clearly specified and defined, the terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two components or the interaction relationship between two components, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0076] It should be understood that each part of the present invention can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following well-known technologies in the art can be used: discrete logic circuits with logic gate circuits for implementing logical functions on data signals, application-specific integrated circuits with appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0077] In the description of this specification, the descriptions referring to terms such as "this embodiment", "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0078] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of such features. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0079] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the present invention.

Claims

1. A combined reset device, characterized in that: The combined reset device comprises a watchdog chip and a first AND logic gate chip; The input end of the watchdog chip is connected to the pulse width modulation output pin of the microprocessor, and the output end of the watchdog chip is connected to the first input end of the first AND logic gate chip, wherein the watchdog chip outputs a first reset signal when detecting an abnormality of the microprocessor; The second input end of the first AND logic gate chip is connected to the hardware reset signal output pin, and the output end of the first AND logic gate chip is connected to the reset pin of the microprocessor, wherein the hardware reset signal output pin is also connected to the reset pin of the field programmable gate array chip, and the hardware reset signal output pin outputs a second reset signal when there is an abnormality in the external hardware. The first AND logic gate chip is used to output a third reset signal when receiving the first reset signal and / or the second reset signal to instruct the microprocessor to perform a reset operation.

2. The combined reset device according to claim 1, characterized in that: The watchdog chip includes a watchdog process detector, a watchdog timer, a resistor and a reset generator; The input end of the watchdog process detector constitutes the input end of the watchdog chip, the output end of the watchdog process detector is connected to the input end of the watchdog timer, the output end of the watchdog timer is connected to the first input end of the reset generator after being connected in series with a resistor, and the output end of the reset generator constitutes the output end of the watchdog chip; The watchdog process detector is used to output a reset signal when receiving a dog feeding signal output by the pulse width modulation output pin to reset the count value of the watchdog timer. The watchdog timer is used to output an overflow signal when the dog feeding signal is not received within a first preset time period. The reset generator is used to convert the overflow signal into the first reset signal.

3. The combined reset device according to claim 2, characterized in that: The watchdog chip also includes a comparator and a second AND logic gate chip; The output end of the watchdog timer is connected to the first input end of the second AND logic gate chip, and the output end of the second AND logic gate chip is connected to the first input end of the reset generator after a resistor is connected in series; The first input terminal of the comparator is connected to the power supply voltage terminal of the microprocessor, the second input terminal of the comparator is connected to the reference potential terminal and then grounded, and the output terminal of the comparator is connected to the second input terminal of the reset generator and the second input terminal of the second AND logic gate chip.

4. The combined reset device according to any one of claims 1 to 3, characterized in that: The first AND logic gate chip includes a NOT logic gate, a NAND logic gate, a first buffer, a second buffer and a third buffer; The input end of the first buffer constitutes the first input end of the first AND logic gate chip, and the output end of the first buffer is connected to the first input end of the NAND logic gate; The input end of the second buffer constitutes the second input end of the first AND logic gate chip, and the output end of the second buffer is connected to the second input end of the NAND logic gate; The output end of the NAND logic gate is connected to the input end of the third buffer, the output end of the third buffer is connected to the input end of the NOT logic gate, and the output end of the NOT logic gate constitutes the output end of the first AND logic gate chip.

5. A display system, characterized in that: The display system comprises a microprocessor, a field programmable gate array chip, a display screen and a combined reset device as described in any one of claims 1 to 4; The microprocessor is electrically connected to the field programmable gate array chip, the field programmable gate array chip is electrically connected to the display screen, the microprocessor performs a reset operation upon receiving a third reset signal, and the field programmable gate array chip performs a reset operation upon receiving a second reset signal.

6. The display system according to claim 5, characterized in that: The microprocessor is also used for receiving first display data from the electronic device, and for performing format conversion and encoding processing on the first display data to obtain second display data, and transmitting the second display data to the field programmable gate array chip.

7. The display system according to claim 6, characterized in that: The field programmable gate array chip is also used to receive second display data from the microprocessor, and to process the second display data to meet the driving requirements of the display screen.

8. The display system according to any one of claims 5 to 7, characterized in that: The microprocessor is a microprocessor of a reduced instruction set computer architecture.

9. The display system according to any one of claims 5 to 7, characterized in that: The display screen is an organic light emitting diode display screen.

10. A combined reset method, characterized in that: A microprocessor applied to a display system according to any one of claims 5 to 9, wherein the combined reset method comprises: Sending a dog feeding signal to the watchdog chip every second preset time period; When receiving the third reset signal sent by the first AND logic gate chip, a reset operation is performed, wherein the first AND logic gate chip generates the third reset signal when receiving the first reset signal output by the watchdog chip and / or the second reset signal output by the hardware reset signal output pin.

Images