Hardware design method and device, equipment, storage medium and program product

Abstract

The invention discloses a hardware design method and device, equipment, a storage medium and a program product, and the method comprises the steps: analyzing a function demand of target hardware according to design description information corresponding to the target hardware through a first intelligent agent, and generating function point information, performing module division processing based on the function correlation of each function point in the function point information to obtain module function information, and generating design description information of each sub-module and connection relation information among the sub-modules based on the module function of each sub-module indicated by the module function information; hardware design codes of the corresponding sub-modules are generated based on the design description information of the sub-modules through the second intelligent agent; through a third agent, according to the design description information and the connection relation information of each sub-module and the hardware design code of each sub-module, a hardware design code of the target hardware is obtained through combination; the accuracy of generating hardware design codes (namely RTL design codes) of large-scale complex hardware can be improved.

Description

Technical Field

[0001] This application relates to a hardware design method, device, equipment, storage medium and program product, belonging to the technical field of hardware design. Background Art

[0002] Inspired by the recent successful applications of large language models (LLMs) such as ChatGPT in multiple fields, researchers are eagerly exploring their potential in agile hardware design, especially using large language models to automatically generate register transfer level (RTL) designs according to natural language instructions. However, the hardware design code (i.e., RTL design code) automatically generated by large language models currently has the problem of small circuit scale and low accuracy when generating RTL design codes for large-scale complex hardware. Summary of the Invention

[0003] This application provides a hardware design method, device, equipment, storage medium and program product, which can improve the accuracy of the hardware design code (i.e., RTL design code) for large-scale complex hardware and realize the automatic generation of the RTL design code for large-scale complex hardware.

[0004] On the one hand, an embodiment of this application provides a hardware design method, specifically including:

[0005] Obtain the design description information required for the target hardware to be designed;

[0006] Through a first intelligent agent, analyze the functional requirements of the target hardware according to the design description information corresponding to the target hardware and generate the functional point information corresponding to the target hardware; wherein, the functional point information includes at least one functional point, and one functional point is used to represent one function of the target hardware;

[0007] Through the first intelligent agent, perform module division processing based on the functional relevance of each functional point in the functional point information to obtain the module function information corresponding to the target hardware; wherein, the module function information is used to indicate each sub-module obtained by division and the module functions of each sub-module;

[0008] Through the first intelligent agent, based on the module functions of each sub-module indicated by the module function information, generate the design description information of each sub-module and the connection relationship information between each sub-module;

[0009] Through a second intelligent agent, generate the hardware design code of the corresponding sub-module based on the design description information of each sub-module respectively;

[0010] Through a third intelligent agent, according to the design description information of each sub-module, the connection relationship information between each sub-module, and the hardware design code of each sub-module, the hardware design code of the target hardware is combined.

[0011] On the one hand, an embodiment of the present application provides a hardware design device, and the device includes:

[0012] An acquisition unit, configured to acquire design description information required for designing a target hardware;

[0013] A processing unit, configured to analyze the function requirements of the target hardware and generate function point information corresponding to the target hardware through a first intelligent agent according to the design description information corresponding to the target hardware; wherein, the function point information includes at least one function point, and one function point is used to characterize a function of the target hardware;

[0014] The processing unit is further configured to perform module division processing based on the functional relevance of each function point in the function point information through the first intelligent agent to obtain module function information corresponding to the target hardware; wherein, the module function information is used to indicate each sub-module obtained by division and the module functions of each sub-module;

[0015] The processing unit is further configured to generate design description information of each sub-module and connection relationship information between each sub-module through the first intelligent agent based on the module functions of each sub-module indicated by the module function information;

[0016] The processing unit is further configured to generate hardware design codes of corresponding sub-modules respectively through a second intelligent agent based on the design description information of each sub-module;

[0017] The processing unit is further configured to combine the hardware design code of the target hardware through a third intelligent agent according to the design description information of each sub-module, the connection relationship information between each sub-module, and the hardware design code of each sub-module.

[0018] On the one hand, an embodiment of the present application provides a computer device, the computer device includes a communication interface, and the computer device further includes:

[0019] A processor and a computer-readable storage medium;

[0020] The computer-readable storage medium is configured to store a computer program;

[0021] The processor is configured to run the computer program to implement the above-mentioned hardware design method.

[0022] On the one hand, an embodiment of the present application provides a computer-readable storage medium storing a computer program, which is adapted to be loaded and executed by a processor to perform the above-mentioned hardware design method.

[0023] On the one hand, an embodiment of the present application provides a computer program product including a computer program, which is adapted to be loaded and executed by a processor to perform the above-mentioned hardware design method.

[0024] In the embodiment of the present application, the first agent can perform design decomposition according to the design description information corresponding to the target hardware to obtain the design description information of at least one sub-module and the connection relationship information between the sub-modules, and the second agent can generate the hardware design code of the corresponding sub-module based on the design description information of each sub-module respectively. The third agent can combine the design description information of each sub-module, the connection relationship information between the sub-modules, and the hardware design code of each sub-module to obtain the hardware design code of the target hardware; it can realize the automatic generation of the hardware design code of the target hardware (i.e., RTL design code) from the design description information (i.e., Spec) of the target hardware described in natural language, which can accelerate the hardware development process, improve the hardware development efficiency, and save the hardware development time; the design decomposition, code generation, and module combination functions are realized through multiple agents, the function point information is generated based on the design description information corresponding to the target hardware, and the module division process is performed based on the functional relevance of each function point in the function point information, which can improve the accuracy of each sub-module obtained by division, and reduce the complexity of generating the RTL design code of a single module through sub-module division, which can improve the accuracy of generating the RTL design code of large-scale complex hardware and realize the automatic generation of the RTL design code of large-scale complex hardware. Description of the Drawings

[0025] Figure 1 It is a schematic flow chart of a hardware design method provided by an embodiment of the present application;

[0026] Figure 2 It is a schematic diagram of iteratively generating a hardware design code provided by an embodiment of the present application;

[0027] Figure 3 It is a schematic diagram of generating a hardware design code based on an iterative error correction mechanism provided by an embodiment of the present application;

[0028] Figure 4 It is a schematic structural diagram of a hardware design device provided by an embodiment of the present application;

[0029] Figure 5 It is a schematic structural diagram of a computer device provided by an embodiment of the present application. Detailed Embodiments

[0030] Next, in combination with the accompanying drawings in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and in no way limits the present application or its application or use. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application. Unless otherwise specified, the relative arrangements, numerical expressions, and numerical values of the components and steps set forth in these embodiments do not limit the scope of the present disclosure. At the same time, it should be understood that, for the sake of convenience of description, the sizes of the various parts shown in the drawings are not drawn in actual proportional relationships. Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the said technologies, methods, and devices should be regarded as part of the specification. In all the examples shown and discussed here, any specific value should be construed as merely exemplary and not as a limitation. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that: similar symbols and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings. At the same time, in the description of the embodiments of the present application, the terms "first", "second", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features.

[0031] Artificial Intelligence (AI) is a technology that studies, develops theories, methods, technologies, and application systems for simulating, extending, and expanding human intelligence. It attempts to understand the essence of intelligence and produce a new intelligent machine that can respond in a way similar to human intelligence. Artificial intelligence technologies can include several major directions such as computer vision technology (Computer Vision, CV), speech processing technology (Speech Technology), natural language processing technology (Nature Language processing, NLP), and machine learning (Machine Learning, ML) / deep learning. Among them, machine learning technology is the core of artificial intelligence, and deep learning technology is a technology that uses deep neural network systems for machine learning. Machine learning technology and deep learning technology can include technologies such as artificial neural networks, belief networks, reinforcement learning, transfer learning, inductive learning, and teaching learning. The pre-trained model (Pre-training model, PTM, also known as the large model, foundation model) developed based on deep learning technology is trained on a large amount of unlabeled data. After fine-tuning (finetune), the pre-trained model can be widely applied to downstream tasks in various directions of artificial intelligence. According to the data modalities processed, pre-trained models can be divided into language models (such as GPT, BERT), visual models (such as V-MOE), speech models (such as VALL-E, ViT), multi-modal models (such as ViBERT, Flamingo, Gato), etc. Among them, multi-modal models refer to models that establish feature representations of two or more data modalities. The fine-tuning techniques of pre-trained models can include supervised fine-tuning (Supervised Fine-Tuning, SFT), instruction tuning, parameter-efficient fine-tuning (PEFT), etc. Among them, large language models (Large Language Models, LLMs) are an important tool in the current field of natural language processing, capable of generating text related to a given input. These models are pre-trained on large-scale corpora and fine-tuned according to human preferences, learning rich language knowledge and world knowledge, and can be transferred in a wide range of tasks through generalization ability. Current large language models can be used for various tasks such as text generation, question answering systems, code writing, translation, etc.

[0032] Embodiments of this application provide a hardware design method based on artificial intelligence technology. The method can implement design decomposition, code generation, and module combination functions through multiple large language model-based agents, reducing the complexity of generating hardware design code (i.e., RTL design code) for a single module and improving the accuracy of generating RTL design code for large-scale complex hardware. The hardware design method can be executed by a hardware design device, which can be a terminal device or a server. Among them, the terminal device can include, but is not limited to, mobile phones, computers, smart wearable devices, intelligent vehicle-mounted devices, etc., and embodiments of this application do not make restrictions; the server can be an independent physical server, a server cluster or a distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, big data, and artificial intelligence platforms, etc., and embodiments of this application do not make restrictions. Optionally, the hardware design method can also be executed collaboratively by multiple electronic devices with computing power. For the convenience of description, subsequent embodiments will be described as being executed by a hardware design device.

[0033] Please refer to Figure 1 , Figure 1 which is a schematic flowchart of a hardware design method provided by an embodiment of this application. The hardware design method can be executed by a hardware design device and can at least include the following steps S101 to S106:

[0034] S101, obtain design description information required for the target hardware to be designed.

[0035] Among them, the design description information (i.e., Spec) refers to information used to describe the functional requirements and performance requirements of a chip. Chip developers can design a chip based on the functional requirements and performance requirements described by the Spec. The design description information can be described in natural language; the design description information required for the target hardware to be designed can include, but is not limited to, design name, function, interface, PPA parameter information, etc. Among them, the PPA parameter information includes power consumption, performance, and area. The PPA parameter information is a key indicator for evaluating and optimizing chip design and plays a crucial role in design decisions, especially in high-performance computing, mobile devices, and other power-sensitive application fields.

[0036] S102, through a first agent, analyze the functional requirements of the target hardware according to the design description information corresponding to the target hardware and generate function point information corresponding to the target hardware; among them, the function point information includes at least one function point, and one function point is used to represent a function of the target hardware.

[0037] S103. Based on the functional correlation of each function point in the function point information, the first intelligent agent performs module division processing to obtain the module function information corresponding to the target hardware. The module function information is used to indicate each divided sub-module and the module function of each sub-module.

[0038] S104. Based on the module functions of each sub-module indicated by the module function information, the first intelligent agent generates the design description information of each sub-module and the connection relationship information between each sub-module.

[0039] Among them, the design description information of the sub-module may include, but is not limited to, module level, name, function, interface, PPA parameter information, etc.; the connection relationship information between each sub-module may include, but is not limited to, the name, type, bit width, description, sender information, receiver information, etc. of the connection signal. Steps S102 to S104 are intended to obtain the design description information of at least one sub-module and the connection relationship information between each sub-module through the design decomposition by the first intelligent agent according to the design description information corresponding to the target hardware, so that subsequently, the second intelligent agent can generate the hardware design code of the corresponding sub-module based on the design description information of each sub-module respectively, and the third intelligent agent can combine the hardware design code of the target hardware based on the connection relationship information between each sub-module; realizing the functions of design decomposition, code generation, and module combination through multiple intelligent agents can reduce the complexity of generating the hardware design code (i.e., RTL design code) for a single module and improve the accuracy of generating the RTL design code of the target hardware.

[0040] In a feasible implementation manner, the first intelligent agent may include a large language model (LLMs) for design decomposition. Optionally, the large language model can be selected according to specific requirements. For example, a general large language model can be selected, or a fine-tuned large language model can be selected. The embodiments of the present application do not make limitations. Among them, the function point information corresponding to the target hardware can be specifically generated by the large language model in the first intelligent agent. The large language model can determine the input and output of the target hardware and list all necessary function points by analyzing the function requirements described in the design description information corresponding to the target hardware. The module function information corresponding to the target hardware can be specifically generated by the large language model in the first intelligent agent. The large language model can group the function points with similar or related functions based on the functional correlation of each function point in the function point information to form a corresponding sub-module list and the module function of each sub-module to obtain the module function information corresponding to the target hardware.

[0041] In a feasible implementation, when the hardware design device generates the design description information of each sub-module and the connection relationship information between each sub-module based on the module functions indicated by the module function information through the first agent, the following steps can be executed: Through the first agent, determine the module boundaries of the corresponding sub-modules based on the module functions of each sub-module indicated by the module function information; Analyze the data interaction between each sub-module according to the module boundaries of each sub-module and define the input interfaces and output interfaces of each sub-module, and determine the connection relationship information between each sub-module according to the input interfaces and output interfaces of each sub-module; Generate the design description information of each sub-module based on the design description information, function point information, module function information, and connection relationship information corresponding to the target hardware. Among them, determining the connection relationship information between each sub-module and the design description information of each sub-module based on the module function information can be specifically implemented through the large language model in the first agent. Optionally, the design description information of each sub-module and the connection relationship information between each sub-module can be in a formatted form.

[0042] In a specific implementation, when the first agent performs design decomposition on the design description information corresponding to the target hardware to obtain the design description information of at least one sub-module and the connection relationship information between each sub-module, the first agent can execute the following steps: (1), The first agent can input the design description information corresponding to the target hardware as the first file into the large language model of the first agent. The large language model can analyze the function requirements of the target hardware according to the first file, determine the input and output of the target hardware, and list all the function points of the target hardware and output them to the second file (including function point information). (2), The first agent can input the first file and the second file into the large language model of the first agent. The large language model can group the function points with similar or related functions to form a corresponding sub-module list and the module functions of each sub-module and output them to the third file (including module function information). (3), The first agent can input the first file, the second file, and the third file into the large language model of the first agent. The large language model can determine the module boundaries of the corresponding sub-modules based on the module functions of each sub-module, analyze the data interaction between each sub-module according to the module boundaries of each sub-module and define the input interfaces and output interfaces of each sub-module, and determine the connection relationship information between each sub-module according to the input interfaces and output interfaces of each sub-module and output it to the fourth file. (4), The first agent can input the first file containing the design description information corresponding to the target hardware, the second file containing the function point information, the third file containing the module function information, and the fourth file containing the connection relationship information into the large language model of the first agent, and the large language model generates the design description information of each sub-module.

[0043] S105. Based on the design description information of each sub-module, the second agent generates the hardware design code for the corresponding sub-module respectively.

[0044] Among them, the target language used to generate the hardware design code (i.e., RTL design code) can be selected according to specific requirements. For example, the target language can be selected as traditional hardware description languages (HDLs), such as Verilog, SystemVerilog, etc. Another example is that the target language can be Chisel (Constructing Hardware In a Scala Embedded Language). Chisel is a hardware construction language embedded in the Scala language, which can be used to facilitate the generation of high-level circuits and design reuse for ASIC and FPGA digital logic design. Chisel adds hardware construction primitives to the Scala programming language, providing designers with the powerful functions of modern programming languages, enabling them to write complex and parameterizable hardware design languages, and thus write complex and parameterizable circuit generators to generate synthesizable Verilog design codes. Compared with the implementation of traditional HDLs, which may encounter problems in maintaining readability and modularity, leading to challenges in code reusability and scalability in complex designs and being unable to meet the requirements of agile design iterations, using Chisel as the target language for automated design generation can achieve better generation effects, higher accuracy, and stronger reusability and scalability. Based on this, in the subsequent embodiments of this application, Chisel is used as the target language for illustration, and the corresponding hardware design code is the Chisel design code.

[0045] In a feasible implementation manner, the second agent may include a large language model (LLMs) for code generation; optionally, the large language model can be selected according to specific requirements. For example, a general large language model can be selected, or a fine-tuned large language model can be selected. The embodiments of this application do not make any restrictions. When the hardware design device generates the hardware design code for each sub-module respectively through the second agent, specifically, the second agent can call the large language model, so that the large language model can perform code generation processing based on the design description information of the sub-module to obtain the corresponding hardware design code, and the second agent can use the hardware design code output by the large language model as the hardware design code for the corresponding sub-module.

[0046] S106. Based on the design description information of each sub-module, the connection relationship information between each sub-module, and the hardware design code of each sub-module, the third agent combines them to obtain the hardware design code of the target hardware.

[0047] In a feasible implementation manner, the third intelligent agent may include a large language model for module combination; optionally, the large language model can be selected according to specific requirements. For example, a general large language model can be selected, or a fine-tuned large language model can be selected. The embodiments of the present application do not make any restrictions. When the hardware design device combines the hardware design codes of the target hardware according to the design description information of each sub-module, the connection relationship information between each sub-module, and the hardware design codes of each sub-module through the third intelligent agent, specifically, the third intelligent agent can call the large language model, so that the large language model can assemble the hardware design codes of each sub-module into a top-level design code according to the design description information of each sub-module and the connection relationship information between each sub-module. The third intelligent agent can use the assembled top-level design code as the hardware design code of the target hardware.

[0048] In a feasible implementation manner, in order to improve the accuracy of the generated hardware design code of the target hardware, the embodiments of the present application provide an iterative feedback mechanism for the top-level design code. Please refer to Figure 2 , which is a schematic diagram of iteratively generating a hardware design code provided by the embodiments of the present application. The hardware design device can obtain the design description information required for designing the target hardware and send it to the first intelligent agent; through the first intelligent agent, the design description information of at least one sub-module and the connection relationship information between each sub-module are obtained by decomposing the design according to the design description information corresponding to the target hardware; through the second intelligent agent, the hardware design codes of the corresponding sub-modules are generated respectively based on the design description information of each sub-module; through the third intelligent agent, the hardware design codes of the target hardware are combined according to the design description information of each sub-module, the connection relationship information between each sub-module, and the hardware design codes of each sub-module; specifically, through the third intelligent agent, the hardware design codes of each sub-module can be assembled into the candidate hardware design code corresponding to the target hardware according to the design description information of each sub-module and the connection relationship information between each sub-module; error detection is performed on the candidate hardware design code; if no error is detected, the candidate hardware design code is used as the hardware design code of the target hardware; if an error is detected, the operation of generating function point information is jumped to and the new function point information corresponding to the target hardware is generated.

[0049] Among them, when obtaining the candidate hardware design code corresponding to the target hardware through the processing of the third intelligent agent, specifically, the top-level design code assembled by the large language model in the third intelligent agent can be used as the candidate hardware design code corresponding to the target hardware. When the hardware design device performs error detection on the candidate hardware design code, it can be achieved by calling the RTL tool chain. The RTL tool chain includes a compiler and a simulator. Specifically, the candidate hardware design code can be compiled by calling the compiler to detect code syntax errors, and errors (i.e., syntax errors) are determined when there are syntax errors in the code; when there are no syntax errors in the code, the simulator can be called to simulate the candidate hardware design code according to the test bench file to detect code functional errors, and errors (i.e., functional errors) are determined in the case of simulation errors. Among them, the test bench file, namely Testbench, includes files used to simulate and test the RTL design code to detect whether there are functional errors in the code; optionally, when the hardware design device performs error detection on the candidate hardware design code, it can also only perform functional error detection.

[0050] In a feasible implementation manner, the embodiment of the present application further provides a code iteration error correction mechanism for sub-modules to improve the accuracy of the generated hardware design code of the sub-modules, and further improve the accuracy of the generated hardware design code of the target hardware. For step S105, taking the generation of the hardware design code of the target sub-module based on the design description information of the target sub-module in each sub-module as an example, where the target sub-module is any one of the sub-modules, during the process of the hardware design device generating the hardware design code of the target sub-module based on the design description information of the target sub-module in each sub-module through the second agent, the following steps can be executed: Through the second agent, perform code generation processing based on the design description information of the target sub-module to obtain the candidate hardware design code corresponding to the target sub-module; perform error detection on the candidate hardware design code to obtain a detection report; if no error is detected, determine the hardware design code with correct detection as the hardware design code of the target sub-module. Optionally, if an error is detected, it can jump to the code generation processing operation to generate a new candidate hardware design code. Optionally, if an error is detected, send the hardware design code with detected error, the detection report, and the design description information of the target sub-module to the fourth agent; through the fourth agent, perform iterative error correction on the hardware design code with detected error according to the hardware design code with detected error, the detection report, and the design description information of the target sub-module; if the number of iterations is less than the threshold number of times, use the error-corrected hardware design code as the new candidate hardware design code and perform error detection; otherwise, jump to the code generation processing operation to generate a new candidate hardware design code. Among them, the fourth agent can include a large language model for code error correction; specifically, the fourth agent can call the large language model to implement the error correction of the hardware design code with detected error; among them, the large language model can be selected according to specific requirements. For example, a general large language model can be selected, or a fine-tuned large language model can be selected. The embodiment of the present application does not make any restrictions. The threshold number of times can be set according to specific requirements. The embodiment of the present application does not make any restrictions.

[0051] In a feasible implementation manner, when the second agent processes to obtain the candidate hardware design code corresponding to the target sub-module, specifically, the second agent can call a large language model, so that the large language model can perform code generation processing based on the design description information of the target sub-module to obtain the corresponding hardware design code, and the second agent can use the hardware design code output by the large language model as the candidate hardware design code corresponding to the target sub-module.

[0052] In another alternative implementation, when the hardware design device performs code generation processing based on the design description information of the target sub-module through the second agent and obtains the candidate hardware design code corresponding to the target sub-module, it can: retrieve the reference corpus related to the target sub-module from the reference corpus through the second agent based on the design description information of the target sub-module; generate the implementation steps of the target sub-module based on the design description information of the target sub-module and the reference corpus; generate the candidate hardware design code corresponding to the target sub-module based on the design description information of the target sub-module, the reference corpus, and the implementation steps of the target sub-module. Among them, the corpus in the reference corpus may include knowledge and codes related to digital integrated circuit design, and the second agent may further include a Retrieval-Augmented Generation (RAG) system for retrieval-enhanced generation; where RAG is a technology that combines information retrieval and natural language generation, and its basic idea is to use information retrieval technology to retrieve text fragments related to the current task from a large-scale corpus (such as stored in a vector database) and provide these text fragments as inputs to LLMs to guide LLMs to produce more accurate and relevant text outputs.

[0053] Based on this, in a specific and feasible implementation, when the hardware design device obtains the candidate hardware design code corresponding to the target sub-module through the processing of the second agent, it can input the design description information of the target sub-module into the RAG system of the second agent, and the RAG system can retrieve the reference corpus related to the target sub-module from the reference corpus based on the design description information of the target sub-module and output it; the second agent can input the design description information of the target sub-module and the reference corpus into the large language model of the second agent, and the large language model can output the implementation steps of the target sub-module; the second agent can input the design description information of the target sub-module, the reference corpus, and the implementation steps of the target sub-module into the large language model of the second agent, and the large language model generates the corresponding hardware design code, and the second agent can use the hardware design code output by the large language model as the candidate hardware design code corresponding to the target sub-module.

[0054] Among them, when the hardware design device performs error detection on the candidate hardware design code to obtain a detection report, it can be achieved by calling an RTL tool chain. The RTL tool chain includes a compiler and a simulator. The compiler is used to compile to detect syntax errors and obtain a compilation report, and the simulator is used to simulate based on a testbench file in the case of successful compilation (i.e., no syntax errors) to detect functional errors and obtain a simulation report; the detection report can include one or more of the compilation report or the simulation report; when the compilation fails, the detection report only includes the compilation report, and when the compilation is successful but the simulation goes wrong, the detection report includes the simulation report and further can also include the compilation report. At this time, the compilation report indicates successful compilation.

[0055] In a specific implementation, when the target language adopted by the hardware design code is Chisel, that is, when the candidate hardware design code corresponding to the target sub-module is Chisel code, it is necessary to convert the Chisel code into a hardware design code in a target format for simulation, where the target format is the format supported by the simulator for simulation. For example, the target format can be Verilog format; based on this, when the hardware design device performs error detection on the candidate hardware design code to obtain a detection report, it can: compile the candidate hardware design code, convert the candidate hardware design code into a hardware design code in a target format, detect code syntax errors during compilation and obtain a corresponding compilation report; in the case of code syntax errors, use the compilation report as the detection report; in the case of no code syntax errors, perform simulation according to the testbench file and the hardware design code in the target format, detect functional errors existing in the hardware design code in the target format during simulation and obtain a corresponding simulation report; in the case of simulation errors, construct a detection report based on the compilation report and the simulation report.

[0056] Please refer to Figure 3 , taking the hardware design code as Chisel code as an example, which is a schematic diagram of a method for generating hardware design code based on an iterative error correction mechanism provided by an embodiment of the present application; specifically, it can include the following steps:

[0057] ①. The hardware design device can obtain the design description information required for the target hardware design. ②. The hardware design device can input the design description information corresponding to the target hardware into the first intelligent agent, which decomposes the design and outputs the design description information of at least one sub-module and the connection relationship information between the sub-modules. ③. The design description information of each sub-module is input into the second intelligent agent one by one, and the second intelligent agent generates and outputs the candidate Chisel design code corresponding to the sub-module (i.e., the candidate hardware design code corresponding to the sub-module). ④. Error detection is performed on the candidate Chisel design code corresponding to the current sub-module to obtain a detection report; if no error is detected, the correctly detected Chisel design code is determined as the Chisel design code of the corresponding sub-module and stored in the code repository, and step ③ is returned to generate the candidate Chisel design code corresponding to the next sub-module; if an error is detected, the detected error Chisel design code, the detection report, and the design description information of the current sub-module are sent to the fourth intelligent agent. ⑤. The fourth intelligent agent can perform iterative error correction on the detected error Chisel design code according to the detected error Chisel design code, the detection report, and the design description information of the current sub-module; if the number of iterations is less than the threshold number of times, the error-corrected Chisel design code is returned as the new candidate Chisel design code to step ④ for error detection; otherwise, it jumps to step ③ to perform the code generation processing operation to generate the new candidate Chisel design code corresponding to the current sub-module. ⑥. If the Chisel design codes of all sub-modules are generated, the third intelligent agent can assemble the hardware design codes of each sub-module according to the design description information of each sub-module and the connection relationship information between the sub-modules to obtain the candidate Chisel design code corresponding to the target hardware (i.e., the candidate hardware design code corresponding to the target hardware). ⑦. Error detection is performed on the candidate Chisel design code corresponding to the target hardware; if no error is detected, the candidate hardware design code is used as the Chisel design code of the target hardware and output; if an error is detected, it jumps to step ② to perform the generation operation of the function point information and generate the new function point information corresponding to the target hardware to re-perform the module decomposition. The use of the large language model involved in the embodiments of the present application can adapt the large language model to different tasks through prompt engineering. Optionally, the prompts used for different tasks can be designed according to specific requirements, and the embodiments of the present application do not make any restrictions.

[0058] In the embodiments of the present application, the first agent can perform design decomposition on the design description information corresponding to the target hardware to obtain the design description information of at least one sub-module and the connection relationship information between the sub-modules, and the second agent can generate the hardware design code of the corresponding sub-module based on the design description information of each sub-module respectively. The third agent can combine the design description information of each sub-module, the connection relationship information between each sub-module, and the hardware design code of each sub-module to obtain the hardware design code of the target hardware. It can realize the automatic generation of the hardware design code of the target hardware (i.e., RTL design code) from the design description information (i.e., Spec) of the target hardware described in natural language, which can accelerate the hardware development process, improve the hardware development efficiency, and save the hardware development time. By using multiple agents to implement functions such as design decomposition, code generation, and module combination, generating function point information based on the design description information corresponding to the target hardware, and performing module division processing based on the functional relevance of each function point in the function point information, the accuracy of each sub-module obtained by division can be improved, and the complexity of generating the RTL design code for a single module is reduced by sub-module division, which can improve the accuracy of generating the RTL design code for large-scale complex hardware and realize the automatic generation of the RTL design code for large-scale complex hardware. Moreover, the embodiments of the present application also provide a code iteration error correction mechanism for sub-modules, which can improve the accuracy of the hardware design code of the generated sub-modules, and further improve the accuracy of the RTL design code of the generated target hardware.

[0059] Based on the above description, the embodiments of the present application also disclose a hardware design device. The hardware design device can be a computer program running on a computer device, and the computer device can be the above-mentioned hardware design device. The hardware design device can execute Figure 1 , Figure 2 or Figure 3 each step in the method flow shown. Please refer to Figure 4 , which is a schematic structural diagram of a hardware design device provided by the embodiments of the present application. The hardware design device can include an acquisition unit 401 and a processing unit 402, where:

[0060] The acquisition unit 401 is configured to acquire the design description information required for designing the target hardware;

[0061] The processing unit 402 is configured to analyze the functional requirements of the target hardware and generate the function point information corresponding to the target hardware through the first agent according to the design description information corresponding to the target hardware. The function point information includes at least one function point, and one function point is used to represent one function of the target hardware;

[0062] The processing unit 402 is further configured to perform module division processing based on the functional relevance of each function point in the function point information through the first agent, so as to obtain the module function information corresponding to the target hardware; wherein, the module function information is used to indicate each sub-module obtained by division and the module functions of the respective sub-modules.

[0063] The processing unit 402 is further configured to generate design description information for each sub-module and connection relationship information between the respective sub-modules based on the module functions of the respective sub-modules indicated by the module function information through the first agent.

[0064] The processing unit 402 is further configured to generate hardware design codes for the respective sub-modules based on the design description information of the respective sub-modules through a second agent.

[0065] The processing unit 402 is further configured to combine to obtain the hardware design code of the target hardware according to the design description information of the respective sub-modules, the connection relationship information between the respective sub-modules, and the hardware design codes of the respective sub-modules through a third agent.

[0066] In a feasible implementation manner, when the processing unit 402 generates the design description information for each sub-module and the connection relationship information between the respective sub-modules based on the module functions of the respective sub-modules indicated by the module function information through the first agent, it may specifically be configured to:

[0067] Determine the module boundaries of the respective sub-modules based on the module functions of the respective sub-modules indicated by the module function information through the first agent.

[0068] Analyze the data interaction between the respective sub-modules according to the module boundaries of the respective sub-modules, define the input interfaces and output interfaces of the respective sub-modules, and determine the connection relationship information between the respective sub-modules according to the input interfaces and output interfaces of the respective sub-modules.

[0069] Generate the design description information for each sub-module based on the design description information corresponding to the target hardware, the function point information, the module function information, and the connection relationship information.

[0070] In a feasible implementation manner, when the processing unit 402 generates the hardware design code of a target sub-module based on the design description information of the target sub-module in the respective sub-modules through a second agent, it may specifically be configured to:

[0071] Perform code generation processing based on the design description information of the target sub-module through the second agent to obtain candidate hardware design codes corresponding to the target sub-module.

[0072] Perform error detection on the candidate hardware design code to obtain a detection report; if no error is detected, determine the hardware design code with correct detection as the hardware design code of the target sub-module; if an error is detected, send the hardware design code with detected error, the detection report, and the design description information of the target sub-module to the fourth intelligent agent;

[0073] Through the fourth intelligent agent, perform iterative error correction on the hardware design code with detected error according to the hardware design code with detected error, the detection report, and the design description information of the target sub-module; if the number of iterations is less than the number threshold, use the error-corrected hardware design code as the new candidate hardware design code and perform error detection; otherwise, jump to the code generation processing operation to generate a new candidate hardware design code.

[0074] In a feasible implementation manner, the candidate hardware design code is Chisel code; when the processing unit 402 performs error detection on the candidate hardware design code to obtain a detection report, it can be specifically used for:

[0075] Compile the candidate hardware design code, convert the candidate hardware design code into a hardware design code in a target format, detect code syntax errors during compilation and obtain a corresponding compilation report;

[0076] In the case where there is a syntax error in the code, use the compilation report as the detection report;

[0077] In the case where there is no syntax error in the code, perform simulation according to the test platform file and the hardware design code in the target format, and detect functional errors existing in the hardware design code in the target format during the simulation process and obtain a corresponding simulation report;

[0078] In the case of simulation error, construct the detection report based on the compilation report and the simulation report.

[0079] In a feasible implementation manner, when the processing unit 402 performs code generation processing based on the design description information of the target sub-module through the second intelligent agent to obtain the candidate hardware design code corresponding to the target sub-module, it can be specifically used for:

[0080] Through the second intelligent agent, retrieve the reference corpus related to the target sub-module from the reference corpus based on the design description information of the target sub-module;

[0081] Generate the implementation steps of the target sub-module based on the design description information of the target sub-module and the reference corpus;

[0082] Generate the candidate hardware design code corresponding to the target sub-module based on the design description information of the target sub-module, the reference corpus, and the implementation steps of the target sub-module.

[0083] In a feasible implementation manner, when the processing unit 402 combines to obtain the hardware design code of the target hardware through the third agent according to the design description information of each sub-module, the connection relationship information between each sub-module, and the hardware design code of each sub-module, it can be specifically used for:

[0084] Through the third agent, assemble the hardware design codes of each sub-module according to the design description information of each sub-module and the connection relationship information between each sub-module to obtain the candidate hardware design code corresponding to the target hardware;

[0085] Perform error detection on the candidate hardware design code;

[0086] If no error is detected, use the candidate hardware design code as the hardware design code of the target hardware;

[0087] If an error is detected, jump to the generation operation of the function point information and generate the new function point information corresponding to the target hardware.

[0088] In the embodiments of the present application, the first intelligent agent can perform design decomposition on the design description information corresponding to the target hardware to obtain the design description information of at least one sub-module and the connection relationship information between the sub-modules, and the second intelligent agent can generate the hardware design code of the corresponding sub-module based on the design description information of each sub-module respectively. The third intelligent agent can combine the design description information of each sub-module, the connection relationship information between the sub-modules, and the hardware design code of each sub-module to obtain the hardware design code of the target hardware; it can realize the automatic generation of the hardware design code of the target hardware (i.e., RTL design code) from the design description information (i.e., Spec) of the target hardware described in natural language, which can accelerate the hardware development process, improve the hardware development efficiency, and save the hardware development time; by using multiple intelligent agents to implement design decomposition, code generation, and module combination functions, generating function point information based on the design description information corresponding to the target hardware, and performing module division processing based on the functional relevance of each function point in the function point information, the accuracy of each sub-module obtained by division can be improved, and the complexity of generating the RTL design code for a single module is reduced by sub-module division, which can improve the accuracy of generating the RTL design code for large-scale complex hardware and realize the automatic generation of the RTL design code for large-scale complex hardware. Moreover, the embodiments of the present application also provide a code iteration and error correction mechanism for sub-modules, which can improve the accuracy of the generated hardware design code of the sub-modules, and further improve the accuracy of the generated RTL design code of the target hardware.

[0089] Based on the descriptions of the above method embodiments and apparatus embodiments, the embodiments of the present application also provide a computer device, which can be the above-mentioned hardware design device. Please refer to Figure 5 , which is a schematic structural diagram of a computer device provided by the embodiments of the present application. The computer device of the embodiments of the present application includes a processor 501, a computer-readable storage medium 502, and a communication interface 503. Data can be exchanged between the processor 501, the computer-readable storage medium 502, and the communication interface 503, and the hardware design method proposed by the embodiments of the present application is implemented by the processor 501.

[0090] The embodiments of this application also provide a computer-readable storage medium (Memory). A computer-readable storage medium is a memory device in a computer device, used to store computer programs and data. The stored computer program is adapted to be loaded and executed by a processor to implement the hardware design method proposed by the embodiments of this application. The computer-readable storage medium 502 may include one or more of volatile memory or non-volatile memory. Exemplarily, volatile memory may include random-access memory (RAM), and non-volatile memory may include flash memory, solid-state drive (SSD), and so on.

[0091] The processor 501 may be a central processing unit (CPU); the processor 501 may also be a combination of a CPU and a Graphics Processing Unit (GPU).

[0092] The communication interface 503 may be used to implement data input and output. For example, it may include a display screen, a microphone, or a speaker, etc.

[0093] In one embodiment, the computer program stored in the computer-readable storage medium may be loaded and executed by the processor to implement the corresponding steps in the method embodiments related to Figure 1 、 Figure 2 or Figure 3 shown above; in specific implementation, the computer program in the computer-readable storage medium may be loaded and executed by the processor to perform the following steps:

[0094] Obtain the design description information required for designing the target hardware;

[0095] Through a first intelligent agent, analyze the functional requirements of the target hardware according to the design description information corresponding to the target hardware and generate the function point information corresponding to the target hardware; wherein, the function point information includes at least one function point, and one function point is used to represent one function of the target hardware;

[0096] Through the first intelligent agent, perform module division processing based on the functional correlation of each function point in the function point information to obtain the module function information corresponding to the target hardware; wherein, the module function information is used to indicate each sub-module obtained by division and the module functions of each sub-module;

[0097] Based on the module functions of each sub-module indicated by the module function information, the first intelligent agent generates design description information of each sub-module and connection relationship information between each sub-module;

[0098] Based on the design description information of each sub-module respectively, the second intelligent agent generates hardware design codes for the corresponding sub-modules;

[0099] Based on the design description information of each sub-module, the connection relationship information between each sub-module, and the hardware design codes of each sub-module, the third intelligent agent combines to obtain the hardware design code of the target hardware.

[0100] An embodiment of the present application provides a computer program product. The computer program product includes a computer program, and the computer program is stored in a computer-readable storage medium; a processor of a computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the above Figure 1 、 Figure 2 or Figure 3 method embodiments shown.

[0101] Those of ordinary skill in the art can understand that all or part of the processes in the above method embodiments can be completed by relevant hardware indicated by a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the above method embodiments.

[0102] The above-disclosed are only some embodiments of the present application. Of course, the scope of rights of the present application cannot be limited thereby. Those of ordinary skill in the art can understand all or part of the processes of the above embodiments, and the equivalent changes made according to the claims of the present application still fall within the scope covered by the present application.

Claims

1. A hardware design method, characterized in that: include: Obtain the design description information required for the design target hardware; By means of a first agent, the functional requirements of the target hardware are analyzed according to the design description information corresponding to the target hardware, and function point information corresponding to the target hardware is generated; wherein the function point information includes at least one function point, and one function point is used to represent one function of the target hardware; By means of the first agent, module division processing is performed based on the functional relevance of each function point in the function point information to obtain module function information corresponding to the target hardware; wherein the module function information is used to indicate each sub-module obtained by the division and the module function of each sub-module; Generate, by the first agent, design description information of each submodule and connection relationship information between each submodule based on the module function of each submodule indicated by the module function information; Generate hardware design codes of corresponding submodules based on the design description information of each submodule respectively through the second agent; The hardware design code of the target hardware is obtained by combining the design description information of each submodule, the connection relationship information between each submodule, and the hardware design code of each submodule through the third agent.

2. The method according to claim 1, characterized in that The generating, by the first agent, design description information of each submodule and connection relationship information between each submodule based on the module function of each submodule indicated by the module function information includes: Determining, by the first agent, module boundaries of corresponding submodules based on module functions of respective submodules indicated by the module function information; Analyzing data interaction between the submodules according to the module boundaries of the submodules and defining input interfaces and output interfaces of the submodules, and determining connection relationship information between the submodules according to the input interfaces and output interfaces of the submodules; Based on the design description information corresponding to the target hardware, the function point information, the module function information, and the connection relationship information, the design description information of each sub-module is generated.

3. The method according to claim 1, characterized in that Generating, by the second agent, a hardware design code of the target submodule based on the design description information of the target submodule in each submodule, including: By means of the second intelligent agent, code generation processing is performed based on the design description information of the target submodule to obtain a candidate hardware design code corresponding to the target submodule; Perform error detection on the candidate hardware design code to obtain a detection report; if no error is detected, determine the hardware design code that is detected correctly as the hardware design code of the target submodule; if an error is detected, send the hardware design code that detects the error, the detection report, and the design description information of the target submodule to the fourth agent; Through the fourth intelligent agent, the hardware design code with detected errors is iteratively corrected according to the hardware design code with detected errors, the detection report and the design description information of the target sub-module; if the number of iterations is less than the threshold number, the corrected hardware design code is used as a new candidate hardware design code and error detection is performed; otherwise, jump to the code generation processing operation to generate a new candidate hardware design code.

4. The method according to claim 3, characterized in that The candidate hardware design code is a Chisel code; and the error detection of the candidate hardware design code to obtain a detection report includes: Compiling the candidate hardware design code, converting the candidate hardware design code into a hardware design code in a target format, detecting code syntax errors during the compilation process and obtaining a corresponding compilation report; In the case where there are syntax errors in the code, the compilation report is used as the detection report; In the case where there are no syntax errors in the code, simulation is performed according to the test platform file and the hardware design code in the target format, and functional errors in the hardware design code in the target format are detected during the simulation process and a corresponding simulation report is obtained; In case of a simulation error, the detection report is constructed based on the compilation report and the simulation report.

5. The method according to claim 3, characterized in that: The step of performing code generation processing based on the design description information of the target submodule by the second intelligent agent to obtain a candidate hardware design code corresponding to the target submodule includes: Retrieving, by the second agent, reference corpus related to the target submodule from a reference corpus based on the design description information of the target submodule; An implementation step of generating the target submodule based on the design description information of the target submodule and the reference corpus; A candidate hardware design code corresponding to the target submodule is generated based on the design description information of the target submodule, the reference corpus, and the implementation steps of the target submodule.

6. The method according to claim 1, characterized in that The third agent combines the design description information of each submodule, the connection relationship information between each submodule, and the hardware design code of each submodule to obtain the hardware design code of the target hardware, including: By means of the third agent, according to the design description information of each submodule and the connection relationship information between each submodule, the hardware design code of each submodule is assembled to obtain the hardware design code to be selected corresponding to the target hardware; Perform error detection on the selected hardware design code; If no error is detected, the hardware design code to be selected is used as the hardware design code of the target hardware; If an error is detected, the process jumps to the function point information generation operation and generates new function point information corresponding to the target hardware.

7. A hardware design device, characterized in that: include: An acquisition unit, used for acquiring design description information required for design target hardware; A processing unit, configured to analyze the functional requirements of the target hardware and generate function point information corresponding to the target hardware through a first agent according to the design description information corresponding to the target hardware; wherein the function point information includes at least one function point, and one function point is used to represent a function of the target hardware; The processing unit is further used to perform module division processing based on the functional relevance of each function point in the function point information through the first agent to obtain module function information corresponding to the target hardware; wherein the module function information is used to indicate each sub-module obtained by the division and the module function of each sub-module; The processing unit is further configured to generate, through the first agent, design description information of each submodule and connection relationship information between the submodules based on the module functions of each submodule indicated by the module function information; The processing unit is further used to generate hardware design codes of corresponding submodules based on the design description information of each submodule through a second agent; The processing unit is also used to combine the design description information of each sub-module, the connection relationship information between each sub-module, and the hardware design code of each sub-module to obtain the hardware design code of the target hardware through a third intelligent agent.

8. A computer device comprising a communication interface, characterized in that: Also includes: A processor and a computer readable storage medium; The computer readable storage medium is used to store a computer program; The processor is used to run the computer program to implement the hardware design method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is suitable for being loaded by a processor and executing the hardware design method according to any one of claims 1 to 6.

10. A computer program product, characterized in that The computer program product comprises a computer program, and the computer program is suitable for being loaded by a processor and executing the hardware design method according to any one of claims 1 to 6.

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