Semiconductor device, debugging system, semiconductor device control method and debugging method

Abstract

The invention relates to a semiconductor device, a debugging system, a semiconductor device control method and a debugging method. The semiconductor device includes: a CPU configured to execute an instruction; a first register configured to store an address of an instruction currently being executed; a second register configured to store a return address when a functional branch occurs; and a generation circuit configured to generate and output functional branch information indicating an address of a functional branch destination when the functional branch occurs. The generation circuit is configured to determine whether a functional branch has occurred based on values of the first register and the second register before and after the CPU executes the instruction, and when it is determined that the functional branch has occurred, output the value of the first register after the CPU executes the instruction as functional branch information.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2023-209862, filed on December 13, 2023, including the specification, drawings, and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device, a debugging system, a control method for a semiconductor device, and a debugging method, and is suitable for use, for example, in a semiconductor device equipped with a central processing unit (CPU). Background Art

[0004] There is a need to check the function execution history of functions executed by a CPU installed on a semiconductor device. For example, as a technique for recording the function execution history of a computer (such as a CPU), this technique is disclosed in Patent Document 1.

[0005] The disclosed techniques are listed below.

[0006] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2009-009201

[0007] According to the technique disclosed in Patent Document 1, a debugger initially stores the instruction addresses of the instructions included in the program to be debugged and the function identifiers (IDs) corresponding to the instruction addresses in an ID memory. When the computer starts executing the program, for each instruction, the debugger reads the function ID corresponding to the instruction address of the instruction from the ID memory and compares the current function ID with the previous function ID. When the current function ID is different from the previous function ID, the debugger records the current function ID in a trace memory. This allows the function execution history of the computer to be recorded. Summary of the Invention

[0008] However, the problem is that the technique disclosed in Patent Document 1 requires an ID memory to store instruction addresses and function IDs, and when the ID memory is installed on a semiconductor device, the cost of the semiconductor device increases. Other objects and novel features will become apparent from the description of this specification and the drawings.

[0009] According to one embodiment, a semiconductor device includes: a central processing unit (CPU) configured to execute instructions included in a program; a first register configured to store an address of an instruction currently being executed by the CPU; a second register configured to store a return address when a functional branch occurs by executing an instruction by the CPU; and a generation circuit configured to generate and output functional branch information indicating an address of a functional branch destination when a functional branch occurs by executing an instruction by the CPU. The generation circuit is configured to determine whether a functional branch has occurred based on values of the first register and the second register before and after the CPU executes an instruction, and when it is determined that a functional branch has occurred, output a value of the first register after the CPU executes the instruction as the functional branch information.

[0010] According to one embodiment, a debugging system includes: a semiconductor device; an emulator configured to add a timestamp to functional branch information output from the semiconductor device and output the functional branch information with the timestamp added; and a debugger configured to display an execution history of functions executed by the CPU based on the functional branch information with the timestamp added output from the emulator.

[0011] According to one embodiment, a control method for a semiconductor device is provided, where the semiconductor device includes: a central processing unit (CPU) configured to execute instructions included in a program; a first register configured to store an address of an instruction currently being executed by the CPU; and a second register configured to store a return address when a functional branch occurs by executing an instruction by the CPU. The control method includes: determining whether a functional branch has occurred based on values of the first register and the second register before and after the CPU executes an instruction, and when it is determined that a functional branch has occurred, outputting a value of the first register after the CPU executes the instruction as the functional branch information, where the functional branch information indicates an address of a functional branch destination.

[0012] According to an embodiment, a debugging method executed by a debugging system is provided, where the debugging system includes a semiconductor device, an emulator, and a debugger. The semiconductor device includes: a central processing unit (CPU) configured to execute instructions included in a program; a first register configured to store an address of an instruction currently being executed by the CPU; and a second register configured to store a return address when a function branch occurs upon execution of an instruction by the CPU. The debugging method includes: the semiconductor device determining whether a function branch has occurred based on values of the first register and the second register before and after the CPU executes an instruction, and when determining that a function branch has occurred, the semiconductor device outputting a value of the first register after the CPU executes the instruction as function branch information indicating an address of a function branch destination; the emulator adding a timestamp to the function branch information output from the semiconductor device and outputting the function branch information with the timestamp added; and the debugger displaying an execution history of functions executed by the CPU based on the function branch information with the timestamp added output from the emulator.

[0013] According to an embodiment, while reducing the cost of a semiconductor device, a semiconductor device, a debugging system, a control method for a semiconductor device, and a debugging method capable of checking an execution history of functions of a CPU installed on the semiconductor device can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a diagram illustrating a configuration example of a debugging system according to a first embodiment.

[0015] Figure 2 is a diagram for illustrating a schematic operation example when a function call and a function return occur in a semiconductor device according to a first embodiment.

[0016] Figure 3 is a diagram illustrating an example of a function execution history displayed by a debugger according to a first embodiment.

[0017] Figure 4 is a diagram for illustrating a schematic operation example of an exception call determination operation and an exception return determination operation executed by a generation circuit according to a first embodiment.

[0018] Figure 5 is a diagram illustrating a configuration example of a generation circuit according to a first embodiment.

[0019] Figure 6 is a diagram for illustrating an operation example when a function call and a function return occur in a CPU according to a first embodiment.

[0020] Figure 7This is a diagram for illustrating an operation example when a function call and a function return occur in a generation circuit according to the first embodiment.

[0021] Figure 8 This is a diagram illustrating an example of an operation flow of a generation circuit according to the first embodiment.

[0022] Figure 9 This is a diagram illustrating a configuration example of a debugging system according to a modification example of the first embodiment.

[0023] Figure 10 This is a diagram illustrating a configuration example of a debugging system according to the second embodiment. Detailed Description of the Embodiment

[0024] Hereinafter, embodiments will be described with reference to the accompanying drawings. It should be noted that the drawings are simplified; thus, the technical scope of the embodiments should not be narrowly interpreted based on the content of the drawings. In addition, the same elements are denoted by the same reference numerals and repeated descriptions will be omitted.

[0025] In addition, in the following embodiments, for convenience, the description is divided into multiple sections or embodiments when necessary. However, unless otherwise clearly stated, they are not unrelated to each other; rather, one embodiment can be a modification example, application example, detailed description, supplementary description, etc. of another embodiment in part or in whole. In addition, in the following embodiments, when referring to the number of elements (including quantity, numerical value, amount, range, etc.), unless otherwise clearly stated or clearly limited to a specific number in principle, the reference is not limited to that specific number, but can be greater than or less than that specific number.

[0026] In addition, in the following embodiments, unless otherwise clearly stated or considered essential in principle, components (including operation steps, etc.) are not necessarily required. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, unless otherwise clearly stated or considered not to be the case in principle, it should be understood to include shapes that are substantially similar or approximate to the described shape, etc. This similarly applies to the above-mentioned number (including quantity, numerical value, amount, range, etc.), etc.

[0027] First Embodiment

[0028] First, with reference to Figure 1 , a configuration example of a debugging system according to the first embodiment will be described. Figure 1 This is a block diagram illustrating the configuration of a debugging system 1 according to the first embodiment. As Figure 1 illustrated, the debugging system 1 according to the first embodiment includes a semiconductor device 10, an emulator 20, and a debugger 30.

[0029] The semiconductor device 10 includes a CPU 11 and a generation circuit 12. The semiconductor device 10 is implemented by a system on chip (SoC), a micro processing unit (MPU), or the like.

[0030] The CPU 11 executes instructions included in a program to be debugged. The CPU 11 includes a program counter 111, a link register 112, and an exception link register 113. In the drawings, the program counter is appropriately represented as PC, the link register is appropriately represented as LR, and the exception link register is appropriately represented as ELR.

[0031] The program counter 111 is a register that stores the address of the instruction currently being executed by the CPU 11. The link register 112 is a register that stores a return address when a function is called by executing an instruction through the CPU 11. The exception link register 113 is a register that stores a return address when an exception occurs while the CPU 11 executes an instruction.

[0032] Before executing an instruction, the CPU 11 outputs the values of the program counter 111, the link register 112, and the exception link register 113 before the instruction execution to the generation circuit 12. Further, after executing the instruction, the CPU 11 outputs the values of the program counter 111, the link register 112, and the exception link register 113 after the instruction execution to the generation circuit 12.

[0033] When a function branch occurs by executing an instruction through the CPU 11, the generation circuit 12 generates and outputs function branch information indicating the address of a function branch destination. Here, a function branch refers to an operation that indicates a process transition based on a function and an exception. In the first embodiment, the generation circuit 12 detects a function call, a function return, an exception call, and an exception return as function branches.

[0034] Specifically, the generation circuit 12 determines whether a function branch has occurred based on the values of the program counter 111, the link register 112, and the exception link register 113 before and after the CPU executes an instruction.

[0035] When it is determined that a function branch has occurred, the generation circuit 12 outputs the value of the program counter 111 after the CPU executes the instruction to the emulator 20 as function branch information.

[0036] The emulator 20 includes a trace memory 21 and a timestamp circuit 22. At the moment when function branch information is input from the generation circuit 12 of the semiconductor device 10, the timestamp circuit 22 adds timestamp information to the function branch information. The trace memory 21 stores the function branch information to which the timestamp information has been added. The function branch information to which the timestamp information has been added and stored in the trace memory 21 is output to the debugger 30.

[0037] The debugger 30 displays the function execution history of the functions executed by the CPU 11 on a display (not shown) based on the function branch information with timestamp information added, output from the trace memory 21 of the emulator 20.

[0038] Next, referring to Figure 2 , a schematic operation example when a function call and a function return occur in the semiconductor device 10 will be described. Figure 2 FIG. is a diagram for describing a schematic operation example when a function call and a function return occur in the semiconductor device 10 according to the first embodiment. In Figure 2 , "Y" indicates "Yes" (the same applies to Figure 4 ).

[0039] In the example of Figure 2 , the CPU 11 executes an instruction to generate a function call, in which a sub-function (Function B) branches from a main function (Function A). At this time, the value of the program counter 111 is the address of Function A before the instruction execution and is the address of Function B after the instruction execution.

[0040] Furthermore, in the operation of the function call, the CPU 11 causes Function B to branch from Function A, and at the same time stores in the link register 112 the added value obtained by adding the value of the instruction length to the value of the program counter 111 before the instruction execution. That is, the CPU 11 stores in the link register 112 the address of the next instruction below the current instruction in Function A.

[0041] Therefore, the value of the link register 112 after the instruction execution is equivalent to the value of the program counter 111 when returning to Function A in the subsequent function return. In the following description, although the instruction length is assumed to be "4", the instruction length is not limited to "4" and can be set to other values.

[0042] Therefore, in the example of Figure 2 , the CPU 11 executes an instruction to cause a function call to occur as a function branch. Therefore, the generation circuit 12 performs the function call determination operation as illustrated in Figure 2 to determine whether a function call has occurred.

[0043] In the function call determination operation, the generation circuit 12 compares the added value obtained by adding the value of the instruction length "4" to the value of the program counter 111 before the instruction execution with the value of the link register 112 after the instruction execution (step S101). If the two match (Y in step S101), the generation circuit 12 determines that a function call has occurred. In this case, the two match; therefore, the generation circuit 12 determines that a function call has occurred.

[0044] When it is determined that a function call has occurred by determining an operation through the above function call, the generation circuit 12 outputs the value of the program counter 111 after instruction execution to the emulator 20 as function branch information (step S102).

[0045] In addition, in Figure 2 the example of , subsequently, the CPU 11 executes an instruction resulting in a function return, in which the main function (function A) branches from the sub-function (function B).

[0046] In the operation of the function return, before function A branches from function B, the CPU 11 stores the value of the link register 112 in the program counter 111. Then, the CPU 11 causes function A to branch from function B.

[0047] Therefore, the values of both the program counter 111 and the link register 112 after instruction execution become values equivalent to the value when the program counter 111 returns to function A.

[0048] Therefore, in Figure 2 the example of , the CPU 11 executes an instruction such that a function return occurs as a function branch. Therefore, the generation circuit 12 executes Figure 2 the function return determination operation illustrated in to determine whether a function return has occurred.

[0049] In the function return determination operation, the generation circuit 12 compares the value of the link register 112 before instruction execution with the value of the program counter 111 after instruction execution (step S111). If the two match (Y in step S111), the generation circuit 12 determines that a function return has occurred. Here, the two match; therefore, the generation circuit 12 determines that a function return has occurred.

[0050] When it is determined that a function return has occurred by the above function return determination operation, the generation circuit 12 outputs the value of the program counter 111 after instruction execution to the emulator 20 as function branch information (step S112).

[0051] Here, an example will be described in which the function execution history of the CPU 11 is displayed by the debugger 30 in the case of the example of Figure 2 . Figure 3 is a diagram illustrating an example of the function execution history displayed by the debugger 30 according to the first embodiment. According to Figure 3 , it can be confirmed that the CPU 11 executes functions A, B, and A in chronological order.

[0052] Although in Figure 2Although not illustrated in the example, an instruction executed by the CPU 11 may generate an exception call as a functional branch (where the exception branches from the main function (Function A)) or an exception return (where the main function (Function A) branches from the exception).

[0053] Figure 4 FIG. is a schematic operation example diagram for illustrating an exception call determination operation and an exception return determination operation executed by the generation circuit 12 according to the first embodiment. As Figure 4 illustrated, the generation circuit 12 executes an exception call determination operation and an exception return determination operation to determine whether an exception call or an exception return has occurred.

[0054] In the exception call determination operation, the generation circuit 12 compares the added value obtained by adding the value of the instruction length "4" to the value of the program counter 111 before the instruction execution with the value of the exception link register 113 after the instruction execution (step S121). If the two match (Y in step S121), the generation circuit 12 determines that an exception call has occurred.

[0055] When it is determined that an exception call has occurred through the above-described exception call determination operation, the generation circuit 12 outputs the value of the program counter 111 after the instruction execution to the emulator 20 as functional branch information (step S122).

[0056] In the exception return determination operation, the generation circuit 12 compares the value of the exception link register 113 before the instruction execution with the value of the program counter 111 after the instruction execution (step S131). If the two match (Y in step S131), the generation circuit 12 determines that an exception return has occurred.

[0057] When it is determined that an exception return has occurred through the above-described exception return determination operation, the generation circuit 12 outputs the value of the program counter 111 after the instruction execution to the emulator 20 as functional branch information (step S132).

[0058] Next, with reference to Figures 5 to 7 the configuration example and operation example of the semiconductor device 10 will be described in further detail. Figure 5 FIG. is a diagram illustrating a configuration example of the generation circuit 12 according to the first embodiment. Figure 6 FIG. is a diagram for illustrating an operation example when a function call and a function return occur in the CPU 11 according to the first embodiment. Figure 7 FIG. is a diagram for illustrating an operation example when a function call and a function return occur in the generation circuit 12 according to the first embodiment.

[0059] First, with reference to Figure 5 the configuration example of the generation circuit 12 will be described. AsFigure 5 As shown in the figure, the generation circuit 12 includes latch circuits 121 and 122, a comparison value calculation circuit 123, a function / exception call determination circuit 124, a function / exception return determination circuit 125, and an output unit 126.

[0060] As described above, before executing an instruction, the CPU 11 outputs the values of the program counter 111, link register 112, and exception link register 113 before the instruction execution to the generation circuit 12. After executing the instruction, the CPU 11 outputs the values of the program counter 111, link register 112, and exception link register 113 after the instruction execution to the generation circuit 12.

[0061] When the values of the program counter 111, link register 112, and exception link register 113 before the instruction execution are output from the CPU 11, the latch circuit 121 stores these values.

[0062] When the values of the program counter 111, link register 112, and exception link register 113 after the instruction execution are output from the CPU 11, the latch circuit 122 stores these values.

[0063] The comparison value calculation circuit 123 calculates an added value by adding the value of the instruction length "4" to the value of the program counter 111 stored in the latch circuit 121 before the instruction execution, and stores the calculated added value.

[0064] The function / exception call determination circuit 124 performs the above-described function call determination operation and exception call determination operation using the value stored in the comparison value calculation circuit 123 and the values of the link register 112 and exception link register 113 stored in the latch circuit 122 after the instruction execution.

[0065] In the function call determination operation, the function / exception call determination circuit 124 compares the value stored in the comparison value calculation circuit 123 with the value of the link register 112 after the instruction execution, and if they match, the function / exception call determination circuit 124 determines that a function call has occurred.

[0066] In addition, in the exception call determination operation, the function / exception call determination circuit 124 compares the value stored in the comparison value calculation circuit 123 with the value of the exception link register 113 after the instruction execution, and if they match, the function / exception call determination circuit 124 determines that an exception call has occurred.

[0067] The function / exception call determination circuit 124 outputs the determination result indicating whether a function call or an exception call has occurred to the output unit 126.

[0068] The function / exception return determination circuit 125 performs the above-described function return determination operation and exception return determination operation by using the values of the link register 112 and the exception link register 113 stored in the latch circuit 121 before the instruction execution, and the value of the program counter 111 stored in the latch circuit 122 after the instruction execution.

[0069] In the function return determination operation, the function / exception return determination circuit 125 compares the value of the link register 112 before the instruction execution with the value of the program counter 111 after the instruction execution, and if the two match, the function / exception return determination circuit 125 determines that a function return has occurred.

[0070] In addition, in the exception return determination operation, the function / exception return determination circuit 125 compares the value of the exception link register 113 before the instruction execution with the value of the program counter 111 after the instruction execution, and if the two match, the function / exception return determination circuit 125 determines that an exception return has occurred.

[0071] The function / exception return determination circuit 125 outputs the determination result to the output unit 126, and the determination result indicates whether a function return or an exception return has occurred.

[0072] Based on the determination results output from the function / exception call determination circuit 124 and the function / exception return determination circuit 125, the output unit 126 determines whether any function branch of a function call, an exception call, a function return, or an exception return has occurred. When it is determined that any function branch has occurred, the output unit 126 outputs the value of the program counter 111 after the instruction execution, which is stored in the latch circuit 122, to the emulator 20 as function branch information.

[0073] Next, with reference to Figure 6 and Figure 7 ,an operation example of the semiconductor device 10 will be described. First, with reference to Figure 6 ,an operation example when a function call and a function return occur in the CPU 11 will be described.

[0074] Figure 6 The figure shows the addresses and codes of the instructions executed for the main function (Function A), and also shows the addresses and codes of the instructions executed for the sub-function (Function B). In addition, in Figure 6 and the example of FIG. 7, similar to Figure 2 ,a function call occurs, in which the sub-function (Function B) branches from the main function (Function A), and subsequently, a function return occurs, in which the main function (Function A) branches from the sub-function (Function B).

[0075] In the initial state, the value of the program counter 111 (the value before instruction execution) is "0x1000". Therefore, the CPU 11 executes an instruction at the address "0x1000" (operation (a)). At this time, the instruction at the address "0x1000" includes a function call instruction (bl instruction). The bl instruction is an instruction that calls a function located at the address "0x2000".

[0076] Therefore, the CPU 11 performs an operation of function call. In the function call, function B branches from function A. In the operation of function call, the CPU 11 causes function B to branch from function A, and at the same time stores the address of the next instruction below the current instruction in the link register 112. In this case, the instruction length is "4"; therefore, the address of the next instruction below the current instruction address "0x1000" is "0x1004", where the instruction length "4" is added to the current instruction address "0x1000". Therefore, the CPU 11 stores "0x1004" in the link register 112. As a result, the value of the link register 112 after the execution of the function call instruction becomes a value equivalent to the value of the program counter 111 when returning to function A in the subsequent function return.

[0077] Here, the value of the program counter 111 after the execution of the function call instruction is the address "0x2000" of function B. Therefore, the CPU 11 executes an instruction at the address "0x2000" (operation (b)). At this time, the instruction at the address "0x2000" includes a no-operation instruction (nop instruction). Therefore, after executing the nop instruction, the CPU 11 changes the value of the program counter 111 to the address of the next instruction. As a result, the value of the program counter 111 becomes "0x2004".

[0078] Next, the CPU 11 executes the next instruction below, that is, the instruction at the address "0x2004" (operation (c)). At this time, the instruction at the address "0x2004" includes a function return instruction (ret instruction).

[0079] Therefore, the CPU 11 performs an operation of function return, in which function A branches from function B. In the operation of function return, before causing function A to branch from function B, the CPU 11 stores the value "0x1004" of the link register 112 in the program counter 111. Then, the CPU 11 causes function A to branch from function B.

[0080] Here, the value of the program counter 111 after the execution of the instruction for function return is the address "0x1004" of function A. Therefore, the CPU 11 executes an instruction (operation (d)) at the address "0x1004". At this time, the instruction at the address "0x1004" includes a nop instruction. Therefore, the CPU 11 executes the nop instruction.

[0081] Next, with reference to Figure 7 , an operation example when a function call and a function return occur in the generation circuit 12 will be described. Figure 7 The operation example of the CPU 11 illustrated in Figure 6 is similar to the operation example of the CPU 11 illustrated in

[0082] As Figure 7 illustrated, the function / exception call determination circuit 124 performs a function call determination operation to determine whether a function call has occurred. Here, the comparison value calculation circuit 123 saves the value "0x1004", and the value "0x1004" is obtained by adding the value of the instruction length "4" to the value "0x1000" at (1) of the program counter 111 before the execution of the instruction for function call.

[0083] Therefore, in the function call determination operation, the function / exception call determination circuit 124 compares the value "0x1004" of the link register 112 at (2) after the execution of the instruction for function call with the value "0x1004" saved by the comparison value calculation circuit 123. In this case, the two match; therefore, the function / exception call determination circuit 124 determines that a function call has occurred.

[0084] Therefore, the output unit 126 outputs the value "0x2000" of the program counter 111 at (3) after the execution of the instruction for function call to the emulator 20 as function branch information.

[0085] In addition, the function / exception return determination circuit 125 performs a function return determination operation to determine whether a function return has occurred. In the function return determination operation, the function / exception return determination circuit 125 compares the value "0x1004" of the link register 112 at (4) before the execution of the instruction for function return with the value "0x1004" of the program counter 111 at (5) after the execution of the instruction for function return. In this case, the two match; therefore, the function / exception return determination circuit 125 determines that a function return has occurred.

[0086] Therefore, the output unit 126 outputs the value "0x1004" of the program counter 111 at (5) after the execution of the instruction for function return to the emulator 20 as function branch information.

[0087] Next, referring to Figure 8 , an example of the operation flow of the generation circuit 12 will be described. Figure 8 is a diagram illustrating an example of the operation flow of the generation circuit 12 according to the first embodiment. In Figure 8 , "Y" indicates "Yes" and "N" indicates "No". As Figure 8 illustrated, the latch circuit 121 stores the values of the program counter 111, the link register 112, and the exception link register 113 before the CPU 11 executes an instruction (step S201).

[0088] When the instruction has been executed by the CPU 11 (step S202), the latch circuit 122 stores the values of the program counter 111, the link register 112, and the exception link register 113 after the CPU executes the instruction (step S203).

[0089] Next, the comparison value calculation circuit 123 calculates an added value by adding the value "4" of the instruction to the value of the program counter 111 stored in the latch circuit 121 before the instruction execution, and stores the calculated added value (step S204).

[0090] Next, the function call determination operation is performed. Specifically, the function / exception call determination circuit 124 compares the value stored in the comparison value calculation circuit 123 with the value of the link register 112 stored in the latch circuit 122 after the instruction execution (step S205). If the two match (Y in step S205), the function / exception call determination circuit 124 determines that a function call has occurred.

[0091] Next, the exception call determination operation is performed. Specifically, the function / exception call determination circuit 124 compares the value stored in the comparison value calculation circuit 123 with the value of the exception link register 113 stored in the latch circuit 122 after the instruction execution (step S206). If the two match (Y in step S206), the function / exception call determination circuit 124 determines that an exception call has occurred.

[0092] Next, the function return determination operation is performed. Specifically, the function / exception return determination circuit 125 compares the value of the link register 112 stored in the latch circuit 121 before the instruction execution with the value of the program counter 111 stored in the latch circuit 122 after the instruction execution (step S207). If the two match (Y in step S207), the function / exception return determination circuit 125 determines that a function return has occurred.

[0093] Next, the abnormal return determination operation is performed. Specifically, the function / abnormal return determination circuit 125 compares the value of the exception link register 113 saved in the latch circuit 121 before instruction execution with the value of the program counter 111 saved in the latch circuit 122 after instruction execution (step S208). If the two match (Y in step S208), the function / abnormal return determination circuit 125 determines that an abnormal return has occurred.

[0094] The output unit 126 determines whether a function branch in which a function call, an exception call, a function return, or an abnormal return has occurred in any of steps S205 to S208 has been determined. When it is determined that any function branch has occurred, the output unit 126 outputs the value of the program counter 111 saved in the latch circuit 122 after instruction execution to the emulator 20 as function branch information (step S209).

[0095] As described above, according to the first embodiment, the semiconductor device 10 determines whether a function branch has occurred based on the values of the program counter 111, the link register 112, and the exception link register 113 before and after instruction execution. When it is determined that a function branch has occurred, the semiconductor device 10 outputs the value of the program counter 111 after instruction execution as function branch information. Therefore, the semiconductor device 10 does not require the ID memory necessary in Patent Document 1, and thus can avoid an increase in the cost of the semiconductor device 10 due to the incorporation of the ID memory. Therefore, the function execution history of the CPU 11 installed on the semiconductor device 10 can be checked while reducing the cost of the semiconductor device 10.

[0096] <Modification Example of the First Embodiment>

[0097] Next, referring to Figure 9 will describe a configuration example of a debugging system according to a modification example of the first embodiment. Figure 9 is a diagram illustrating a configuration example of a debugging system 1A according to a modification example of the first embodiment. The modification example is an example in which a plurality of CPUs 11 are installed on the semiconductor device 10A.

[0098] As Figure 9 illustrated, the debugging system 1A according to the modification example includes a semiconductor device 10A, an emulator 20A, and a debugger 30A. The semiconductor device 10A is different from the above-described semiconductor device 10 in that the semiconductor device 10A includes a plurality of the above-described CPUs 11 and a plurality of the above-described generation circuits 12.

[0099] Each of the plurality of generation circuits 12 is provided in association with one of the plurality of CPUs 11. Further, each of the plurality of CPUs 11 is associated with a CPU number, which is a number for identifying the CPU. When it is determined that a function branch has occurred after the associated CPU 11 executes an instruction, each of the plurality of generation circuits 12 adds the CPU number of the associated CPU 11 to the function branch information, and outputs the function branch information with the added CPU number to the emulator 20A.

[0100] The emulator 20A has a configuration similar to that of the above-described emulator 20. At the moment when the function branch information with the added CPU number is input from the generation circuit 12 of the semiconductor device 10A, the timestamp circuit 22 adds timestamp information to the function branch information with the added CPU number. The trace memory 21 stores the function branch information with the added CPU number and timestamp information. The function branch information with the added CPU number and timestamp information and stored in the trace memory 21 is output to the debugger 30A.

[0101] The debugger 30A displays the function execution history of each CPU 11 on a display (not shown) based on the function branch information with the added CPU number and timestamp information, and the function branch information is output from the trace memory 21 of the emulator 20A.

[0102] As described above, according to this modification example, similar to the above-described semiconductor device 10, the semiconductor device 10A does not require the ID memory necessary in Patent Document 1, and thus can avoid an increase in the cost of the semiconductor device 10A due to incorporating the ID memory. Further, the function branch information output from the semiconductor device 10A is limited to function branches related to function calls, function returns, exception calls, and exception returns; thus, information on other types of function branches other than the above (such as function branches generated by "if" statements or "while" statements) is not included, resulting in a smaller amount of information. Therefore, the semiconductor device 10A can output all function branch information of the plurality of CPUs 11 installed on the semiconductor device 10A. Therefore, it is possible to check all function execution histories of the plurality of CPUs 11 installed on the semiconductor device 10A while reducing the cost of the semiconductor device 10A.

[0103] <Second Embodiment>

[0104] The second embodiment is an embodiment corresponding to the above-described general first embodiment. Referring to Figure 10 , a configuration example of the debugging system according to the second embodiment will be described. Figure 10 is a diagram illustrating a configuration example of the debugging system 2 according to the second embodiment.

[0105] As Figure 10 illustrated, the debugging system 2 according to the second embodiment includes a semiconductor device 40, an emulator 50, and a debugger 60.

[0106] The semiconductor device 40 includes a CPU 41 and a generation circuit 42. The semiconductor device 40 corresponds to the semiconductor device 10. The CPU 41 executes instructions included in the program to be debugged. The CPU 41 also includes a first register 411 and a second register 412. The CPU 41 corresponds to the CPU 11.

[0107] The first register 411 stores the address of the instruction currently being executed by the CPU 41. The first register 411 corresponds to the program counter 111. When a function branch occurs by executing an instruction by the CPU 41, the second register 412 stores the return address. The second register 412 corresponds to the link register 112 or the exception link register 113.

[0108] When a function branch occurs by executing an instruction by the CPU 41, the generation circuit 42 generates and outputs function branch information indicating the address of the function branch destination. The generation circuit 42 corresponds to the generation circuit 12.

[0109] Specifically, the generation circuit 42 determines whether a function branch has occurred based on the values of the first register 411 and the second register 412 before and after the CPU 41 executes an instruction. When it is determined that a function branch has occurred, the generation circuit 42 outputs the value of the first register 411 after the CPU 41 executes the instruction to the emulator 50 as function branch information.

[0110] The emulator 50 adds a timestamp to the function branch information output from the semiconductor device 40, and outputs the function branch information with the timestamp added to the debugger 60. The emulator 50 corresponds to the emulator 20.

[0111] The debugger 60 displays the function execution history of the functions executed by the CPU 41 based on the function branch information with the timestamp added, output from the emulator 50. The debugger 60 corresponds to the debugger 30.

[0112] As described above, according to the second embodiment, the semiconductor device 40 determines whether a functional branch has occurred based on the values of the first register 411 and the second register 412 before and after the execution of an instruction. When it is determined that a functional branch has occurred, the semiconductor device 40 outputs the value of the first register 411 after the execution of the instruction as functional branch information. Therefore, the semiconductor device 40 does not require the ID memory that is necessary in Patent Document 1, and thus can avoid an increase in the cost of the semiconductor device 40 due to the incorporation of the ID memory. Therefore, the functional execution history of the CPU 41 installed on the semiconductor device 40 can be checked while reducing the cost of the semiconductor device 10.

[0113] In addition, when the second register 412 is a link register, when the added value obtained by adding a predetermined value equivalent to the instruction length to the value of the program counter before the CPU 41 executes the instruction matches the value of the link register after the CPU 41 executes the instruction, the generation circuit 42 can determine that a function call has occurred as a functional branch.

[0114] In addition, when the second register 412 is a link register, when the value of the link register before the CPU 41 executes the instruction matches the value of the program counter after the CPU 41 executes the instruction, the generation circuit 42 can determine that a function return has occurred as a functional branch.

[0115] In addition, when the second register 412 is an exception link register, when the added value obtained by adding a predetermined value equivalent to the instruction length to the value of the program counter before the CPU 41 executes the instruction matches the value of the exception link register after the CPU 41 executes the instruction, the generation circuit 42 can determine that an exception call has occurred as a functional branch.

[0116] In addition, when the second register 412 is an exception link register, when the value of the exception link register before the CPU 41 executes the instruction matches the value of the program counter after the CPU 41 executes the instruction, the generation circuit 42 can determine that an exception return has occurred as a functional branch.

[0117] In addition, the semiconductor device 40 may include a plurality of CPUs 41 and a plurality of generation circuits 42. That is, the semiconductor device 40 may include a plurality of first registers 411 and a plurality of second registers 412. In addition, when it is determined that a functional branch has occurred by the execution of an instruction by the associated CPU 41, each of the plurality of generation circuits 42 can add the CPU number of the associated CPU 11 to the functional branch information, and output the functional branch information with the added CPU number to the emulator 50. The semiconductor device 40 may also be an SoC or an MPU.

[0118] In the above description, the invention made by the inventors of the present application has been specifically described based on the embodiments. However, needless to say, the present invention is not limited to the foregoing embodiments, and various modifications and changes can be made within the scope of the present invention.

[0119] In addition, in the present disclosure, part or all of the processing of the semiconductor devices 10, 10A, 40, the emulators 20, 20A, 50, and the debuggers 30, 30A, 60 can be implemented by causing a CPU to execute a computer program.

[0120] In addition, the above program includes an instruction set (or software code), and when the instruction set (or software code) is loaded into a computer, it causes the computer to execute one or more functions described in the embodiments. The program can be stored in a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, the computer-readable medium or tangible storage medium includes random access memory (RAM), read-only memory (ROM), flash memory, solid state drive devices (SSDs), or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD), Blu-ray (registered trademark) disc, or other optical disc storage devices, magnetic tape cartridges, magnetic tapes, and disk storage devices, or other magnetic storage devices. The program can be transmitted on a transitory computer-readable medium or a communication medium. By way of example and not limitation, the transitory computer-readable medium or communication medium includes electrical, optical, acoustic, or other forms of propagated signals.

Claims

1. A semiconductor device, comprising: a central processing unit CPU configured to execute instructions included in the program; a first register configured to store an address of the instruction currently being executed by the CPU; A second register is configured to store a return address when a functional branch occurs by executing the instruction by the CPU; as well as generating circuit configured to generate and output functional branch information indicating an address of a functional branch destination when the functional branch occurs by the CPU executing the instruction, The generating circuit is configured as follows: determining whether the functional branch has occurred based on the values ​​of the first register and the second register before and after the CPU executes the instruction, and When it is determined that the functional branch has occurred, the value of the first register after the CPU executes the instruction is output as the functional branch information.

2. The semiconductor device according to claim 1, wherein the first register is a program counter, and The second register is a link register configured to store the return address when a function is called by the CPU executing the instruction, or the second register is an exception link register configured to store the return address when an exception occurs when the CPU executes the instruction.

3. The semiconductor device according to claim 2, in, When the second register is the link register, the generating circuit is configured to determine that a function call has occurred as the function branch when an added value obtained by adding a predetermined value equivalent to the instruction length to the value of the program counter before the CPU executes the instruction matches the value of the link register after the CPU executes the instruction.

4. The semiconductor device according to claim 2, in, When the second register is the link register, the generating circuit is configured to determine that a function return has occurred as the function branch when a value of the link register before the CPU executes the instruction matches a value of the program counter after the CPU executes the instruction.

5. The semiconductor device according to claim 2, in, When the second register is the exception link register, the generating circuit is configured to determine that an exception call has occurred as the functional branch when an added value obtained by adding a predetermined value equivalent to the instruction length to the value of the program counter before the CPU executes the instruction matches the value of the exception link register after the CPU executes the instruction.

6. The semiconductor device according to claim 2, in, When the second register is the exception link register, the generating circuit is configured to determine that an exception return has occurred as the functional branch when a value of the exception link register before the CPU executes the instruction matches a value of the program counter after the CPU executes the instruction.

7. The semiconductor device according to claim 1, comprising: a plurality of said CPUs; a plurality of said first registers; a plurality of said second registers; as well as A plurality of said generating circuits are provided in association with said plurality of said CPUs, When it is determined that the functional branch occurs by executing an instruction by an associated CPU, each of the plurality of generating circuits is configured to add a CPU number of the associated CPU to the functional branch information and output the functional branch information to which the CPU number is added.

8. The semiconductor device according to claim 1, The semiconductor device is a system on chip SoC or a micro processing unit MPU.

9. A debugging system, comprising: The semiconductor device according to claim 1; a simulator configured to add a time stamp to the functional branch information output from the semiconductor device, and output the functional branch information to which the time stamp is added; as well as A debugger is configured to display an execution history of a function executed by the CPU based on the function branch information output from the emulator to which the time stamp is added.

10. A control method for a semiconductor device, The semiconductor device comprises: a central processing unit CPU configured to execute instructions included in the program; a first register configured to store an address of the instruction currently being executed by the CPU; as well as a second register configured to store a return address when a functional branch occurs by executing the instruction by the CPU, The control method comprises: determining whether the functional branch has occurred based on the values ​​of the first register and the second register before and after the CPU executes the instruction, and When it is determined that the functional branch has occurred, the value of the first register after the CPU executes the instruction is output as functional branch information indicating an address of a functional branch destination.

11. The control method for a semiconductor device according to claim 10, wherein the first register is a program counter, and The second register is a link register configured to store the return address when a function is called by the CPU executing the instruction, or the second register is an exception link register configured to store the return address when an exception occurs when the CPU executes the instruction.

12. A debugging method performed by a debugging system, The debugging system comprises: A semiconductor device comprising a central processing unit (CPU), a first register, and a second register, wherein the CPU is configured to execute instructions included in a program, the first register is configured to store an address of the instruction currently being executed by the CPU, and the second register is configured to store a return address when a functional branch occurs by the CPU executing the instruction. emulator, and debugger, The debugging method comprises: The semiconductor device determines whether the functional branch has occurred based on the values ​​of the first register and the second register before and after the CPU executes the instruction, and When it is determined that the functional branch has occurred, the semiconductor device outputs the value of the first register after the CPU executes the instruction as functional branch information, the functional branch information indicating an address of a functional branch destination; a simulator adding a time stamp to the functional branch information output from the semiconductor device and outputting the functional branch information to which the time stamp is added; and The debugger displays the execution history of the function executed by the CPU based on the function branch information output from the emulator to which the time stamp is added.

13. The debugging method according to claim 12, wherein the first register is a program counter, and The second register is a link register configured to store the return address when a function is called by the CPU executing the instruction, or the second register is an exception link register configured to store the return address when an exception occurs when the CPU executes the instruction.

Images