Axi bus monitor verification system and method, electronic equipment and storage medium

Abstract

The embodiment of the invention provides an axi bus monitor verification system and method, electronic equipment and a storage medium. The verification system comprises a to-be-verified module, a data interaction module and a verification judgment module. The to-be-verified module can detect the level of a data transmission channel between the master device and the slave device in the data interaction module, so that when a handshake feedback channel between the slave device and the master device is at a high level, the response time of the slave device for feeding back target data to the master device is counted. The verification judgment module can obtain expected information corresponding to verification information output by the to-be-verified module, and compares the verification information with the expected information when the to-be-verified module outputs the verification information so as to determine whether the hang-up prevention function of the to-be-verified module operates normally or not. Therefore, verification of the hang-up prevention function of the to-be-verified module can be realized, and normal operation of a chip carrying the to-be-verified module can be maintained.

Description

Technical Field

[0001] This application belongs to the technical field of chip verification, and particularly relates to an AXI bus monitor verification system, method, electronic device, and storage medium. Background Art

[0002] The master device and the slave device in a chip can transmit data through a data transmission channel based on the AXI (Advanced eXtensible Interface) protocol to complete data interaction. However, during the data transmission process, data transmission anomalies may occur due to the operating states of the master device or the slave device. For example, when the master device reads data from the slave device and the slave device is in a busy state, it is difficult to timely feedback the read data to the master device, which may cause the AXI bus to hang, and further cause the chip system to malfunction.

[0003] Therefore, during the chip design process, a monitor can be set up to determine whether there is a situation where the AXI bus hangs by monitoring the status of the data transmission channel through the monitor, and generate an exception message in a timely manner when there is an AXI bus hang, or the monitor can assist the master device and the slave device to solve the problem of the AXI bus hang.

[0004] Since the monitor needs to monitor a large number of data channels and the monitor is used to maintain the normal operation of the chip, it is necessary to verify the design of the monitor to ensure the normal operation of the monitor and further maintain the normal operation of the chip. Summary of the Invention

[0005] This application provides an AXI bus monitor verification system, method, electronic device, and storage medium to solve the problem that there is a lack of a suitable verification method for the anti-hang function of the monitor in the chip.

[0006] In a first aspect, this application provides an AXI bus monitor verification system, including: a module to be verified, a data interaction module, and a verification and judgment module; the data interaction module includes a master device and a slave device connected based on a data transmission channel; the data transmission channel between the master device and the slave device at least includes a handshake request channel, a handshake feedback channel, and a data feedback channel;

[0007] The module to be verified is configured to: start a counter when it is detected that the levels corresponding to the handshake request channel and the handshake feedback channel are both high levels; the high level corresponding to the handshake request channel is used to indicate that the master device has sent a handshake request instruction to the slave device; the high level corresponding to the handshake feedback channel is used to indicate that the slave device has fed back a confirmation handshake instruction to the master device;

[0008] If it is detected that the level of the data feedback channel is pulled up to a high level, stop the counter;

[0009] If the data response time of the slave device represented by the count value of the counter is greater than the time threshold, verification information is generated; and the verification information is sent to the verification judgment module; the verification information at least includes a verification interruption result and a verification timestamp; the verification interruption result is used to represent the data feedback state between the master device and the slave device; the verification timestamp is used to represent the generation moment of the verification interruption result;

[0010] The verification judgment module is configured to:

[0011] Obtain expected information corresponding to the module to be verified; the expected information includes an expected interruption result and an expected timestamp;

[0012] If the expected interruption result is the same as the verification interruption result, and the expected timestamp is the same as the verification timestamp, a first report information for representing that the module to be verified passes the verification is generated;

[0013] If the expected interruption result is different from the verification interruption result, and / or the expected timestamp is different from the verification timestamp, a second report information for representing that the module to be verified fails the verification is generated.

[0014] In some feasible embodiments, the handshake request channel includes a read handshake request channel; the handshake feedback channel includes a read handshake feedback channel; the data feedback channel includes a read data feedback channel; the module to be verified at least includes a read detection port connected to the read handshake request channel, the read handshake feedback channel, and the read data feedback channel;

[0015] When the master device and the slave device perform a read data interaction process, the module to be verified is configured to:

[0016] If it is detected through the read detection port that the electrical levels of the read handshake request channel and the read handshake feedback channel are both high level, start the counter;

[0017] If it is detected that the electrical level of the read data feedback channel is pulled up to a high level, stop the counter;

[0018] If the read data response time of the slave device represented by the count value of the counter is greater than the time threshold, verification information is generated.

[0019] In some feasible embodiments, the handshake request channel includes a write handshake request channel; the handshake feedback channel includes a write handshake feedback channel; the data feedback channel includes a write data feedback channel; the module to be verified at least includes a write detection port connected to the write handshake request channel, the write data feedback channel, and the write data feedback channel;

[0020] When the master device and the slave device perform a write data interaction process, the module to be verified is configured to:

[0021] If it is detected through the write detection port that the electrical levels of the write handshake request channel and the write handshake feedback channel are both high, start a counter;

[0022] If it is detected that the level of the write data feedback channel is pulled up to a high level, stop the counter;

[0023] If the write data response time of the slave device characterized by the count value of the counter is greater than a time threshold, generate verification information.

[0024] In some feasible embodiments, the verification judgment module includes a reference model and a scoreboard; the reference model at least includes model detection ports connected to the handshake request channel, the handshake feedback channel, and the data feedback channel;

[0025] The scoreboard is configured to: obtain expected information generated by the reference model based on the data interaction process executed by the master device and the slave device;

[0026] If the expected interrupt result is the same as the verification interrupt result, and the expected timestamp is the same as the verification timestamp, generate first report information for characterizing that the module to be verified passes the verification;

[0027] If the expected interrupt result is different from the verification interrupt result, and / or, the expected timestamp is different from the verification timestamp, generate second report information for characterizing that the module to be verified fails to pass the verification.

[0028] In some feasible embodiments, a verification information transfer port is further included;

[0029] The module to be verified is configured to send the verification information to the verification judgment module, specifically: send the verification information to the scoreboard through the verification information transfer port.

[0030] In some feasible embodiments, a configuration module is further included;

[0031] The configuration module is configured to: generate configuration information in response to a configuration information write instruction; the configuration information at least includes the time threshold or the counting threshold of the counter;

[0032] Before the master device and the slave device execute a data interaction process, the module to be verified is further configured to:

[0033] Obtain the configuration information from the configuration module.

[0034] In some feasible embodiments, the verification interruption result at least includes a read interruption result, a write interruption result, and an overall interruption result;

[0035] When the module to be verified generates verification information when the data response time of the slave device characterized by the count value of the counter is greater than the time threshold, it is further configured to:

[0036] Perform a bitwise OR operation on the read interruption result and the write interruption result to obtain the overall interruption result;

[0037] Generate the verification information according to the read interruption result, the write interruption result, and the overall interruption result;

[0038] Send the verification information to the verification judgment module.

[0039] In a second aspect, the present application provides an AXI bus monitor verification method, which can be applied to the AXI bus monitor verification system in the first aspect. The verification method includes:

[0040] When it is detected that the electrical levels corresponding to the handshake request channel and the handshake feedback channel are both high levels, start the counter; the high level of the electrical level corresponding to the handshake request channel is used to represent that the master device has sent a handshake request instruction to the slave device; the high level of the electrical level corresponding to the handshake feedback channel is used to represent that the slave device has fed back a confirmation handshake instruction to the master device;

[0041] If it is detected that the electrical level of the data feedback channel is pulled up to a high level, stop the counter;

[0042] If the data response time of the slave device characterized by the count value of the counter is greater than the time threshold, generate verification information; and send the verification information to the verification judgment module; the verification information at least includes a verification interruption result and a verification timestamp; the verification interruption result is used to represent the data feedback state between the master device and the slave device; the verification timestamp is used to represent the generation moment of the verification interruption result;

[0043] Obtain the expected information corresponding to the verification information; the expected information includes an expected interruption result and an expected timestamp;

[0044] If the expected interruption result is the same as the verification interruption result, and the expected timestamp is the same as the verification timestamp, generate a first report information for representing that the verification is passed;

[0045] If the expected interruption result is different from the verified interruption result, and / or the expected timestamp is different from the verified timestamp, then generate second report information for characterizing that the verification fails.

[0046] In a third aspect, the present application provides an electronic device, which includes a processor and a memory communicatively connected to the processor. The memory stores instructions executable by the processor to enable the processor to execute the steps of the verification method in the second aspect.

[0047] In a fourth aspect, the present application provides a computer-readable storage medium, which includes at least one computer instruction for causing a computer to execute the steps of the verification method in the second aspect.

[0048] As can be seen from the above technical content, the embodiments of the present application provide an AXI bus monitor verification system, method, electronic device and storage medium. The verification system includes a module to be verified, a data interaction module and a verification judgment module. The module to be verified can detect the level of the data transmission channel between the master device and the slave device in the data interaction module, and then, when the handshake feedback channel between the slave device and the master device is at a high level, count the response time of the slave device to feedback the target data to the master device. The verification judgment module can obtain the expected information corresponding to the verification information output by the module to be verified, and compare the verification information with the expected information when the module to be verified outputs the verification information, so as to determine whether the anti-hang function of the module to be verified operates normally. In this way, the verification of the anti-hang function of the module to be verified can be realized, which is beneficial to maintaining the normal operation of the chip equipped with the module to be verified. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0050] Figure 1 It is the schematic diagram of the monitor working principle provided by the embodiment of the present application;

[0051] Figure 2 It is the structural diagram of the monitor anti-hang function verification system provided by the embodiment of the present application;

[0052] Figure 3 It is the flowchart of the monitor anti-hang function verification provided by the embodiment of the present application;

[0053] Figure 4 It is the judgment flowchart when the module to be verified generates verification information provided by the embodiment of the present application;

[0054] Figure 5A flowchart for judging verification information and expected information provided by an embodiment of the present application;

[0055] Figure 6 A flowchart for judging a module to be verified during the read data interaction between the master device and the slave device provided by an embodiment of the present application;

[0056] Figure 7 A flowchart for judging a module to be verified during the write data interaction between the master device and the slave device provided by an embodiment of the present application. Detailed implementation manners

[0057] The embodiments will be described in detail below, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following embodiments do not represent all implementation manners consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application detailed in the claims.

[0058] During the operation of the chip, the master device and the slave device in the chip can perform data interaction based on the AXI bus (Advanced eXtensible Interface). For example, the master device reads data from the slave device based on the AXI bus, or the master device writes data to the slave device based on the AXI bus. During the interaction between the master device and the slave device, the slave device may take too long to reply to the read request or write request of the master device due to being in a busy state or an abnormal state, which may cause the bus to hang. In this way, it is easy to cause the chip to have a systematic deadlock problem due to the AXI bus hanging.

[0059] Therefore, during the chip design process, a monitor can be designed to monitor the data interaction between the master device and the total device through the anti-hang function of the monitor, so as to prevent the problem that the AXI bus is easily hung due to communication abnormalities of the devices participating in the data interaction, resulting in a systematic deadlock of the chip. Taking the read data process between the master device and the slave device as an example, when the slave device does not feedback the read data to the master device for a long time, the monitor can report information such as the hang state and hang time to the master device, so that the master device pauses the current read data interaction process, which is beneficial to reducing the risk of systematic deadlock of the chip caused by the AXI bus hanging.

[0060] As Figure 1 shown, the monitor can be connected to the data interaction channels between the master device and the slave device through preset ports, such as the handshake channel and data transmission channel between the master device and the slave device. In this way, the monitor can learn about the interaction situation between the master device and the slave device, and judge whether there is a phenomenon of AXI bus hanging between the master device and the slave device according to the response situation of the slave device to the request initiated by the master device.

[0061] The monitor can characterize the data interaction status between the master device and the slave device by outputting different interruption messages. Therefore, during the chip design process, it is also necessary to verify the monitor to determine whether the anti-hang function design of the monitor is appropriate, thereby improving the stability of the chip during operation. That is, it is necessary to comprehensively verify the anti-hang function of the monitor.

[0062] As Figure 2 and Figure 3 shown, an AXI bus monitor verification system is provided in an embodiment of the present application to comprehensively verify the anti-hang function of the monitor. The verification system includes a module to be verified, a data interaction module, and a verification and judgment module. The data interaction module includes a master device and a slave device connected based on a data transmission channel. The data transmission channel between the master device and the slave device includes at least a handshake request channel, a handshake feedback channel, and a data feedback channel.

[0063] In some embodiments, the module to be verified can be a monitor with an anti-hang function. The master device and the slave device in the data interaction module can both be vip components based on the UVM environment (Universal Verification Methodology). By configuring the vip components, the vip components can have the same functions as the master device and the slave device, facilitating the simulation of the operation scenario of the anti-hang function of the monitor. Among them, the vip components used to simulate the master device and the slave device can be denoted as axi_mst_if and axi_slv_if respectively.

[0064] The verification and judgment module can include components such as a scoreboard (scrb) and a reference model (Ref, Reference Model) integrated in the UVM environment. Furthermore, the verification and judgment module can compare the verification information output by the module to be verified with the preset expected information to determine whether the anti-hang function of the monitor is operating normally based on the comparison result.

[0065] In some embodiments, the data interaction module can be set in the amba_env layer in the UVM environment, that is, the amba_env layer is used to simulate the data interaction between the master and slave devices in the chip, providing a data source for verifying the anti-hang function of the monitor. The verification and judgment module can be set in the env layer in the UVM environment to facilitate the verification and judgment module to obtain the data generated in the module to be verified and the amba_env layer.

[0066] In addition, the UVM environment can also include a test layer for providing test cases and configuration information, and a top layer for providing components, interfaces, component connection methods, and interface connection methods required for verification.

[0067] In this way, after building an AXI bus monitor verification system based on the UVM environment, the master device and the slave device can be stimulated by pre-prepared test cases to perform data interaction, thereby realizing the verification of the module to be verified.

[0068] As Figure 4 shown, in some embodiments, when the master device and the slave device in the verification environment perform data interaction, the module to be verified is configured as:

[0069] When it is detected that the electrical levels corresponding to the handshake request channel and the handshake feedback channel are both high, start a counter; the high level of the electrical level corresponding to the handshake request channel is used to indicate that the master device has sent a handshake request instruction to the slave device; the high level of the electrical level corresponding to the handshake feedback channel is used to indicate that the slave device has fed back a confirmation handshake instruction to the master device.

[0070] If it is detected that the electrical level of the data feedback channel is pulled up to a high level, stop the counter.

[0071] If the data response time of the slave device represented by the count value of the counter is greater than the time threshold, generate verification information; and send the verification information to the verification judgment module; the verification information at least includes a verification interruption result and a verification timestamp; the verification interruption result is used to indicate the data feedback state between the master device and the slave device; the verification timestamp is used to indicate the generation time of the verification interruption result.

[0072] The module to be verified can be connected to the handshake request channel, the handshake feedback channel, and the data feedback channel through a preset port. In this way, when the master device and the slave device perform data interaction, the module to be verified can obtain the interaction state of the master device and the slave device. It can be understood that when the master device issues a data interaction instruction to the slave device, it can first send a handshake instruction to the slave device to determine whether the slave device can currently perform a data interaction action. In this way, when the master device sends a handshake request instruction to the slave device, the module to be verified can detect that the electrical level corresponding to the handshake request channel changes from low level to high level. Similarly, when the slave device feeds back a confirmation handshake instruction to the master device through the handshake feedback channel, the electrical level corresponding to the handshake feedback channel also changes from low level to high level. After the slave device feeds back a confirmation handshake instruction to the master device, it can feed back data to the master device through the data feedback channel.

[0073] Therefore, in some embodiments, the module to be verified is configured to count the response time of the slave device to start feeding back data to the master device at the moment when the electrical level corresponding to the handshake feedback channel becomes high, so as to determine whether there is a hanging phenomenon in the data feedback channel. Among them, the module to be verified can count the response time of the slave device by means of counter counting. And in combination with the time threshold, it is judged whether there is a hanging phenomenon in the data feedback channel.

[0074] In some embodiments, the module to be verified determines whether the slave device feeds back data to the master device by detecting whether the level of the data feedback channel changes from low level to high level. When detecting that the data feedback channel is pulled high to the high level, the module to be verified may stop the counting function of the counter. In addition, interruption information for characterizing the normal operation of the current data request may also be generated.

[0075] In other embodiments, when the time represented by the count value generated by the counter is greater than the time threshold, the module to be verified generates verification information including a verification interruption result and a verification timestamp to characterize that there is a hang-up phenomenon in the data feedback channel through the verification information. Among them, the verification interruption result can be used to characterize the hang-up state, and the verification timestamp can characterize the output time of the verification interruption result. Furthermore, the verification judgment result can judge whether the anti-hang-up function of the module to be verified operates normally from two aspects: the verification interruption result output by the module to be verified and the output time of the verification interruption result.

[0076] It can be understood that after generating the verification information, the module to be verified may send the verification information to the verification judgment module, and then the verification judgment module compares the verification information with the expected information.

[0077] As Figure 5 shown, the verification judgment module is configured to:

[0078] Obtain expected information corresponding to the module to be verified; the expected information includes an expected interruption result and an expected timestamp.

[0079] If the expected interruption result is the same as the verification interruption result, and the expected timestamp is the same as the verification timestamp, a first report information for characterizing that the module to be verified passes the verification is generated.

[0080] If the expected interruption result is different from the verification interruption result, and / or, the expected timestamp is different from the verification timestamp, a second report information for characterizing that the module to be verified fails to pass the verification is generated.

[0081] In some embodiments, the verification judgment module may obtain expected information corresponding to the verification information, and judge whether the anti-hang-up function of the module to be verified operates normally by comparing the expected information with the verification information. For example, when the expected interruption result is the same as the verification interruption result, and the expected timestamp is the same as the verification timestamp, a first report information for characterizing that the module to be verified passes the verification may be generated.

[0082] For another example, when any one of these two judgment aspects is different, a second report information for characterizing that the module to be verified fails to pass the verification may be generated.

[0083] It can be understood that when judging the interruption result, the expected interruption result and the verified interruption result can be determined according to the specific interruption bits and the corresponding values of the interruption bits. Moreover, the judgment logic of the verification judgment module can be adjusted according to actual requirements to adapt to the specific verification scenarios of the anti-hang function.

[0084] As Figure 6 shown, the handshake request channel between the master device and the slave device may include a read handshake request channel (arval id), and the handshake feedback channel may include a read handshake feedback channel (arready). The read data feedback channel includes a read data feedback channel (rvalid). In this way, the module to be verified at least includes a read detection port connected to the read handshake request channel, the read handshake feedback channel, and the read data feedback channel. In addition, the module to be verified can also be connected to the read response ready channel (rready) between the master device and the slave device through the read detection port. It can be understood that the slave device needs to have the read response ready channel at a high level to feedback data to the master device. Furthermore, when the master device and the slave device perform the read data interaction process, the module to be verified is configured as:

[0085] If the electrical levels of the read handshake request channel and the read handshake feedback channel are both detected as high level through the read detection port, start the counter.

[0086] If the electrical level of the read data feedback channel is detected as being pulled high to a high level, stop the counter.

[0087] If the read data response time of the slave device characterized by the count value of the counter is greater than the time threshold, generate verification information.

[0088] In some embodiments, after receiving the stimulus, the master device in the verification environment can send a read handshake request to the slave device to initiate a read data interaction process. And after receiving the read handshake request, the slave device will feedback a confirmation handshake command to the master device through the read feedback channel. During the process of the master device sending a read handshake request to the slave device and the slave device feedbacking a confirmation handshake command to the master device, the electrical levels of the read handshake request channel and the read handshake feedback channel will both be pulled high from a low level. And after the slave device feedbacks a confirmation handshake command to the master device, it will feedback data to the master device through the read data feedback channel.

[0089] In this way, after the module to be verified detects that the level corresponding to the read feedback channel is pulled up to a high level, it can start the counter to count, and detect the level state of the read data feedback channel through the read detection port connected to the read data feedback channel. When the time represented by the count value of the counter is less than or equal to the time threshold, and the module to be verified detects that the level state of the read data feedback channel is pulled up to a high level, it can stop the counting operation of the counter. At this time, it indicates that the data interaction between the master device and the slave device is normal. Moreover, after the module to be verified stops the counting operation of the counter, it can initialize the counter so that the counter can be used for subsequent monitoring processes. In addition, for the channels that need to be monitored, counters can be set to implement a full-range anti-hang function verification.

[0090] When the time represented by the count value of the counter is greater than the time threshold, it indicates that there is a hang phenomenon in the read data feedback channel between the master device and the slave device. In this way, the module to be verified will immediately generate verification information and send it to the verification judgment module, so that the verification judgment module can judge whether the anti-hang function of the module to be verified is operating normally based on the interrupt result and the timestamp.

[0091] In some other embodiments, the test cases can be adjusted according to the verification requirements, so that the module to be verified monitors other channels between the master device and the slave device. Then, the verification judgment module judges whether the module to be verified detects the anti-hang function provided for other channels based on the interrupt result and the timestamp output by the module to be verified during the monitoring process of other channels, so as to comprehensively verify whether the anti-hang function of the monitor can operate normally. Among them, other functions include but are not limited to the read handshake request channel, the read handshake feedback channel, and the read response ready channel.

[0092] As Figure 7 shown, the handshake request channel between the master device and the slave device may further include a write handshake request channel (awval id), and the handshake feedback channel may further include a write handshake feedback channel (awready). The data feedback channel may further include a write data feedback channel (bvalid). In this way, the module to be verified may further include write detection ports connected to the write handshake request channel, the write handshake feedback channel, and the write data feedback channel. In addition, the module to be verified may also be connected to the write response ready channel (bready) through the write detection port to monitor the write response state of the master device. Furthermore, when the master device and the slave device perform a write data interaction process, the module to be verified is configured as:

[0093] When the master device and the slave device perform a write data interaction process, the module to be verified is configured as:

[0094] If it is detected through the write detection port that the levels of the write handshake request channel and the write handshake feedback channel are both high, start the counter.

[0095] If it is detected that the level of the write data feedback channel is pulled high to a high level, stop the counter.

[0096] If the write data response time of the master device represented by the count value of the counter is greater than the time threshold, generate verification information.

[0097] In some embodiments, the master device in the verification environment can send a write handshake request instruction to the slave device through the write handshake request channel after receiving the stimulus, so as to simulate the write data interaction process in the slave device simulation chip. After receiving the write handshake request instruction, the slave device can feedback a write handshake confirmation instruction to the master device through the write handshake feedback channel. Furthermore, during the interaction process of the write handshake request instruction and the write handshake confirmation instruction, the module to be verified can detect that the levels of the write handshake request channel and the write handshake feedback channel are pulled high. And when the levels of both the write handshake request channel and the write handshake feedback channel are pulled high, the module to be verified can start the counter to count the write response time of the master device.

[0098] In this way, when the master device writes data to the slave device through the write data feedback channel, the module to be verified can detect the level state corresponding to the write data feedback channel through the write detection port connected to the write data feedback channel. Furthermore, it is combined with the write response time of the slave device represented by the count value of the counter and the time threshold to judge whether there is a hanging phenomenon in the write data feedback channel.

[0099] For example, when the module to be verified detects that the level of the write data feedback channel is pulled high to a high level within a time less than or equal to the time threshold, it can stop the counting operation of the counter. At this time, there is no hanging phenomenon in the write data feedback channel.

[0100] For another example, when the write response time of the slave device represented by the count value of the module to be verified is greater than the time threshold, the module immediately outputs verification information including a verification interruption result and a verification timestamp, and sends the verification information to the verification judgment module, and the verification judgment module judges whether the anti-hanging function of the module to be verified is running normally according to the verification information.

[0101] It can be understood that the corresponding response time can be determined by adjusting the timing frequency of the counter and coordinating with the counting quantity of the counter. The timing frequency can be determined according to the clock cycle provided in the verification environment.

[0102] Such as Figure 2As shown in the figure, the verification and judgment module may include a reference model and a scoreboard. Among them, the reference model is an ideal model built based on components, interfaces, etc. provided in the UVM environment for simulating the module to be verified. The reference model can output the expected values corresponding to the verification scenarios in a timely manner based on monitoring each channel between the master device and the slave device. That is, the reference model includes at least model detection ports connected to the handshake request channel, the handshake feedback channel, and the data feedback channel. Among them, the model detection ports can be further divided into ports connected to the read handshake request channel, the read handshake feedback channel, the read data feedback channel, the write handshake request channel, the write handshake feedback channel, and the write data feedback channel, so that the reference model can comprehensively monitor the status of each channel between the master device and the slave device in the verification environment.

[0103] The scoreboard can be used to compare the verification information output by the module to be verified with the expected information output by the reference model, and then determine whether the anti-hang function of the module to be verified is operating normally. In some embodiments, the scoreboard is configured to:

[0104] Obtain the expected information generated by the reference model based on the data interaction process between the master device and the slave device.

[0105] If the expected interrupt result is the same as the verification interrupt result, and the expected timestamp is the same as the verification timestamp, then generate the first report information for characterizing that the module to be verified passes the verification.

[0106] If the expected interrupt result is different from the verification interrupt result, and / or, the expected timestamp is different from the verification timestamp, then generate the second report information for characterizing that the module to be verified fails to pass the verification.

[0107] In some embodiments, the scoreboard can obtain the expected information output by the reference model and the verification information output by the module to be verified. Furthermore, the scoreboard can compare the expected interrupt result with the verification interrupt result and compare the expected timestamp with the verification timestamp.

[0108] For example, when the expected interrupt result is the same as the verification interrupt result, and the expected timestamp and the verification timestamp are both the same, it means that the anti-hang function of the module to be verified is operating normally. Furthermore, the scoreboard can generate the first report information and output it.

[0109] For another example, when the expected interrupt result is different from the verification interrupt result, or the expected timestamp is different from the verification timestamp, it means that the anti-hang function of the module to be verified is operating abnormally. Furthermore, the scoreboard can generate the second report information and output it.

[0110] It should be noted that the verification timestamp can represent the time when the module to be verified generates the verification interruption result. Therefore, the response speed of the anti-hang function of the module to be verified can be verified based on the verification timestamp. Thus, even if the expected interruption result is the same as the verification interruption result, but the expected timestamp and the verification timestamp are different, the anti-hang function of the module to be verified is still regarded as operating abnormally. Among them, the verification timestamp can be denoted as tmr_cnt.

[0111] Similarly, even if the expected timestamp and the verification timestamp are the same, but the verification interruption result is different from the expected interruption result, the anti-hang function of the module to be verified is still regarded as operating abnormally.

[0112] As Figure 2 shown, the verification environment further includes a verification information transfer port. The interruption output port of the module to be verified can be connected to the verification information transfer port, and then the verification information is sent to the scoreboard through the verification information transfer port. In this way, the transfer of the output data of the module to be verified can be realized by means of the verification information transfer port.

[0113] In some embodiments, the time threshold can be denoted as time_out, and the time threshold can be pre-configured according to the verification requirements. That is, the verification system further includes a configuration module for configuring the time threshold.

[0114] The configuration module is configured to:

[0115] Respond to the configuration information write instruction to generate configuration information; the configuration information at least includes the time threshold or the counting threshold of the counter.

[0116] Before the master device and the slave device perform data interaction, the module to be verified is further configured to:

[0117] Obtain the configuration information from the configuration module.

[0118] In some embodiments, the configuration module can be a module integrated in the test layer, and the time threshold or the counting threshold of the counter can be configured in the configuration module. Among them, the time threshold can be replaced by the counting threshold, and the scoreboard determines whether the expected timestamp and the verification timestamp are the same according to the counting threshold. By comparing with the counting threshold, its essence also belongs to the comparison of time.

[0119] It can be understood that the counting threshold or the time threshold can be adjusted in advance according to the actual verification scenario. For example, in the scenario where the verification environment simulates a large number of data interaction transactions, the time threshold can be set larger to adapt to the actual interaction state between the master device and the slave device. On the contrary, in the scenario where the verification environment simulates a small number of data interaction transactions, the time threshold can be set smaller.

[0120] In this way, before running, the module to be verified and the reference model can both obtain the time threshold or the count threshold from the configuration module, so as to monitor the status of each channel between the master device and the slave device in the verification environment according to the time threshold or the count threshold.

[0121] In some embodiments, the verification interruption result may include an initial read interruption (rd_int_raw) corresponding to the read data feedback channel, a masked read interruption (rd_int_sts), an initial write interruption (wr_int_raw) corresponding to the write data feedback channel, a masked write interruption (wr_int_sts), and an overall interruption situation (wr_int_sts|rd_int_sts). In this way, by comprehensively comparing these interruptions, the operating status of the anti-hang function of the module to be verified can be judged. Among them, when the data response time of the slave device represented by the count value of the counter in the module to be verified is greater than the time threshold and generating verification information, it is further configured to:

[0122] Perform a bitwise OR operation on the read interruption result and the write interruption result to obtain the overall interruption result;

[0123] Generate the verification information according to the read interruption result, the write interruption result, and the overall interruption result;

[0124] Send the verification information to the verification judgment module.

[0125] It can be understood that the overall interruption situation = wr_int_sts|rd_int_sts, that is, the overall interruption result is the result obtained by performing a bitwise OR operation on the masked read interruption and the masked write interruption. The overall interruption result can reflect the overall operating status of the anti-hang function of the monitor. The module to be verified can send each verification interruption result to the scoreboard through the interruption output port, or send the integrated verification information to the scoreboard.

[0126] In this way, the scoreboard can comprehensively compare the operating status of the anti-hang function when the channels between the master device and the slave device in the module to be verified are in a hang state.

[0127] In some embodiments, an AXI bus monitor verification method is provided, which can be applied to the AXI bus monitor verification system in system-level embodiments. The verification method includes:

[0128] When it is detected that the electrical levels corresponding to the handshake request channel and the handshake feedback channel are both high levels, start the counter; the high level corresponding to the handshake request channel is used to represent that the master device has sent a handshake request instruction to the slave device; the high level corresponding to the handshake feedback channel is used to represent that the slave device has fed back an acknowledgment handshake instruction to the master device;

[0129] If it is detected that the level of the data feedback channel is pulled high to a high level, stop the counter;

[0130] If the data response time of the slave device represented by the count value of the counter is greater than the time threshold, generate verification information; and send the verification information to the verification judgment module; the verification information at least includes a verification interruption result and a verification timestamp; the verification interruption result is used to represent the data feedback state between the master device and the slave device; the verification timestamp is used to represent the generation time of the verification interruption result;

[0131] Obtain expected information corresponding to the verification information; the expected information includes an expected interruption result and an expected timestamp;

[0132] If the expected interruption result is the same as the verification interruption result, and the expected timestamp is the same as the verification timestamp, generate a first report information for indicating that the verification is passed;

[0133] If the expected interruption result is different from the verification interruption result, and / or, the expected timestamp is different from the verification timestamp, generate a second report information for indicating that the verification fails.

[0134] In some embodiments, an electronic device is provided. The electronic device includes a processor and a memory communicatively connected to the processor. Among them, the memory stores instructions executable by the processor, so that the processor executes the steps of the verification method in the method embodiments.

[0135] In some embodiments, a computer-readable storage medium is provided. The computer-readable storage medium includes at least one computer instruction, and the at least one computer instruction is used to make a computer execute the steps of the verification method in the method embodiments.

[0136] The embodiments of the present application provide an AXI bus monitor verification system, method, electronic device and storage medium. The verification system includes a module to be verified, a data interaction module and a verification judgment module. The module to be verified can detect the level of the data transmission channel between the master device and the slave device in the data interaction module, and then, when the handshake feedback channel between the slave device and the master device is at a high level, count the response time of the slave device to feedback the target data to the master device. The verification judgment module can obtain the expected information corresponding to the verification information output by the module to be verified, and when the module to be verified outputs the verification information, compare the verification information with the expected information to determine whether the anti-hang function of the module to be verified is operating normally. In this way, the verification of the anti-hang function of the module to be verified can be realized, which is beneficial to maintaining the normal operation of the chip equipped with the module to be verified.

[0137] For the similar parts among the embodiments provided in this application, reference may be made to each other. The specific embodiments provided above are only several examples under the general concept of this application and do not constitute a limitation on the protection scope of this application. For those skilled in the art, any other embodiments extended based on the solution of this application without creative efforts fall within the protection scope of this application.

Claims

1. An axi bus monitor verification system, characterized in that, include: Module to be verified, data interaction module, verification judgment module; The data interaction module includes a master device and a slave device connected based on a data transmission channel; The data transmission channel between the master device and the slave device at least includes a handshake request channel, a handshake feedback channel and a data feedback channel; The module to be verified is configured to: start a counter when it is detected that the levels corresponding to the handshake request channel and the handshake feedback channel are both high levels; the level corresponding to the handshake request channel is high level to indicate that the master device has sent a handshake request instruction to the slave device; The level corresponding to the handshake feedback channel is a high level, which is used to indicate that the slave device has fed back a confirmation handshake instruction to the master device; If it is detected that the level of the data feedback channel is pulled up to a high level, stop the counter; If the data response time of the slave device represented by the count value of the counter is greater than the time threshold, then generating verification information; and sending the verification information to the verification judgment module; the verification information at least includes a verification interrupt result and a verification timestamp; The verification interrupt result is used to characterize the data feedback state between the master device and the slave device; the verification timestamp is used to characterize the generation time of the verification interrupt result; The verification judgment module is configured as follows: Acquire expected information corresponding to the module to be verified; the expected information includes an expected interrupt result and an expected timestamp; If the expected interruption result is the same as the verification interruption result, and the expected timestamp is the same as the verification timestamp, generating first report information for indicating that the module to be verified has passed the verification; If the expected interruption result is different from the verification interruption result, and / or the expected timestamp is different from the verification timestamp, second report information is generated to indicate that the module to be verified has not passed the verification.

2. The axi bus monitor verification system according to claim 1, characterized in that, The handshake request channel includes a read handshake request channel; the handshake feedback channel includes a read handshake feedback channel; The data feedback channel includes a read data feedback channel; The module to be verified at least includes a read detection port connected to the read handshake request channel, the read handshake feedback channel and the read data feedback channel; When the master device and the slave device perform a data reading interaction process, the module to be verified is configured as follows: If it is detected through the read detection port that the levels of the read handshake request channel and the read handshake feedback channel are both high, start the counter; If it is detected that the level of the read data feedback channel is pulled up to a high level, stop the counter; If the read data response time of the slave device represented by the count value of the counter is greater than a time threshold, verification information is generated.

3. The axi bus monitor verification system according to claim 1, characterized in that: The handshake request channel includes a write handshake request channel; the handshake feedback channel includes a write handshake feedback channel; the data feedback channel includes a write data feedback channel; The module to be verified at least includes a write detection port connected to the write handshake request channel, the write data feedback channel and the write data feedback channel; When the master device and the slave device perform a data writing interaction process, the module to be verified is configured as follows: If it is detected through the write detection port that the levels of the write handshake request channel and the write handshake feedback channel are both high, start a counter; If it is detected that the level of the write data feedback channel is pulled up to a high level, stop the counter; If the write data response time of the slave device represented by the count value of the counter is greater than a time threshold, verification information is generated.

4. The axi bus monitor verification system according to claim 1, characterized in that: The verification and judgment module includes a reference model and a scoreboard; the reference model at least includes a model detection port connected to the handshake request channel, the handshake feedback channel and the data feedback channel; The scoreboard is configured to: obtain expected information generated by the reference model based on a data interaction process performed by the master device and the slave device; If the expected interruption result is the same as the verification interruption result, and the expected timestamp is the same as the verification timestamp, generating first report information for indicating that the module to be verified has passed the verification; If the expected interruption result is different from the verification interruption result, and / or the expected timestamp is different from the verification timestamp, second report information is generated to indicate that the module to be verified has not passed the verification.

5. The axi bus monitor verification system according to claim 4, characterized in that: It also includes a verification information transfer port; The module to be verified executes sending the verification information to the verification judgment module, and is specifically configured to: send the verification information to the scoreboard through the verification information transfer port.

6. The axi bus monitor verification system according to claim 1, characterized in that: Also includes: Configuration module; The configuration module is configured to: generate configuration information in response to a configuration information write instruction; the configuration information at least includes the time threshold or the count threshold of the counter; Before the master device and the slave device perform a data interaction process, the module to be verified is further configured to: The configuration information is obtained from the configuration module.

7. The axi bus monitor verification system according to claim 1, characterized in that: The verification interruption result at least includes a read interruption result, a write interruption result, and an overall interruption result; When the data response time of the slave device represented by the count value of the counter is greater than the time threshold, the module to be verified is further configured to: Performing a bitwise OR operation on the read interrupt result and the write interrupt result to obtain the overall interrupt result; Generate the verification information according to the read interruption result, the write interruption result and the overall interruption result; The verification information is sent to the verification judgment module.

8. An Axi bus monitor verification method, characterized in that: An AXI bus monitor verification system applied to any one of claims 1-7; the verification method comprises: When it is detected that the levels corresponding to the handshake request channel and the handshake feedback channel are both high, the counter is started; the level corresponding to the handshake request channel is high, which is used to indicate that the master device has sent a handshake request instruction to the slave device; the level corresponding to the handshake feedback channel is high, which is used to indicate that the slave device has fed back a confirmation handshake instruction to the master device; If it is detected that the level of the data feedback channel is pulled up to a high level, the counter is stopped; If the data response time of the slave device represented by the count value of the counter is greater than the time threshold, verification information is generated; and the verification information is sent to the verification judgment module; the verification information at least includes a verification interrupt result and a verification timestamp; the verification interrupt result is used to represent the data feedback state between the master device and the slave device; the verification timestamp is used to represent the time when the verification interrupt result is generated; Acquire expected information corresponding to the verification information; the expected information includes an expected interruption result and an expected timestamp; If the expected interruption result is the same as the verification interruption result, and the expected timestamp is the same as the verification timestamp, generating first report information for indicating that the verification is passed; If the expected interruption result is different from the verification interruption result, and / or the expected timestamp is different from the verification timestamp, second report information for indicating that the verification has not passed is generated.

9. An electronic device, characterized in that: include: A processor, and a memory communicatively connected to the processor; The memory stores instructions executable by the processor so that the processor performs the steps of the method described in claim 8.

10. A computer-readable storage medium, characterized in that: include: The computer-readable storage medium includes at least one computer instruction, and the at least one computer instruction is used to make a computer execute the steps of the method as claimed in claim 8.

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