Prediction acknowledgment for a cache subsystem

Abstract

The present disclosure relates to prediction validation for a cache subsystem. A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information into cache lines arranged into a plurality of ways. A request circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction as to which way of the ways includes the particular cache line. A comparison circuit validates the prediction by comparing a particular address tag associated with the particular cache line and a cache tag corresponding to the predicted way of the ways. In response to determining that the prediction is correct, a validation indication is stored indicating the correct prediction. For subsequent requests for the particular cache line, the cache is configured to forego validating the prediction that the particular cache line is included in a way of the ways based on the validation indication.

Description

[0001] This application is a divisional application of the invention patent application filed on July 20, 2022, with application number 202280054983.X and invention title "Predictive Verification of Cache Subsystem". Technical Field

[0002] This disclosure relates to computer systems, and more specifically to caching subsystems. Background Technology

[0003] Description of related technologies

[0004] Computer systems employ various types of memory within a memory hierarchy. This hierarchy extends from architectural registers in the processor (for example, to store operands for instructions to be executed) to large-capacity storage such as hard disk drives or solid-state drives. Many computer systems also include multi-level cache memory.

[0005] A cache is a type of memory that is below registers in the memory hierarchy but above system memory, such as random access memory (RAM). Caches store information based on the principle of locality, including temporal locality (e.g., recently accessed information is likely to be accessed again within a given time) and spatial locality (e.g., recently accessed information is likely to be stored near other information that will be accessed). Information stored in a cache based on these principles can be accessed much faster than if it were stored solely in system RAM or large-capacity storage. Therefore, caches can improve the overall performance of a computer system by reducing the time it takes for the processor to access at least some information (e.g., data or instructions). Summary of the Invention

[0006] A means for prediction verification in a caching subsystem is disclosed. In one embodiment, the caching subsystem includes a cache configured to store information in cache lines arranged in a multiplexed manner. A request circuit is configured to generate a request to access a specific cache line in the cache. A prediction circuit is configured to generate a prediction about which of the multiplexed manners of the cache includes the specific cache line. A comparison circuit is configured to verify the prediction by comparing a specific address tag associated with the specific cache line with a cache tag corresponding to one of the predicted multiplexed manners. The prediction circuit is further configured to, in response to the comparison circuit determining that the prediction is correct, store a verification indication indicating that the prediction is correct, and wherein, for subsequent access requests to the specific cache line, the cache is configured to, based on the verification indication indicating that the prediction is correct, abandon verification of the prediction about which of the multiplexed manners the specific cache line is included.

[0007] In one implementation, verifying the prediction involves reading an address tag from an address tag memory. This address tag, along with the cache tag, is provided to the comparator. Upon determining that the address tag and the cache tag match, the prediction is confirmed as correct, and the prediction circuitry gives the same indication, setting a confirmation bit. This confirmation bit is stored in a confirmation bit memory. For subsequent requests of correctly predicted cache lines, the confirmation bit memory is queried. Since the confirmation bit is determined to be set, the cache subsystem abandons reading the cache tag from the cache and the comparison operation. Therefore, abandoning the tag read and comparison operation saves non-negligible power consumption. Attached Figure Description

[0008] The following detailed description refers to the accompanying drawings, which will now be briefly described.

[0009] Figure 1 This is a block diagram of one implementation scheme for the caching subsystem.

[0010] Figure 2 This is a block diagram of one implementation of a cache subsystem with instruction caching.

[0011] Figure 3 This is a block diagram of one implementation of a caching subsystem with data caching.

[0012] Figure 4 This is a block diagram of one implementation scheme of the confirmation bit memory.

[0013] Figure 5 This is a flowchart illustrating one implementation of a method for operating the cache subsystem.

[0014] Figure 6 This is a flowchart illustrating one implementation of a method for operating the cache subsystem.

[0015] Figure 7 This is a block diagram of one implementation of an exemplary system. Detailed Implementation

[0016] This disclosure relates to an apparatus and method for determining path prediction in a cache subsystem. Path prediction is used in the cache to reduce power consumption. Instead of searching for the block / page of a requested cache line across all paths, a prediction can be made about which specific path the cache line is stored in. If the prediction is correct, less power will be consumed compared to searching all paths.

[0017] When making a prediction, the address tag array can be read to obtain the address tag corresponding to the requested cache line. Alternatively, the cache tag corresponding to the predicted path can be read from the cache. The address tag and the cache tag corresponding to the predicted path are then compared. If the tags match, the path storing the requested cache line has been correctly predicted. However, even when the prediction is correct, reading the cache tag and subsequent comparison operations can still consume significant power, even though only a single path is searched instead of all paths in the cache. Furthermore, predictions can be made for every subsequent access to the cache line, thus repeating the work of the original correct prediction.

[0018] This disclosure is based on the view that once a cache line prediction is correct, the prediction will remain correct for subsequent accesses to that cache line unless the state of the cache line changes. Possible changes include the eviction of the cache line, the invalidation of the cache line, a context switch, or the prediction of a different virtual page. However, the prediction can also remain valid if the cache line is still effectively stored in the predicted path.

[0019] Based on the points discussed above, when a specific cache line is correctly predicted to be stored in a specific path, an acknowledgment bit can be added to that cache line. When a specific cache line is predicted and verified to be stored in that specific path, the acknowledgment bit is set and held until the state changes, as in one example provided in the preceding paragraphs. For subsequent access requests to that specific cache line, the acknowledgment bit is read, and the cache subsystem can abandon reading the cache tag, thus abandoning the comparison operation. This can save more power compared to correctly predicting the cache line in multiple different accesses. Furthermore, performance gains can be achieved by unacknowledging the prediction and thus avoiding repeating the steps required for the original prediction. The use of this acknowledgment bit can be particularly useful in certain situations, such as in program loops that repeatedly access specific cache lines.

[0020] It should be noted that while prediction verification as discussed herein may include label reading and comparison operations, this disclosure is not intended to limit it in this manner. Rather, this disclosure is intended to cover any suitable mechanism for verifying whether a cached line is stored in the predicted path of the cache.

[0021] This disclosure will now be discussed in more detail. First, a cache subsystem and its operations regarding prediction, acknowledgment of the prediction, and subsequent operations are discussed. Then, examples of cache subsystems utilizing an acknowledgment bit mechanism are discussed, including instruction cache subsystems and data cache subsystems. Next, an embodiment of a memory for storing acknowledgment bits is described. Following this, a flowchart illustrating a method for operating a cache subsystem with tagged acknowledgment bits is described. The description concludes with a discussion of an example system.

[0022] A caching subsystem with predictive confirmation:

[0023] Figure 1 This is a block diagram of one implementation of the caching subsystem, where the path to the requested cache line is predicted, and a confirmation bit is set if the prediction is correct. It is important to note that... Figure 1 Only a portion of the caching subsystem is shown, and the caching subsystem may include other circuitry, as will be referenced below. Figure 2 and Figure 3 The circuit under discussion.

[0024] In the illustrated embodiment, the cache subsystem 100 includes a prediction circuit 102, a cache 104, and a comparator circuit 120. The cache 104 in the illustrated embodiment includes N-way, and is an N-way set-associative cache. Alternatively, a fully associative embodiment of the cache 104 can also be considered.

[0025] Cache subsystem 100 is configured to receive cache access requests from requester 110. Requester 110 can be one of several different types of functional circuit units that can request cache access. In one embodiment, cache 104 is an instruction cache configured to store instructions executed by the processor. Therefore, requester 110 in this embodiment can be an instruction fetching unit that initiates a cache request to fetch instructions. In another embodiment, cache 104 is a data cache, and requester 110 can be a processor core or part thereof that initiates a request for data used during instruction execution. Generally, cache 104 can be either an instruction cache or a data cache, and requester 110 can be any type of functional circuit submitting an access request to the corresponding cache type.

[0026] In the illustrated embodiment, prediction circuit 102 is configured to predict the path that stores a specific cache line. More specifically, prediction circuit 102 generates a prediction in response to an incoming access request for the predicted cache line. Upon receiving an indication of the requested cache line, prediction circuit 102 generates the prediction and provides it to comparison circuit 120. In the illustrated embodiment, the requested address tag associated with the cache line is accessed by prediction circuit 102 and provided as part of the prediction process.

[0027] Comparison circuit 120 may also receive a cache tag provided by cache 104 in response to a request to verify the prediction. This cache tag provided by cache 104 may correspond to the predicted cache path. After obtaining the cache tag and the address tag (from prediction circuit 102), comparison circuit 120 performs a comparison operation. If the address tag matches the cache tag, the prediction is considered correct. Otherwise, the prediction is considered incorrect, and if the requested cache line exists in the cache, other paths are searched to find the requested cache line. If the requested cache line is not stored in the cache, it can be accessed from system memory.

[0028] In response to a correct prediction that a requested cache line is stored in a specific path, prediction circuitry 102 is configured to generate and store an acknowledgment indication. As described below, this acknowledgment indication, or acknowledgment bit, may be stored in dedicated memory. For subsequent predictions of that specific cache line, the setting of this acknowledgment bit indicates that a previous prediction regarding the specific path storing that cache line was correct. Therefore, in response to observing that the acknowledgment bit is set, cache subsystem 100 may abandon certain operations if a cache line associated with that correct prediction is requested again.

[0029] If the cache subsystem 100 determines that the acknowledgment bit has been set in the illustrated embodiment, the cache tag will not be read from cache 104. Furthermore, the comparison circuit 120 does not perform a comparison operation because no cache tag is provided. Therefore, for subsequent requests that have been correctly predicted as cache lines stored in a specific path, the cache tag read and comparison operations are canceled. More generally, verification is not performed when the corresponding acknowledgment bit indicates that the path storing the requested cache line has been correctly predicted in a previous access. Canceling the verification operation significantly saves power and improves performance.

[0030] When the acknowledgment bit is set in response to a correct prediction, it remains set as long as the prediction itself remains valid. The acknowledgment bit can be reset in response to various events affecting the cache line associated with the correct prediction. For example, if the cache line becomes invalid, the acknowledgment bit is reset. Similarly, if the cache line is evicted from the cache, the acknowledgment bit is reset. Context switching can also reset the acknowledgment bit because the cache can be flushed. However, the acknowledgment bit remains set as long as the cache line associated with the correct prediction remains stored in the predicted cache line and remains valid.

[0031] Instruction and data caching subsystem:

[0032] Figure 2This is a block diagram of one implementation of a cache subsystem for implementing instruction caching. In the illustrated implementation, cache subsystem 200 includes an N-way set-associative cache, namely instruction cache 204. In this particular implementation, each set contains 2 paths, with path 0 and path 1 forming set 0. Although not explicitly shown, for this implementation, set 1 would include path 1 and path 2, and so on. Other implementations with different arrangements are also conceivable. Instruction cache 204 also includes a cache controller 209 that performs various cache control functions. These functions include, but are not limited to, storing cache lines, evicting cache lines, writing cache lines to instruction cache 204, invalidating cache lines, and reading and providing the requested cache line to the requesting party.

[0033] In the illustrated embodiment, instruction cache 204 is configured to store instructions executed by the processor. Therefore, the requester in this particular embodiment is instruction fetch unit 210, which requests access to instructions that will be executed as part of a program or instruction thread. The instruction fetch request is provided by instruction fetch circuitry 210 to prediction circuitry 202 and cache controller 209.

[0034] When a request to retrieve a cache line is issued, the request is received by prediction circuitry 202 and cache controller 209. In the illustrated embodiment, prediction circuitry 202 responds to the request by generating a prediction about a specific path in the instruction cache 204 where the requested cache line is stored. After generating the prediction, prediction circuitry 202 can access address tag memory 206 to obtain the address tag corresponding to the requested cache line. This address tag can then be provided to comparison circuitry 209 for use in a verification operation. The predicted path can also be provided to cache controller 209, which can use this information to determine whether the requested cache line is a previously correctly predicted object that is still valid.

[0035] The address tag memory 206 in the illustrated embodiment may store virtual addresses, although an embodiment storing physical addresses in the address tag memory is also conceivable. An alternative embodiment may also be considered where the address tag memory 206 stores virtual addresses, while the corresponding physical addresses are accessed from a translation back buffer (TLB) and used as the basis for comparisons performed by the comparator circuit 208. For the purposes of this disclosure, the address tag memory 206 may be considered as storing virtual addresses, physical addresses, and / or may also be considered as comprising multiple memories in which virtual addresses are stored in one memory circuit and corresponding physical addresses are stored in another memory circuit (e.g., the TLB mentioned above). Regardless of whether the provided address tag is virtual or physical, the comparator circuit 208 in the illustrated embodiment performs a comparison to determine whether the path prediction for the requested cache line is correct.

[0036] In the illustrated embodiment, the cache controller 209 initially responds to a request for a cache line by querying the acknowledgment bit memory 212. In this embodiment, the acknowledgment bit memory 212 is configured to correspond to acknowledgment bits that store cache indexes and corresponding paths that can store various cache lines. Using information about the predicted path and information about the requested cache line, the cache controller 209 can query the acknowledgment bit memory to determine whether an acknowledgment bit has already been set in that particular path for the requested cache line.

[0037] If the acknowledgment bit is not set (e.g., the acknowledgment bit is reset), indicating that a previous correct prediction for the requested cache line is currently invalid, the cache controller 209 can respond by providing an instruction cache tag to the comparator circuit 209, the instruction cache tag corresponding to the predicted path. In response, the comparator circuit 208 compares the address tag received from the address tag memory with the instruction tag received from the instruction cache 204. If the tags match (“hit”), the comparator circuit 208 provides an indication that the tags match to the prediction circuit 202. In response to receiving the hit indication, the prediction circuit 202 provides an indication to the acknowledgment bit memory 212 to indicate the correctly predicted path and corresponding index. The acknowledgment bit is then set in the acknowledgment bit memory 212 for the predicted path and index. Furthermore, by providing the cache controller 209 with the indication that the prediction is correct, the cache controller can respond by accessing the requested cache line and providing the requested cache line to the instruction fetch circuit 210.

[0038] It should be noted that an implementation could also combine the functions of the prediction circuit 202 and the comparator circuit 208 into a single unit. In such an implementation, the comparator circuit could serve as a source indicating that the prediction is correct. Figure 2 In the implementation scheme explicitly shown, it is also possible to consider the comparison circuit 208 providing an indication of the correct prediction to the confirmation bit memory 212.

[0039] If the prediction is incorrect (if the address label and the instruction label do not match), the prediction circuit 202 (or the comparison circuit 208) may provide an indication of the incorrect prediction to the cache controller 209. In response to the incorrect prediction, the cache controller 209 may search other paths in cache 204 to determine if the requested cache line is stored in another path. If the requested cache line is not stored in any path of instruction cache 204, a search in main system memory may be performed by the memory controller. If the requested cache line is stored in a path different from the predicted path, the requested cache line is provided to the instruction fetch circuit 210.

[0040] If a subsequent access request exists for an object (a specific cache line) that was previously correctly predicted, the verification process is not performed in the illustrated embodiment. Specifically, cache controller 209 may query the acknowledgment bit memory 212 again in response to a request for the specific cache line. Upon receiving an indication from the acknowledgment bit memory that the acknowledgment bit is set for the predicted path of the specific cache line, cache controller 209 in the illustrated embodiment issues a "disable verification" signal, which is received by comparator circuit 208. When comparator circuit 208 receives this signal, it indicates that cache controller 209 will no longer read the instruction tag used for comparison and therefore will not perform a comparison operation for that specific request. Significant power savings are achieved by abandoning the instruction tag reading and comparison operations. Canceling the tag reading and comparison operations also improves performance. Because the acknowledgment bit is set, cache controller 209 also responds by providing the specific cache line from the corresponding path instruction fetch circuit 210 of instruction cache 204, without the delay caused by waiting to confirm that the prediction has been verified.

[0041] In the illustrated embodiment, cache controller 209 is configured to reset acknowledgment bits stored in acknowledgment bit memory 212 in response to certain conditions. For example, if a cache line that was previously correctly predicted becomes invalid at some later time, cache controller 209 can reset the corresponding acknowledgment bit. Evicting a cache line that was previously correctly predicted and stored in a specific path can also reset the corresponding acknowledgment bit. Other conditions for resetting acknowledgment bits include a corresponding virtual-to-physical address translation failure, a context switch that flushes the cache (thus resetting all acknowledgment bits), and so on.

[0042] Figure 3 This is a block diagram of one implementation scheme for a caching subsystem that implements data caching. In the illustrated implementation scheme, the caching subsystem 300 and... Figure 2 The illustrated cache subsystem 200 is similar, with the main difference being that cache 304 is a data cache including cache controller 309. The requester 310 in the illustrated embodiment can be, for example, one of one or more processor cores utilizing data cache 304. More generally, requester 310 can be any type of functional circuit capable of accessing and utilizing the data cache. The functions of prediction circuit 302, comparison circuit 308, address tag memory 306, cache controller 309, and acknowledgment bit memory 312 can be similar to... Figure 2The corresponding portions shown are substantially similar. Furthermore, as with the case of cache subsystem 200 discussed above, these circuit units can differ between embodiments. In short, the cache subsystem 300 and its components in the illustrated embodiment are configured to make and verify predictions for a specific path of a requested cache line containing data, set an acknowledgment bit in response to a correct prediction, and abandon the verification process, including tag reading and comparison operations, when the acknowledgment bit indicates that a previous prediction of the requested cache line was correct.

[0043] Example of a confirmation bit memory:

[0044] Figure 4 This is a block diagram of one embodiment of an acknowledgment bit memory for storing acknowledgment bits corresponding to correct predictions, according to the present disclosure. In the illustrated embodiment, the acknowledgment bit memory 412 is arranged to store a plurality of acknowledgment bits 411. In the illustrated embodiment, when an acknowledgment bit is set (e.g., with a logic value of 1), it indicates that the path to store the requested cache line was previously correctly predicted and that the prediction remains valid. The prediction remains valid as long as the corresponding cache line remains validly stored in the cache. As described above, if the corresponding cache line has expired, been evicted, etc., and the corresponding path and index have not been correctly predicted, the acknowledgment bits can be placed in a reset state (e.g., with a logic value of 0). After the cache is refilled following a context switch, each acknowledgment bit can remain in the reset state until the cache line stored in the cache is correctly predicted.

[0045] In the illustrated embodiment, the acknowledgment bit memory 412 is arranged in a road and index manner, with the index associated with various address tags. Therefore, if a cache line associated with an address tag corresponding to a correctly predicted index A is stored, for example, in road 2, an acknowledgment bit 411 can be set at the intersection of the row of index A and the column of road 2. For subsequent requests of that particular cache line, the cache controller's reading of this acknowledgment bit can cancel the verification of the prediction process (e.g., the cache tag reading and comparison operation as described above).

[0046] Methods for operating the caching subsystem:

[0047] Figure 5 This is a flowchart of one implementation of a method for operating a cache subsystem. As disclosed herein, method 500 can be executed by any of the various hardware implementations described above. Hardware implementations not discussed herein but otherwise capable of executing method 500 are also considered to fall within the scope of this disclosure.

[0048] Method 500 includes: storing a cache line into a cache multiplexer (block 505). The method further includes: generating a request using request circuitry to access a specific cache line in the cache (block 510), and subsequently generating a prediction using prediction circuitry about which of the multiplexers includes the specific cache line (block 515). After generating the prediction, the method continues to verify the prediction using comparison circuitry, wherein the verification includes comparing a specific address tag associated with the specific cache line with a cache tag corresponding to one of the predicted multiplexers (block 520). The method further includes: storing an acknowledgment bit using the prediction circuitry in response to the comparison indicating that the prediction is correct (block 525), and for subsequent access requests to the specific cache line, abandoning verification of subsequent predictions about which of the multiplexers includes the specific cache line based on the acknowledgment bit indicating that the prediction is correct (block 530).

[0049] In various implementations, abandoning subsequent verification requests includes: abandoning the reading of the cached tag from the cache; and abandoning the comparison of the specific address tag and the cached tag. By abandoning these two operations, power savings and performance improvements can be achieved.

[0050] Various embodiments of method 500 include storing a plurality of address tags, including the particular address tag, in a tag memory, wherein some of the plurality of address tags correspond to entries stored in the cache. In such an embodiment, the prediction is determined to be correct based on a match between the particular address tag and the cache tag. After confirming the prediction is correct, the method includes storing the confirmation bit in a confirmation bit memory. For a request to access a cache line, embodiments of the method include querying the confirmation bit memory in response to a subsequent prediction of the particular cache line to determine whether the previous prediction was correct.

[0051] Sometimes a correctly predicted cache line can be evicted from the cache. Therefore, an embodiment of method 500 includes resetting the specific acknowledgment bit stored in the acknowledgment bit memory in response to evicting the cache line corresponding to the specific acknowledgment bit from the cache. Other conditions may also cause the acknowledgment bit to be reset. For example, an embodiment of method 500 may include resetting the specific acknowledgment bit stored in the acknowledgment bit memory in response to an address translation failure associated with the cache line corresponding to the specific acknowledgment bit.

[0052] Figure 6 This is a flowchart of another implementation of a method for operating the cache subsystem. Similar to method 500 described above, method 600 can be derived from [reference needed]. Figures 1 to 4 Some of the various hardware implementations and components described herein are used to perform the method. Implementations of a cache subsystem capable of performing method 600 but not disclosed herein may also be considered to fall within the scope of this disclosure.

[0053] Method 600 includes: a caching subsystem receiving a request for a cache line (block 605). The method then includes: for the requested cache line, reading an acknowledgment bit memory and a tag memory (block 610). In various embodiments, the tag memory includes address tags, and thus the address tag corresponding to the requested cache line can be retrieved from the tag memory. Simultaneously, the acknowledgment bit memory can be read to determine whether a previous prediction regarding the specific path for storing the requested cache line is correct. If it is determined that the corresponding acknowledgment bit is set (block 615, Yes), indicating that the previous prediction regarding the specific path for storing the requested cache line is correct, the method continues skipping the cache tag read and comparison operations while retrieving the requested cache line from the cache (block 620). Method 600 then returns to block 605 and waits for the next cache line request.

[0054] If no acknowledgment bit is set (box 615, No), the cache tag corresponding to the predicted path is read (box 625). A comparison operation is then performed, comparing the cache tag with the address tag corresponding to the requested cache line (box 630). If the address tag matches the cache tag (box 635, Yes), the prediction is correct, and the method continues to set and store the acknowledgment bit while accessing the cache line from the predicted path (box 640). Method 600 then returns to box 605 to wait for the next cache request.

[0055] On the other hand, if the address label and the cache label do not match (box 635, No), the requested cache line is searched in other paths of the cache (box 645), and if the requested line exists in the cache, the requested line is provided. Then, method 600 returns to box 605.

[0056] Exemplary system:

[0057] Next turn Figure 7 A block diagram of one embodiment of system 700 is shown, which may utilize the methods and mechanisms described herein in combination with and / or otherwise. In the illustrated embodiment, system 700 includes at least one instance of a system-on-a-chip (SoC) 706, which may include various types of processing units (such as a central processing unit (CPU), graphics processing unit (GPU), or others), communication architectures, and interfaces to memory and input / output devices. In some embodiments, one or more processors in SoC 706 include multiple execution lanes and instruction dispatch queues. In various embodiments, SoC 706 is coupled to external memory 702, peripheral devices 704, and power supply 708.

[0058] A power supply 708 is also provided, which supplies power voltage to the SoC 706 and one or more power voltages to the memory 702 and / or peripheral devices 704. In various embodiments, the power supply 708 represents a battery (e.g., a rechargeable battery in a smartphone, laptop, tablet, or other device). In some embodiments, more than one instance of the SoC 706 is included (and more than one external memory 702 is also included).

[0059] Memory 702 is any type of memory, such as Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Dual Data Rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, and / or low-power versions of SDRAM, such as LPDDR2), RAMBUSDRAM (RDRAM), Static RAM (SRAM), etc. One or more memory devices are coupled to a circuit board to form a memory module, such as a Single In-line Memory Module (SIMM), a Dual In-line Memory Module (DIMM), etc. Alternatively, these devices are mounted with a SoC or integrated circuit in a chip stack configuration, a package stack configuration, or a multi-chip module configuration.

[0060] The SoC 706 in the illustrated embodiment may include various levels of cache memory, some of which may be shared among various components, while others may be dedicated caches. Such cache memory may be implemented as part of a corresponding cache subsystem. At least some of the cache subsystems on the SoC 706 can be based on the above references. Figures 1 to 6 The various hardware and methodological implementations discussed operate as follows. Therefore, at least some of the various cache subsystems on the SoC 706 can be arranged to predict the path to store a requested cache line and are also configured to generate and store an indication when the prediction is correct. For subsequent access requests to the currently valid cache line, such cache subsystems can use this indication to confirm that the cache line is stored in the predicted path and thus cancel verification operations (e.g., the tag read and comparison operations discussed above, although other mechanisms for verification can also be considered). Canceling verification operations can reduce power consumption and also improve the performance of the cache subsystems.

[0061] Depending on the type of system 700, peripheral device 704 includes any desired circuitry. For example, in one embodiment, peripheral device 704 includes devices for various types of wireless communications such as Wi-Fi, Bluetooth, cellular, GPS, etc. In some embodiments, peripheral device 704 also includes additional storage devices, including RAM storage devices, solid-state storage devices, or disk storage devices. Peripheral device 704 includes user interface devices such as displays, including touch displays or multi-touch displays, keyboards or other input devices, microphones, speakers, etc.

[0062] As shown in the figure, system 700 is illustrated as having applications in a wide range of fields. For example, system 700 can be used as part of a chip, circuit, component, etc., in a desktop computer 710, laptop computer 720, tablet computer 730, cellular or mobile phone 740, or television 750 (or a set-top box coupled to a television). A smartwatch and health monitoring device 760 are also shown. In some embodiments, smartwatch 760 may include various general computing-related functions. For example, smartwatch 760 may provide access to email, mobile phone services, user calendars, etc. In various embodiments, the health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functions. For example, the health monitoring device may monitor a user's vital signs, track the user's proximity to other users for epidemiological social distancing purposes, contact tracing, provide communication to emergency services in the event of a health crisis, etc. In various embodiments, the aforementioned smartwatch may or may not include some or any health monitoring-related functions. Other wearable devices are also envisioned, such as devices worn around the neck, implantable devices, glasses designed to provide augmented and / or virtual reality experiences, etc.

[0063] System 700 can also be used as part of cloud-based service 770. For example, the previously mentioned devices and / or other devices can access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, system 700 can be used in one or more devices in the home in addition to those previously mentioned. For example, home appliances can monitor and detect noteworthy situations. For example, various devices in the home (e.g., refrigerators, cooling systems, etc.) can monitor the status of the devices and provide alerts to the homeowner (or, for example, a repair service) upon detecting a specific event. Alternatively, a thermostat can monitor the temperature in the home and can automatically adjust the heating / cooling system based on the homeowner's history of responses to various situations. Figure 7The application of System 700 to various modes of transportation is also illustrated. For example, System 700 can be used as a control and / or entertainment system for airplanes, trains, buses, taxis, private cars, watercraft ranging from private boats to cruise ships, and (for rental or private use) scooters. In various cases, System 700 can be used to provide automated guidance (e.g., self-driving vehicles), general system control, etc. Many other implementations are possible and envisioned. It should be noted that... Figure 7 The devices and applications shown are merely illustrative and not intended to be limiting. Other devices are possible and envisioned.

[0064] This disclosure includes references to “implementation” or groups of “implementation” (e.g., “some implementations” or “various implementations”). An implementation is a different specific implementation or instance of the disclosed concepts. References to “implementation,” “an implementation,” “a particular implementation,” etc., do not necessarily refer to the same implementation. A large number of possible implementations are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the substance or scope of this disclosure.

[0065] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all specific implementations of all these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular embodiment achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an embodiment falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure, in conjunction with an embodiment of the disclosed embodiments, which negates or diminishes one or more of the disclosed advantages. Furthermore, suboptimal design execution of a particular embodiment (e.g., the implementing technique or tool) may also negate or diminish the disclosed advantages. Even assuming an implementation of the technique, the realization of advantages may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular embodiment may prevent one or more problems addressed in this disclosure from occurring in a particular context, and as a result, the benefits of its solution may not be realized. Given the existence of possible factors outside this disclosure, any potential advantages described herein should not be construed as a claim limitation that must be satisfied in order to prove infringement. Rather, the identification of such potential advantages is intended to show one or more types of improvements available to a designer who benefits from this disclosure. Describing such advantages permanently (e.g., stating that a particular advantage "may occur") is not intended to convey a question about whether such advantages can actually be realized, but rather to recognize that the realization of such advantages often depends on the technological reality of additional factors.

[0066] Unless otherwise indicated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even if only a single example is described for a particular feature. The disclosed embodiments of the present invention are intended to be exemplary rather than limiting, without any contrary statement in this disclosure. Therefore, this application intends to allow claims that cover the disclosed embodiments, as well as such alternative forms, modifications, and equivalent forms, which will be obvious to those skilled in the art who are aware of the effective effects of this disclosure.

[0067] For example, the features in this application may be combined in any suitable manner. Thus, new claims may be made for any such combination of features during the prosecution of this patent application (or a patent application claiming priority therefrom). Specifically, referring to the appended claims, the features of dependent claims may, where appropriate, be combined with the features of other dependent claims, including claims that depend on other independent claims. Similarly, the features from corresponding independent claims may be combined where appropriate.

[0068] Thus, while the appended dependent claims may be drafted such that each dependent claim depends on a single other claim, additional dependencies are also contemplated. Any combination of dependent claims consistent with this disclosure is contemplated, and such combinations may be claimed in this patent application or another patent application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0069] Where appropriate, it is also contemplated that claims drafted in one format or statutory type (e.g., apparatus) are intended to support corresponding claims in another format or statutory type (e.g., method).

[0070] ***

[0071] Because this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. Notice is hereby given that the following paragraphs and the definitions provided throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0072] References to items in the singular form (i.e., a noun or noun phrase preceded by "a," "an," or "the") are intended to mean "one or more" unless the context clearly dictates otherwise. Thus, without accompanying context, a reference to an "item" in a claim does not exclude additional instances of that item. "A plurality" of items means a collection of two or more items.

[0073] The word "may" is used herein in the permissive sense (i.e., having the potential to, being able to), rather than in the mandatory sense (i.e., must).

[0074] The terms “include” and “including” and their forms are open-ended and mean “including but not limited to”.

[0075] When the term “or” is used in this disclosure in relation to a list of options, it will generally be understood to be used in an inclusive sense unless the context otherwise provides. Thus, the expression “x or y” is equivalent to “x or y, or both,” and therefore covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as “either x or y, but not both” make it clear that “or” is used in an exclusive sense.

[0076] The expressions “w, x, y, or z, or any combination thereof” or “at least one of w, x, y, and z” are intended to cover all possibilities involving a single element, up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “...at least one of w, x, y, and z” therefore refers to at least one element in the set [w, x, y, z], thus covering all possible combinations of that list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0077] In this disclosure, various “labels” may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different instances of the feature. Furthermore, unless otherwise stated, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0078] The phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors may influence the determination. That is, a decision can be based solely on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on another factor such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0079] The phrases “responding to” and “responding” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, whether used in conjunction with or independently of the specified factor. That is, the effect may respond solely to these factors, or it may respond to the specified factor along with other unspecified factors. Consider the phrase “responding to B to execute A.” This phrase specifies that B is a factor that triggers the execution of A or a specific result of A. This phrase does not exclude that the execution of A may also respond to certain other factors, such as C. This phrase also does not exclude that the execution of A may be performed jointly in response to B and C. This phrase is also intended to cover implementations where A is executed solely in response to B. As used herein, the phrase “responding” is synonymous with the phrase “at least partially responding to.” Similarly, the phrase “responding to” is synonymous with the phrase “at least partially responding to.”

[0080] ***

[0081] Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or claimed to be “configured to” perform one or more tasks or operations. This expression—[entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be “configured” to perform certain tasks even if the structure is not currently being operated. Therefore, an entity described or stated as “configured to” perform certain tasks refers to a physical thing used to perform that task, such as a device, circuit, system with processor units, and memory storing executable program instructions. This phrase is not used herein to refer to intangible things.

[0082] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured" to perform those tasks / operations, even if not specifically stated.

[0083] The term "configured as" is not intended to mean "configurable as". For example, an unprogrammed FPGA is not considered "configured as" to perform a specific function. However, the unprogrammed FPGA may be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform a specific function.

[0084] For the purposes of this U.S. patent application based on this disclosure, the statement in the claims that the structure is “configured” to perform one or more tasks is expressly intended not to invoke 35 U.SC § 112(f) for that claim element. If an applicant wishes to invoke part 112(f) in the course of filing a U.S. patent application based on this disclosure, it will use the structure “means for [performing a function]” to state the elements of the claims.

[0085] Different “circuits” may be described in this disclosure. These circuits or “circuits” constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom-designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be commonly referred to as “cells” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such cells also refer to circuits or circuit systems.

[0086] Therefore, the circuits / units / components and other elements disclosed in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoding unit” can be described as having the function of executing “the opcode of a processing instruction and routing that instruction to one or more of a plurality of functional units,” meaning that the decoding unit is “configured” to perform that function. To those skilled in the art of computers, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0087] In various implementations, as described in the preceding paragraphs, circuits, cells, and other elements can be defined by the functions or operations they are configured to perform. The arrangement of these circuits / cells / components relative to each other and the manner in which they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, a microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitecture definition. That is, those skilled in the art, with the microarchitecture definition provided according to this disclosure, can implement this structure without excessive experimentation and using the application of a person of ordinary skill in the art, by encoding the description of the circuits / cells / components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a way that can be revealed as functional. However, for those skilled in the art, the HDL description is a way of translating the structure of a circuit, cell, or component into the details of the next level of implementation. Such HDL descriptions can take the following forms: behavioral code (which is typically non-synthesizable), Register Transfer Language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). HDL descriptions can be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain the final design database that is transferred to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry system. The integrated circuit may include transistors and other circuit elements (e.g., passive components such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete components may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a Field Programmable Gate Array (FPGA) and implemented in the FPGA. This decoupling between the design of a set of circuits and their subsequent low-level implementations often results in a situation where the circuit or logic designer never specifies a particular set of structures for the low-level implementation that goes beyond a description of what the circuit is configured to do, because that process is performed at different stages of the circuit implementation process.

[0088] The fact that a circuit of the same specifications can be implemented using many different low-level combinations of circuit elements results in a large number of equivalent circuit structures. As noted, these low-level circuit implementations can vary depending on the manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell library provided for a particular project, and so on. In many cases, the choice of different design tools or methods to produce these different implementations can be arbitrary.

[0089] Furthermore, for a given implementation, a single concrete implementation of the circuit's specific functional specifications typically involves a large number of devices (e.g., millions of transistors). Therefore, the shearing volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single implementation, let alone a large number of equivalent possible implementations. To this end, this disclosure describes the structure of a circuit using functional abbreviations commonly used in industry.

[0090] Once the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. This disclosure is intended to make the following claims interpretable as encompassing all such variations and modifications.

Claims

1. An apparatus comprising: The tag array circuit is configured to store and cache the tags corresponding to multiple cache lines arranged in a cache storage circuit. The prediction circuit is configured to generate a prediction for a specific path in the multiplex, including a specific cache line associated with the request, in response to an access request to the tag array circuit. as well as The comparison circuit is configured to verify the prediction based on a comparison of a first tag associated with the particular cache line and a second tag associated with the particular path in the multiplex; The prediction circuit is further configured to store an acknowledgment bit indicating a correct prediction in response to a comparison indicating a match between the first tag and the second tag; and Based on this confirmation bit, the comparison circuit is configured to indicate that the first tag matches the second tag for subsequent access requests to the specific cache line without reading the tag array circuit or performing a comparison.

2. The apparatus of claim 1, wherein the first tag is an address tag and the second tag is a cache tag.

3. The apparatus of claim 2, wherein the comparison circuit is configured to verify that the prediction is correct in response to determining that the address tag matches the cache tag.

4. The apparatus of claim 1 further includes a confirmation bit memory configured to store a plurality of confirmation bits, wherein a particular confirmation bit among the plurality of confirmation bits, when set, indicates that the prediction made by the prediction circuit is correct.

5. The apparatus of claim 4, further comprising a cache controller configured to query an acknowledgment bit memory in response to a subsequent prediction in the specific path of the multiplexing being stored in the specific cache line.

6. The apparatus of claim 5, wherein the buffer controller is configured to generate a signal that causes the comparison circuit to disable verification of the subsequent prediction in response to determining that one of the plurality of acknowledgment bits is set.

7. The apparatus of claim 5, wherein the cache controller is configured to provide the particular cache line from the cache storage circuit in response to determining that one of the plurality of acknowledgment bits is set.

8. The apparatus of claim 5, wherein the cache controller is configured to reset the acknowledgment bit among the plurality of acknowledgment bits in response to evicting the particular cache line from the path in the plurality of paths.

9. The apparatus of claim 5, wherein the cache controller is configured to reset the acknowledgment bit among the plurality of acknowledgment bits in response to an address translation failure associated with the particular cache line.

10. The apparatus of claim 1, wherein the cache storage circuit is an instruction cache, and the apparatus further comprises an instruction fetching unit configured to fetch instructions from the cache storage circuit.

11. A method comprising: The tag array circuit stores the tags corresponding to the cache rows arranged in multiple paths in the cache storage circuit; Using predictive circuitry, in response to an access request to the tag array circuitry, a specific path in the multiplex that stores a specific cache line is predicted; The comparison circuit is used to verify whether the prediction is correct, wherein the verification includes the comparison circuit performing a comparison to determine whether the label associated with the particular cache line matches the label associated with the particular path in the multiplex; In response to determining that the prediction is correct, the prediction circuit stores a confirmation bit indicating that the prediction is correct in the confirmation bit memory; as well as For subsequent access requests to the specific cache line, a match is indicated without reading the tag array circuitry or performing a comparison.

12. The method of claim 11, further comprising clearing the acknowledgment bit from the acknowledgment bit memory in response to the particular cache line being evicted from the cache.

13. The method of claim 11, further comprising clearing the acknowledgment bit from the acknowledgment bit memory in response to an address translation failure associated with the particular cache line.

14. The method of claim 11, wherein the tag associated with the particular cache line is an address tag stored in an address tag memory, and wherein the tag associated with the particular path in the multiplex is a cache tag, and wherein the method further comprises: In response to the request, an address tag is provided from the address tag memory to the comparison circuit; as well as In response to the request, a cache tag is provided from the cache to the comparison circuit.

15. The method of claim 11, further comprising prediction circuitry providing an indication to a cache controller associated with the cache storage circuitry that the prediction is correct.

16. The method of claim 11, wherein the method further comprises providing the requested instruction stored in the particular cache line from the cache storage circuitry to the instruction fetch circuitry.

17. A system comprising: A caching subsystem, comprising: Tag array circuit, the tag array circuit is configured to store and cache the tags arranged in multiple cache lines corresponding to the storage circuit; A prediction circuit, configured to generate a prediction for a specific path in the multiplex, including a specific cache line associated with the request, in response to an access request to the tag array circuit; and A comparison circuit is configured to verify whether the prediction is correct by comparing the address tag associated with the particular cache line and the cache tag associated with the particular path in the multiplex. The prediction circuit is configured to store the confirmation bit in the confirmation bit memory in response to a comparator circuit indicating that the prediction is correct; and Based on this confirmation bit, the comparison circuit is configured to indicate that the address tag matches the cache tag for subsequent access requests to the specific cache line without reading the tag array circuit or performing a comparison.

18. The system of claim 17, wherein the comparison circuit is configured to verify that the prediction is correct in response to determining that the address tag matches the cache tag.

19. The system of claim 17, wherein the cache storage circuit is an instruction cache, and the system further includes an instruction fetching unit configured to request instructions from the instruction cache.

20. The system of claim 17, wherein the cache subsystem further comprises a cache controller configured to clear the acknowledgment bit from the acknowledgment bit memory in response to at least one of the following: Evict the specific cache line from the cache storage circuit; The address translation associated with the specific cache line failed.

21. An apparatus comprising: A prediction circuit is configured to generate a prediction for a specific path in a multiplexed cache memory, including a specific cache line associated with the cache access request, in response to a cache access request. A comparison circuit is configured to determine whether a prediction is correct, wherein, in order to determine whether a prediction is correct, the comparison circuit is configured to compare a first tag associated with the specific cache line and a second tag associated with the specific path in the multiplex; and A confirmation bit memory, wherein the prediction circuit is configured to set a confirmation bit in the confirmation bit memory in response to the comparison circuit determining that the prediction is correct; Specifically, for subsequent cache access requests to the specific cache line, the comparison circuit is configured to abandon the comparison of the first tag and the second tag in response to determining that the acknowledgment bit is set in the acknowledgment bit memory.

22. The apparatus of claim 21, further comprising a tag array circuit configured to store address tags corresponding to the multiplexed cache memory, wherein, When the comparison is abandoned, the comparison circuit is configured to abandon access to the tag array circuit to obtain the second tag.

23. The apparatus according to claim 21, wherein, When the comparison is abandoned, the comparison circuit is configured to abandon access to the cache memory to obtain the first tag.

24. The apparatus of claim 21, wherein the comparison circuit is configured to determine that the prediction is correct if the first tag matches the second tag.

25. The apparatus of claim 21, wherein the confirmation bit memory is configured to store a plurality of confirmation bits corresponding to a correct prediction generated by the prediction circuit.

26. The apparatus of claim 21, further comprising a cache controller coupled to the cache and prediction circuitry, wherein the cache controller is configured to determine whether the acknowledgment bit is set in response to a subsequent cache access request in the specific path where the particular cache line is stored in the multiplex.

27. The apparatus of claim 26, wherein the cache controller is configured to reset the acknowledgment bit in response to evicting the particular cache line from the cache memory.

28. The apparatus of claim 26, wherein the cache controller is configured to reset the acknowledgment bit in response to determining that an address translation associated with the particular cache line is invalid.

29. The apparatus of claim 26, wherein the cache controller is configured to provide the specific cache line to the requester in response to determining that the acknowledgment bit is set.

30. The apparatus of claim 26, wherein the buffer controller is configured to generate a signal that causes the comparison circuit to abandon the comparison in response to a determination acknowledgment bit being set.

31. A method comprising: Using predictive circuitry, in response to a cache access request, a prediction is generated for a specific path in the multiplex of the cache memory, including a specific cache line associated with that cache access request; A comparison circuit is used to determine whether the prediction is correct, wherein the determination includes comparing a first tag associated with a particular cache line and a second tag associated with the particular path in the multiplex; In response to confirming that the prediction is correct, a confirmation bit is set in the confirmation bit memory; as well as In response to determining that the acknowledgment bit is set in the acknowledgment bit memory, for subsequent cache access requests to the particular cache line, the determination of whether the prediction is correct is abandoned.

32. The method of claim 31, wherein abandoning the determination of whether the prediction is correct comprises: Discontinue reading the first tag from the cache memory, wherein the first tag is a cache tag associated with the path in the multiplex; as well as Abandon reading the second tag from the tag array circuit, wherein the second tag is the address tag associated with the particular cache line.

33. The method of claim 31, wherein abandoning the determination of whether the prediction is correct includes using a cache controller to determine whether the acknowledgment bit is set in response to a subsequent cache access request in a specific path of the multiplexing where a specific cache line is stored.

34. The method of claim 31, further comprising determining that the prediction is correct in response to a match between the first label and the second label.

35. The method of claim 31, further comprising using a cache controller to reset the acknowledgment bit in response to the particular cache line being evicted from the cache.

36. The method of claim 31, further comprising using a cache controller to reset the acknowledgment bit in response to determining that an address translation associated with the particular cache line is invalid.

37. The method of claim 31, further comprising using a cache controller to provide the specific cache line to the requester that initiated the cache access request.

38. A system comprising: The request circuit is configured to initiate cache access requests; as well as The caching subsystem includes: A cache controller, configured to receive cache access requests; A prediction circuit is configured to generate a prediction for a specific path in a multiplex of the cache memory, including a specific cache line associated with the cache access request, in response to a cache access request. A comparison circuit is configured to determine whether a prediction is correct, wherein, in order to determine whether a prediction is correct, the comparison circuit is configured to compare a first tag associated with the particular cache line and a second tag associated with the particular path in the multiplexing; and A confirmation bit memory, wherein the prediction circuit is configured to set a confirmation bit in the confirmation bit memory in response to the comparison circuit determining that the prediction is correct; The cache controller is configured to disable the comparison circuitry from determining whether a prediction is correct in response to a subsequent cache access request for the specific cache line, in response to determining that the acknowledgment bit is set in the acknowledgment bit memory.

39. The system according to claim 38, wherein, To prevent the comparison circuit from determining whether a prediction is correct for subsequent cache access requests for the specific cache line, the cache controller is configured to: The comparator circuit is instructed to abandon reading the first tag from the cache memory, wherein the first tag is a cache tag associated with the path in the multiplex; and The comparator circuit abandons reading the second tag from the tag array circuit, where the second tag is the address tag associated with the particular cache line.

40. The system of claim 38, wherein the comparison circuit is configured to determine that the prediction is correct in response to determining that the first tag matches the second tag.

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