Cascadable on-chip memory peripheral control circuit capable of correcting and detecting errors

Abstract

The invention discloses an on-chip memory peripheral control circuit capable of cascading and correcting and detecting errors, belongs to the technical field of integrated circuits, and is adaptive to an on-chip single-port or dual-port memory with the scale of 4K * 72. The peripheral control circuit is provided with a cascade path, bottom-to-top cascade of memories can be completed without additional circuit interconnection resources, a large-scale storage matrix is formed, and meanwhile, the peripheral control circuit is provided with a coding and decoding circuit, so that error correction and detection of data streams can be realized. Meanwhile, the peripheral control circuit has the advantages of flexible configuration, high efficiency, chip resource saving and the like, can assist the memory in realizing scenes of caching a large amount of data on the chip and the like, and meets the requirements of emerging electronic technologies on high speed, mass data and stability of the memory.

Description

Technical Field

[0001] The present invention relates to an on-chip memory peripheral control circuit that can be cascaded and error-corrected and detected, and particularly to a peripheral control circuit adapted to a 4K×72 scale on-chip single-port or dual-port memory, belonging to the field of integrated circuit technology. Background Art

[0002] Generally in an electronic module, data storage is an essential functional requirement. The memory module is embedded in chips such as CPU, SoC, FPGA, and CPLD, and is one of the main modules of different types of chips, occupying most of the transistor count and chip area on the chip. Users can specify an address when reading and writing the memory to achieve random access to the memory. Integrating a memory circuit in the chip enables the chip to process data signals faster and more efficiently, and at the same time facilitates developers to simplify the design. The integration degree of the chip is continuously increasing with the continuous progress of semiconductor manufacturing technology, and more memory modules will be embedded inside it. Modern digital systems have higher and higher requirements for the read / write rate, storage capacity, and storage reliability of the memory. Therefore, it is necessary to focus on designing new configurable, cascaded, and error-corrected memory modules. Studying memory modules is of great significance for the development of various chip industries.

[0003] With the progress of semiconductor process technology, the market has put forward higher requirements for the data processing speed and capacity of chips. In addition, the deployment of 5G base stations and the development of artificial intelligence have all promoted the high-speed, high-capacity, and stable development of memory design. The single memory block in traditional chips far cannot meet the requirements. Due to the influence of semiconductor manufacturing technology, when the scale of a single memory block is too large, the influence brought by its parasitic parameters will also increase accordingly. At the same time, the process consistency factor of the memory block causes a significant decrease in its yield rate. These factors restrict the maximum capacity of a single memory block. In order to meet the requirements of emerging electronic technologies for high-speed, high-capacity, and stable memory, cascading multiple memories through the memory peripheral circuit and using the peripheral encoding and decoding circuit to implement error correction and detection of transmitted data have become new research hotspots and one of the key breakthroughs in high-performance storage technology. Summary of the Invention

[0004] The technical problem solved by the present invention is: overcoming the deficiencies of the prior art, a cascaded and error-corrected and detected on-chip memory peripheral control circuit is proposed, which is adapted to a 4K×72 scale on-chip single-port or dual-port memory, realizes multiple memories forming a storage matrix, and at the same time provides a data error correction and detection function, providing a stable and reliable buffer for application scenarios with a large amount of high-speed data stream transmission.

[0005] The technical solution of the present invention is:

[0006] An on-chip memory peripheral control circuit that can be cascaded and error-corrected and error-detected, including an input port controller and an output port controller;

[0007] The input port controller is provided with pipeline registers and an error-correction and error-detection coding module, and performs corresponding processing according to external input settings: If the external input is a receive and store setting, it receives the receive clock, reset, enable, input data, address, and write enable signals and transmits them to the memory; if the external input is a cascade setting, it forms a cascade structure, receives signals from the lower memory, and transmits them to the memory or the upper memory; if the external input is a coding setting, it selects to enable the error-correction and error-detection coding module to insert a check code for the input data; if the external input is a pipeline setting, it selects to enable the pipeline registers of the input port.

[0008] The output port controller is provided with output data pipeline registers, error-correction and error-detection decoding pipeline registers, and an error-correction and error-detection decoding module, and performs corresponding processing according to external input settings: If the external input is a receive and send setting, it receives the output data signal from the memory and outputs it; if the external input is a cascade setting, it forms a cascade structure, receives signals from the lower memory, and outputs or transmits them to the upper memory; if the external input is a decoding setting, it enables the error-correction and error-detection decoding module to decode and correct errors in the output data; if the external input is a pipeline setting, it selects to enable the output data pipeline registers or the error-correction and error-detection decoding pipeline registers.

[0009] The advantages of the present invention compared with the prior art are as follows:

[0010] (1) The present invention integrates the cascade control circuit and the error-correction and error-detection encoding and decoding circuit into one, providing a solution that can not only increase the memory capacity but also achieve reliable data transmission, effectively avoiding the situation where the capacity of a single memory is difficult to increase due to process limitations and data errors caused by memory read-write mismatch, and meeting the reliability requirements in the scenario of massive data buffering.

[0011] (2) The present invention adds optional pipeline registers at key parts affecting the data transmission rate, realizes the avoidance of transmission delay, effectively improves the data transmission rate, and realizes the characteristics of high-speed reading and writing in the environment of large-scale data storage.

[0012] (3) The present invention has a built-in data-level connection path, avoids the consumption of external logic interconnection resources in the cascade mode, effectively saves on-chip circuit resources, and reduces the chip area occupation.

[0013] (4) The present invention has a simple structure, strong scalability, can adapt to various specifications of memories, and does not require additional circuit modification. Description of the Drawings

[0014] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0015] Figure 1 It is a schematic diagram of the overall structure of the on-chip memory peripheral control circuit of the present invention that can be cascaded and can correct and detect errors;

[0016] Figure 2 It is a circuit diagram of the input port controller of the present invention;

[0017] Figure 3 It is a circuit diagram of the output port controller of the present invention;

[0018] Figure 4 It is a circuit diagram of the cascaded address decoder of the present invention;

[0019] Figure 5 It is a circuit diagram of the error correction and detection encoder of the present invention;

[0020] Figure 6 It is a circuit diagram of the error correction and detection decoder of the present invention;

[0021] Figure 7 It is a circuit diagram of the encoding and decoding unit of the present invention;

[0022] Figure 8 It is a circuit diagram of the error correction unit of the present invention;

[0023] Figure 9 It is a circuit diagram of the lookup unit of the present invention. Detailed Embodiments

[0024] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0025] The present invention provides an on-chip memory peripheral control circuit that can be cascaded and can correct and detect errors, which is adapted to a single-port or dual-port on-chip memory with a scale of 4K×72. The peripheral control circuit has a built-in cascading path, which can realize the cascading of memories from bottom to top without additional circuit interconnection resources to form a large-scale storage matrix. At the same time, it has a built-in encoding and decoding circuit, which can realize the error correction and detection of data streams. It has the advantages of flexible configuration, high efficiency, and saving chip resources, and can assist the memory to realize scenarios such as a large amount of on-chip data caching, meeting the requirements of emerging electronic technologies for the high speed, large capacity, and stability of memories.

[0026] The on-chip memory peripheral control circuit includes an input port controller and an output port controller, which are respectively used for input data control and output data control of the memory, and realize functions such as cascading, error correction and detection.

[0027] The input port controller has three independent functions and can be independently enabled without being affected by other functions. The first function is: according to the settings of the set port, it can receive signals such as clock, reset, enable, input data, address, write enable, etc., and after conversion, transmit them to the memory. The second function is: to form a cascaded structure, receive signals from the lower memory, and after conversion, transmit them to the memory or the upper memory. The third function is: according to the settings of the set port, it can choose to enable the pipeline register to eliminate the influence of port or interconnect line delay, or choose to enable the error correction and detection coding module to realize the insertion of check codes for input data.

[0028] The output port controller also has three independent functions and can be independently enabled without being affected by other functions. The first function is: according to the settings of the set port, it can receive the output data signal from the memory, and after conversion, form output data for output. The second function is: to form a cascaded structure, receive signals from the lower memory, and after conversion, form output data for output or transmit them to the upper memory. It can also choose to enable the error correction and detection decoding module according to the settings of the set port to realize the decoding of output data and correct one-bit errors and detect two-bit errors. The third function is: to choose to enable the output data pipeline register or the error correction and detection decoding pipeline register to eliminate the influence of port, interconnect line or error correction and detection decoding module delay.

[0029] As Figure 1 shown, an on-chip memory peripheral control circuit that can be cascaded and can correct and detect errors shown in the embodiment of the present invention is composed of an input port controller 1 and an output port controller 2.

[0030] (1) Input port controller 1

[0031] The ports of the input port controller include:

[0032] 1) Set ports: CAS_IN_OUT_SET, INPUT_REG_SET, CAS_IN_IN_SET, SELF_MASK[10:0], SELF_ADDR[10:0], ECC_ENC_SEL;

[0033] 2) Input ports: CLK, RST, EN, ADDR[22:0], BWE[7:0], RDB_WR, DI[71:0];

[0034] 3) Output ports: EN_RAM, ADDR_RAM[11:0], BWE_RAM[7:0], RDB_WR_RAM, DI_RAM[71:0];

[0035] 4) Cascade input ports: CAS_IN_EN, CAS_IN_ADDR[22:0], CAS_IN_BWE[7:0], CAS_IN_RDB_WR, CAS_IN_DI[71:0];

[0036] 5) Cascade output ports: CAS_OUT_EN, CAS_OUT_ADDR[22:0], CAS_OUT_BWE[7:0], CAS_OUT_RDB_WR, CAS_OUT_DI[71:0].

[0037] The connection relationship is as follows: The setting port is connected to the external setting signal. Usually, the value of the external setting signal is determined by the chip configuration; the external input signal is connected to the input port, where the external signal CLK is also connected to the CLK port of the memory body and the CLK port of the output port controller, and the external signal RST is also connected to the RST port of the output port controller; the output port is connected to the memory body, where EN_RAM is also connected to the EN_RAM port of the output port controller, and RDB_WR_RAM is also connected to the RDB_WR_RAM port of the output port controller; all cascade input ports are connected to the cascade output ports of the input port controller of the lower memory; all cascade output ports are connected to the cascade input ports of the input port controller of the upper memory.

[0038] Such as Figure 2As shown in the figure, the input port controller 1 consists of a latch LAT3; two-input AND gates AND4, AND9, AND10, AND17, AND25, AND33, AND42, AND50, AND58; buffers BUF5, BUF6, BUF8, BUF11, BUF12, BUF14, BUF19, BUF20, BUF22, BUF26, BUF27, BUF28, BUF30, BUF36, BUF37, BUF39, BUF43, BUF44, BUF45, BUF47, BUF51, BUF52, BUF53, BUF55, BUF59; two-input multiplexers MUX7, MUX13, MUX16, MUX21, MUX24, MUX29, MUX32, MUX34, MUX38, MUX41, MUX46, MUX49, MUX54, MUX57; registers DFF15, DFF23, DFF31, DFF40, DFF48, DFF56; a cascaded address decoder ADDDEC18; and an error correction and detection encoder ECCENC35; the connection relationships are as follows: the CLK port is connected to the CP end of LAT3 and an output end of AND4, the Q end of LAT3 is connected to the other output end of AND4, the D end is connected to the EN_RAM port, and the output end of AND4 is connected to the CP ends of DFF15, DFF23, DFF31, DFF40, DFF48, DFF56; the RST port is connected to the CD ends of DFF15, DFF23, DFF31, DFF40, DFF48, DFF56; CAS_IN_IN_SET is connected to the selection ends of MUX7, MUX13, MUX21, MUX29, MUX38, MUX46, MUX54 and the CAS_IN_IN_SET end of ADDDEC18; the CAS_IN_EN and EN ports are respectively connected to the 0th input end and the 1st input end of MUX7 through BUF5 and BUF6, and the output end is connected to an input end of AND9 and AND10 through BUF8; the CAS_IN_ADDR[22:12] and ADDR[22:12] ports are respectively connected to the 0th input end and the 1st input end of MUX13 through BUF11 and BUF12, the output end is connected to the 0th input end of MUX16, and at the same time is connected to the D end of DFF15 through BUF14, the Q end of DFF15 is connected to the 1st input end of MUX16, and the output end is connected to an input end of AND17 and the ADDR[22:12] end of ADDDEC18;The CAS_IN_ADDR[11:0] and ADDR[11:0] ports are respectively connected to the 0th input terminal and the 1st input terminal of MUX21 through BUF19 and BUF20, and the output terminal is connected to the 0th input terminal of MUX24. At the same time, it is connected to the D terminal of DFF23 through BUF22. The Q terminal of DFF23 is connected to the 1st input terminal of MUX24, and the output terminal is connected to one input terminal of AND25 and the input terminal of BUF26; The CAS_IN_DI[71:64] and DI[71:64] ports are respectively connected to the 0th input terminal and the 1st input terminal of MUX29 through BUF27 and BUF28, and the output terminal is connected to the 0th input terminal of MUX32. At the same time, it is connected to the D terminal of DFF31 through BUF30. The Q terminal of DFF31 is connected to the 1st input terminal of MUX32, and the output terminal is connected to one input terminal of AND33 and the 0th input terminal of MUX34; The CAS_IN_DI[63:0] and DI[63:0] ports are respectively connected to the 0th input terminal and the 1st input terminal of MUX38 through BUF36 and BUF37, and the output terminal is connected to the 0th input terminal of MUX41. At the same time, it is connected to the D terminal of DFF40 through BUF39. The Q terminal of DFF40 is connected to the 1st input terminal of MUX41, and the output terminal is connected to one input terminal of AND42, the input terminal of BUF43 and the DI[63:0] terminal of ECCENC35; The CAS_IN_BWE[7:0] and BWE[7:0] ports are respectively connected to the 0th input terminal and the 1st input terminal of MUX46 through BUF44 and BUF45, and the output terminal is connected to the 0th input terminal of MUX49. At the same time, it is connected to the D terminal of DFF48 through BUF47. The Q terminal of DFF48 is connected to the 1st input terminal of MUX49, and the output terminal is connected to one input terminal of AND50 and the input terminal of BUF51; The CAS_IN_RDB_WR and RDB_WR ports are respectively connected to the 0th input terminal and the 1st input terminal of MUX54 through BUF52 and BUF53, and the output terminal is connected to the 0th input terminal of MUX57. At the same time, it is connected to the D terminal of DFF56 through BUF55. The Q terminal of DFF56 is connected to the 1st input terminal of MUX57, and the output terminal is connected to one input terminal of AND58 and the input terminal of BUF59; The INPUT_REG_SET port is connected to the selection terminals of MUX16, MUX24, MUX32, MUX41, MUX49, and MUX57; The CAS_IN_OUT_SET port is connected to one input terminal of AND9, AND17, AND25, AND33, AND42, AND50, AND58 and the CAS_IN_OUT_SET terminal of ADDDEC18;The SELF_MASK[10:0] and SELF_ADDR[10:0] terminals of ADDDEC18 are connected to the SELF_MASK[10:0] and SELF_ADDR[10:0] ports, and the EN_ADDR_SEL terminal is connected to the other input terminal of AND10; the ECC_ENC_SEL port is connected to the ECC_ENC_SEL terminal of ECCENC35 and the selection terminal of MUX34; the output terminal of AND9 is the CAS_OUT_EN port, the output terminal of AND10 is the EN_RAM port, the output terminal of AND17 is the CAS_OUT_ADDR[22:12] port, the output terminal of AND25 is the CAS_OUT_ADDR[11:0] port, the output terminal of BUF26 is the ADDR_RAM[11:0] port, the output terminal of AND33 is the CAS_OUT_DI[71:64] port, the output terminal of MUX34 is the DI_RAM[71:64] port, the output terminal of AND42 is the CAS_OUT_DI[63:0] port, the output terminal of BUF43 is the DI_RAM[63:0] port, the output terminal of AND50 is the CAS_OUT_BWE[7:0] port, the output terminal of BUF51 is the BWE_RAM[7:0] port, the output terminal of AND58 is the CAS_OUT_RDB_WR port, and the output terminal of BUF59 is the RDB_WR_RAM port.;

[0039] The function of the input port controller 1 is determined by its setting ports. The correspondence between the setting ports and the functions of the input port controller is as follows: CAS_IN_OUT_SET is used for the control of the cascaded output function. When it is 1, the cascaded output port sends data to the upper memory, and at the same time, the memory body is controlled by EN_RAM not to operate. When it is 0, the cascaded output port does not output data, and at the same time, the memory body is controlled by EN_RAM to perform read and write operations; INPUT_REG_SET is used for the control of the input port pipeline register. When it is 1, the input port pipeline register is enabled. When it is 0, the register is not enabled; CAS_IN_IN_SET is used for the control of the cascaded input port. When it is 1, the cascaded input port receives data from the lower memory, and the input port does not receive data. When it is 0, the input port receives data, and the cascaded input port does not receive data from the lower memory; SELF_MASK[10:0] is used to mask the unused address ports when the cascaded function is enabled. When SELF_MASK[i] is 0, the ADDR[i + 12] port is masked. When it is 1, the corresponding port is enabled, where 0 ≤ i ≤ 10; SELF_ADDR[10:0] is used to determine the cascaded address of the current memory when the cascaded function is enabled; ECC_ENC_SEL is used for the control of the error correction and detection coding module. When it is 1, the error correction and detection coding function is enabled. When it is 0, the function is not enabled.

[0040] For the cascaded address decoder ADDDEC18 in the input port controller 1, an implementable circuit structure is as follows Figure 4As shown, specifically: the ports include input ports ADDR[22:12], CAS_IN_IN_SET, CAS_IN_OUT_SET, SELF_MASK[10:0], SELF_ADDR[10:0], and output port EN_ADDR_SEL; it is composed of 11 exclusive-OR gates XOR108, XOR109, XOR110, XOR111, XOR112, XOR113, XOR114, XOR115, XOR116, XOR117, XOR118, 13 two-input NAND gates NAND120, NAND121, NAND122, NAND123, NAND124, NAND125, NAND126, NAND127, NAND128, NAND129, NAND130, NAND137, NAND138, 3 three-input AND gates AND132, AND134, AND135, 3 two-input AND gates AND131, AND133, AND136, and 1 two-input OR gate OR119.The connection relationship is as follows: The ADDR[22:12] and SELF_ADDR[10:0] ports are respectively and sequentially connected to the two input terminals of 11 exclusive-OR gates XOR108, XOR109, XOR110, XOR111, XOR112, XOR113, XOR114, XOR115, XOR116, XOR117, XOR118. The outputs of XOR108, XOR109, XOR110, XOR111, XOR112, XOR113, XOR114, XOR115, XOR116, XOR117, XOR118 are respectively connected to one input terminal of two-input NAND gates NAND120, NAND121, NAND122, NAND123, NAND124, NAND125, NAND126, NAND127, NAND128, NAND129, NAND130; The SELF_MASK[10:0] port is sequentially connected to the other input terminals of NAND120, NAND121, NAND122, NAND123, NAND124, NAND125, NAND126, NAND127, NAND128, NAND129, NAND130; The output terminals of two-input NAND gates NAND120 and NAND121 are respectively connected to the input terminals of two-input AND gate AND131; The output terminals of two-input NAND gates NAND122, NAND123 and NAND124 are respectively connected to the input terminals of three-input AND gate AND132; The output terminals of two-input NAND gates NAND125, NAND126 and NAND127 are respectively connected to the input terminals of three-input AND gate AND134; The output terminals of two-input NAND gates NAND128, NAND129 and NAND130 are respectively connected to the input terminals of three-input AND gate AND135; The output terminals of AND131 and AND132 are respectively connected to the input terminals of two-input AND gate AND133; The output terminals of AND134 and AND135 are respectively connected to the input terminals of two-input AND gate AND136; The output terminals of AND133 and AND136 are respectively connected to the input terminals of two-input NAND gate NAND137, and the output terminal of NAND137 is connected to one input terminal of two-input NAND gate NAND138; The CAS_IN_IN_SET and CAS_IN_OUT_SET ports are respectively connected to the input terminals of two-input OR gate OR119, and the output terminal of OR119 is connected to the other input terminal of two-input NAND gate NAND138; The output terminal of NAND138 is the EN_ADDR_SEl port.

[0041] The cascade address decoder ADDDEC18 has the following functions: First, it judges the values of CAS_IN_IN_SET and CAS_IN_OUT_SET. When one of them is 1, it indicates that the memory enables the cascade function and the cascade address decoder is enabled. When both of them are 0, it indicates that the memory does not enable the cascade function and the cascade address decoder is not enabled. When the cascade address decoder is enabled, it masks the unused ADDR ports according to the value of SELF_MASK[10:0], and then determines the cascade address of the current memory according to the value of SELF_ADDR[10:0]. By comparing ADDR[22:12] and SELF_ADDR[10:0], when they are equal, it indicates that the current memory is selected and 1 is output through EN_ADDR_SEL. At this time, the memory can perform read and write operations. When they are not equal, it indicates that the current memory is not selected and 0 is output through EN_ADDR_SEL. At this time, the memory does not perform any operations. The logical relationship formed by the cascade address decoder ADDDEC18 is as follows:

[0042] EN_ADDR_SEL = ~((CAS_IN_IN_SET | CAS_IN_OUT_SET) & Π(~(SELF_MASK & (ADDR ⊙ SELF_ADDR))))

[0043] For the error correction and detection encoder ECCENC35 in the input port controller 1, a realizable circuit structure is as Figure 5As shown in the figure, specifically: the port includes input ports DI[63:0] and ECC_ENC_SEL, and output port PARITY[7:0]; it is composed of 8 encoding and decoding units. The function of the error correction and detection encoder ECCENC35 is as follows: First, it judges the value of ECC_ENC_SEL. When it is 1, it means that the error correction and detection encoding function is enabled, and the error correction and detection encoder is enabled. When it is 0, it means that the error correction and detection encoding function is not enabled, and the error correction and detection encoder is not enabled; when the error correction and detection encoder is enabled, an eight-bit parity code can be generated according to the value of DI[63:0] and output through PARITY[7:0]. The connection relationship is: the ECC_ENC_SEL port is connected to the ECC_SEL end of each encoding and decoding unit. The D[35:0] end of the first encoding and decoding unit is respectively connected to GND, DI

[63] , DI

[61] , DI

[59] , DI

[57] , DI

[56] , DI

[54] , DI

[52] , DI

[50] , DI

[48] , DI

[46] , DI

[44] , DI

[42] , DI

[40] , DI

[38] , DI

[36] , DI

[34] , DI

[32] , DI

[30] , DI

[28] , DI

[26] , DI

[25] , DI

[23] , DI

[21] , DI

[19] , DI

[17] , DI

[15] , DI

[13] , DI

[11] , DI

[10] , DI[8], DI[6], DI[4], DI[3], DI[1], DI[0], and the P end is connected to PARITY[0]. The D[35:0] end of the second encoding and decoding unit is respectively connected to GND, DI

[63] , DI

[62] , DI

[59] , DI

[58] , DI

[56] , DI

[55] , DI

[52] , DI

[51] , DI

[48] , DI

[47] , DI

[44] , DI

[43] , DI

[40] , DI

[39] , DI

[36] , DI

[35] , DI

[32] , DI

[31] , DI

[28] , DI

[27] , DI

[25] , DI

[24] , DI

[21] , DI

[20] , DI

[17] , DI

[16] , DI

[13] , DI

[12] , DI

[10] , DI[9], DI[6], DI[5], DI[3], DI[2], DI[0], and the P end is connected to PARITY[1].The D[35:0] terminals of the third decoding unit are respectively connected to GND, DI

[63] , DI

[62] , DI

[61] , DI

[60] , DI

[56] , DI

[55] , DI

[54] , DI

[53] , DI

[48] , DI

[47] , DI

[46] , DI

[45] , DI

[40] , DI

[39] , DI

[38] , DI

[37] , DI

[32] , DI

[31] , DI

[30] , DI

[29] , DI

[25] , DI

[24] , DI

[23] , DI

[22] , DI

[17] , DI

[16] , DI

[15] , DI

[14] , DI

[10] , DI[9], DI[8], DI[7], DI[3], DI[2], DI[1]. The P terminal is connected to PARITY[2]. The D[35:0] terminals of the fourth decoding unit are respectively connected to GND, GND, GND, GND, GND, DI

[56] , DI

[55] , DI

[54] , DI

[53] , DI

[52] , DI

[51] , DI

[50] , DI

[49] , DI

[48] , DI

[47] , DI

[46] , DI

[45] , DI

[44] , DI

[43] , DI

[42] , DI

[41] , DI

[25] , DI

[24] , DI

[23] , DI

[22] , DI

[21] , DI

[20] , DI

[19] , DI

[18] , DI

[10] , DI[9], DI[8], DI[7], DI[6], DI[5], DI[4]. The P terminal is connected to PARITY[3]. The D[35:0] terminals of the fifth decoding unit are respectively connected to GND, GND, GND, GND, GND, DI

[56] , DI

[55] , DI

[54] , DI

[53] , DI

[52] , DI

[51] , DI

[50] , DI

[49] , DI

[48] , DI

[47] , DI

[46] , DI

[45] , DI

[44] , DI

[43] , DI

[42] , DI

[41] , DI

[25] , DI

[24] , DI

[23] , DI

[22] , DI

[21] , DI

[20] , DI

[19] , DI

[18] , DI

[17] , DI

[16] , DI

[15] , DI

[14] , DI

[13] , DI

[12] , DI

[11] . The P terminal is connected to PARITY[4].The D[35:0] terminals of the sixth decoding unit are respectively connected to GND, GND, GND, GND, GND, DI

[56] , DI

[55] , DI

[54] , DI

[53] , DI

[52] , DI

[51] , DI

[50] , DI

[49] , DI

[48] , DI

[47] , DI

[46] , DI

[45] , DI

[44] , DI

[43] , DI

[42] , DI

[41] , DI

[40] , DI

[39] , DI

[38] , DI

[37] , DI

[36] , DI

[35] , DI

[34] , DI

[33] , DI

[32] , DI

[31] , DI

[30] , DI

[29] , DI

[28] , DI

[27] , DI

[26] , and the P terminal is connected to PARITY[5]. The D[35:0] terminals of the seventh decoding unit are respectively connected to GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, DI

[63] , DI

[62] , DI

[61] , DI

[60] , DI

[59] , DI

[58] , DI

[57] , and the P terminal is connected to PARITY[6]. The D[35:0] terminals of the eighth decoding unit are respectively connected to GND, DI

[63] , DI

[60] , DI

[58] , DI

[57] , DI

[56] , DI

[53] , DI

[51] , DI

[50] , DI

[47] , DI

[46] , DI

[44] , DI

[41] , DI

[39] , DI

[38] , DI

[36] , DI

[33] , DI

[32] , DI

[29] , DI

[27] , DI

[26] , DI

[24] , DI

[23] , DI

[21] , DI

[18] , DI

[17] , DI

[14] , DI

[12] , DI

[11] , DI

[10] , DI[7], DI[5], DI[4], DI[2], DI[1], DI[0], and the P terminal is connected to PARITY[7].

[0044] (2) Output port controller 2

[0045] The ports of the output port controller 2 include:

[0046] 1) Setting ports: CAS_OUT_OUT_SET, CAS_OUT_IN_SET, CAS_OUT_REG_SET, OUTPUT_REG_SET, ECC_REG_SET, ECC_DEC_SEL;

[0047] 2) Input ports: EN_RAM, CLK, RST, RDB_WR_RAM, DO_RAM[71:0];

[0048] 3) Output ports: RD_ACCESS, SBITERR, DBITERR, DO[71:0];

[0049] 4) Cascade input ports: CAS_IN_RD_ACCESS, CAS_IN_SBITERR, CAS_IN_DBITERR, CAS_IN_DO[71:0];

[0050] 5) Cascade output ports: CAS_OUT_RD_ACCESS, CAS_OUT_SBITERR, CAS_OUT_DBITERR, CAS_OUT_DO[71:0].

[0051] The connection relationship is as follows: The setting port is connected to the external setting signal. Usually, the value of the external setting signal is determined by the chip configuration; DO_RAM[71:0] of the memory body is connected to the input port DO_RAM[71:0]; EN_RAM and RDB_WR_RAM of the input port controller are connected to the input ports EN_RAM and RDB_WR_RAM; the external signals CLK and RST are connected to the input ports CLK and RST; the output port is connected to the external output signal; all the cascade input ports are connected to the cascade output ports of the output port controller of the memory below; all the cascade output ports are connected to the cascade input ports of the output port controller of the memory above.

[0052] Such as Figure 3As shown, the output port controller consists of latch LAT60; two-input AND gates AND61, AND89, AND95, AND101, AND107; registers DFF62, DFF64, DFF67, DFF73, DFF76, DFF79, DFF82, DFF85, DFF91, DFF97, DFF103; buffers BUF63, BUF66, BUF69, BUF72, BUF75, BUF78, BUF81, BUF84, BUF88, BUF90, BUF94, BUF96, BUF100, BUF102, BUF106; two-input multiplexers MUX65, MUX68, MUX71, MUX74, MUX77, MUX80, MUX83, MUX86, MUX87, MUX92, MUX93, MUX98, MUX99, MUX104, MUX105; The connection relationship is as follows: The CLK port is connected to the CP end of LAT60 and one output end of AND61. The Q end of LAT60 is connected to the other output end of AND61. The D end is connected to the EN_RAM port. The output end of AND61 is connected to the CP ends of DFF62, DFF64, DFF67, DFF73, DFF76, DFF79, DFF82, DFF85, DFF91, DFF97, DFF103; The RST port is connected to the CD ends of DFF62, DFF64, DFF67, DFF73, DFF76, DFF79, DFF82, DFF85, DFF91, DFF97, DFF103; The D end of DFF62 is connected to the RDB WRRAM port, the Q end is connected to the 0th input end of MUX65, and at the same time, it is connected to the D end of DFF64 through BUF63. The Q end of DFF64 is connected to the 1st input end of MUX65; The DO_RAM[71:0] port is connected to the 0th input end of MUX68, and at the same time, it is connected to the D end of DFF67 through BUF66. The Q end of DFF67 is connected to the 1st input end of MUX68; The ECC_REG_SET port is connected to the selection ends of MUX65 and MUX68; The output end of MUX65 is connected to the 0th input end of MUX74 through BUF69, and at the same time, it is connected to the D end of DFF73 through BUF72. The Q end of DFF73 is connected to the 1st input end of MUX74;The output terminal of MUX68 is connected to the DI[71:0] terminal of ECCDEC70 and the 0th input terminal of MUX71. The ECC_DEC_SEL port is connected to the ECC_DEC_SEL terminal of ECCDEC70 and the selection terminal of MUX71. The DO[71:0] terminal of ECCDEC70 is connected to the 1st input terminal of MUX71. The SBITERR terminal is connected to the 0th input terminal of MUX77 and is simultaneously connected to the D terminal of DFF76 through BUF75. The DBITERR terminal is connected to the 0th input terminal of MUX80 and is simultaneously connected to the D terminal of DFF79 through BUF78. The Q terminal of DFF76 is connected to the 1st input terminal of MUX77. The Q terminal of DFF79 is connected to the 1st input terminal of MUX80. The output terminal of MUX71 is connected to the 0th input terminal of MUX83 and is simultaneously connected to the D terminal of DFF82 through BUF81. The Q terminal of DFF82 is connected to the 1st input terminal of MUX83. The OUTPUT_REG_SET port is connected to the selection terminals of MUX74, MUX77, MUX80, and MUX83. The output terminal of MUX74 is connected to the 0th input terminal of MUX87. The output terminal of MUX77 is connected to the 0th input terminal of MUX93. The output terminal of MUX80 is connected to the 0th input terminal of MUX99. The output terminal of MUX83 is connected to the 0th input terminal of MUX105. The CAS_RD_ACCESS port is connected to the 0th input terminal of MUX86 and is simultaneously connected to the D terminal of DFF85 through BUF84. The Q terminal of DFF85 is connected to the 1st input terminal of MUX86. The CAS_IN_SBITERR port is connected to the 0th input terminal of MUX92 and is simultaneously connected to the D terminal of DFF91 through BUF90. The Q terminal of DFF91 is connected to the 1st input terminal of MUX92. The CAS_IN_DBITERR port is connected to the 0th input terminal of MUX98 and is simultaneously connected to the D terminal of DFF97 through BUF96. The Q terminal of DFF97 is connected to the 1st input terminal of MUX98. The CAS_IN_DO[71:0] port is connected to the 0th input terminal of MUX104 and is simultaneously connected to the D terminal of DFF103 through BUF102. The Q terminal of DFF103 is connected to the 1st input terminal of MUX104. The CAS_OUT_REG_SET port is connected to the selection terminals of MUX86, MUX92, MUX98, and MUX104. The CAS_OUT_IN_SET port is connected to the selection terminals of MUX87, MUX93, MUX99, and MUX105. The output terminal of MUX86 is connected to the 1st input terminal of MUX87. The output terminal of MUX92 is connected to the 1st input terminal of MUX93. The output terminal of MUX98 is connected to the 1st input terminal of MUX99. The output terminal of MUX104 is connected to the 1st input terminal of MUX105. The output terminal of MUX87 is connected to one input terminal of AND89 and is simultaneously connected to the RD_ACCESS port through BUF88.The output terminal of MUX93 is connected to one input terminal of AND95, and at the same time is connected to the SBITERR port through BUF94; the output terminal of MUX99 is connected to one input terminal of AND101, and at the same time is connected to the DBITERR port through BUF100; the output terminal of MUX105 is connected to one input terminal of AND107, and at the same time is connected to the DO[71:0] port through BUF106; the CAS_OUT_OUT_SET port is connected to the other input terminals of AND89, AND95, AND101, AND107. The output terminal of AND89 is connected to the CAS_OUT_RD_ACCESS port, the output terminal of AND95 is connected to the CAS_OUT_SBITERR port, the output terminal of AND101 is connected to the CAS_OUT_DBITERR port, and the output terminal of AND107 is connected to the CAS_OUT_DO[71:0] port.;

[0053] The function of the output port controller 2 is determined by its setting ports. The correspondence between the setting ports and the functions of the output port controller is as follows: CAS_OUT_OUT_SET is used for the control of the cascaded output function. When it is 1, the cascaded output port sends data to the upper memory. When it is 0, the cascaded output port does not output data; CAS_OUT_IN_SET is used for the control of the cascaded input port. When it is 1, the cascaded input port receives data from the lower memory, and the input port does not receive data from the memory body. When it is 0, the input port receives data from the memory body, and the cascaded input port does not receive data from the lower memory; CAS_OUT_REG_SET is used for the control of the cascaded input port pipeline register. When it is 1, the cascaded input port pipeline register is enabled. When it is 0, this register is not enabled; OUTPUT_REG_SET is used for the control of the output port pipeline register. When it is 1, the output port pipeline register is enabled. When it is 0, this register is not enabled; ECC_REG_SET is used for the control of the error correction and detection decoding module pipeline register. When it is 1, the error correction and detection decoding module pipeline register is enabled. When it is 0, this register is not enabled; ECC_DEC_SEL is used for the control of the error correction and detection decoding module. When it is 1, the error correction and detection decoding function is enabled. When it is 0, this function is not enabled.

[0054] For the error correction and detection encoder ECCDEC70 in the output port controller 2, an implementable circuit structure is as Figure 6As shown in the figure, specifically: the ports include input ports DI[71:0] and ECC_DEC_SEL, and output ports DO[71:0], SBITERR, and DBITERR; it is composed of 9 encoding and decoding units and 1 error correction unit. The function of the error detection and correction decoder ECCDEC70 is as follows: First, it judges the value of ECC_DEC_SEL. When it is 1, it means that the error detection and correction decoding function is enabled, and the error detection and correction decoder is enabled. When it is 0, it means that the error detection and correction decoding function is not enabled, and the error detection and correction decoder is not enabled; when the error detection and correction decoder is enabled, it can decode DI[71:0]. When a single-bit error is found in DI[71:0], it corrects the error and outputs it through DO[71:0], and at the same time sets SBITERR to 1, indicating that a single-bit error has been detected and corrected. When a two-bit error is found in DI[71:0], it directly outputs it to DO[71:0], and at the same time sets DBITERR to 1, indicating that a two-bit error has been detected; the connection relationship is: the ECC_DEC_SEL port is connected to the ECC_SEL end of each encoding and decoding unit and the error correction unit. The D[35:0] end of the ninth encoding and decoding unit is respectively connected to DI

[64] , DI

[63] , DI

[61] , DI

[59] , DI

[57] , DI

[56] , DI

[54] , DI

[52] , DI

[50] , DI

[48] , DI

[46] , DI

[44] , DI

[42] , DI

[40] , DI

[38] , DI

[36] , DI

[34] , DI

[32] , DI

[30] , DI

[28] , DI

[26] , DI

[25] , DI

[23] , DI

[21] , DI

[19] , DI

[17] , DI

[15] , DI

[13] , DI

[11] , DI

[10] , DI[8], DI[6], DI[4], DI[3], DI[1], DI[0], and the P end is connected to the P[0] end of the error correction unit. The D[35:0] end of the tenth encoding and decoding unit is respectively connected to DI

[65] , DI

[63] , DI

[62] , DI

[59] , DI

[58] , DI

[56] , DI

[55] , DI

[52] , DI

[51] , DI

[48] , DI

[47] , DI

[44] , DI

[43] , DI

[40] , DI

[39] , DI

[36] , DI

[35] , DI

[32] , DI

[31] , DI

[28] , DI

[27] , DI

[25] , DI

[24] , DI

[21] , DI

[20] , DI

[17] , DI

[16] , DI

[13] , DI

[12] , DI

[10] , DI[9], DI[6], DI[5], DI[3], DI[2], DI[0], and the P end is connected to the P[1] end of the error correction unit.The D[35:0] terminals of the eleventh decoding unit are respectively connected to DI

[66] , DI

[63] , DI

[62] , DI

[61] , DI

[60] , DI

[56] , DI

[55] , DI

[54] , DI

[53] , DI

[48] , DI

[47] , DI

[46] , DI

[45] , DI

[40] , DI

[39] , DI

[38] , DI

[37] , DI

[32] , DI

[31] , DI

[30] , DI

[29] , DI

[25] , DI

[24] , DI

[23] , DI

[22] , DI

[17] , DI

[16] , DI

[15] , DI

[14] , DI

[10] , DI[9], DI[8], DI[7], DI[3], DI[2], DI[1]. The P terminal is connected to the P[2] terminal of the error correction unit. The D[35:0] terminals of the twelfth decoding unit are respectively connected to GND, GND, GND, GND, DI

[67] , DI

[56] , DI

[55] , DI

[54] , DI

[53] , DI

[52] , DI

[51] , DI

[50] , DI

[49] , DI

[48] , DI

[47] , DI

[46] , DI

[45] , DI

[44] , DI

[43] , DI

[42] , DI

[41] , DI

[25] , DI

[24] , DI

[23] , DI

[22] , DI

[21] , DI

[20] , DI

[19] , DI

[18] , DI

[10] , DI[9], DI[8], DI[7], DI[6], DI[5], DI[4]. The P terminal is connected to the P[3] terminal of the error correction unit. The D[35:0] terminals of the thirteenth decoding unit are respectively connected to GND, GND, GND, GND, DI

[68] , DI

[56] , DI

[55] , DI

[54] , DI

[53] , DI

[52] , DI

[51] , DI

[50] , DI

[49] , DI

[48] , DI

[47] , DI

[46] , DI

[45] , DI

[44] , DI

[43] , DI

[42] , DI

[41] , DI

[25] , DI

[24] , DI

[23] , DI

[22] , DI

[21] , DI

[20] , DI

[19] , DI

[18] , DI

[17] , DI

[16] , DI

[15] , DI

[14] , DI

[13] , DI

[12] , DI

[11] . The P terminal is connected to the P[4] terminal of the error correction unit.The D[35:0] terminals of the fourteenth decoding unit are respectively connected to GND, GND, GND, GND, DI

[69] , DI

[56] , DI

[55] , DI

[54] , DI

[53] , DI

[52] , DI

[51] , DI

[50] , DI

[49] , DI

[48] , DI

[47] , DI

[46] , DI

[45] , DI

[44] , DI

[43] , DI

[42] , DI

[41] , DI

[40] , DI

[39] , DI

[38] , DI

[37] , DI

[36] , DI

[35] , DI

[34] , DI

[33] , DI

[32] , DI

[31] , DI

[30] , DI

[29] , DI

[28] , DI

[27] , DI

[26] . The P terminal is connected to the P[5] terminal of the error correction unit. The D[35:0] terminals of the fifteenth decoding unit are respectively connected to GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, DI

[70] , DI

[63] , DI

[62] , DI

[61] , DI

[60] , DI

[59] , DI

[58] , DI

[57] . The P terminal is connected to the P[6] terminal of the error correction unit. The D[35:0] terminals of the sixteenth decoding unit are respectively connected to DI

[70] , DI

[68] , DI

[66] , DI

[64] , DI

[62] , DI

[60] , DI

[58] , DI

[56] , DI

[54] , DI

[52] , DI

[50] , DI

[48] , DI

[46] , DI

[44] , DI

[42] , DI

[40] , DI

[38] , DI

[36] , DI

[34] , DI

[32] , DI

[30] , DI

[28] , DI

[26] , DI

[24] , DI

[22] , DI

[20] , DI

[18] , DI

[16] , DI

[14] , DI

[12] , DI

[10] , DI[8], DI[6], DI[4], DI[2], DI[0]. The P terminal is connected to the P[7] terminal of the error correction unit.The D[35:0] terminals of the decoding unit in the seventeenth part are respectively connected to DI

[71] , DI

[69] , DI

[67] , DI

[65] , DI

[63] , DI

[61] , DI

[59] , DI

[57] , DI

[55] , DI

[53] , DI

[51] , DI

[49] , DI

[47] , DI

[45] , DI

[43] , DI

[41] , DI

[39] , DI

[37] , DI

[35] , DI

[33] , DI

[31] , DI

[29] , DI

[27] , DI

[25] , DI

[23] , DI

[21] , DI

[19] , DI

[17] , DI

[15] , DI

[13] , DI

[11] , DI[9], DI[7], DI[5], DI[3], DI[1], and the P terminal is connected to the P[8] terminal of the error correction unit; DI[71:0] is simultaneously connected to the DI[71:0] terminals of the error correction unit, and the DO[71:0], SBITERR, and DBITERR terminals of the error correction unit are respectively connected to DO[71:0], SBITERR, and DBITERR.,

[0055] As Figure 7 shown, the ports of the encoding and decoding unit in the error correction encoder ECCENC35 and the error correction decoder ECCDEC70 include the input ports D[35:0] and ECC_SEL, and the output port P; it is composed of 36 two-input AND gates, 9 four-input XOR gates, and 4 three-input XOR gates; the function of the encoding and decoding unit is: first, judge the value of ECC_SEL. When it is 1, the encoding and decoding unit is enabled, and when it is 0, the encoding and decoding unit is not enabled; when the encoding and decoding unit is enabled, convert DI[35:0] into a check code and output it through P for encoding or error correction and detection; the logical relationship formed by the encoding and decoding unit is as follows:

[0056] P = ECC_SEL & (DI

[35] ⊕ DI

[34] ⊕ DI

[33] ⊕ DI

[32] ⊕ DI

[31] ⊕ DI

[30] ⊕ DI

[29] ⊕ DI

[28] ⊕ DI

[27] ⊕ DI

[26] ⊕ DI

[25] ⊕ DI

[24] ⊕ DI

[23] ⊕ DI

[22] ⊕ DI

[21] ⊕ DI

[20] ⊕ DI

[19] ⊕ DI

[18] ⊕ DI

[17] ⊕ DI

[16] ⊕ DI

[15] ⊕ DI

[14] ⊕ DI

[13] ⊕ DI

[12] ⊕ DI

[11] ⊕ DI

[10] ⊕ DI[9] ⊕ DI[8] ⊕ DI[7] ⊕ DI[6] ⊕ DI[5] ⊕ DI[4] ⊕ DI[3] ⊕ DI[2] ⊕ DI[1] ⊕ DI[0])

[0057] As Figure 8As shown in the figure, the ports of the error correction unit in the error correction and detection decoder ECCDEC70 include the input ports DI[71:0], ECC_SEL, and P[8:0], and the output ports SBITERR, DBITERR, and DO[71:0]; it is composed of 9 inverters, 1 two-input NAND gate, 11 two-input OR gates, 1 two-input XOR gate, 2 three-input OR gates, and 72 lookup units; the function of the error correction unit is: first, judge the value of ECC_SEL. When it is 1, the error correction unit is enabled, and when it is 0, the error correction unit is not enabled; when the error correction unit is enabled, judge whether there is an error in DI[71:0] according to the value of P[8:0]. When a single-bit error is found in DI[71:0], correct the error and output it through DO[71:0], and at the same time set SBITERR to 1, indicating that a single-bit error has been detected and corrected. When a two-bit error is found in DI[71:0], directly output it to DO[71:0], and at the same time set DBITERR to 1, indicating that a two-bit error has been detected; the logical relationship formed by the error correction unit is as follows:

[0058] DO[0] = (~P0 & ~P1 & P2 & ~P3 & P4 & P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI[0]

[0059] DO[1] = (P0 & ~P1 & P2 & P3 & P4 & ~P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI[1]

[0060] DO[2] = (P0 & ~P1 & P2 & P3 & P4 & P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI[2]

[0061] DO[3] = (~P0 & ~P1 & P2 & P3 & P4 & P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI[3]

[0062] DO[4] = (P0 & P1 & P2 & P3 & P4 & ~P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI[4]

[0063] DO[5] = (P0 & P1 & P2 & P3 & P4 & P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI[5]

[0064] DO[6] = (~P0 & P1 & P2 & P3 & P4 & P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI[6]

[0065] DO[7] = (~P0 & P1~P2 & P3~P4 & ~P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI[7]

[0066] DO[8] = (P0 & ~P1 ~P2 & P3 ~P4 & ~P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI[8]

[0067] DO[9] = (P0 & P1 & P2 & ~P3 ~P4 & P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI[9]

[0068] DO

[10] = (~P0 & P1 & P2 & ~P3 ~P4 & P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[10]

[0069] DO

[11] = (~P0 & P1 ~P2 & ~P3 ~P4 & P5 & P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[11]

[0070] DO

[12] = (~P0 & P1 ~P2 & ~P3 ~P4 & ~P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[12]

[0071] DO

[13] = (P0 & P1 ~P2 & ~P3 ~P4 & ~P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[13]

[0072] DO

[14] = (~P0 & ~P1 & P2 & P3 ~P4 & ~P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[14]

[0073] DO

[15] = (P0 & P1 ~P2 & P3 ~P4 & ~P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[15]

[0074] DO

[16] = (~P0 & P1 ~P2 & P3 ~P4 & P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[16]

[0075] DO

[17] = (P0 & P1 ~P2 & P3 ~P4 & P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[17]

[0076]

[0077]

[0078] DO

[60] = (~P0 & P1 & P2 & P3 ~P4 & ~P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[60]

[0079] DO

[61] = (P0 & ~P1 & P2 & P3 ~P4 & ~P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[61]

[0080] DO

[62] = (~P0 & ~P1 & P2 & P3 ~P4 & P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[62]

[0081] DO

[63] = (P0 & P1 ~P2 & P3 ~P4 & P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[63]

[0082] DO

[64] = (P0 & ~P1 & P2 & ~P3 & P4 & ~P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[64]

[0083] DO

[65] = (P0 & ~P1 & P2 & ~P3 & P4 & P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[65]

[0084] DO

[66] = (~P0 & P1 & P2 & P3 & P4 & ~P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[66]

[0085] DO

[67] = (P0 & ~P1 ~P2 & ~P3 ~P4 & P5 & P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[67]

[0086] DO

[68] = (P0 & P1 ~P2 & ~P3 ~P4 & P5 & P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[68]

[0087] DO

[69] = (P0 & P1 & P2 & ~P3 ~P4 & P5 & P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[69]

[0088] DO

[70] = (P0 & ~P1 & P2 & ~P3 ~P4 & P5 & P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[70]

[0089] DO

[71] = (~P0 & P1 & P2 & ~P3 & P4 & ~P5 & ~P6 & (P7 ⊕ P8) | (~ECC_SEL)) ⊕ DI

[71]

[0090] SBITERR = ~(P0 | P1 | P2 | P3 | P4 | P5 | P6 | (~ECC_SEL) & (P7 ⊙ P8))

[0091] DBITERR = P7 ⊙ P8

[0092] As Figure 9 shown, the ports of the lookup unit in the error correction unit include input ports C0, C1, C2, C3, C4, C5, C6, C7, D, and output port Q, and consist of 1 two-input AND gate, 3 three-input AND gates, and 1 two-input XOR gate; the function of the lookup unit is: to determine whether D is in error according to the values of C0, C1, C2, C3, C4, C5, C6, C7, and if there is an error, correct it and output it to Q, and if there is no error, directly output it to Q; the logical relationship formed by the lookup unit is as follows:

[0093] Q = (C0 & C1 & C2 & C3 & C4 & C5 & C6 & C7) ⊕ D

[0094] The above-described embodiments are only relatively preferred specific embodiments of the present invention, and the ordinary changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. A cascadable, error-correcting and error-detecting on-chip memory peripheral control circuit, characterized in that: including an input port controller and an output port controller; The input port controller is provided with a pipeline register and an error correction and detection coding module, and performs corresponding processing according to the external input setting: if the external input is a receiving storage setting, the clock, reset, enable, input data, address, and write enable signals are received and transmitted to the memory; If the external input is set in cascade, a cascade structure is formed to receive signals from the lower memory and transmit them to the memory or the upper memory; If the external input is set as encoding, then select to enable the error correction and detection encoding module to insert the checksum of the input data; if the external input is set as pipeline, then select to enable the pipeline register of the input port; The output port controller is provided with an output data pipeline register, an error correction and detection decoding pipeline register and an error correction and detection decoding module, and performs corresponding processing according to the external input setting: if the external input is a receiving and sending setting, the output data signal from the memory is received and output; if the external input is a cascade setting, a cascade structure is formed, and a signal from the lower memory is received and output or transmitted to the upper memory; if the external input is a decoding setting, the error correction and detection decoding module is turned on to decode the output data and correct errors; if the external input is a pipeline setting, the output data pipeline register or the error correction and detection decoding pipeline register is selected to be turned on.

2. The on-chip memory peripheral control circuit capable of cascading and error correction according to claim 1, characterized in that: The input port controller includes a latch, a two-input AND gate, a buffer, a two-input multiplexer, a register, a cascade address decoder and an error correction encoder, and is provided with a plurality of setting ports, input ports, output ports, cascade input ports and cascade output ports; The input port CLK is connected to the CP terminal of the latch LAT3 and an output terminal of the two-input AND gate AND4, the Q terminal of the latch LAT3 is connected to the other output terminal of the two-input AND gate AND4, and the D terminal is connected to the output port EN_RAM; the output terminal of the two-input AND gate AND4 is connected to the CP terminals of the registers DFF15, DFF23, DFF31, DFF40, DFF48 and DFF56; The input port RST is connected to the CD terminals of register DFF15, register DFF23, register DFF31, register DFF40, register DFF48, and register DFF56; The port CAS_IN_IN_SET is set to connect the selection terminals of the two-input multiplexers MUX7, MUX13, MUX21, MUX29, MUX38, MUX46 and MUX54 and the CAS_IN_IN_SET terminal of the cascade address decoder ADDDEC18; The cascade input port CAS_IN_EN and the input port EN are connected to the input terminal 0 and the input terminal 1 of the two-input multiplexer MUX7 through the buffer BUF5 and the buffer BUF6 respectively, and the output terminal is connected to one input terminal of the two-input AND gates AND9 and AND10 through the buffer BUF8; The cascade input port CAS_IN_ADDR[22:12] and the input port ADDR[22:12] are connected to the input terminal 0 and the input terminal 1 of the two-input multiplexer MUX13 respectively through the buffers BUF11 and BUF12, the output terminal of the two-input multiplexer MUX13 is connected to the input terminal 0 of the two-input multiplexer MUX16, and at the same time connected to the D terminal of the register DFF15 through the buffer BUF14, the Q terminal of the register DFF15 is connected to the input terminal 1 of the two-input multiplexer MUX16, the output terminal of the two-input multiplexer MUX16 is connected to one input terminal of the two-input AND gate AND17 and the ADDR[22:12] terminal of the cascade address decoder ADDDEC18; CAS_IN_ADDR[11:0] and ADDR[11:0] ports are connected to input terminal 0 and input terminal 1 of a two-input multiplexer MUX21 through buffers BUF19 and BUF20 respectively, the output terminal of the two-input multiplexer MUX21 is connected to input terminal 0 of a two-input multiplexer MUX24, and connected to the D terminal of a register DFF23 through a buffer BUF22, the Q terminal of the register DFF23 is connected to input terminal 1 of a two-input multiplexer MUX24, the output terminal of the two-input multiplexer MUX24 is connected to one input terminal of a two-input AND gate AND25 and the input terminal of a buffer BUF26; The cascade input port CAS_IN_DI[71:64] and the input port DI[71:64] are respectively connected to the No. 0 input terminal and the No. 1 input terminal of the two-input multiplexer MUX29 through the buffer BUF27 and the buffer BUF28, the output terminal of the two-input multiplexer MUX29 is connected to the No. 0 input terminal of the two-input multiplexer MUX32, and at the same time connected to the D terminal of the register DFF31 through the buffer BUF30, the Q terminal of the register DFF31 is connected to the No. 1 input terminal of the two-input multiplexer MUX32, and the output terminal of the two-input multiplexer MUX32 is connected to one input terminal of the two-input AND gate AND33 and the No. 0 input terminal of the two-input multiplexer MUX34; The cascade input port CAS_IN_DI[63:0] and the input port DI[63:0] are connected to the input terminal 0 and the input terminal 1 of the two-input multiplexer MUX38 respectively through the buffers BUF36 and BUF37, the output terminal of the two-input multiplexer MUX38 is connected to the input terminal 0 of the two-input multiplexer MUX41, and at the same time connected to the D terminal of the register DFF40 through the buffer BUF39, the Q terminal of the register DFF40 is connected to the input terminal 1 of the two-input multiplexer MUX41, the output terminal of the two-input multiplexer MUX41 is connected to one input terminal of the two-input AND gate AND42, the input terminal of the buffer BUF43 and the DI[63:0] terminal of the error correction encoder ECCENC35; The cascade input port CAS_IN_BWE[7:0] and the input port BWE[7:0] are connected to the input terminal 0 and the input terminal 1 of the two-input multiplexer MUX46 respectively through the buffer BUF44 and the buffer BUF45, the output terminal of the two-input multiplexer MUX46 is connected to the input terminal 0 of the two-input multiplexer MUX49, and is connected to the D terminal of the register DFF48 through the buffer BUF47, the Q terminal of the register DFF48 is connected to the input terminal 1 of the two-input multiplexer MUX49, and the output terminal of the two-input multiplexer MUX49 is connected to one input terminal of the two-input AND gate AND50 and the input terminal of the buffer BUF51; The cascade input port CAS_IN_RDB_WR and the input port RDB_WR are connected to the input terminal No. 0 and the input terminal No. 1 of the two-input multiplexer MUX54 respectively through the buffer BUF52 and the buffer BUF53, the output terminal of the two-input multiplexer MUX54 is connected to the input terminal No. 0 of the two-input multiplexer MUX57, and connected to the D terminal of the register DFF56 through the buffer BUF55, the Q terminal of the register DFF56 is connected to the input terminal No. 1 of the two-input multiplexer MUX57, and the output terminal of the two-input multiplexer MUX57 is connected to one input terminal of the two-input AND gate AND58 and the input terminal of the buffer BUF59; Set the port INPUT_REG_SET to connect the selection end of the two-input multiplexers MUX16, MUX24, MUX32, MUX41, MUX49, and MUX57; The setting port CAS_IN_OUT_SET is connected to one input end of the two-input AND gates AND9, AND17, AND25, AND33, AND42, AND50, and AND58 and the CAS_IN_OUT_SET end of the cascade address decoder ADDDEC18; the SELF_MASK[10:0] and SELF_ADDR[10:0] ends of the cascade address decoder ADDDEC18 are connected to the setting ports SELF_MASK[10:0] and SELF_ADDR[10:0] ports, and the EN_ADDR_SEL end of the cascade address decoder ADDDEC18 is connected to the other input end of the two-input AND gate AND10; The port ECC_ENC_SEL is set to connect the ECC_ENC_SEL terminal of the error correction encoder ECCENC35 and the selection terminal of the two-input multiplexer MUX34; the output terminal of the two-input AND gate AND9 is the cascade output port CAS_OUT_EN, the output terminal of the two-input AND gate AND10 is the output port EN_RAM, the output terminal of the two-input AND gate AND17 is the cascade output port CAS_OUT_ADDR[22:12], the output terminal of the two-input AND gate AND25 is the cascade output port CAS_OUT_ADDR[11:0], the output terminal of the buffer BUF26 is the output port ADDR_RAM[11:0], and the output terminal of the two-input AND gate AND33 is the cascade output port CAS_OUT_DI[71:64], the output end of the two-input multiplexer MUX34 is the output port DI_RAM[71:64], the output end of the two-input AND gate AND42 is the cascade output port CAS_OUT_DI[63:0], the output end of the buffer BUF43 is the output port DI_RAM[63:0], the output end of the two-input AND gate AND50 is the cascade output port CAS_OUT_BWE[7:0], the output end of the buffer BUF51 is the output port BWE_RAM[7:0], the output end of the two-input AND gate AND58 is the cascade output port CAS_OUT_RDB_WR, and the output end of the buffer BUF59 is the output port RDB_WR_RAM.

3. The on-chip memory peripheral control circuit capable of cascading and error correction according to claim 2, characterized in that: The setting port is connected to the external setting signal; the external input signal is connected to the input port, wherein the external signal CLK is connected to the input port CLK, the CLK port of the memory body and the output port controller; the external signal RST is connected to the input port RST and the output port controller; The output port is connected to the memory body, wherein the output ports EN_RAM and RDB_WR_RAM are also connected to the output port controller; The cascade input ports are all connected to the cascade output ports of the input port controller of the lower memory; the cascade output ports are all connected to the cascade input ports of the input port controller of the upper memory.

4. The on-chip memory peripheral control circuit capable of cascading and error correction according to claim 2 or 3, characterized in that: Through the external setting signal, the setting port of the input port controller is controlled to make the input port controller perform the corresponding task operation: The setting port CAS_IN_OUT_SET is used to control the cascade output function. When it is 1, the cascade output port sends data to the upper memory, and at the same time, the output port EN_RAM is used to control the memory body not to operate; When it is 0, the cascade output port does not output data, and the memory body is controlled to perform read and write operations through the output port EN_RAM; Set port INPUT_REG_SET to control the input port pipeline register. When it is 1, the input port pipeline register is enabled. When it is 0, the input port pipeline register is not enabled. The setting port CAS_IN_IN_SET is used to control the cascade input port. When it is 1, the cascade input port receives data from the lower memory and the input port does not receive data. When it is 0, the input port receives data and the cascade input port does not receive data from the lower memory. Set port SELF_MASK[10:0] to mask unused address ports when enabling the cascade function. When SELF_MASK[i] is 0, mask the ADDR[i+12] port, and when it is 1, enable the corresponding port, 0≤i≤10; The setting port SELF_ADDR[10:0] is used to determine the cascade address of the current memory when the cascade function is enabled; The port ECC_ENC_SEL is set to control the error correction coding module. When it is 1, the error correction coding function is enabled, and when it is 0, the function is not enabled.

5. The on-chip memory peripheral control circuit capable of cascading and error correction according to claim 2, characterized in that: The ports of the cascade address decoder ADDDEC18 include input ports ADDR[22:12], CAS_IN_IN_SET, CAS_IN_OUT_SET, SELF_MASK[10:0], SELF_ADDR[10:0], and output port EN_ADDR_SEL; The cascade address decoder ADDDEC18 first determines the values ​​of CAS_IN_IN_SET and CAS_IN_OUT_SET. When one of the two is 1, it indicates that the memory enables the cascade function and the cascade address decoder is enabled. When both are 0, it indicates that the memory does not enable the cascade function and the cascade address decoder is not enabled. When the cascade address decoder ADDDEC18 is enabled, the unused ADDR port is masked according to the value of SELF_MASK[10:0], and then the cascade address of the current memory is determined according to the value of SELF_ADDR[10:0]. By comparing ADDR[22:12] and SELF_ADDR[10:0], when the two are equal, it means that the current memory is selected, and EN_ADDR_SEL outputs 1. At this time, the memory performs read and write operations. When the two are not equal, it means that the current memory is not selected, and EN_ADDR_SEL outputs 0. At this time, the memory does not perform any operation.

6. The on-chip memory peripheral control circuit capable of cascading and error correction according to claim 2, characterized in that: The error correction encoder ECCENC35 is composed of multiple encoding and decoding units, and is provided with input ports DI[63:0] and ECC_ENC_SEL, and output ports PARITY[7:0]; The error correction encoder ECCENC35 first determines the value of ECC_ENC_SEL. When it is 1, it indicates that the error correction coding function is enabled, and the error correction encoder is enabled. According to the value of DI[63:0], a multi-bit check code is generated and output through PARITY[7:0]. When it is 0, it indicates that the error correction coding function is not enabled, and the error correction encoder is not enabled.

7. The on-chip memory peripheral control circuit capable of cascading and error correction according to claim 1, characterized in that: The output port controller includes a latch, a two-input AND gate, a buffer, a two-input multiplexer, a register, a cascade address decoder and an error correction and detection decoder, and is provided with a plurality of setting ports, input ports, output ports, cascade input ports and cascade output ports; The input port CLK is connected to the CP terminal of the latch LAT60 and one input terminal of the two-input AND gate AND61, the input port EN_RAM is connected to the D terminal of the latch LAT60, the Q terminal of the latch LAT60 is connected to the other input terminal of the two-input AND gate AND61, and the output terminal of the two-input AND gate AND61 is connected to the CP terminals of the registers DFF62, DFF64, DFF67, DFF73, DFF76, DFF79, DFF82, DFF85, DFF91, DFF97, and DFF103; The input port RST is connected to the CD terminals of registers DFF62, DFF64, DFF67, DFF73, DFF76, DFF79, DFF82, DFF85, DFF91, DFF97, and DFF103; the input port RDB_WR_RAM port is connected to the D terminal of register DFF62, the Q terminal of register DFF62 is connected to the No. 0 input terminal of the two-input multiplexer MUX65, and is connected to the D terminal of register DFF64 through BUF63, and the Q terminal of register DFF64 is connected to the No. 1 input terminal of the two-input multiplexer MUX65; the input port DO_RAM[71:0] is connected to the No. 0 input terminal of the two-input multiplexer MUX68, and is connected to the D terminal of DFF67 through BUF66, and the Q terminal of register DFF67 is connected to the No. 1 input terminal of the two-input multiplexer MUX68; Set port ECC_REG_SET to connect the selection end of two-input multiplexers MUX65 and MUX68; the output end of two-input multiplexer MUX65 is connected to input end 0 of two-input multiplexer MUX74 through BUF69, and at the same time connected to D end of register DFF73 through BUF72, and Q end of register DFF73 is connected to input end 1 of two-input multiplexer MUX74; the output end of two-input multiplexer MUX68 is connected to DI[71:0] end of error correction and detection decoder ECCDEC70 and input end 0 of MUX71; set port ECC_DEC_SEL to connect ECC_DEC_SEL end of error correction and detection decoder ECCDEC70 and selection end of two-input multiplexer MUX71; DO[71:0] of error correction and detection decoder ECCDEC70 is connected to DO[71:0] of error correction and detection decoder ECCDEC70. The SBITERR end is connected to the No. 1 input end of the two-input multiplexer MUX71, the SBITERR end is connected to the No. 0 input end of the two-input multiplexer MUX77, and is connected to the D end of the register DFF76 through BUF75, the DBITERR end is connected to the No. 0 input end of the two-input multiplexer MUX80, and is connected to the D end of the register DFF79 through BUF78; the Q end of the register DFF76 is connected to the No. 1 input end of the two-input multiplexer MUX77, and the Q end of the register DFF79 is connected to the No. 1 input end of the two-input multiplexer MUX80; the output end of the two-input multiplexer MUX71 is connected to the No. 0 input end of the two-input multiplexer MUX83, and is connected to the D end of the register DFF82 through BUF81, and the Q end of the register DFF82 is connected to the No. 1 input end of the two-input multiplexer MUX83; The port OUTPUT_REG_SET is set to be connected to the selection terminals of the two-input multiplexers MUX74, MUX77, MUX80, and MUX83; the output terminal of the two-input multiplexer MUX74 is connected to the input terminal No. 0 of MUX87, the output terminal of the two-input multiplexer MUX77 is connected to the input terminal No. 0 of the two-input multiplexer MUX93, the output terminal of the two-input multiplexer MUX80 is connected to the input terminal No. 0 of MUX99, and the output terminal of the two-input multiplexer MUX83 is connected to the input terminal No. 0 of the two-input multiplexer MUX105; The cascade input port CAS_RD_ACCESS is connected to the input terminal 0 of the two-input multiplexer MUX86, and is connected to the D terminal of the register DFF85 through BUF84, and the Q terminal of the register DFF85 is connected to the input terminal 1 of the two-input multiplexer MUX86; The cascade input port CAS_IN_SBITERR is connected to the input terminal 0 of the two-input multiplexer MUX92, and is connected to the D terminal of the register DFF91 through BUF90, and the Q terminal of the register DFF91 is connected to the input terminal 1 of the two-input multiplexer MUX92; The cascade input port CAS_IN_DBITERR is connected to the input terminal 0 of the two-input multiplexer MUX98, and is connected to the D terminal of the register DFF97 through BUF96, and the Q terminal of the register DFF97 is connected to the input terminal 1 of the two-input multiplexer MUX98; The cascade input port CAS_IN_DO[71:0] is connected to the input terminal 0 of the two-input multiplexer MUX104, and is connected to the D terminal of the register DFF103 through the BUF102, and the Q terminal of the register DFF103 is connected to the input terminal 1 of the two-input multiplexer MUX104; Set the port CAS_OUT_REG_SET to connect the selection end of the two-input multiplexers MUX86, MUX92, MUX98, and MUX104; set the port CAS_OUT_IN_SET to connect the selection end of the two-input multiplexers MUX87, MUX93, MUX99, and MUX105; the output end of the two-input multiplexer MUX86 is connected to the No. 1 input end of the two-input multiplexer MUX87, the output end of the two-input multiplexer MUX92 is connected to the No. 1 input end of the two-input multiplexer MUX93, the output end of the two-input multiplexer MUX98 is connected to the No. 1 input end of the two-input multiplexer MUX99, and the output end of the two-input multiplexer MUX104 is connected to the No. 1 input end of the two-input multiplexer MUX1 05; the output end of the two-input multiplexer MUX87 is connected to an input end of the two-input AND gate AND89, and is connected to the output port RD_ACCESS through BUF88; the output end of the two-input multiplexer MUX93 is connected to an input end of the two-input AND gate AND95, and is connected to the output port SBITERR through BUF94; the output end of the two-input multiplexer MUX99 is connected to an input end of the two-input AND gate AND101, and is connected to the output port DBITERR through BUF100; the output end of the two-input multiplexer MUX105 is connected to an input end of the two-input AND gate AND107, and is connected to the output port DO[71:0] through BUF106; The set port CAS_OUT_OUT_SET is connected to the other input end of the two-input AND gates AND89, AND95, AND101, and AND107, the output end of the two-input AND gate AND89 is connected to the cascade output port CAS_OUT_RD_ACCESS, the output end of the two-input AND gate AND95 is connected to the cascade output port CAS_OUT_SBITERR, the output end of the two-input AND gate AND101 is connected to the cascade output port CAS_OUT_DBITERR, and the output end of the two-input AND gate AND107 is connected to the cascade output port CAS_OUT_DO[71:0].

8. The on-chip memory peripheral control circuit capable of cascading and error correction according to claim 7, characterized in that: The setting port is connected to the external setting signal; DO_RAM[71:0] of the memory body is connected to the input port DO_RAM[71:0]; EN_RAM and RDB_WR_RAM of the input port controller are connected to the input ports EN_RAM and RDB_WR_RAM; external signals CLK and RST are connected to the input ports CLK and RST; The output port is connected to the external output signal; The cascade input ports are all connected to the cascade output ports of the output port controller of the memory below; The cascade output ports are all connected to the cascade input ports of the output port controller of the upper memory.

9. The on-chip memory peripheral control circuit capable of cascading and error correction according to claim 7 or 8, characterized in that: By controlling the setting port of the output port controller, the output port controller performs the corresponding task operation: The setting port CAS_OUT_OUT_SET is used to control the cascade output function. When it is 1, the cascade output port sends data to the upper memory, and when it is 0, the cascade output port does not output data; The setting port CAS_OUT_IN_SET is used to control the cascade input port. When it is 1, the cascade input port receives data from the lower memory, and the input port does not receive data from the memory body. When it is 0, the input port receives data from the memory body, and the cascade input port does not receive data from the lower memory. The setting port CAS_OUT_REG_SET is used to control the cascade input port pipeline register. When it is 1, the cascade input port pipeline register is enabled, and when it is 0, it is not enabled; Set the port OUTPUT_REG_SET to control the output port pipeline register. When it is 1, the output port pipeline register is enabled, and when it is 0, it is not enabled. Set port ECC_REG_SET to control the pipeline register of the error correction and decoding module. When it is 1, the pipeline register of the error correction and decoding module is enabled, and when it is 0, it is not enabled; The port ECC_DEC_SEL is set to control the error correction decoding module. When it is 1, the error correction decoding function is enabled, and when it is 0, it is not enabled.

10. The on-chip memory peripheral control circuit capable of cascading and error correction according to claim 7, characterized in that: The error correction and detection decoder ECCDEC70 in the output port controller includes multiple codec units and one error correction unit, and is provided with input ports DI[71:0] and ECC_DEC_SEL, and output ports DO[71:0], SBITERR and DBITERR; wherein the input port ECC_DEC_SEL is connected to the ECC_SEL end of each codec unit and the error correction unit, and the input port DI[71:0] is connected to the D[35:0] end of each codec unit according to different encoding sequences to form corresponding decoding logic, and is also connected to the error correction unit; The error correction and detection decoder ECCDEC70 first determines the value of ECC_DEC_SEL. When it is 1, it indicates that the error correction and detection decoding function is enabled and the error correction and detection decoder is enabled. When it is 0, it indicates that the error correction and detection decoding function is not enabled and the error correction and detection decoder is not enabled. When the error correction and detection decoder is enabled, DI[71:0] is decoded. When a single bit error is found in DI[71:0], the error is corrected and output through DO[71:0], and SBITERR is set to 1 at the same time, indicating that a single bit error is detected and corrected. When a double bit error is found in DI[71:0], it is directly output to DO[71:0], and DBITERR is set to 1 at the same time, indicating that a double bit error is detected.

11. The on-chip memory peripheral control circuit capable of cascading and error correction according to claim 10, characterized in that: A search unit is provided in the error correction unit, and the ports of the search unit include input ports C0, C1, C2, C3, C4, C5, C6, C7 and D, and an output port Q; the search unit determines whether D is wrong according to the values ​​of C0, C1, C2, C3, C4, C5, C6, and C7. If there is an error, it is corrected and output to Q. If there is no error, it is directly output to Q.

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