Continuous microfluidic biochip application mapping method considering actual fluid operation

Abstract

The invention relates to a continuous micro-fluidic biochip application mapping method considering actual fluid operation, and belongs to the field of micro-fluidic biochip electronic automation. According to the method, in order to obtain the shortest flow path of all fluid transportation tasks, the invention provides a fluid position driven flow path binding algorithm to sense the position of fluid. In addition, the invention further provides an actual fluid operation constraint sensing architecture adjustment algorithm, and by adjusting the position of the intersection point of the port of the chip, the equipment and the flow channel, immediate execution constraint and parallel execution constraint can be better met, and the completion time of bioassay is shortened. Experimental results prove that the method provided by the invention can better meet actual fluid operation constraints. Meanwhile, according to the method, under the given actual fluid operation constraint, the completion time of the biological assay and the chip architecture cost are well balanced.

Description

Technical Field

[0001] The present invention belongs to the field of electronic automation of microfluidic biochips, and particularly relates to a continuous microfluidic biochip application mapping method considering actual fluid operations. Background Art

[0002] With the progress of manufacturing technology, CFMBs can integrate millions of microvalves today, compared with thousands of microvalves that could be integrated on a coin-sized chip before. The increasing integration of CFMBs makes traditional manual design no longer applicable, and Electronic Design Automation (EDA) technology has begun to be applied to the field of CFMBs. More and more computer and electronics laboratories are committed to automating the entire design process of microfluidic biochips. The architecture synthesis of CFMBs mainly includes three stages, namely the high-level synthesis stage, the physical design stage, and the application mapping stage. Since the chip architecture is not determined in the high-level synthesis stage, it is usually assumed that the duration of transportation tasks is a fixed constant, and there are no shared flow channels between transportation tasks. This results in the binding scheduling results generated in the high-level synthesis stage being unable to be directly applied to the chip architecture generated in the physical design. Therefore, after the physical design is completed, application mapping needs to be performed to adjust the binding scheduling scheme according to the obtained chip architecture. At the same time, the deviation between the duration of transportation tasks and the actual duration will violate the immediate execution constraint and the parallel execution constraint in actual fluid operations, and the chip architecture needs to be adjusted according to the actual fluid operation constraints. Therefore, the present invention proposes a continuous microfluidic biochip application mapping method considering actual fluid operations. The method senses the position of the fluid to obtain the shortest flow path of all fluid transportation tasks. At the same time, by adjusting the positions of the ports, devices, and flow channel intersections of the chip, the immediate execution constraint and the parallel execution constraint can be better satisfied, and the completion time of the bioassay can be shortened. Summary of the Invention

[0003] The purpose of the present invention is to provide a continuous microfluidic biochip application mapping method considering actual fluid operations, which can better balance the completion time of the bioassay and the chip architecture cost under given actual fluid operation constraints.

[0004] To achieve the above purpose, the technical solution of the present invention is: a continuous microfluidic biochip application mapping method considering actual fluid operations, including:

[0005] Propose a fluid position-driven flow path binding algorithm to sense the position of the fluid to obtain the shortest flow path of all fluid transportation tasks;

[0006] A framework adjustment algorithm for actual fluid operation constraint perception is proposed, which adjusts the positions of the ports, devices, and flow channel intersections of the chip to better meet the immediate execution constraint and parallel execution constraint and shorten the completion time of biometric measurement.

[0007] The method specifically includes:

[0008] First, find the fluid transportation tasks executed at the initial moment in the binding scheduling scheme, and record the set of nodes FP where the fluid is currently located; since there may be multiple fluid transportation tasks executed in parallel at the same moment, the set of nodes FP is used to represent the nodes where the fluid is currently located; second, since the execution time of each operation is fixed, the optimization goal of minimizing the completion time of biometric measurement is modeled as the execution time of the fluid transportation tasks; and the Dijkstra shortest path algorithm is used to find the shortest flow path of the nodes; after finding the bound flow path for a node, the nodes in this flow path cannot appear in the flow paths of other nodes in FP; when all nodes in FP are bound with flow paths, set the set FP to empty; then enter the next moment, find all the fluid transportation tasks at this moment, and record them in the set of nodes FP where the fluid is located; then use the Dijkstra shortest path algorithm to find the shortest flow path of the nodes; after all the fluid transportation tasks in the binding scheduling scheme are bound with flow paths, the flow path set L is obtained; after obtaining the flow path set L, the actual execution time T of the fluid transportation task trans can be obtained. i of the actual execution time T;

[0009] Next, after obtaining the flow path set L and the completion time T of the biometric measurement, the algorithm finds the flow path with the immediate execution constraint, and adds the nodes where the fluid is located and the target nodes in this flow path to the set of movable nodes P. m Next, find the flow paths of the fluid transportation tasks for parallel execution operations, and add the nodes where the fluid is located and the target nodes in this flow path to the set of movable nodes P. m At the same time, calculate the waiting time for parallel execution operations. The waiting time for parallel execution operations is the moment when the last parallel operation fluid is input into the device minus the moment when the first parallel operation fluid is input into the device; next, the algorithm starts to calculate the movement cost of all nodes in the set of movable nodes P. m in.

[0010] After that, after obtaining the movement costs of all nodes in the set of movable nodes, the movable nodes are sorted in ascending order of movement cost, and the nodes with negative movement costs are selected to move in the direction of increasing movement cost; at the same time, the adjusted chip architecture topology map is updated; when the movement costs of all nodes in the set of movable nodes are positive, it means that the movement of all nodes will not bring benefits to the chip architecture; the chip architecture adjustment ends; finally, the adjusted chip architecture is determined and the completion time T of biometric measurement is recalculated.

[0011] In an embodiment of the present invention, the flow path binding is implemented as follows:

[0012] In the application mapping stage, the chip architecture is modeled as a topology graph G(P, E), where the vertex p i ∈P represents a device or a flow channel intersection point in the chip architecture; the edge e i,j ∈E represents the flow channel between vertices p i and p j , and w i,j in e i =(p j , p i,j , w i,j ) represents the weight of edge e i,j , and this weight is modeled as the length of the flow channel between vertices p i and p j ;

[0013] According to the binding scheduling scheme and the chip architecture, the goal of application mapping is to find the corresponding shortest flow path for the fluid transportation task; in the chip architecture considering the actual fluid operation, each fluid transportation task needs to occupy a separate flow path during execution; the flow paths occupied by the parallel execution transportation tasks cannot be shared, and they cannot share flow channels; at the same time, the flow path bound to each transportation task needs to be minimized to minimize the execution time of the transportation task.

[0014] In an embodiment of the present invention, the flow path consists of a flow port, the starting position of the fluid, the target position of fluid transportation, a waste liquid port, and the flow channels between them.

[0015] In an embodiment of the present invention, the fluid transportation task and time calculation method are as follows:

[0016] When all fluid transportation tasks in the binding scheduling scheme are bound to flow paths, the flow path set L is obtained; after obtaining the flow path set L, the actual execution time of the fluid transportation task trans i can be obtained; the time of fluid transportation is calculated as:

[0017]

[0018] Among them, node p i g ∈P represents the target node of the fluid transportation task trans i ; in the chip architecture considering actual fluid operations, there are three fluid transportation tasks, namely the fluid transportation task between devices, the redundant fluid discharge task, and the waste liquid removal task; the target node of the fluid transportation task between devices is the target device, and the target nodes of the redundant fluid discharge task and the waste liquid removal task are the waste liquid ports of the fluid path; len(fp i , p i g ) represents the distance between the current node fp i of the fluid and the target node p i g , and v f represents the transportation speed of the fluid in the chip.

[0019] In an embodiment of the present invention, the calculation method of the waiting time for parallel execution operations is as follows:

[0020]

[0021] Among them, represents the arrival time of the fluid for the parallel operation o i , represents the start execution time of the fluid transportation task for the parallel operation o i , represents the waiting time between the parallel operation o i and the parallel operation o j , and n represents the number of parallel execution operations.

[0022] In an embodiment of the present invention, the movement cost cos i of a single node p i is calculated as follows:

[0023]

[0024] Among them, represents the movement cost in the x-axis direction, and the movement cost in the y-axis direction.

[0025] In an embodiment of the present invention, the movement cost in the x-axis direction is calculated as follows:

[0026] On the one hand, the moving cost needs to consider the cost of the immediate execution constraint and the parallel execution constraint after moving, which is reflected in whether the execution interval between the immediate execution constraint operations is shortened and the waiting time of the parallel execution constraint operations; on the other hand, since it involves chip architecture adjustment, the constraints in physical design need to be considered during the adjustment process; therefore, the moving cost in the x-axis direction is calculated as follows:

[0027]

[0028] where phy x,i represents whether node p i violates the constraints in physical design after moving in the x-axis direction, M represents a very large positive number, dis x,i respectively represent whether the device wiring area constraint, the port wiring area constraint, and the minimum spacing constraint are violated. When the value is 1, it means violation, and when the value is 0, it means no violation; represents the change in the waiting time of the parallel execution constraint operations, represents the change in the execution interval between the immediate execution constraint operations; represents node p i the change in the total length of the flow channel after moving in the x-axis direction; α, β, γ are adjustable weight coefficients.

[0029] In an embodiment of the present invention, the implementation method of chip architecture adjustment is as follows:

[0030] The chip architecture needs to be adjusted to adapt to the immediate execution constraint and the parallel execution constraint; the input is the set of flow paths L, the chip architecture diagram G(P, E), the node coordinates CO(X, Y), and the given set of constraints C; x i ∈X represents the x-axis coordinate of node p i , y i ∈Y represents the y-axis coordinate of node p i ; c i,j ∈C represents the constraint between operation o i and operation o j ; when c i,j =1, it means there is an immediate execution constraint between operation o i and operation o j ; when c i,j =2, it means there is a parallel execution constraint between operation o i and operation o j ; when c i,j =0, it means there is no constraint between operation o i and operation o jThere is no given constraint between them; the output of the algorithm is the adjusted chip architecture and the biometric completion time T; the goal is to minimize the execution interval between immediately executable constraint operations and the waiting time for parallelly executable constraint operations; among them, the execution interval between immediately executable constraint operations refers to the fluid transportation time between two operations, and the waiting time for parallelly executable constraint operations refers to the time when the fluid is input into the device for the last parallel operation minus the time when the fluid is input into the device for the first parallel operation.

[0031] The present invention also provides a computer-readable storage medium, on which computer program instructions capable of being run by a processor are stored. When the processor runs the computer program instructions, the method steps as described in any one of the above can be implemented.

[0032] Compared with the prior art, the present invention has the following beneficial effects: the method proposed by the present invention can better meet the actual fluid operation constraints. At the same time, under the given actual fluid operation constraints, the method better balances the biometric completion time and the chip architecture cost. Description of the Drawings

[0033] Figure 1 It is an example of the synthesis result of the CFMBs architecture.

[0034] Figure 2 For correspondence Figure 1 The topological diagram for chip architecture modeling. Detailed Embodiments

[0035] Next, in conjunction with the drawings, the technical solution of the present invention will be specifically described.

[0036] The present invention provides a continuous microfluidic biochip application mapping method considering actual fluid operations, including:

[0037] Propose a fluid position-driven flow path binding algorithm to sense the position of the fluid to obtain the shortest flow path for all fluid transportation tasks;

[0038] Propose an architecture adjustment algorithm for sensing actual fluid operation constraints to better meet the immediate execution constraints and parallel execution constraints and shorten the biometric completion time by adjusting the positions of the ports, devices, and flow channel intersections of the chip.

[0039] The method specifically includes:

[0040] First, find the fluid transportation tasks executed at the initial moment in the binding scheduling scheme, and record the set of nodes FP where the fluid is currently located. Since there may be multiple fluid transportation tasks executed in parallel at the same moment, the set of nodes FP is used to represent the nodes where the fluid is currently located. Second, since the execution time of each operation is fixed, the optimization goal of minimizing the completion time of biometric measurement is modeled as the execution time of the fluid transportation task. The Dijkstra shortest path algorithm is used to find the shortest flow path of the nodes. After finding the bound flow path for a node, the nodes in this flow path cannot appear in the flow paths of other nodes in FP. When all nodes in FP are bound with flow paths, set the set FP to empty. Then enter the next moment, find all fluid transportation tasks at this moment, and record them in the set of nodes FP where the fluid is located. Then use the Dijkstra shortest path algorithm to find the shortest flow path of the nodes. After all fluid transportation tasks in the binding scheduling scheme are bound with flow paths, the set of flow paths L is obtained. After obtaining the set of flow paths L, the actual execution time T of the fluid transportation task trans can be obtained. i The actual execution time T of

[0041] Next, after obtaining the set of flow paths L and the completion time T of the biometric measurement, the algorithm finds the flow path with the immediate execution constraint, and adds the nodes where the fluid is located and the target nodes in this flow path to the set of movable nodes P. m Then, find the flow paths of the fluid transportation tasks with parallel execution operations, and add the nodes where the fluid is located and the target nodes in this flow path to the set of movable nodes P. m At the same time, calculate the waiting time of the parallel execution operations. The waiting time of the parallel execution operations is the time when the last parallel operation fluid is input into the device minus the time when the first parallel operation fluid is input into the device. Next, the algorithm starts to calculate the movement cost of all nodes in the set of movable nodes P. m

[0042] After that, after obtaining the movement costs of all nodes in the set of movable nodes, sort the movable nodes in ascending order of the movement cost, and select the nodes with negative movement costs to move in the direction of increasing movement cost. At the same time, update the adjusted chip architecture topology diagram. When the movement costs of all nodes in the set of movable nodes are positive, it means that the movement of all nodes will not bring benefits to the chip architecture. The chip architecture adjustment ends. Finally, determine the adjusted chip architecture and recalculate the completion time T of the biometric measurement.

[0043] The following details the calculation methods and implementation methods of flow path binding, fluid transportation task and time calculation, chip architecture adjustment, waiting time of parallel execution operations, movement cost, etc. involved in the method of the present invention:

[0044] ​1. Flow Path Binding:

[0045] In the application mapping phase, the chip architecture is modeled as a topological graph G(P, E), where the vertex p i ∈P represents a device or a flow channel intersection point in the chip architecture. The edge e i,j ∈E represents the flow channel between vertices p i and p j , and e i,j =(p i , p j , w i,j ), where w i,j represents the weight of edge e i,j , and this weight is modeled as the length of the flow channel between vertices p i and p j . In the chip architecture shown in Figure 1 , there are 6 flow ports, 7 waste liquid ports, 6 devices, 1 flow channel intersection point, and 20 flow channels between them. The topological graph modeled with this chip architecture is shown in Figure 2 , which contains 20 vertices and 19 edges.

[0046] According to the binding scheduling scheme and the chip architecture, the goal of application mapping is to find the corresponding shortest flow path for the fluid transportation task. Under the chip architecture considering actual fluid operations, each fluid transportation task needs to occupy a separate flow path during its execution. A flow path consists of a flow port, the starting position of the fluid, the target position of the fluid transportation, a waste liquid port, and the flow channels between them. It should be noted that the flow paths occupied by parallel execution transportation tasks cannot share, and they cannot share flow channels. At the same time, the flow path bound to each transportation task needs to be minimized to minimize the execution time of the transportation task.

[0047] 2. Fluid Transportation Task and Time Calculation:

[0048] After all fluid transportation tasks in the binding scheduling scheme are bound to flow paths, the flow path set L is obtained. After obtaining the flow path set L, the actual execution time of the fluid transportation task trans i can be obtained. The time of fluid transportation can be calculated as:

[0049]

[0050] where the node p i g ∈P represents the fluid transportation task trans iThe target node. In a chip architecture considering actual fluid operations, there are three fluid transportation tasks, namely the fluid transportation task between devices, the task of discharging excess fluid, and the task of removing waste fluid. The target node of the fluid transportation task between devices is the target device, and the target nodes of the tasks of discharging excess fluid and removing waste fluid are the waste fluid ports of the fluid path. len(fp i ,p i g ) represents the current node where the fluid is located, fp i and the target node p i g The distance between them, v f represents the transportation speed of the fluid in the chip.

[0051] 3. Chip architecture adjustment:

[0052] The chip architecture needs to be adjusted to adapt to these immediate execution constraints and parallel execution constraints. The input is the set of fluid paths L, the chip architecture graph G(P, E), the node coordinates CO(X, Y), and the given set of constraints C. x i ∈X represents the x-axis coordinate of the node p i , and y i ∈Y represents the y-axis coordinate of the node p i . c i,j ∈C represents the constraint between the operations o i and the operation o j . When c i,j = 1, it means there is an immediate execution constraint between the operation o i and the operation o j ; when c i,j = 2, it means there is a parallel execution constraint between the operation o i and the operation o j ; when c i,j = 0, it means there is no given constraint between the operation o i and the operation o j . The output of the algorithm is the adjusted chip architecture and the biometric completion time T. The goal is to minimize the execution interval between the immediately executable constrained operations and the waiting time of the parallel execution constrained operations. Among them, the execution interval between the immediately executable constrained operations refers to the fluid transportation time between the two operations, and the waiting time of the parallel execution constrained operations refers to the time when the fluid of the last parallel operation is input into the device minus the time when the fluid of the first parallel operation is input into the device.

[0053] 4. Waiting time for parallel execution operations:

[0054] The waiting time for parallel execution operations is the time when the fluid of the last parallel operation is input into the device minus the time when the fluid of the first parallel operation is input into the device. Its calculation method is:

[0055]

[0056] Among them, represents the fluid arrival time of parallel operation o i of, represents the start execution time of the fluid transportation task of parallel operation o i of, represents the waiting time between parallel operation o i and parallel operation o j ; n represents the number of parallel execution operations.

[0057] 5. Movement cost:

[0058] The movement cost cos of a single node p i is calculated as follows: i is calculated as follows:

[0059]

[0060] Among them, represents the movement cost in the x-axis direction, in the y-axis direction. The movement cost in the x-axis direction will be mainly introduced below of the calculation method, and the calculation of the movement cost in the y-axis direction is similar

[0061] On the one hand, the movement cost needs to consider the cost of the immediate execution constraint and the parallel execution constraint after movement, which is mainly reflected in whether it shortens the execution interval between the immediate execution constraint operations and the waiting time of the parallel execution constraint operations. On the other hand, due to the chip architecture adjustment, the constraints in the physical design need to be considered during the adjustment process. For example, the port cannot be moved to the device layout area, the device cannot be moved to the port layout area, and the distance between two nodes cannot be less than the minimum distance. Therefore, the movement cost cos in the x-axis direction i x is calculated as follows:

[0062]

[0063] Among them, phy x,i represents whether node p i violates the constraints in the physical design after moving in the x-axis direction, M represents a very large positive number, dis x,i respectively represent whether the device wiring area constraint, the port wiring area constraint, and the minimum distance constraint are violated. When the value is 1, it means violation, and when the value is 0, it means non-violation. represents the change in the waiting time of the parallel execution constraint operation, Indicates the change in the execution interval between immediately executed constraint operations. Indicates node p i The change in the total length of the flow channel after moving in the x-axis direction. α, β, and γ are adjustable weight coefficients.

[0064] The present invention also provides a computer-readable storage medium, on which computer program instructions capable of being run by a processor are stored. When the processor runs the computer program instructions, the method steps described in any of the above can be implemented.

[0065] The above are the preferred embodiments of the present invention. All changes made according to the technical solution of the present invention, when the functions and effects produced do not exceed the scope of the technical solution of the present invention, fall within the protection scope of the present invention.

Claims

1. A method for mapping continuous microfluidic biochip applications taking into account actual fluid manipulation, characterized in that: include: A fluid position driven flow path binding algorithm is proposed to sense the location of the fluid and obtain the shortest flow path for all fluid transportation tasks. A practical fluid operation constraint-aware architecture adjustment algorithm is proposed to adjust the positions of the chip's ports, devices, and flow channel intersections to better meet immediate execution constraints and parallel execution constraints and shorten the completion time of bioassays.

2. The continuous microfluidic biochip application mapping method considering actual fluid operations according to claim 1, characterized in that: The method specifically comprises: First, find the fluid transport task executed at the initial moment in the binding scheduling scheme, and record the node set FP where the fluid is currently located; since multiple fluid transport tasks may be executed in parallel at the same moment, the node where the fluid is currently located is represented by the node set FP; secondly, since the execution time of each operation is fixed, the optimization goal of minimizing the completion time of the bioassay is modeled as the execution time of the fluid transport task; and use the Dijkstra shortest path algorithm to find the shortest flow path of the node; after finding the bound flow path for the node, the node in the flow path cannot appear in the flow path of other nodes in FP; when all nodes in FP are bound to the flow path, the set FP is empty; then enter the next moment, find all the fluid transport tasks at that moment, and record them in the node set FP where the fluid is located; then use the Dijkstra shortest path algorithm to find the shortest flow path of the node; when all the fluid transport tasks in the binding scheduling scheme are bound to the flow path, the flow path set L is obtained; after obtaining the flow path set L, the fluid transport task trans i The actual execution time T; Next, after obtaining the flow path set L and the completion time T of the bioassay, the algorithm finds the flow path with the immediate execution constraint and adds the node where the fluid is located and the target node in the flow path to the movable node set P m Next, find the flow path of the fluid transport task that executes the operation in parallel, and add the node where the fluid is located and the target node in the flow path to the movable node set P m At the same time, the waiting time of the parallel execution operation is calculated. The waiting time of the parallel execution operation is the time when the last parallel operation fluid is input to the device minus the time when the first parallel operation fluid is input to the device; Next, the algorithm starts to calculate the movable node set P m The movement cost of all nodes in; Then, after obtaining the moving costs of all nodes in the movable node set, the movable nodes are sorted in ascending order of moving costs, and nodes with negative moving costs are selected to move in the direction of increasing moving costs; at the same time, the adjusted chip architecture topology is updated; when the moving costs of all nodes in the movable node set are positive, it means that the movement of all nodes will not bring any gain to the chip architecture; the chip architecture adjustment is completed; finally, the adjusted chip architecture is determined and the completion time T of the bioassay is recalculated.

3. The continuous microfluidic biochip application mapping method considering actual fluid operations according to claim 2, characterized in that: Flow path binding is implemented as follows: In the application mapping phase, the chip architecture is modeled as a topological graph G(P,E), with vertex p i ∈P represents a device or flow channel intersection in a chip architecture; edge e i,j ∈E represents vertex p i and p j The flow channel between i,j =(p i ,p j ,w i,j ) i,j Represents edge e i,j The weight of the vertex p i and p j The length of the flow channel between According to the binding scheduling scheme and chip architecture, the goal of application mapping is to find the corresponding shortest flow path for the fluid transportation task; Under the chip architecture that takes actual fluid operations into consideration, each fluid transport task needs to occupy a separate flow path during execution; the flow paths occupied by transport tasks executed in parallel cannot be shared, and they cannot share flow channels; at the same time, the flow path bound to each transport task needs to be shortest to minimize the execution time of the transport task.

4. The continuous microfluidic biochip application mapping method considering actual fluid operations according to claim 3, characterized in that: The flow path consists of the flow port, the starting location of the fluid, the destination location of the fluid transport, the waste port, and the flow channels between them.

5. The continuous microfluidic biochip application mapping method considering actual fluid operations according to claim 3, characterized in that: The fluid transportation tasks and time calculation methods are as follows: When all fluid transport tasks in the binding scheduling scheme are bound to flow paths, the flow path set L is obtained; after obtaining the flow path set L, the fluid transport task trans i The actual execution time of the fluid transport Calculated as: Among them, node p i g ∈P, represents the fluid transport task trans i The target node of the flow path is len(fp); in the chip architecture considering actual fluid operation, there are three fluid transport tasks, namely, inter-device fluid transport task, excess fluid discharge task and waste liquid removal task; the target node of the inter-device fluid transport task is the target device, and the target node of the excess fluid discharge task and the waste liquid removal task is the waste liquid port of the flow path; i ,p i g ) indicates the node fp where the fluid is currently located i and the target node p i g The distance between f Indicates the transport speed of fluid in the chip.

6. The continuous microfluidic biochip application mapping method considering actual fluid operations according to claim 5, characterized in that: The waiting time for parallel execution of operations is calculated as follows: in, Indicates parallel operation o i The arrival time of the fluid, Indicates parallel operation o i The fluid transport task starts execution time, Indicates parallel operation o i and parallel operations j The waiting time between them, n represents the number of operations executed in parallel.

7. The continuous microfluidic biochip application mapping method considering actual fluid operations according to claim 2, characterized in that: A single node p i The cost of movement i The calculation is as follows: in, Represents the movement cost in the x-axis direction, The cost of moving in the y-axis direction.

8. The continuous microfluidic biochip application mapping method considering actual fluid operations according to claim 7, characterized in that: The cost of moving in the x-axis direction The calculation method is as follows: On the one hand, the moving cost should consider the cost of the immediate execution constraint and the parallel execution constraint after the move, which is reflected in whether the execution interval between the immediate execution constraint operations and the waiting time of the parallel execution constraint operations are shortened; on the other hand, since it involves chip architecture adjustment, the constraints in the physical design need to be considered during the adjustment process; therefore, the moving cost in the x-axis direction The calculation is as follows: Among them, phy x,i Represents node p i Whether the physical design constraints are violated after moving in the x-axis direction, M represents a very large positive number, dis x,i Indicates whether the device routing area constraint, port routing area constraint and minimum spacing constraint are violated. When the value is 1, it means violation, and when the value is 0, it means no violation. represents the change in waiting time for parallel execution of constraint operations, Indicates the change in the execution interval between immediate execution constraint operations; Represents node p i The change in the total length of the flow channel after moving in the x-axis direction; α, β, γ are adjustable weight coefficients.

9. The continuous microfluidic biochip application mapping method considering actual fluid operations according to claim 2, characterized in that: The chip architecture adjustment is implemented as follows: The chip architecture needs to be adjusted to accommodate immediate execution constraints and parallel execution constraints; the input is the flow path set L, the chip architecture graph G(P,E), the node coordinates CO(X,Y) and the given constraint set C; x i ∈X represents node p i The x-axis coordinate, y i ∈Y represents node p i The y-axis coordinate of i,j ∈C represents operation o i and operation j The constraints between i,j =1, indicating operation o i and operation j There is an immediate execution constraint between them; when c i,j =2, indicating operation o i and operation j There is a parallel execution constraint between them; when c i,j =0, indicating operation o i and operation j There are no given constraints between them; the output of the algorithm is the adjusted chip architecture and bioassay completion time T; the goal is to minimize the execution interval between immediately executed constraint operations and the waiting time of parallel execution constraint operations; among them, the execution interval between immediately executed constraint operations refers to the fluid transportation time between the two operations, and the waiting time of parallel execution constraint operations refers to the time when the last parallel operation fluid is input to the device minus the time when the first parallel operation fluid is input to the device.

10. A computer-readable storage medium having stored thereon computer program instructions that can be executed by a processor, and when the processor executes the computer program instructions, the method steps according to any one of claims 1 to 9 can be implemented.

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