Cache verification method and device, electronic equipment and storage medium

Abstract

The invention provides a cache verification method, and relates to the technical field of artificial intelligence, in particular to the technical field of cache units and formalized verification. The specific implementation scheme is as follows: generating a to-be-processed address by using an analog computation unit according to one of at least one symbol constant; generating a simulation request by using a simulation calculation unit according to the to-be-processed address; providing the simulation request to a simulation cache unit by using a simulation calculation unit to obtain a simulation processing result of the simulation request; and determining a verification result of the simulation cache unit according to the simulation processing result and an expected processing result of the simulation request. The invention further provides a cache verification device, electronic equipment and a storage medium.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technologies, and particularly to the fields of cache units and formal verification technologies. More specifically, the present disclosure provides a cache verification method, apparatus, electronic device, and storage medium. Background Art

[0002] With the development of artificial intelligence technologies, the applications of artificial intelligence processors are continuously increasing. Artificial intelligence processing may include cache units, which can effectively improve the memory access efficiency. Summary of the Invention

[0003] The present disclosure provides a cache verification method, apparatus, device, and storage medium.

[0004] According to one aspect of the present disclosure, there is provided a cache verification method, the method including: generating a to-be-processed address by using a simulation calculation unit according to one of at least one symbolic constant; generating a simulation request by using the simulation calculation unit according to the to-be-processed address; providing the simulation request to a simulation cache unit by using the simulation calculation unit to obtain a simulation processing result of the simulation request; and determining a verification result of the simulation cache unit according to the simulation processing result and an expected processing result of the simulation request.

[0005] According to another aspect of the present disclosure, there is provided a cache verification apparatus, the apparatus including: a first generation module configured to generate a to-be-processed address by using a simulation calculation unit according to one of at least one symbolic constant; a second generation module configured to generate a simulation request by using the simulation calculation unit according to the to-be-processed address; a providing module configured to provide the simulation request to a simulation cache unit by using the simulation calculation unit to obtain a simulation processing result of the simulation request; and a determining module configured to determine a verification result of the simulation cache unit according to the simulation processing result and an expected processing result of the simulation request.

[0006] According to another aspect of the present disclosure, there is provided an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to execute the method provided by the present disclosure.

[0007] According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the method provided by the present disclosure.

[0008] According to another aspect of the present disclosure, there is provided a computer program product including a computer program, and when the computer program is executed by a processor, the method provided by the present disclosure is implemented.

[0009] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings are used to better understand the solution and do not constitute a limitation to the present disclosure. Among them:

[0011] Figure 1 is a schematic diagram of an exemplary system architecture to which a cache verification method and apparatus according to an embodiment of the present disclosure can be applied;

[0012] Figure 2 is a flowchart of a cache verification method according to an embodiment of the present disclosure;

[0013] Figure 3 is a schematic diagram of the principle of a cache verification method according to an embodiment of the present disclosure;

[0014] Figure 4 is a block diagram of a cache verification apparatus according to an embodiment of the present disclosure; and

[0015] Figure 5 is a block diagram of an electronic device to which a cache verification method according to an embodiment of the present disclosure can be applied. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] The following describes exemplary embodiments of the present disclosure with reference to the accompanying drawings. Various details of the embodiments of the present disclosure are included to assist in understanding, and they should be considered merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0017] In order to verify whether the cache mechanism of the cache unit is correct, developers can use the Systemverilog programming language and the Universal Verification Methodology (UVM) framework to write random test cases. Next, based on one or more random test cases, an electronic design automation (EDA) tool can be used to create a simulation verification environment for simulation testing. The simulation verification environment includes a detector. The detector can compare the expected tag information and expected data with the tag information and expected data of the cache unit to be tested. However, randomized simulation is difficult to complete the verification of all features and design state spaces of the cache unit in a short period of time.

[0018] To verify whether the caching mechanism of the cache unit is correct, formal verification can also be performed. Formal verification uses mathematical analysis methods to build a model through an algorithm engine and exhaustively analyze the state space to be tested (including all input states, state transitions, etc.). Formal verification does not require building a verification platform and writing test cases. However, formal verification is applicable to the verification of small-scale hardware modules. As the design complexity and cycle depth increase, formal verification will consume a large amount of hardware resources, making it difficult to converge.

[0019] Therefore, to efficiently verify the cache unit, the present disclosure provides a cache verification method, which will be described below.

[0020] Figure 1 FIG. is a schematic diagram of an exemplary system architecture to which the cache verification method and apparatus according to an embodiment of the present disclosure can be applied. It should be noted that Figure 1 The figure shown is only an example of the system architecture to which the embodiments of the present disclosure can be applied, to help those skilled in the art understand the technical content of the present disclosure, but it does not mean that the embodiments of the present disclosure cannot be used in other devices, systems, environments or scenarios.

[0021] As Figure 1 shown, the system architecture 100 according to this embodiment may include terminal devices 101, 102, 103, a network 104, and a server 105. The network 104 is used to provide a medium for communication links between the terminal devices 101, 102, 103 and the server 105. The network 104 may include various connection types, such as wired and / or wireless communication links, etc.

[0022] Users can use the terminal devices 101, 102, 103 to interact with the server 105 through the network 104 to receive or send messages, etc. The terminal devices 101, 102, 103 may be various electronic devices with a display screen and supporting web browsing, including but not limited to smart phones, tablet computers, laptop portable computers, and desktop computers, etc.

[0023] The server 105 may be a server providing various services, such as a background management server (only an example) that supports the websites browsed by users using the terminal devices 101, 102, 103. The background management server can analyze and process data such as user requests received, and feedback the processing results (such as web pages, information, or data obtained or generated according to user requests) to the terminal devices.

[0024] It should be noted that the cache verification method provided by the embodiments of the present disclosure can generally be executed by the server 105. Correspondingly, the cache verification device provided by the embodiments of the present disclosure can generally be set in the server 105. The cache verification method provided by the embodiments of the present disclosure can also be executed by the terminal devices 101, 102, and 103. Correspondingly, the cache verification device provided by the embodiments of the present disclosure can also be set in the terminal devices 101, 102, and 103. The cache verification method provided by the embodiments of the present disclosure can also be executed by a server or a server cluster different from the server 105 and capable of communicating with the terminal devices 101, 102, 103 and / or the server 105. Correspondingly, the cache verification device provided by the embodiments of the present disclosure can also be set in a server or a server cluster different from the server 105 and capable of communicating with the terminal devices 101, 102, 103 and / or the server 105.

[0025] It can be understood that the system architecture of the present disclosure has been described above, and the method of the present disclosure will be described below.

[0026] Figure 2 It is a flowchart of a cache verification method according to an embodiment of the present disclosure.

[0027] As Figure 2 shown, the method 200 may include operation S210 to operation S240.

[0028] In operation S210, according to one of at least one symbolic constant, a to-be-processed address is generated by using a simulation calculation unit.

[0029] In the embodiments of the present disclosure, the simulation calculation unit may be a processor core of an artificial intelligence processor constructed by using simulation software. The artificial intelligence processor may be various processing units such as a general-purpose graphics processing unit (GPGPU), a tensor processing unit (TPU), or a neural network processing unit (NPU).

[0030] In the embodiments of the present disclosure, one or more symbolic constants may be randomly generated within a preset numerical range. The preset data range may be, for example, 0 to 1024. In one example, one symbolic constant may be 1, and another symbolic constant may be 2.

[0031] In the embodiments of the present disclosure, according to the symbolic constant, a to-be-processed address may be generated by using a preset algorithm. For example, the preset algorithm may be various algorithms. In one example, the symbolic constant may be converted into binary. The binary symbolic constant is used as the to-be-processed address.

[0032] In operation S220, according to the to-be-processed address, a simulation request is generated by using the simulation calculation unit.

[0033] In the embodiments of the present disclosure, the simulation request may be a simulation read request or a simulation write request. For example, the simulation read request may include an address to be processed. For another example, the simulation write request may include an address to be processed and data to be processed. The data to be processed may also be generated according to symbolic constants. For the same simulation write request, the symbolic constant for generating the data to be processed may be the same as the symbolic constant for generating the address to be processed.

[0034] In operation S230, the simulation request is provided to the simulation cache unit by using the simulation calculation unit, and a simulation processing result of the simulation request is obtained.

[0035] In the embodiments of the present disclosure, the simulation cache unit may be a cache unit of an artificial intelligence processor constructed by simulation software.

[0036] In the embodiments of the present disclosure, when the simulation request is a simulation read request, the simulation processing result of the simulation read request may be return data corresponding to the address to be processed.

[0037] In another embodiment of the present disclosure, when the simulation request is a simulation write request, the simulation processing result of the simulation write request may be data at the address to be processed in the simulation storage unit. The simulation storage unit may be a global storage unit of an artificial intelligence processor constructed by simulation software.

[0038] In operation S240, according to the simulation processing result and the expected processing result of the simulation request, a verification result of the simulation cache unit is determined.

[0039] In the embodiments of the present disclosure, the verification result may be a first verification result or a second verification result. The first verification result may indicate that the simulation processing result is consistent with the expected processing result, or may indicate successful verification. The second verification result may indicate that the simulation processing result is inconsistent with the expected processing result, or may indicate verification failure. It can be understood that after the cache unit receives a memory access request, it is processed according to a preset processing mechanism. If there is a problem with the processing mechanism, it may lead to verification failure.

[0040] Through the embodiments of the present disclosure, an address to be processed is generated according to a symbolic constant, and then a simulation request is generated. That is, the input conditions of the simulation verification are constrained by using the symbolic constant. The simulation request generated based on the symbolic constant is provided to the simulation cache unit, and the processing result is verified, effectively constraining the input conditions, which can effectively reduce the computational resource overhead required for verifying the cache unit and improve the verification efficiency.

[0041] It can be understood that the method of the present disclosure has been described above, and the symbolic constants of the present disclosure will be further described below.

[0042] In some embodiments, when verifying a cache unit, the verification method adopted can be formal verification. Formal verification can constrain input conditions through assume property syntax. It can be understood that if the random simulation method is used for constraint, during the formal verification process, the logic involved in unnecessary assume properties will be considered, and a large number of clock cycles and hardware resources will be used to process these unnecessary logics, resulting in waste of computing resources and storage resources and an increase in time cost.

[0043] In some embodiments, one or more symbolic constants can be generated to constrain the input conditions of formal verification. For example, the assume property can be: emblematic_signal: assume property (@(posedgeclk##1 $stable(variable)). Based on this assume property, in the first clock cycle, one or more values can be randomly generated within a preset numerical range. In multiple clock cycles after the first clock cycle, after the first clock cycle, the one or more values are retained as one or more symbolic constants. Through the embodiments of the present disclosure, the symbolic constants can be any values within the preset numerical range, which can achieve sufficient verification of the cache unit and effectively save computing resources. It can be understood that generating symbolic constants in the first clock cycle is only an example, and symbolic constants can be generated in the first to the mth clock cycles. m can be an integer greater than 1.

[0044] It can be understood that the symbolic constants of the present disclosure have been described above, and the simulated cache unit of the present disclosure will be described below.

[0045] In some embodiments, the simulated cache unit can include a first simulated cache module and a second simulated cache module. The first simulated cache module can store the simulated cache address. The second simulated cache module can store the simulated cache data corresponding to the simulated cache address. For example, the simulated cache address can be the tag of a cache line. The simulated cache data can be the data in the cache line.

[0046] In some embodiments, the simulated cache data can be determined based on at least one of the following data: the data to be processed in the simulated request; and the return data provided by the simulated storage unit. For example, when the simulated request is a simulated read request, the simulated cache unit can obtain data from the simulated storage unit. In this case, the simulated storage unit can provide the return data to the simulated cache unit. The return data can be used as the simulated cache data. Another example is that when the simulated request is a simulated write request, the simulated write request can include the data to be processed. The data to be processed can be used as the simulated cache data.

[0047] It can be understood that the above has described the analog cache unit of the present disclosure, and the first analog cache module and the second analog cache module will be further described below.

[0048] In some embodiments, the first analog cache module and the second analog cache module can be implemented by a multi-dimensional array. For example, taking the first analog cache module and the multi-dimensional array being a two-dimensional array as an example, the first analog cache module can be implemented by the following two-dimensional array: Cache RTL memory array: reg [WIDTH -1:0] memory [DEPTH -1:0]. Cache RTL memory array can be a cache unit register transfer level (RTL) storage array. WIDTH can represent the number of bits of the address, and WIDTH can be an integer greater than 1. DEPTH can represent the number of addresses. DEPTH can be an integer greater than 1. It can be understood that the two-dimensional array is only an example. The multi-dimensional array can also include other dimensions. For example, one dimension of the multi-dimensional array can also represent the type of data. Another example is that one dimension of the multi-dimensional array can also represent the type of instruction.

[0049] It can be understood that the above has described the present disclosure by taking the implementation of the analog cache module using a multi-dimensional array as an example. However, the present disclosure is not limited thereto, and the analog cache module can be implemented using a simple abstraction model.

[0050] In some other embodiments, the abstraction model can be an array. The number of bits dimension of the array can represent the number of bits of the address. The number dimension of the array can represent a preset number of addresses. The analog cache module can be implemented using the following abstraction model: abstraction model: reg [WIDTH -1:0] memory [1-1:0]. WIDTH can be the number of bits dimension, representing the number of addresses. memory [1-1:0] can represent that the number of addresses is 1. That is, the preset number can be 1. Through the embodiments of the present disclosure, using a simpler abstraction model to implement the analog storage unit can reduce the complexity from DEPTH×WIDTH to 1×WIDTH, and can further improve the cache verification efficiency.

[0051] Next, the processing mechanism of the analog cache unit will be described.

[0052] In some other embodiments, the analog cache addresses in the first analog cache module are stored at the first cache symbol addresses of the first analog cache module. The address to be processed includes a first address symbol to be processed and a second address symbol to be processed. The analog computing unit is used to provide an analog request to the analog cache unit, and the analog processing result of the analog request includes: determining a target analog cache address according to the address symbol to be processed. The target analog cache address is stored at the first cache symbol address hit by the first address symbol to be processed. Next, it can be determined whether the second address symbol to be processed hits the target analog cache address. For example, the first address symbol to be processed may hit a first cache symbol address in the first analog cache module. The analog cache address stored at the first cache symbol address can be used as the target analog cache address. It can be determined whether the target analog cache address is consistent with the second address symbol to be processed to determine whether the second address symbol to be processed hits the target analog cache address. Thus, the analog read request can be processed based on the address symbol. It can be understood that the address symbol is a symbolized address and can be an identifier. For example, for a matrix with I rows and J columns, the symbol [i, j] can represent the i-th row and the j-th column. The symbol [i, j] can represent a position in the matrix. The symbol [i, j] can be used as an address symbol. I is an integer greater than 1. J is an integer greater than 1. i is an integer greater than or equal to 1 and less than or equal to I. j is an integer greater than or equal to 1 and less than or equal to J.

[0053] In some other embodiments, the analog processing result of the analog request obtained by using the analog computing unit to provide the analog request to the analog cache unit further includes: writing the second address symbol to be processed into the first cache symbol address hit by the first address symbol to be processed. Writing the data to be processed in the analog request into the position indicated by the second address symbol to be processed in the second analog cache module. For example, in the case where the analog request is an analog write request, the second address symbol to be processed may indicate a position in the second analog cache module. The data to be processed can be written into the position indicated by the second address symbol to be processed. Thus, the analog write request can be processed based on the address symbol. Through the embodiments of the present disclosure, the analog request can be processed based on the address symbol, the cache verification can be performed more efficiently, the verification efficiency can be improved, and it is also convenient to find possible problems in the cache.

[0054] It can be understood that the above has described the analog cache module of the present disclosure. The following will further describe Figure 3 the method of the present disclosure.

[0055] Figure 3 is a schematic diagram of a cache verification method according to an embodiment of the present disclosure.

[0056] As Figure 3As shown, an artificial intelligence processor can be constructed using simulation software. The artificial intelligence processor may include an analog computing unit core_agent30, an analog cache unit cache30, and an analog storage unit mem_agent30. The analog cache unit cache30 includes a first analog cache module tag_ram30 and a second analog cache module data_ram30.

[0057] In some embodiments, one or more analog cache addresses and one or more expected processing results can be generated based on one or more symbolic constants. For example, multiple analog addresses can be generated using a first preset algorithm based on multiple symbolic constants. Also, multiple expected processing results respectively for the multiple analog addresses can be generated using a second preset algorithm based on the multiple symbolic constants. The expected processing result for an analog address and the analog address can be generated based on the same symbolic constant. As Figure 3 shown, multiple analog addresses and multiple expected processing results respectively for the multiple analog addresses can be stored in the expected result array golden_mem30. Also, multiple analog addresses and multiple expected processing results respectively for the multiple analog addresses can be stored in the analog storage unit mem_agent30. Another example is that one or more analog addresses can be used as analog cache addresses and stored in the first analog cache module tag_ram30. And the expected processing results for the one or more analog cache addresses can be stored in the second analog cache module data_ram30.

[0058] In some embodiments, the analog request can be an analog read request. Using the analog computing unit to provide the analog request to the analog cache unit, obtaining the analog processing result of the analog request includes: using the analog computing unit to provide the analog read request to the analog cache unit. As Figure 3 shown, the address to be processed of the first analog read request can be generated using the above first preset algorithm based on one of the above multiple symbolic constants. The analog computing unit core_agent30 can provide the first analog read request to the analog cache unit cache30. Next, it can be determined whether the address to be processed of the first analog read request hits the analog cache address in the first analog cache module tag_ram30.

[0059] In some embodiments, providing a simulation request to a simulation cache unit by using a simulation computing unit, and obtaining a simulation processing result of the simulation request includes: in response to the simulation cache unit generating a hit signal for a simulation read request, determining the simulation cache data corresponding to the simulation cache address that hits the to-be-processed address in the second simulation cache module as the simulation processing result of the simulation read request. The hit signal is generated when the to-be-processed address of the simulation read request hits at least one of the simulation cache addresses in the first simulation cache module. For example, if the to-be-processed address hits the simulation cache address in the tag_ram30 of the first simulation cache module, it can be determined that the data required by the first simulation read request is stored in the data_ram30 of the second simulation cache module in the simulation cache unit cache30. The simulation cache address that the to-be-processed address hits can indicate a simulation cache data in the second simulation cache module data_ram30. This simulation cache data can be used as the simulation processing result of the first simulation read request. Next, the simulation processing result can be provided to the simulation computing unit core_agent30.

[0060] In some embodiments, the expected result array includes the to-be-processed address and the expected processing result corresponding to the to-be-processed address. As described above, the to-be-processed address of the first simulation read request can be generated according to the above-mentioned first preset algorithm based on the above-mentioned symbolic constant. The multiple simulation addresses in the expected result array include the simulation addresses generated according to this symbolic constant. That is, the expected result array includes the to-be-processed address of the first simulation read request and also includes the expected processing result corresponding to this to-be-processed address.

[0061] In some embodiments, determining the verification result of the simulation cache unit according to the simulation processing result and the expected processing result of the simulation request includes: obtaining the expected processing result of the simulation request from the expected result array. Determining the verification result of the simulation cache unit according to the simulation processing result of the simulation request and the expected processing result of the simulation request. As Figure 3As shown, the simulation calculation unit core_agent30 may include a first detection module rd_checker30. The first detection module rd_checker30 may obtain, from the expected result array golden_mem30, the expected processing result corresponding to the to-be-processed address of the first simulation read request as the expected processing result of the first simulation read request. Next, the first detection module rd_checker30 may determine whether the expected processing result and the simulation processing result of the first simulation read request are consistent. If the expected processing result and the simulation processing result of the first simulation read request are consistent, the first detection module rd_checker30 may output a first verification result indicating successful verification. If the expected processing result and the simulation processing result of the first simulation read request are inconsistent, the first detection module rd_checker30 may output a second verification result indicating failed verification. Through the embodiments of the present disclosure, when the address of the simulation request hits the data in the simulation cache unit, the simulation cache unit can be verified, the mechanism of the cache unit can be effectively verified, the verification efficiency can be improved, and the accuracy of the cache unit after successful verification can be improved.

[0062] It can be understood that the above description of the present disclosure is given by taking the to-be-processed address of the first simulation read request hitting the simulation cache address in the simulation cache unit as an example. However, the present disclosure is not limited thereto. During the verification process, there may be no simulation cache address and simulation cache data in the simulation cache unit cache30, which will be described below.

[0063] In some other embodiments, providing the simulation request to the simulation cache unit by using the simulation calculation unit to obtain the simulation processing result of the simulation request includes: providing the simulation read request to the simulation cache unit by using the simulation calculation unit. As Figure 3 shown, the to-be-processed address of the second simulation read request may be generated by using the above first preset algorithm according to one of the above multiple symbolic constants. The simulation calculation unit core_agent30 may provide the second simulation read request to the simulation cache unit cache30. Next, it may be determined whether the to-be-processed address of the second simulation read request hits the simulation cache address in the first simulation cache module tag_ram30. It can be understood that the to-be-processed address of the first simulation read request and the to-be-processed address of the second simulation read request may be generated based on different symbolic constants respectively.

[0064] In some other embodiments, providing a simulation request to a simulation cache unit by using a simulation computing unit, and obtaining a simulation processing result of the simulation request includes: in response to the simulation cache unit generating a signal indicating a miss in a simulation read request, using the simulation cache unit to provide a data acquisition request to a simulation storage unit. The data acquisition request includes a simulation cache address for the simulation read request, and the simulation cache address for the simulation read request is obtained according to the address to be processed in the simulation read request. The miss signal is generated when there is no simulation cache address in the first simulation cache module. For example, if there is no simulation cache address in the first simulation cache module, a data acquisition request can be generated according to the address to be processed. In addition, the address to be processed in the second simulation read request can be used as the simulation cache address for the second simulation read request and stored in the tag_ram30 of the first simulation cache module. A data acquisition request can be generated according to the simulation cache address for the second simulation read request. The data acquisition request includes the simulation cache address for the second simulation read request. The simulation cache unit cache30 can provide the data acquisition request to the simulation storage unit mem_agent30. After receiving the data acquisition request, the simulation storage unit mem_agent30 determines, from multiple expected processing results stored in the simulation storage unit mem_agent30, the expected processing result corresponding to the data acquisition request as the returned data. The simulation storage unit mem_agent30 can provide the returned data corresponding to the data acquisition request to the simulation cache unit cache30. It can be understood that the miss signal can also be generated when the address to be processed in the simulation read request misses any simulation cache address in the first simulation cache module.

[0065] In some other embodiments, providing a simulation request to a simulation cache unit by using a simulation computing unit, and obtaining a simulation processing result of the simulation request includes: determining the returned data corresponding to the data acquisition request as the simulation processing result of the simulation read request. For example, the simulation cache unit cache30 can use the returned data corresponding to the data acquisition request as the simulation processing result of the second simulation read request. Next, the simulation cache unit cache30 can provide the simulation processing result corresponding to the second simulation read request to the simulation computing unit core_agent30.

[0066] Such as Figure 3As shown, from the expected result array golden_mem30, the first detection module rd_checker30 of the simulation calculation unit core_agent30 can obtain the expected processing result corresponding to the to-be-processed address of the second simulation read request as the expected processing result of the second simulation read request. Next, the first detection module rd_checker30 can determine whether the expected processing result and the simulation processing result of the second simulation read request are consistent. If the expected processing result and the simulation processing result of the second simulation read request are consistent, the first detection module rd_checker30 can output the first verification result indicating successful verification. If the expected processing result and the simulation processing result of the second simulation read request are inconsistent, the first detection module rd_checker30 can output the second verification result indicating failed verification. It can be understood that the processing mechanism of the simulation cache unit cache30 is to be verified. Errors may occur when generating the data acquisition request. Or errors may also occur when establishing the mapping between the returned data and the simulation cache address in the first simulation cache, resulting in failed verification. It can also be understood that the reasons for failed verification are not limited to this, and the present disclosure does not limit this. Through the embodiments of the present disclosure, the simulation cache unit can be verified in the case where the address of the simulation request misses the data in the simulation cache unit, the mechanism of the cache unit can be effectively and comprehensively verified, the verification efficiency can be further improved, and the accuracy of the cache unit after successful verification can be further improved.

[0067] It can be understood that the above description has taken the simulation read request as an example to illustrate the present disclosure, and the following will take the simulation write request as an example for illustration.

[0068] In some embodiments, the simulation request is a simulation write request. Using the simulation calculation unit to provide the simulation request to the simulation cache unit, obtaining the simulation processing result of the simulation request includes: using the simulation calculation unit to provide the simulation write request to the simulation cache unit. As Figure 3 shown, the to-be-processed address of the simulation write request can be generated according to the above first preset algorithm based on the above symbolic constants. The to-be-processed data of the simulation write request can also be generated according to one of the multiple symbolic constants. The simulation calculation unit core_agent30 can provide the simulation write request to the simulation cache unit cache30. It can be understood that the to-be-processed address of the first simulation read request, the to-be-processed address of the second simulation read request, and the to-be-processed address of the simulation write request can be generated based on different symbolic constants respectively. The to-be-processed address and the to-be-processed data of the simulation write request are generated according to the same symbolic constant.

[0069] In some embodiments, providing a simulation request to a simulation cache unit by a simulation computing unit to obtain a simulation processing result of the simulation request includes: providing a data write request to a simulation storage unit by the simulation cache unit. The data write request includes a simulation cache address for a simulation write request and simulation cache data for the simulation write request. The simulation cache address for the simulation write request is obtained according to the address to be processed of the simulation write request, and the simulation cache data for the simulation write request is obtained according to the data to be processed of the simulation write request. For example, the address to be processed of the simulation write request can be used as the simulation cache address for the simulation write request and stored in the first simulation cache module tag_ram30. The data to be processed of the simulation write request is used as the simulation cache data for the simulation write request and stored in the second simulation cache module data_ram30. Based on the simulation cache address and simulation cache data for the simulation write request, a data write request can be generated. The data write request is provided to the simulation storage unit mem_agent30.

[0070] In some embodiments, providing a simulation request to a simulation cache unit by a simulation computing unit to obtain a simulation processing result of the simulation request includes: in response to determining that the simulation storage unit has processed the data write request, determining the data at the address to be processed of the simulation storage unit as the simulation processing result of the simulation write request. For example, the simulation storage unit mem_agent30 can store the simulation cache data for the simulation write request at the position indicated by the simulation cache address for the simulation write request. Next, the data at the address to be processed in the simulation storage unit mem_agent30 is used as the simulation processing result of the simulation write request.

[0071] Such as Figure 3As shown, from the expected result array golden_mem30, the second detection module wr_checker30 of the simulation storage unit mem_agent30 can obtain the expected processing result corresponding to the to-be-processed address of the simulation write request as the expected processing result of the simulation write request. Next, the second detection module wr_checker30 can determine whether the expected processing result of the simulation write request is consistent with the simulation processing result. If the expected processing result of the simulation write request is consistent with the simulation processing result, the second detection module wr_checker30 can output the first verification result indicating successful verification. If the expected processing result of the second simulation read request is inconsistent with the simulation processing result, the second detection module wr_checker30 can output the second verification result indicating verification failure. It can be understood that the processing mechanism of the simulation cache unit cache30 is to be verified. Errors may occur when generating data write requests. It can also be understood that the reasons for verification failure are not limited to this, and the present disclosure does not limit this. Through the embodiments of the present disclosure, when the simulation computing unit sends a simulation write request, the simulation cache unit can be verified, and the mechanism of the cache unit can be verified more effectively and comprehensively, which can further improve the verification efficiency and further improve the accuracy of the cache unit after verification passes.

[0072] It can be understood that the method of the present disclosure has been described above, and the device of the present disclosure will be described below.

[0073] Figure 4 is a block diagram of a cache verification device according to an embodiment of the present disclosure.

[0074] As Figure 4 shown, the device 400 may include a first generation module 410, a second generation module 420, a providing module 430, and a determining module 440.

[0075] The first generation module 410 is configured to generate a to-be-processed address by using a simulation computing unit according to at least one of the symbolic constants.

[0076] The second generation module 420 is configured to generate a simulation request by using a simulation computing unit according to the to-be-processed address.

[0077] The providing module 430 is configured to provide the simulation request to the simulation cache unit by using a simulation computing unit to obtain a simulation processing result of the simulation request.

[0078] The determining module 440 is configured to determine a verification result of the simulation cache unit according to the simulation processing result and the expected processing result of the simulation request.

[0079] In some embodiments, the analog cache unit includes a first analog cache module and a second analog cache module. The first analog cache module is used to store analog cache addresses, and the second analog cache module is used to store analog cache data corresponding to the analog cache addresses. Among them, the analog cache data is determined according to at least one of the following data: the data to be processed in the analog request; the return data provided by the analog storage unit.

[0080] In some embodiments, the analog request is an analog read request. The providing module includes: a first providing sub-module, configured to use the analog computing unit to provide the analog read request to the analog cache unit; a first determining sub-module, configured to, in response to the analog cache unit generating a hit signal for the analog read request, determine the analog cache data corresponding to the analog cache address that hits the to-be-processed address in the second analog cache module as the analog processing result of the analog read request. The hit signal is generated when the to-be-processed address of the analog read request hits at least one of the analog cache addresses in the first analog cache module.

[0081] In some embodiments, the analog request is an analog read request. The providing module includes: a second providing sub-module, configured to use the analog computing unit to provide the analog read request to the analog cache unit; a third providing sub-module, configured to, in response to the analog cache unit generating a miss signal for the analog read request, use the analog cache unit to provide a data acquisition request to the analog storage unit. The data acquisition request includes the analog cache address for the analog read request, and the analog cache address for the analog read request is obtained according to the to-be-processed address of the analog read request; a second determining sub-module, configured to determine the return data corresponding to the data acquisition request as the analog processing result of the analog read request. For example, the miss signal is generated when the to-be-processed address of the analog read request does not hit any of the analog cache addresses in the first analog cache module. Or, for another example, the miss signal is generated when there is no analog cache address in the first analog cache module.

[0082] In some embodiments, the analog request is an analog write request. The providing module includes: a fourth providing sub-module, configured to use the analog computing unit to provide the analog write request to the analog cache unit; a fifth providing sub-module, configured to use the analog cache unit to provide a data write request to the analog storage unit. The data write request includes the analog cache address for the analog write request and the analog cache data for the analog write request. The analog cache address for the analog write request is obtained according to the to-be-processed address of the analog write request, and the analog cache data for the analog write request is obtained according to the to-be-processed data of the analog write request; a third determining sub-module, configured to, in response to determining that the analog storage unit has processed the data write request, determine the data at the to-be-processed address of the analog storage unit as the analog processing result of the analog write request.

[0083] In some embodiments, the expected processing result of the simulation request is stored in an expected result array, and the expected result array includes the address to be processed and the expected processing result corresponding to the address to be processed. The determination module includes: an acquisition sub-module, configured to acquire the expected processing result of the simulation request from the expected result array. A fourth determination sub-module, configured to determine the verification result of the simulation cache unit according to the simulation processing result of the simulation request and the expected processing result of the simulation request.

[0084] In some embodiments, the expected processing result of the simulation request is also stored in at least one of the second simulation cache module and the simulation storage unit.

[0085] In some embodiments, the simulation cache address in the first simulation cache module is stored at the first cache symbol address of the first simulation cache module, and the address to be processed includes a first address symbol to be processed and a second address symbol to be processed. The providing module includes: a fifth determination sub-module, configured to determine a target simulation cache address according to the first address symbol to be processed. The target simulation cache address is stored at the first cache symbol address hit by the first address symbol to be processed. A sixth determination sub-module, configured to determine whether the second address symbol to be processed hits the target simulation cache address.

[0086] In some other embodiments, the providing module further includes: a first writing sub-module, configured to write the second address symbol to be processed into the first cache symbol address hit by the first address symbol to be processed. A second writing sub-module, configured to write the data to be processed of the simulation request into the position indicated by the second address symbol to be processed in the second simulation cache module.

[0087] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision, and disclosure of the user's personal information involved all comply with the provisions of relevant laws and regulations and do not violate public order and good customs.

[0088] According to the embodiments of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0089] Figure 5 FIG. shows a schematic block diagram of an exemplary electronic device 500 that can be used to implement the embodiments of the present disclosure. The electronic device is intended to represent various forms of digital computers, such as, for example, a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, for example, a personal digital processor, a cellular phone, a smart phone, a wearable device, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0090] As shown Figure 5 in FIG. 500, the device 500 includes a computing unit 501, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 into a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the device 500 can also be stored. The computing unit 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0091] Multiple components in the device 500 are connected to the I / O interface 505, including: an input unit 506, such as a keyboard, a mouse, etc.; an output unit 507, such as various types of displays, speakers, etc.; a storage unit 508, such as a magnetic disk, an optical disk, etc.; and a communication unit 509, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 509 allows the device 500 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0092] The computing unit 501 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 501 include but are not limited to a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 501 executes the various methods and processes described above, such as the cache verification method. For example, in some embodiments, the cache verification method can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as the storage unit 508. In some embodiments, part or all of the computer program can be loaded and / or installed onto the device 500 via the ROM 502 and / or the communication unit 509. When the computer program is loaded into the RAM 503 and executed by the computing unit 501, one or more steps of the cache verification method described above can be executed. Alternatively, in other embodiments, the computing unit 501 can be configured to execute the cache verification method in any other appropriate way (e.g., by means of firmware).

[0093] The various embodiments of the systems and techniques described above in this document can be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard parts (ASSPs), system on chip (SOC) systems, complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be a special-purpose or general-purpose programmable processor that receives data and instructions from a storage system, at least one input device, and at least one output device, and transmits the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0094] The program code for implementing the methods of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the program codes are executed by the processor or controller, the functions / operations specified in the flowchart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0095] In the context of this disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory (EPROM) or flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0096] To provide for interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a cathode ray tube (CRT) monitor or a liquid crystal display (LCD)) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can also be used to provide for interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, speech input, or tactile input).

[0097] The systems and techniques described herein can be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of a communication network include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0098] A computer system may include a client and a server. The client and the server are generally far away from each other and usually interact via a communication network. The relationship between the client and the server is generated by computer programs running on the respective computers and having a client-server relationship with each other.

[0099] It should be understood that various forms of the processes shown above can be used, steps can be reordered, added, or deleted. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and no limitations are imposed herein.

[0100] The above specific embodiments do not constitute a limitation on the protection scope of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the protection scope of this disclosure.

Claims

1. A cache verification method, comprising: generating an address to be processed using an analog computing unit according to one of at least one symbolic constant; generating a simulation request using the simulation calculation unit according to the address to be processed; Using the simulation calculation unit to provide the simulation request to a simulation cache unit to obtain a simulation processing result of the simulation request; A verification result of the simulation cache unit is determined according to the simulation processing result and the expected processing result of the simulation request.

2. The method according to claim 1, wherein: The simulation cache unit includes a first simulation cache module and a second simulation cache module, the first simulation cache module is used to store a simulation cache address, and the second simulation cache module is used to store simulation cache data corresponding to the simulation cache address, wherein the simulation cache data is determined according to at least one of the following data: The data to be processed in the simulation request; Simulates the return data provided by the storage unit.

3. The method according to claim 2, wherein: The simulated request is a simulated read request, The step of providing the simulation request to the simulation cache unit by using the simulation calculation unit to obtain the simulation processing result of the simulation request includes: Providing the simulated read request to the simulated cache unit using the simulated computing unit; In response to the simulation cache unit generating a hit signal for the simulated read request, the simulated cache data in the second simulation cache module corresponding to the simulated cache address that hits the pending address is determined as the simulated processing result of the simulated read request, wherein the hit signal is generated when the pending address of the simulated read request hits one of at least one simulated cache addresses in the first simulation cache module.

4. The method according to claim 2, wherein: The simulated request is a simulated read request, The step of providing the simulation request to the simulation cache unit by using the simulation calculation unit to obtain the simulation processing result of the simulation request includes: Providing the simulated read request to the simulated cache unit using the simulated computing unit; In response to the simulated cache unit generating a miss signal for the simulated read request, using the simulated cache unit to provide a data acquisition request to the simulated storage unit, wherein the data acquisition request includes a simulated cache address for the simulated read request, and the simulated cache address for the simulated read request is obtained according to a pending address of the simulated read request; Determine the returned data corresponding to the data acquisition request as the simulation processing result of the simulation read request, The miss signal is generated when the pending address of the simulated read request misses any simulated cache address in the first simulated cache module, or the miss signal is generated when the simulated cache address does not exist in the first simulated cache module.

5. The method according to claim 2, wherein: The simulated request is a simulated write request, The step of providing the simulation request to the simulation cache unit by using the simulation calculation unit to obtain the simulation processing result of the simulation request includes: Providing the simulated write request to the simulated cache unit using the simulated computing unit; Providing a data write request to the simulated storage unit by using the simulated cache unit, wherein the data write request includes a simulated cache address for the simulated write request and simulated cache data for the simulated write request, the simulated cache address for the simulated write request is obtained according to a pending address of the simulated write request, and the simulated cache data for the simulated write request is obtained according to the pending data of the simulated write request; In response to determining that the analog storage unit has processed the data write request, the data at the to-be-processed address of the analog storage unit is determined as the analog processing result of the analog write request.

6. The method according to claim 2, wherein: The expected processing result of the simulation request is stored in an expected result array, and the expected result array includes the address to be processed and the expected processing result corresponding to the address to be processed; Determining the verification result of the simulation cache unit according to the simulation processing result and the expected processing result of the simulation request includes: Obtain the expected processing result of the simulation request from the expected result array; The verification result of the simulation cache unit is determined according to the simulation processing result of the simulation request and the expected processing result of the simulation request.

7. The method according to claim 6, wherein: The expected processing result of the simulation request is also stored in at least one of the second simulation cache module and the simulation storage unit.

8. The method according to claim 2, wherein: The simulated cache address in the first simulated cache module is stored in the first cache symbol address of the first simulated cache module, and the to-be-processed address includes a first to-be-processed symbol address and a second to-be-processed symbol address. The step of providing the simulation request to the simulation cache unit by using the simulation calculation unit to obtain the simulation processing result of the simulation request includes: Determine a target simulation cache address according to the first to-be-processed symbol address, wherein the target simulation cache address is stored at the first cache symbol address hit by the first to-be-processed symbol address; Determine whether the second to-be-processed symbol address hits the target simulation cache address.

9. A cache verification device, comprising: A first generating module, configured to generate an address to be processed by using an analog computing unit according to one of at least one symbolic constant; A second generating module, configured to generate a simulation request using the simulation calculation unit according to the address to be processed; A providing module, used to provide the simulation request to a simulation cache unit by using the simulation calculation unit, and obtain a simulation processing result of the simulation request; A determination module is used to determine the verification result of the simulation cache unit according to the simulation processing result and the expected processing result of the simulation request.

10. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 8.

11. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 8.

12. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 8.

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