Wiring Method, Device, Storage Medium and Electronic Device for 2.5D Stacked Chips

Abstract

The present application discloses a wiring method, device, storage medium and electronic device for a 2.5D stacked chip. Among them, the wiring method for the 2.5D stacked chip includes: obtaining the minimum enclosing rectangle of each interconnect network on the chip; constructing an R-Tree data structure based on the minimum enclosing rectangle; performing a merging process on the nodes of the R-Tree data structure to form a wiring group to be routed; dividing the area to which the wiring group belongs into a number of regular grids, and counting the number of minimum enclosing rectangles covered on each regular grid to form a resource demand matrix; determining the wiring order of each interconnect network in the wiring group based on the resource demand matrix; and sequentially routing each interconnect network in the wiring group according to the wiring order. The present application can improve the wiring efficiency of the 2.5D stacked chip.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit technology, and particularly to a wiring method, device, storage medium and electronic device for 2.5D stacked chips. Background Art

[0002] As the integrated circuit process technology evolves towards smaller nodes, 2.5D packaging technology, as an important means to improve system performance, reduce power consumption and increase integration density, has been widely used in the fields of high-performance computing, artificial intelligence, server chips, etc. 2.5D stacked chips usually integrate multiple die on the same interposer (such as a silicon interposer) to achieve high-speed interconnection of different functional modules.

[0003] In 2.5D stacked chips, the interconnection network between die needs to be routed on the interposer. Due to the physical concentration and interconnection density of communication between die, the wiring resource requirements in some areas are significantly higher than those in other areas, thus forming a local congestion phenomenon.

[0004] Currently, two strategies of global routing or detailed routing are usually adopted. However, whether it is the global routing or detailed routing strategy, generally trial routing is used, and it is easy to occur that the previously routed interconnection network occupies the key wiring resources, and the later routed interconnection network needs to be repeatedly torn up and re-routed due to insufficient wiring resources. The randomness of tearing up and re-routing leads to low wiring efficiency. Summary of the Invention

[0005] The embodiments of the present application provide a wiring method, device, storage medium and electronic device for 2.5D stacked chips, which can improve the wiring efficiency of 2.5D stacked chips.

[0006] In a first aspect, the embodiments of the present application provide a wiring method for 2.5D stacked chips, including:

[0007] Obtain the Minimum Bounding Rectangle (MBR) of each interconnection network on the chip;

[0008] Construct an R-Tree data structure based on the minimum bounding rectangle;

[0009] Perform a merging process on the nodes of the R-Tree data structure to form a group of networks to be routed;

[0010] Divide the area where the group of networks to be routed is located into several regular grids, and count the number of minimum bounding rectangles covered on each regular grid to form a resource demand matrix;

[0011] Determine the routing order of each interconnection network in the group of networks to be routed based on the resource demand matrix;

[0012] Route each of the interconnected networks in the to-be-routed group in accordance with the said routing sequence.

[0013] In the routing method for a 2.5D stacked chip provided in an embodiment of the present application, the determining the routing sequence of each interconnected network in the to-be-routed group based on the resource demand matrix includes:

[0014] Perform gradient analysis on the resource demand matrix to obtain a critical area;

[0015] Move the interconnected networks in the critical area from the to-be-routed group to a routing sequence list;

[0016] Update the resource demand matrix and return to execute the step of performing gradient analysis on the resource demand matrix to obtain a critical area until all the interconnected networks in the to-be-routed group are moved to the routing sequence list, so as to obtain the routing sequence of each interconnected network in the to-be-routed group.

[0017] In the routing method for a 2.5D stacked chip provided in an embodiment of the present application, the performing gradient analysis on the resource demand matrix to obtain a critical area includes:

[0018] Use a Sobel operator to calculate a first gradient of the resource demand matrix in the horizontal direction and a second gradient in the vertical direction respectively;

[0019] Determine the critical area based on the first gradient and the second gradient.

[0020] In the routing method for a 2.5D stacked chip provided in an embodiment of the present application, the determining the critical area based on the first gradient and the second gradient includes:

[0021] Determine a candidate area where both the first gradient and the second gradient are zero, and identify the edge points of the candidate area;

[0022] Obtain the resource demand value of the edge points and the resource demand values of their adjacent non-zero gradient points;

[0023] Compare the resource demand value of the edge points with the resource demand values of the adjacent non-zero gradient points, and determine the critical area according to the comparison result.

[0024] In the routing method for a 2.5D stacked chip provided in an embodiment of the present application, the merging and processing the nodes of the R-Tree data structure to form a to-be-routed group includes:

[0025] Obtain a first network direction of each leaf node in the R-Tree data structure;

[0026] Perform a merging process on the leaf nodes of each minimum non-leaf node in the R-Tree data structure in sequence based on the first network direction to form a group of nets to be routed.

[0027] In the routing method for a 2.5D stacked chip provided by an embodiment of the present application, performing a merging process on the leaf nodes of each minimum non-leaf node in the R-Tree data structure in sequence based on the first network direction to form a group of nets to be routed includes:

[0028] Randomly determine a target non-leaf node from multiple minimum non-leaf nodes in the R-Tree data structure;

[0029] Judge whether multiple leaf nodes in the target non-leaf node meet the merging condition according to the first network direction;

[0030] If all leaf nodes in the target non-leaf node meet the merging condition, delete the target non-leaf node and merge all leaf nodes in the target non-leaf node into a new leaf node;

[0031] If some leaf nodes in the target non-leaf node meet the merging condition, merge the part of the leaf nodes that meet the merging condition into a new leaf node, mark the target non-leaf node as processed, and retain the unmerged leaf nodes;

[0032] Return to execute the step of randomly determining a target non-leaf node from multiple minimum non-leaf nodes in the R-Tree data structure until all minimum non-leaf nodes are processed, generate a new R-Tree data structure, and use each leaf node in the new R-Tree data structure as a group of nets to be routed.

[0033] In the routing method for a 2.5D stacked chip provided by an embodiment of the present application, obtaining the first network direction of each leaf node in the R-Tree data structure includes:

[0034] Obtain the second network direction of the interconnected networks of each leaf node in the R-Tree data structure;

[0035] Determine the first network direction of each leaf node according to the second network direction.

[0036] In a second aspect, an embodiment of the present application provides a routing device for a 2.5D stacked chip, including:

[0037] A rectangle obtaining unit, configured to obtain the minimum enclosing rectangle of each interconnected network on the chip;

[0038] A structure constructing unit, configured to construct an R-Tree data structure based on the minimum enclosing rectangle;

[0039] A node merging unit for merging the nodes of the R-Tree data structure to form a wiring group to be routed;

[0040] A matrix forming unit for dividing the area to which the wiring group to be routed belongs into a plurality of regular grids, and counting the number of minimum bounding rectangles covered on each regular grid to form a resource requirement matrix;

[0041] An order determination unit for determining the routing order of each interconnected network in the wiring group to be routed based on the resource requirement matrix;

[0042] A network routing unit for routing each of the interconnected networks in the wiring group to be routed in sequence according to the routing order.

[0043] In a third aspect, the present application provides a storage medium storing a plurality of instructions adapted to be loaded by a processor to execute the wiring method of the 2.5D stacked chip described in any one of the above.

[0044] In a fourth aspect, the present application provides an electronic device including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the computer program, the wiring method of the 2.5D stacked chip described in any one of the above is implemented.

[0045] In summary, the wiring method of the 2.5D stacked chip provided in the embodiments of the present application includes: obtaining the minimum bounding rectangles of each interconnected network on the chip; constructing an R-Tree data structure based on the minimum bounding rectangles; merging the nodes of the R-Tree data structure to form a wiring group to be routed; dividing the area to which the wiring group to be routed belongs into a plurality of regular grids, and counting the number of minimum bounding rectangles covered on each regular grid to form a resource requirement matrix; determining the routing order of each interconnected network in the wiring group to be routed based on the resource requirement matrix; and routing each of the interconnected networks in the wiring group to be routed in sequence according to the routing order. The solution of the embodiments of the present application determines the routing order of each interconnected network in the wiring group to be routed based on the resource requirement matrix, ensuring that when there is a routing resource competition among multiple interconnected networks in the wiring group to be routed, the interconnected network with a greater congestion risk is preferentially processed, avoiding the problems of local resource preemption and repeated tearing and re-routing caused by unreasonable routing order in the traditional method, and thus improving the wiring efficiency of the 2.5D stacked chip. Description of the Drawings

[0046] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0047] Figure 1 It is a schematic diagram of the application scenario of the wiring method for 2.5D stacked chips provided by the embodiments of the present application.

[0048] Figure 2 It is a schematic flowchart of the wiring method for 2.5D stacked chips provided by the embodiments of the present application.

[0049] Figure 3 It is a schematic structural diagram of the wiring device for 2.5D stacked chips provided by the embodiments of the present application.

[0050] Figure 4 It is a schematic structural diagram of the electronic device provided by the embodiments of the present application. Detailed implementation manners

[0051] Here, the exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are only examples of the devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0052] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without further limitations, the element defined by the statement "including one..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined according to their explanations in the specific embodiments or further in combination with the context of the specific embodiments.

[0053] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0054] In the following description, suffixes such as "module", "component", or "unit" used to denote elements are only for the convenience of describing the present application and have no specific meaning in themselves. Therefore, "module", "component", or "unit" can be used interchangeably.

[0055] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present application. In addition, terms such as "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance.

[0056] In a 2.5D stacked chip, the interconnection network between dies needs to be routed on the same interposer (such as a silicon interposer). Due to the physical concentration and interconnection density of communication between dies, the wiring resource requirements in some areas are significantly higher than those in other areas, resulting in local congestion.

[0057] Currently, two strategies, global routing or detailed routing, are usually adopted. However, whether it is the global routing or detailed routing strategy, trial routing is generally used, and it is easy to occur that the interconnection network routed first occupies the key wiring resources, and the interconnection network routed later needs to be repeatedly torn up and re-routed due to insufficient wiring resources, resulting in low wiring efficiency.

[0058] Based on this, the embodiments of the present application provide a wiring method, device, storage medium, and electronic device for a 2.5D stacked chip. Specifically, the wiring device for the 2.5D stacked chip can be integrated in an electronic device, which can be a server or a terminal device, etc.; among them, the terminal can include a mobile phone, a wearable intelligent device, a tablet computer, a laptop computer, and a personal computer (PC), etc.; the server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0059] For example, as Figure 1As shown, the electronic device can first obtain the minimum bounding rectangles of each interconnect network on the chip; then construct an R-Tree data structure based on the minimum bounding rectangles; then perform a merging process on the nodes of the R-Tree data structure to form a group of nets to be routed; then divide the area where the group of nets to be routed belongs into several regular grids, and count the number of minimum bounding rectangles covered on each regular grid to form a resource demand matrix; finally, determine the routing order of each interconnect network in the group of nets to be routed based on the resource demand matrix; and route each interconnect network in the group of nets to be routed in sequence according to the routing order.

[0060] By determining the routing order of each interconnect network in the group of nets to be routed based on the resource demand matrix, the electronic device ensures that when there is a routing resource competition among multiple interconnect networks in the group of nets to be routed, the interconnect networks with a greater congestion risk are processed preferentially, avoiding the problems of local resource preemption and repeated tearing and re-routing caused by unreasonable routing order in the traditional method, and thus improving the routing efficiency of the 2.5D stacked chip.

[0061] The following will specifically describe the technical solutions shown in this application through specific embodiments. It should be noted that the description order of the following embodiments does not limit the priority order of the embodiments.

[0062] Please refer to Figure 2 , Figure 2 which is a schematic flowchart of the routing method for a 2.5D stacked chip provided by an embodiment of this application. The specific process of the routing method for the 2.5D stacked chip can be as follows:

[0063] 101. Obtain the minimum bounding rectangles of each interconnect network on the chip.

[0064] For each interconnect network on the chip, a minimum bounding rectangle can be calculated through the coordinates of its start point and end point. The minimum bounding rectangle can cover the routing path of the interconnect network and is the smallest rectangle that can cover the routing path of the interconnect network. That is, the minimum bounding rectangle can represent the resource area required by the interconnect network during routing.

[0065] For example, for each interconnect network, assuming the start point coordinates are (x1, y1) and the end point coordinates are (x2, y2), the four sides of the minimum bounding rectangle can be obtained according to min(x1, x2), max(x1, x2), min(y1, y2), and max(y1, y2). Specifically, the coordinates of the four vertices of the minimum bounding rectangle are as follows:

[0066] The coordinates of the bottom-left corner are: (min(x1, x2), min(y1, y2));

[0067] The coordinates of the top - left corner are: (min(x1, x2)), max(y1, y2));

[0068] The coordinates of the top - right corner are: (max(x1, x2), max(y1, y2));

[0069] The coordinates of the bottom - right corner are: (max(x1, x2), min(y1, y2)).

[0070] Based on the coordinates of the above four vertices, the four sides of the minimum bounding rectangle can be obtained, and thus the minimum bounding rectangle can be obtained.

[0071] 102. Construct an R - Tree data structure based on the minimum bounding rectangle.

[0072] Specifically, leaf nodes can be constructed according to the spatial position, overlap, and inclusion relationship of the minimum bounding rectangles. Each leaf node can contain one or more minimum bounding rectangles.

[0073] Among them, the spatial position refers to the two - dimensional coordinate region determined by the minimum bounding rectangle of the interconnection network in the chip plane coordinate system, which is used to represent the wiring coverage range of the interconnection network on the chip. Overlap refers to the intersection relationship between the regions covered by two or more minimum bounding rectangles on the chip plane, which is used to measure the sharing degree of wiring resources by different interconnection networks. The inclusion relationship means that one minimum bounding rectangle completely encloses another minimum bounding rectangle geometrically.

[0074] Specifically, if two minimum bounding rectangles do not intersect: it means that the spatial positions of the interconnection networks where the two minimum bounding rectangles are located are separated from each other, and the two minimum bounding rectangles can be added to the upper layer as two leaf nodes respectively; if two minimum bounding rectangles have an intersection (overlap): it indicates that wiring resource conflicts may occur, and they should be grouped into the same leaf node as much as possible; if one minimum bounding rectangle completely contains another minimum bounding rectangle: it means that there is a clear inclusion relationship between the two minimum bounding rectangles, and the two minimum bounding rectangles should be grouped into the same leaf node.

[0075] For example, starting from the minimum bounding rectangle, leaf nodes can be constructed according to the following logic: several minimum bounding rectangles with adjacent spatial positions (spacing less than the threshold) or having an overlap / inclusion relationship are merged into one leaf node.

[0076] During the construction of leaf nodes, when the number of minimum bounding rectangles in a certain leaf node exceeds the first preset capacity, a splitting strategy is triggered. The splitting operation redistributes all the minimum bounding rectangles in the original leaf node to two new leaf nodes. When the original leaf node splits into two new leaf nodes, a minimum non-leaf node is created as the parent node of the two new leaf nodes to mount these two new leaf nodes.

[0077] It can be understood that the bounding rectangle of each leaf node should be the minimum common covering area of all the minimum bounding rectangles it contains.

[0078] Similarly, when the number of leaf nodes in a certain minimum non-leaf node exceeds the second preset capacity, a splitting strategy is triggered. The splitting operation redistributes all the leaf nodes in the original minimum non-leaf node to two new minimum non-leaf nodes. When the original minimum non-leaf node splits into two new minimum non-leaf nodes, a higher-level non-leaf node is created as the parent node of the two new minimum non-leaf nodes to mount these two new minimum non-leaf nodes.

[0079] The construction process of the R-Tree data structure is a recursive upward process starting from the minimum bounding rectangle until the root node.

[0080] It can be understood that the minimum non-leaf node is the parent node that directly mounts the leaf nodes.

[0081] 103. Merge the nodes of the R-Tree data structure to form a group of nets to be routed.

[0082] Specifically, the first network direction of each leaf node in the R-Tree data structure can be obtained; based on the first network direction, the leaf nodes of each minimum non-leaf node in the R-Tree data structure are merged in sequence to form a group of nets to be routed.

[0083] Specifically, a target non-leaf node is randomly determined from multiple minimum non-leaf nodes in the R-Tree data structure; it is judged whether the multiple leaf nodes in the target non-leaf node meet the merging conditions according to the first network direction.

[0084] If all leaf nodes in the target non-leaf node satisfy the merging condition, then delete the target non-leaf node and merge all leaf nodes in the target non-leaf node into a new leaf node. If some leaf nodes in the target non-leaf node satisfy the merging condition, then merge the part of leaf nodes that satisfy the merging condition into a new leaf node, mark the target non-leaf node as processed, and retain the unmerged leaf nodes. After that, the step of randomly determining a target non-leaf node from multiple minimum non-leaf nodes in the R-Tree data structure can be returned for execution until all minimum non-leaf nodes are processed, generating a new R-Tree data structure, and using each leaf node in the new R-Tree data structure as a routing group to be routed.

[0085] It should be noted that each time a target non-leaf node is randomly determined from multiple minimum non-leaf nodes in the R-Tree data structure, it is randomly determined from the currently unprocessed minimum non-leaf nodes. The minimum non-leaf nodes marked as processed no longer participate in the iterative process. It can be understood that the termination condition of the iteration is that all minimum non-leaf nodes have been processed, and at this time all leaf nodes do not satisfy the merging condition.

[0086] Among them, the merging condition means that the first network directions are the same and the proximity condition is satisfied. The proximity condition means that the gap between the bounding rectangles of two leaf nodes is less than or equal to a gap threshold (such as ≤2μm), and the overlapping ratio of the gap region and the region where the minimum enclosing rectangle of other leaf nodes is located is less than or equal to an overlapping threshold.

[0087] The gap threshold can prevent missing the merging opportunity due to extremely small gaps and enhance the grouping coherence; at the same time, it can avoid unnecessary group expansion caused by merging due to too large gaps and improve the local routing consistency. The overlapping threshold can ensure that the new leaf nodes generated after merging will not "occupy" too much third-party network resources, and at the same time limit the excessive coverage of the gap by the minimum enclosing rectangles of other leaf nodes to avoid causing new high congestion points after merging.

[0088] For each interconnect network, a vector can be formed by its start point and end point. By calculating the cosine value of the vector and a reference direction (horizontal, vertical or diagonal), the direction of each interconnect network can be quantified into one of the three reference directions (horizontal, vertical or diagonal). Specifically, the cosine values of the vector and the three reference directions can be calculated respectively, and then the reference direction with the largest obtained cosine value can be used as the third direction of the interconnect network.

[0089] For each leaf node, the second network directions of the interconnect networks included in it can be counted. If the proportion of the number of interconnect networks with a certain second network direction f1 in the leaf node exceeds a threshold t, then the second network direction f1 can be used as the first network direction of the leaf node.

[0090] That is, the step of "obtaining the direction of each leaf node in the R-Tree data structure" can be: obtaining the second network direction of the interconnected network of each leaf node in the R-Tree data structure; determining the first direction of each leaf node according to the third direction; and determining the first network direction of each non-leaf node according to the second network direction.

[0091] 104. Divide the area where the to-be-routed group belongs into several regular grids, and count the number of minimum bounding rectangles covered on each regular grid to form a resource requirement matrix.

[0092] For each to-be-routed group, the area where the to-be-routed group belongs can be divided into several regular grids according to the physical routing resource (Track) information occupied by the interconnected network in the area where the to-be-routed group belongs.

[0093] Specifically, the y-coordinates (vertical coordinates) of all horizontal Tracks and the x-coordinates (horizontal coordinates) of all vertical Tracks can be extracted by using the Track list defined in the physical design tool or design rule library; then, taking these Track positions as grid lines, the area where the to-be-routed group belongs is divided into several "Track units" (regular grids), and each "Track unit" exactly corresponds to the rectangular area between one horizontal Track and one vertical Track.

[0094] Finally, map the minimum bounding rectangles of each interconnected network to the regular grids, and count the number of minimum bounding rectangles covered on each regular grid to form the resource requirement matrix.

[0095] It can be understood that the value of each regular grid in the resource requirement matrix represents the wiring resource requirement value occupied at the position of this regular grid. As the minimum bounding rectangles of multiple interconnected networks overlap, the value of the corresponding regular grid will increase accordingly, thus reflecting the tension degree of the wiring resources in the area corresponding to this regular grid.

[0096] 105. Determine the routing order of each interconnected network in the to-be-routed group based on the resource requirement matrix.

[0097] First, gradient analysis can be performed on the resource requirement matrix to obtain the critical area; then, the interconnected networks in the critical area are moved from the to-be-routed group to the routing order list; after that, the resource requirement matrix is updated, and the step of "performing gradient analysis on the resource requirement matrix to obtain the critical area" is returned until all the interconnected networks in the to-be-routed group are moved to the routing order list, so as to obtain the routing order of each interconnected network in the to-be-routed group.

[0098] Among them, the key area refers to the area with the highest current congestion risk in the area to which the wiring group to be routed belongs. The order of moving to the wiring sequence list is the wiring order of each interconnection network in the wiring group to be routed.

[0099] In some embodiments, the Sobel operator can be used to calculate the first gradient in the horizontal (x) direction and the second gradient in the vertical (y) direction of the resource demand matrix respectively; then the key area is determined based on the first gradient and the second gradient.

[0100] Specifically, the horizontal kernel Sobel_x of the Sobel operator can be applied to perform a convolution operation on the resource demand matrix in the horizontal direction to obtain the first gradient. The vertical kernel Sobel_y of the Sobel operator is applied to perform a convolution operation on the resource demand matrix in the vertical direction to obtain the second gradient.

[0101] It can be understood that in the area where both the first gradient and the second gradient are zero, it indicates that the resource demand change in this area is small, and it may form a maximum value area, a minimum value area, or a saddle point area. And the key area refers to the area with the highest current congestion risk (i.e., the maximum value area).

[0102] Therefore, in this embodiment, it is necessary to first determine the candidate areas where both the first gradient and the second gradient are zero, and then determine the maximum value areas from the candidate areas.

[0103] In some embodiments, the boundaries of the candidate areas can be traversed. For each edge point, the resource demand values of its adjacent non-zero points (which may be a group) are obtained. If the resource demand value of the edge point is greater than or equal to the resource demand values of all adjacent non-zero points, it can be determined that the candidate area is a maximum value area (key area).

[0104] That is to say, the step of "determining the key area based on the first gradient and the second gradient" can be: determining the candidate areas where the first gradient and the second gradient are both zero, and identifying the edge points of the candidate areas; obtaining the resource demand values of the edge points in the resource demand matrix and the resource demand values of their adjacent non-zero gradient points; comparing the resource demand value of the edge point with the resource demand values of the adjacent non-zero gradient points, and determining the key area according to the comparison result.

[0105] It can be understood that since the routing of the interconnection network for determining the routing order will occupy certain resources, the subsequent impact on other interconnection networks needs to be considered. Therefore, after moving a certain interconnection network in the wiring group to the wiring sequence list, the resource demand values of the area to which the wiring group belongs can be updated (that is, the resource demand matrix is updated), which helps to re-evaluate the conflict risk of other interconnection networks subsequently. Then, gradient analysis can be performed on the resource demand matrix again to obtain the key area, so as to re-evaluate the routing priorities of the remaining interconnection networks.

[0106] In some embodiments, when there are more than one interconnect networks in the critical area, the interconnect network with the largest resource requirement value can be determined as the target network based on the resource requirement values of each interconnect network in the critical area, and the target network can be moved from the to-be-wired group to the wiring order list.

[0107] In some embodiments, when there are more than one interconnection networks with the largest resource demand value, an interconnection network with a longer path physical length may be used as a target network.

[0108] 106. Routing each interconnection network in the wiring group in turn according to the wiring order.

[0109] Specifically, the starting point coordinates and the end point coordinates of the target interconnect network can be obtained based on the wiring sequence; the path search algorithm is executed in the area to which it belongs to plan the wiring path; if the planned wiring path is available, the wiring path is locked and wiring is performed, and the wiring resource requirements are updated; the process is repeated until all the interconnect networks in the group to be wired are wired.

[0110] In some embodiments, after completing the path search and confirming that the routing path is available, each routing resource unit (such as grid lines, routing lanes, metal layer channels) on the routing path can be marked as occupied by the target interconnect network; if the routing path spans multiple routing layers, VIAs (through holes) are inserted at the intersections between layers to achieve cross-layer connections; network endpoint connections are created at both ends of the routing path to form a complete physical connectivity relationship; and the physical location information of the routing path is recorded in the layout for subsequent timing simulation, electrical verification, and layout convergence.

[0111] That is, after locking the routing path, the lines can be laid out sequentially on the chip layout based on the locked routing path; if the routing path contains multiple routing layers, VIA is inserted at the inter-layer transfer position of the routing path to achieve cross-layer connection; the starting point and end point of the routing path are physically connected to the corresponding logic unit to complete the layout of the interconnection network.

[0112] It is understandable that the target interconnection network is the interconnection network with the best current wiring sequence. In some embodiments, the path search algorithm may be a heuristic A* path finding algorithm, a maze routing algorithm or other path finding algorithms based on cost function optimization.

[0113] In summary, the wiring method for the 2.5D stacked chip provided by the embodiments of the present application includes: obtaining the minimum enclosing rectangle of each interconnect network on the chip; constructing an R-Tree data structure based on the minimum enclosing rectangle; performing a merging process on the nodes of the R-Tree data structure to form a wiring group to be routed; dividing the area to which the wiring group belongs into several regular grids, and counting the number of minimum enclosing rectangles covered on each regular grid to form a resource demand matrix; determining the routing order of each interconnect network in the wiring group based on the resource demand matrix; and sequentially routing each interconnect network in the wiring group according to the routing order. By introducing the R-Tree data structure, grouping in combination with the direction analysis of the interconnect network, calculating the resource demand change trend using the Sobel gradient, and preferentially determining the routing order based on the gradient maximum region, the present application realizes hierarchical, graded, and orderly control of the routing process. It can effectively avoid the problems of routing failure and re-routing caused by local resource contention, improve the routing efficiency and quality, and is particularly suitable for application scenarios with dense cross-die interconnects in 2.5D stacked chips.

[0114] To facilitate better implementation of the wiring method for the 2.5D stacked chip provided by the embodiments of the present application, the embodiments of the present application also provide a wiring device for the 2.5D stacked chip. The meanings of the terms are the same as those in the above-mentioned wiring method for the 2.5D stacked chip, and the specific implementation details can refer to the description in the method embodiments.

[0115] Please refer to Figure 3 , Figure 3 which is a schematic structural diagram of the wiring device for the 2.5D stacked chip provided by the embodiments of the present application. The wiring device for the 2.5D stacked chip may include a rectangle obtaining unit 201, a structure constructing unit 202, a node merging unit 203, a matrix forming unit 204, an order determining unit 205, and a network wiring unit 206. Among them,

[0116] The rectangle obtaining unit 201 is configured to obtain the minimum enclosing rectangle of each interconnect network on the chip;

[0117] The structure constructing unit 202 is configured to construct an R-Tree data structure based on the minimum enclosing rectangle;

[0118] The node merging unit 203 is configured to perform a merging process on the nodes of the R-Tree data structure to form a wiring group to be routed;

[0119] The matrix forming unit 204 is configured to divide the area to which the wiring group belongs into several regular grids, and count the number of minimum enclosing rectangles covered on each regular grid to form a resource demand matrix;

[0120] The order determining unit 205 is configured to determine the routing order of each interconnect network in the wiring group based on the resource demand matrix;

[0121] A network wiring unit 206 is configured to wire each interconnected network in a group to be wired in sequence according to a wiring order.

[0122] For the specific implementation manners of each of the above units, reference may be made to the embodiments of the wiring method for 2.5D stacked chips described above, which will not be elaborated herein one by one.

[0123] In summary, the wiring device for 2.5D stacked chips provided in the embodiment of the present application can obtain the minimum enclosing rectangle of each interconnected network on the chip through the rectangle acquisition unit 201; construct an R-Tree data structure based on the minimum enclosing rectangle by the structure construction unit 202; merge the nodes of the R-Tree data structure by the node merging unit 203 to form a group to be wired; divide the area to which the group to be wired belongs into a plurality of regular grids by the matrix formation unit 204, and count the number of minimum enclosing rectangles covered on each regular grid to form a resource requirement matrix; determine the wiring order of each interconnected network in the group to be wired based on the resource requirement matrix by the order determination unit 205; and wire each interconnected network in the group to be wired in sequence according to the wiring order by the network wiring unit 206. The present application realizes hierarchical, graded, and orderly regulation of the wiring process by introducing an R-Tree data structure, grouping by combining the analysis of the direction of interconnected networks, calculating the change trend of resource requirements using Sobel gradients, and preferentially determining the wiring order based on the gradient maximum region. It can effectively avoid wiring failures and re-wiring problems caused by local resource contention, improve wiring efficiency and quality, and is particularly suitable for application scenarios with dense cross-die interconnects in 2.5D stacked chips.

[0124] The embodiment of the present application further provides an electronic device, which may integrate the wiring device for 2.5D stacked chips of the embodiment of the present application, as Figure 4 shown, which shows a schematic structural diagram of the electronic device involved in the embodiment of the present application. Specifically:

[0125] The electronic device may include components such as a processor 301 with one or more processing cores and a memory 302 with one or more computer-readable storage media. Those skilled in the art can understand that Figure 4 the structure of the electronic device shown in

[0126] The processor 301 is the control center of the electronic device, connecting various parts of the entire electronic device through various interfaces and circuits. By running or executing software programs stored in the memory 302 and / or the present application, and by calling the data stored in the memory 302, it executes various functions of the electronic device and processes data, thereby monitoring the electronic device as a whole. Optionally, the processor 301 may include one or more processing cores; preferably, the processor 301 may integrate an application processor and a modem processor. Among them, the application processor mainly processes operating storage media, user interfaces, application programs, etc., and the modem processor mainly processes wireless communications. It can be understood that the above-mentioned modem processor may not be integrated into the processor 301 either.

[0127] The memory 302 can be used to store software programs and the present application. The processor 301 executes various functional applications and data processing by running the software programs and the present application stored in the memory 302. The memory 302 may mainly include a program storage area and a data storage area. Among them, the program storage area can store operating storage media, application programs required for at least one function, etc.; the data storage area can store data created according to the use of the electronic device, etc. In addition, the memory 302 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other volatile solid-state storage devices. Correspondingly, the memory 302 may also include a memory controller to provide the processor 301 with access to the memory 302.

[0128] Although not shown, the electronic device may also include a display unit, an input unit, a power supply, etc., which will not be elaborated here. Specifically in this embodiment, the processor 301 in the electronic device will load the executable files corresponding to the processes of one or more application programs into the memory 302 according to the following instructions, and the processor 301 will run the application programs stored in the memory 302 to implement various functions as follows:

[0129] Obtain the minimum bounding rectangle of each interconnect network on the chip;

[0130] Construct an R-Tree data structure based on the minimum bounding rectangle;

[0131] Perform a merging process on the nodes of the R-Tree data structure to form a group of nets to be routed;

[0132] Divide the area to which the group of nets to be routed belongs into several regular grids, and count the number of minimum bounding rectangles covered on each regular grid to form a resource requirement matrix;

[0133] Determine the routing order of each interconnect network in the group of nets to be routed based on the resource requirement matrix;

[0134] Route each interconnect network in the group to be routed in sequence according to the routing order.

[0135] Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions, or by controlling relevant hardware through instructions. The instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0136] For this reason, an embodiment of the present application provides a storage medium, which stores multiple instructions that can be loaded by a processor to execute the steps in any one of the methods provided by the embodiments of the present application. For example, the instructions can perform the following steps:

[0137] Obtain the minimum bounding rectangle of each interconnect network on the chip;

[0138] Construct an R-Tree data structure based on the minimum bounding rectangle;

[0139] Perform a merging process on the nodes of the R-Tree data structure to form a group to be routed;

[0140] Divide the area to which the group to be routed belongs into several regular grids, and count the number of minimum bounding rectangles covered on each regular grid to form a resource demand matrix;

[0141] Determine the routing order of each interconnect network in the group to be routed based on the resource demand matrix;

[0142] Route each interconnect network in the group to be routed in sequence according to the routing order.

[0143] For the specific implementation of each of the above operations, reference can be made to the previous embodiments, which will not be elaborated here.

[0144] Among them, the storage medium may include: Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk or optical disc, etc.

[0145] Since the instructions stored in the storage medium can execute the steps in any one of the methods provided by the embodiments of the present application, the beneficial effects that can be achieved by any one of the methods provided by the embodiments of the present application can be realized. For details, refer to the previous embodiments, which will not be elaborated here.

[0146] The wiring method, device, storage medium, and electronic device of the 2.5D stacked chip provided in the present application have been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A wiring method for a 2.5D stacked chip, characterized in that Including: Obtaining the minimum bounding rectangle of each interconnection network on the chip; Constructing an R-Tree data structure based on the minimum bounding rectangle; Performing a merging process on the nodes of the R-Tree data structure to form a group of nets to be routed; Dividing the area where the group of nets to be routed is located into a number of regular grids, and counting the number of minimum bounding rectangles covered on each regular grid to form a resource demand matrix; Performing gradient analysis on the resource demand matrix to obtain a critical area; Moving the interconnection networks in the critical area from the group of nets to be routed to a routing order list; Updating the resource demand matrix, and returning to execute the step of performing gradient analysis on the resource demand matrix to obtain a critical area until all the interconnection networks in the group of nets to be routed are moved to the routing order list, so as to obtain the routing order of each interconnection network in the group of nets to be routed; Routing each interconnection network in the group of nets to be routed in sequence according to the routing order.

2. The wiring method of the 2.5D stacked chip according to claim 1, characterized in that The performing gradient analysis on the resource demand matrix to obtain a critical area includes: Calculating a first gradient of the resource demand matrix in the horizontal direction and a second gradient in the vertical direction respectively by using a Sobel operator; Determining the critical area based on the first gradient and the second gradient.

3. The wiring method of the 2.5D stacked chip according to claim 2, wherein The determining the critical area based on the first gradient and the second gradient includes: Determining candidate areas where both the first gradient and the second gradient are zero, and identifying the edge points of the candidate areas; Obtaining the resource demand values of the edge points and the resource demand values of their adjacent non-zero gradient points; Comparing the resource demand values of the edge points with the resource demand values of the adjacent non-zero gradient points, and determining the critical area according to the comparison result.

4. The wiring method of the 2.5D stacked chip according to claim 1, characterized in that, The performing a merging process on the nodes of the R-Tree data structure to form a group of nets to be routed includes: Obtaining a first network direction of each leaf node in the R-Tree data structure; Based on the first network direction, sequentially performing a merging process on the leaf nodes of each minimum non-leaf node in the R-Tree data structure to form a group of nets to be routed.

5. The wiring method of the 2.5D stacked chip according to claim 4, wherein, Based on the first network direction, sequentially performing a merging process on the leaf nodes of each minimum non-leaf node in the R-Tree data structure to form a group of nets to be routed includes: Randomly determining a target non-leaf node from multiple minimum non-leaf nodes in the R-Tree data structure; Judging whether multiple leaf nodes in the target non-leaf node meet the merging condition according to the first network direction; If all the leaf nodes in the target non-leaf node meet the merging condition, deleting the target non-leaf node, and merging all the leaf nodes in the target non-leaf node into a new leaf node; If some of the leaf nodes in the target non-leaf node meet the merging condition, merging the part of the leaf nodes that meet the merging condition into a new leaf node, marking the target non-leaf node as processed, and retaining the unmerged leaf nodes; Return to execute the step of randomly determining a target non-leaf node from multiple minimum non-leaf nodes in the R-Tree data structure until all minimum non-leaf nodes are processed, generate a new R-Tree data structure, and use each leaf node in the new R-Tree data structure as a wiring group to be routed.

6. The wiring method of the 2.5D stacked chip according to claim 3, characterized in that, The obtaining the first network direction of each leaf node in the R-Tree data structure includes: Obtaining the second network direction of the interconnected networks of each leaf node in the R-Tree data structure; Determining the first network direction of each leaf node according to the second network direction.

7. A wiring device for a 2.5D stacked chip, characterized in that, It includes: A rectangle obtaining unit for obtaining the minimum enclosing rectangle of each interconnected network on the chip; A structure constructing unit for constructing an R-Tree data structure based on the minimum enclosing rectangle; A node merging unit for merging the nodes of the R-Tree data structure to form a wiring group to be routed; A matrix forming unit for dividing the area to which the wiring group belongs into a number of regular grids and counting the number of minimum enclosing rectangles covered on each regular grid to form a resource requirement matrix; An order determining unit for performing gradient analysis on the resource requirement matrix to obtain a critical area; Moving the interconnected networks in the critical area from the wiring group to the wiring order list; Updating the resource requirement matrix and returning to execute the step of performing gradient analysis on the resource requirement matrix to obtain a critical area until all interconnected networks in the wiring group are moved to the wiring order list, so as to obtain the wiring order of each interconnected network in the wiring group; A network routing unit for sequentially routing each interconnected network in the wiring group according to the wiring order.

8. A storage medium, characterized in that, The storage medium stores multiple instructions, and the instructions are suitable for being loaded by a processor to execute the wiring method of the 2.5D stacked chip according to any one of claims 1-6.

9. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored on the memory and executable on the processor. Wherein, when the processor executes the computer program, it implements the wiring method of the 2.5D stacked chip according to any one of claims 1-6.

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