A self-feedback upper cross-coupled sensitive amplifier circuit and its control method

Abstract

The present invention relates to the technical field of sense amplifier circuits, and specifically discloses a self-feedback upper cross-coupled sense amplifier circuit and a control method therefor. The circuit includes: an input circuit, an upper cross-coupled circuit, and a self-feedback circuit; the input circuit includes two NMOS transistors and two PMOS transistors, each NMOS transistor is connected between an output node and VSS, and the current conduction of the NMOS transistor is controlled by a PMOS transistor; two PMOS transistors in the upper cross-coupled circuit are cross-connected between two output nodes and VDD, and are used to control the charging of VDD to one of the output nodes according to the voltage magnitude between the two output nodes; each PMOS transistor in the self-feedback circuit is connected between a PMOS transistor of the input circuit and VSS, and the current conduction thereof is controlled by an output node, so as to cut off one NMOS transistor in the input circuit. The self-feedback upper cross-coupled sense amplifier circuit and the control method therefor disclosed by the present invention can reduce the offset voltage and power consumption of the sense amplifier circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of sense amplifier circuits, and particularly to a self-feedback upper cross-coupled sense amplifier circuit and a control method thereof. Background Art

[0002] In a memory, a sense amplifier is usually used to amplify the weak voltage difference between two ends of a bit line to achieve fast reading of stored data. The performance indicators for measuring the design of a sense amplifier are mainly divided into three aspects: offset voltage, amplification delay, and power consumption. There are generally two existing sense amplifier structures:

[0003] One is a current latch type sense amplifier structure, as shown in Figure 2 , which uses cross-coupled inverters as the core amplification structure and adds a pair of input NMOSs (N-channel Metal-Oxide-Semiconductor Field-Effect Transistors) to avoid the problem of common nodes between input and output, effectively reducing the power consumption of the sense amplifier. However, the mismatch of the NMOSs participating in feedback amplification easily leads to a large offset voltage of the sense amplifier, and only by significantly increasing their size can the offset voltage be effectively reduced. At the same time, the stacking of NMOSs also increases the amplification delay of the sense amplifier.

[0004] The other is an upper cross-coupled type sense amplifier structure, as shown in Figure 3 , where the NMOSs only serve as input transistors and do not participate in the feedback amplification process. This design can effectively reduce the influence of NMOS mismatch on the offset voltage of the sense amplifier, thus having a lower offset voltage. However, in the working stage of the sense amplifier, the bit line causes the two NMOS input transistors to be always turned on, which results in a direct current path from the power supply to the ground at the node with an output of 1, causing a great power consumption loss.

[0005] Aiming at the problems of large offset voltage and high power consumption in the sense amplifier circuit in the related art, no effective solution has been proposed yet. Summary of the Invention

[0006] An embodiment of the present invention provides a self-feedback upper cross-coupled sense amplifier circuit and a control method thereof, which at least solve the problems of large offset voltage and high power consumption in the sense amplifier circuit in the related art.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] In a first aspect, the present invention provides a self-feedback upper cross-coupled sensitive amplifier circuit, comprising: an input circuit, including two NMOS transistors, two intermediate nodes, and two PMOS transistors. Each of the NMOS transistors is connected between an output node and VSS, and the current conduction of the NMOS transistor is controlled by one of the intermediate nodes. Wherein, each of the intermediate nodes controls the transmission of the voltage of a bit line through one of the PMOS transistors according to an enable signal; an upper cross-coupled circuit, including two other PMOS transistors, the two PMOS transistors in the upper cross-coupled circuit are cross-connected between the two output nodes and VDD, and are used to control the charging of VDD to one of the output nodes according to the voltage magnitude between the two output nodes; a self-feedback circuit, including two other PMOS transistors, each of the PMOS transistors in the self-feedback circuit is connected between an intermediate node and VSS, and the current conduction thereof is controlled by one of the output nodes to cut off one of the NMOS transistors in the input circuit. Wherein, the PMOS transistor is turned on when the voltage of the output node is lower than a set threshold value.

[0009] Preferably, the two NMOS transistors of the input circuit are respectively denoted as N1 and N2; the source of N1 is connected to node C, the drain of N1 is connected to an output node OUT; the gate of N1 is connected to an intermediate node A, and the intermediate node A is used to connect one of the PMOS transistors in the input circuit; the source of N2 is connected to node C, the drain of N2 is connected to another output node OUTB; the gate of N2 is connected to another intermediate node B, and the intermediate node B is used to connect the other PMOS transistor in the input circuit; node C is connected to VSS, and the current conduction of node C is controlled by the enable signal to make the line between node C and VSS connected.

[0010] Preferably, the two PMOS transistors of the input circuit are respectively denoted as P3 and P4; the source of P3 is connected to a bit line BL, the drain of P3 is connected to an intermediate node A; the source of P4 is connected to another bit line BLB, the drain of P4 is connected to another intermediate node B; the gates of P3 and P4 are both connected to the enable signal, and are used to control the transmission of the voltage of bit line BL or bit line BLB to intermediate node A or intermediate node B according to the enable signal and the potentials of bit line BL and bit line BLB.

[0011] Preferably, the circuit further includes: an enable circuit; the enable circuit includes: another NMOS transistor, denoted as N3; the source of N3 is connected to VSS, the drain of N3 is connected to node C, the gate of N3 is connected to the enable signal, and the current conduction of N3 is controlled by the enable signal to make the line between node C and VSS connected.

[0012] Preferably, the upper cross-coupling circuit includes: two other PMOSs, denoted as P1 and P2 respectively; the source of P1 is connected to the VDD, the drain of P1 is connected to an output node OUT; the gate of P1 is connected to another output node OUTB; the source of P2 is connected to the VDD, the drain of P2 is connected to the output node OUTB; the gate of P2 is connected to the output node OUT, and is used to control the charging of the VDD to the output node with a higher voltage according to the voltage magnitude between the output node OUT and the output node OUTB.

[0013] Preferably, the two PMOSs of the self-feedback circuit are denoted as P5 and P6; the source of P5 is connected to an intermediate node A, the drain of P5 is connected to the VSS, and the gate of P5 is connected to an output node OUTB, and is used to control the current conduction of P5 according to the voltage of the output node OUTB, and discharge the voltage of the bit line BL through a PMOS in the input circuit, the intermediate node A, and P5 to the VSS, so as to cut off N1; the source of P6 is connected to another intermediate node B, the drain of P6 is connected to the VSS, and the gate of P6 is connected to another output node OUT, and is used to control the current conduction of P6 according to the voltage of the output node OUT, and discharge the voltage of the bit line BLB through a PMOS in the input circuit, the intermediate node B, and P6 to the VSS, so as to cut off N2.

[0014] In a second aspect, the present invention discloses a control method for a self-feedback upper cross-coupling sense amplifier circuit, which is applied to the foregoing self-feedback upper cross-coupling sense amplifier circuit, and includes the following steps: when the enable signal is at a low level, pre-charge the two output nodes to a high level, control the conduction of the two PMOSs in the input circuit, transmit the voltages of the two bit lines to the intermediate node A and the intermediate node B respectively, and transmit the voltages from the intermediate node A and the intermediate node B to the gates of the two NMOSs in the input circuit to make the currents of the two NMOSs conduct; when the enable signal is at a high level, control the two PMOSs in the input circuit to turn off; when there is a potential difference between the two bit lines, use the upper cross-coupling circuit to amplify the voltage difference between the two output nodes, and control the VDD to charge the output node with a higher voltage, while the other output node continues to discharge to the VSS through an NMOS; when the voltage of the output node discharges to be lower than the set threshold, control the current conduction of the PMOS connected to the output node in the self-feedback circuit, and discharge to the VSS through the intermediate node connected to the PMOS, so as to cut off an NMOS in the input circuit.

[0015] Preferably, when the enable signal is at a high level, two PMOSs in the control input circuit are turned off, including: when the enable signal is at a high level, the line between node C and VSS is turned on, so that the two output nodes discharge to the VSS through two NMOSs in the input circuit; wherein, node C is connected to the sources of the two NMOSs in the input circuit, and the drains of the two NMOSs are respectively connected to an output node OUT and an output node OUTB.

[0016] Preferably, when there is a potential difference between the two bit lines, the upper cross-coupling circuit is used to amplify the voltage difference between the two output nodes, and control the VDD to charge the output node with a lower voltage, while the other output node continues to discharge to the VSS through an NMOS, including: when the potential of bit line BL is higher than that of bit line BLB, control the voltage of output node OUT to be less than the voltage of output node OUTB; use the upper cross-coupling circuit to amplify the voltage difference between the two output nodes, and control the VDD to charge output node OUTB, charging the voltage of output node OUTB to the VDD to output a logic "1" level; output node OUT continues to discharge to the VSS; when the potential of bit line BL is lower than that of bit line BLB, control the voltage of output node OUT to be greater than the voltage of output node OUTB; use the upper cross-coupling circuit to amplify the voltage difference between the two output nodes, and control the VDD to charge output node OUT, charging the voltage of output node OUT to the VDD to output a logic "1" level; output node OUTB continues to discharge to the VSS.

[0017] Preferably, when the output node discharges to a voltage lower than the set threshold, control the current conduction of the PMOS connected to this output node in the self-feedback circuit, and discharge to the VSS through the intermediate node connected to the PMOS to cut off an NMOS in the input circuit, including: when output node OUT outputs a logic "1" level, output node OUTB continuously discharges to VSS until it is lower than the set threshold; control the current conduction of the PMOS connected to OUTB in the self-feedback circuit, so that intermediate node A discharges to the VSS to cut off N1 in the input circuit, thereby cutting off the DC conduction path between output node OUT and VSS; when output node OUTB outputs a logic "1" level, output node OUT continuously discharges to VSS until it is lower than the set threshold; control the current conduction of the PMOS connected to OUT in the self-feedback circuit, so that intermediate node B discharges to the VSS to cut off N2 in the input circuit, thereby cutting off the DC conduction path between output node OUTB and VSS.

[0018] The beneficial effects of the present invention are as follows:

[0019] A self-feedback upper cross-coupled sense amplifier circuit and its control method provided by an embodiment of the present invention create add a self-feedback circuit in the amplifier circuit. When the voltage of an output node is lower than a set threshold, the current of a PMOS connected to the output node in the self-feedback circuit can be conducted, enabling a bit line to discharge its voltage through a PMOS in the input circuit and this PMOS in the self-feedback circuit to VSS, and cutting off an NMOS in the input circuit. As a result, among the two output nodes, the DC conduction path between the output node with an output of "1" and VSS is cut off, thus cutting off unnecessary pull-down paths and achieving the effect of reducing power consumption. In addition, when cutting off an NMOS in the present invention, discharging the voltage of the bit line through two PMOSs to VSS can reduce the static power consumption of the bit line discharging to VSS, thereby further reducing the overall circuit power consumption. At the same time, the NMOS in the present invention only participates in the input circuit and does not participate in the feedback circuit, which can avoid the influence of NMOS mismatch on the offset voltage, thereby reducing the offset voltage. The sense amplifier circuit of the present invention has a more streamlined structure, clearer control logic, lower power consumption, and can reduce the offset voltage, thus solving the problems of large offset voltage and high power consumption in the sense amplifier circuit in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other embodiments can be obtained based on these drawings without creative efforts.

[0021] Figure 1 FIG. is a circuit structure diagram of a self-feedback upper cross-coupled sense amplifier circuit provided for Embodiment 1 of the present invention;

[0022] Figure 2 FIG. is a circuit structure diagram of a current latch type sense amplifier circuit in the related art;

[0023] Figure 3 FIG. is a circuit structure diagram of an upper cross-coupled sense amplifier circuit in the related art;

[0024] Figure 4 FIG. is a working waveform diagram of the self-feedback upper cross-coupled sense amplifier circuit provided for Embodiment 1 of the present invention;

[0025] Figure 5 FIG. is a comparison diagram of the offset voltages of the circuit of Embodiment 1 of the present invention and Figure 2 circuit, Figure 3 circuit under different process corners;

[0026] Figure 6 In order to use the circuit of the first embodiment of the present invention in the CMOS process Figure 2 Circuits, Figure 3 A comparison of the circuit's amplification delay at different process angles;

[0027] Figure 7 In order to use the circuit of the first embodiment of the present invention in the CMOS process Figure 2 Circuits, Figure 3 Comparison of energy consumption delay product of circuits at different process angles;

[0028] Figure 8 A pin distribution diagram of a self-feedback upper cross-coupled sense amplifier circuit module provided in Embodiment 2 of the present invention;

[0029] Figure 9 It is a flow chart of a self-feedback upper cross-coupled sensitive amplifier circuit control method provided in Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0030] The embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are only for exemplary purposes and are not intended to limit the scope of protection of the present invention.

[0031] With the continuous breakthroughs in CMOS (Complementary Metal-Oxide-Semiconductor) technology, the size of a single tube has been continuously reduced, and the density of MOS tubes carried on the chip has been greatly improved. In the memory circuit, the data of the storage unit is read through the bit line. However, the high-density storage array increases the number of storage units mounted on the same bit line, and the parasitic capacitance of the bit line increases accordingly. This means that the delay of the full swing discharge of the bit line increases and the power consumption increases. Therefore, a sensitive amplifier is usually used in the memory to amplify the weak voltage difference between the two ends of the bit line to achieve fast readout of the stored data.

[0032] In SRAM (Static Random Access Memory), the bit lines BL and BLB are precharged to VDD before the read operation. During the read operation, the word line is pulled high, the storage node is connected to the bit line, and the stored data affects the bit line voltage, forming a voltage difference between the bit lines BL and BLB. The amplifier compares the potential difference between the bit lines BL and BLB and amplifies it.

[0033] When the potential of BL is higher than that of BLB, the SRAM reads the stored data as "1", and the sense amplifier amplifies the voltage difference between the two bit lines, causing the voltage of the output node OUT to rise to VDD to represent the output logic "1" level;

[0034] When the potential of BL is lower than that of BLB, the SRAM reads the stored data as "0", and the sense amplifier amplifies the voltage difference between the two bit lines, causing the output node OUT to discharge to the ground level VSS to represent the output logic "0" level.

[0035] In the related art, there are usually two sense amplifier circuit structures in SRAM. One is the current latch type sense amplifier structure (abbreviation: CLSA), and the other is the upper cross-coupled type sense amplifier structure (abbreviation: UCSA).

[0036] In the Figure 2 example of the current latch type sense amplifier structure, a cross-coupled inverter is used as the core amplification structure. Among them, the cross-coupled inverter includes a pair of PMOS (P-channel Metal-Oxide-Semiconductor Field-Effect Transistor) and a pair of NMOS, and the gate of one NMOS and the gate of one PMOS are commonly connected to an output node, so that the NMOS participates in the feedback process. Affected by the process, the NMOS mismatch problem will inevitably occur between the two NMOS in the cross-coupled inverter, and the NMOS mismatch is likely to cause a large offset voltage of the sense amplifier. Only by greatly increasing its size can the offset voltage be effectively reduced. However, greatly increasing the size of the NMOS will not only increase the manufacturing cost, but also increase the power consumption. Moreover, the stacking of NMOS will also increase the amplification delay of the sense amplifier.

[0037] In the Figure 3 example of the upper cross-coupled type sense amplifier structure, only PMOS is used in its cross-coupled structure, so that the NMOS does not participate in the feedback amplification process and only serves as an input transistor. Since the NMOS does not participate in the feedback, the output of the circuit is mainly determined by the PMOS and other related factors. The characteristics of the PMOS are relatively stable and are not directly interfered by the NMOS mismatch, which can make the output state more stable, thereby reducing the change of the offset voltage. However, in the sense amplifier circuit, when there is a potential difference between the two bit lines, the inputs of the two NMOS will always be turned on, so that a direct current path is formed between the output node with an output of 1 and VSS, discharging to VSS, thereby generating an unnecessary pull-down path, causing a great power consumption loss and increasing the total power consumption.

[0038] At present, there is also a self-adaptive turn-off type SRAM sense amplifier circuit based on upper cross-coupling in the related technology (abbreviated as The proposed SA). Taking the Chinese invention patent with the authorization announcement number CN 116168736 B as an example, it mainly sets four groups of inverters on two groups of bit lines, and the inverters are used to accelerate the signal transmission speed on the bit lines, so that the sense amplifier can obtain a faster amplification speed. However, when the two groups of bit lines work simultaneously, the non-target bit lines will participate in the signal transmission, resulting in a long delay time. Therefore, the related technology introduces a self-turn-off bit line part, which can adaptively cut off the connection between the non-target bit line and the intermediate node of the response input circuit part according to the voltage changes of the output nodes A0 and A1, so as to reduce the offset voltage and amplification delay. However, this related technology uses a large number of inverters, and there may be relatively large static power consumption and open-circuit power consumption. In addition, even if the connection between the non-target bit line and the input circuit is cut off, there are still multiple direct current paths formed between the output node with an output of 1 and VSS, thus increasing the total power consumption of the amplifier circuit.

[0039] See Figure 1 , in order to reduce the offset voltage and power consumption of the sense amplifier circuit, Embodiment 1 of the present invention provides a self-feedback upper cross-coupling sense amplifier circuit, including: an input circuit, an upper cross-coupling circuit, and a self-feedback circuit.

[0040] The input circuit includes two NMOSs, two intermediate nodes, and two PMOSs. Each NMOS is connected between an output node and VSS, and the current conduction of the NMOS is controlled by an intermediate node; wherein, each intermediate node controls the transmission of the voltage of a bit line through a PMOS according to the enable signal.

[0041] The upper cross-coupling circuit includes two other PMOSs. The two PMOSs in the upper cross-coupling circuit are cross-connected between the two output nodes and VDD, and are used to control the charging of VDD to one of the output nodes according to the voltage magnitude between the two output nodes.

[0042] The self-feedback circuit includes two other PMOSs. Each PMOS in the self-feedback circuit is connected between an intermediate node and VSS, and its current conduction is controlled by an output node, so as to cut off one of the NMOSs in the input circuit. When the voltage of the output node is lower than the set threshold, the PMOS is turned on.

[0043] A self-feedback cross-coupled sensitive amplifier circuit provided by an embodiment of the present invention creates a self-feedback circuit. When the voltage of an output node is lower than a set threshold, the current of a PMOS connected to the output node in the self-feedback circuit is turned on, enabling a bit line to discharge its voltage to VSS through a PMOS in the input circuit and this PMOS in the self-feedback circuit, and cutting off an NMOS in the input circuit. As a result, a direct current path between the output node with an output of "1" and VSS among the two output nodes is cut off to cut off an unnecessary pull-down path, thereby achieving the effect of reducing power consumption.

[0044] In addition, in the present invention, when an NMOS is cut off, the voltage of the bit line is discharged to VSS through two PMOSs, which can reduce the static power consumption of the bit line discharging to VSS, thereby further reducing the overall circuit power consumption.

[0045] At the same time, the NMOS in the present invention only participates in the input circuit and does not participate in the feedback circuit, which can avoid the influence of NMOS mismatch on the offset voltage, thereby reducing the offset voltage. The sensitive amplifier circuit of the present invention has a more concise structure, clearer control logic, lower power consumption, and can reduce the offset voltage, thus solving the problems of large offset voltage and high power consumption in the sensitive amplifier circuit in the related art.

[0046] In a preferred but non-limiting embodiment of the present invention, the two NMOSs in the input circuit are respectively denoted as N1 and N2. The source of N1 is connected to node C, the drain of N1 is connected to an output node OUT; the gate of N1 is connected to an intermediate node A. The source of N2 is connected to node C, the drain of N2 is connected to another output node OUTB; the gate of N2 is connected to another intermediate node B. Node C is connected to VSS, and the current conduction of node C is controlled by an enable signal to connect the line between node C and VSS.

[0047] When there is a voltage input to intermediate node A and intermediate node B, the gates of N1 and N2 are turned on. When the enable signal is also at a high level, both output node OUT and output node OUTB form direct current paths with VSS.

[0048] Further, the two PMOSs in the input circuit are respectively denoted as P3 and P4; the source of P3 is connected to a bit line BL, the drain of P3 is connected to an intermediate node A; the source of P4 is connected to another bit line BLB, the drain of P4 is connected to another intermediate node B; the gates of P3 and P4 are both connected to the enable signal, and are used to control the transmission of the voltage of bit line BL or bit line BLB to intermediate node A or intermediate node B according to the enable signal, the potentials of bit line BL and bit line BLB.

[0049] Specifically, when the enable signal is set to a low level, the currents of P3 and P4 are conducted, and the voltage of bit line BL or bit line BLB is transmitted to intermediate node A or intermediate node B.

[0050] The circuit of the embodiment of the present invention further includes an enable circuit, and the enable circuit includes: another NMOS, denoted as N3. The source of N3 is connected to VSS, the drain of N3 is connected to node C, and the gate of N3 is connected to the enable signal.

[0051] Specifically, when the sense amplifier circuit of the embodiment of the present invention works, the enable signal is set to a high level. At this time, the gate of N3 is conducted, so that the line between node C and VSS is conducted, thereby controlling that the sense amplifier circuit can work normally. When the enable signal is set to a low level, the gate of N3 is not conducted, and the sense amplifier circuit is controlled not to work.

[0052] In addition, when the gate of N3 is conducted, each output node discharges to VSS through N1, N3 or N2, N3 in the input circuit. Therefore, during the discharging process of the output node, it passes through two NMOSs. By setting the stacked structure of the NMOSs, the subthreshold leakage can be reduced, thereby reducing the static power consumption and reducing the short-circuit current, and thus reducing the dynamic power consumption.

[0053] The upper cross-coupled circuit includes: two other PMOSs, denoted as P1 and P2 respectively. Among them, the source of P1 is connected to VDD, the drain of P1 is connected to an output node OUT; the gate of P1 is connected to another output node OUTB; the source of P2 is connected to VDD, the drain of P2 is connected to output node OUTB; the gate of P2 is connected to output node OUT, and is used to control VDD to charge the output node with a higher voltage according to the voltage magnitude between output node OUT and output node OUTB, so as to raise its voltage to VDD to output a logic "1" level, while the other output node continuously discharges to VSS until VSS to output a logic "0" level.

[0054] Among them, when controlling VDD to charge the output node with a higher voltage to raise its voltage to VDD, a certain error is allowed, that is, when the error between the voltage of the output node with a higher voltage and the voltage of VDD is within a certain range, it is also considered that the voltage of the output node has been raised to VDD.

[0055] Specifically, when the voltage of output node OUT is greater than the voltage of output node OUTB, output node OUTB controls P1 in the self-feedback circuit to be conducted, and uses VDD to charge OUT through P1, so as to raise the voltage of output node OUT to VDD.

[0056] In the embodiment of the present invention, the upper cross-coupling circuit only uses PMOS, and NMOS does not participate in the feedback amplification process, thereby avoiding the influence of NMOS mismatch on the offset voltage and reducing the offset voltage of the amplifier circuit.

[0057] The two PMOSs of the self-feedback circuit are denoted as P5 and P6; the source of P5 is connected to an intermediate node A, the drain of P5 is connected to VSS, and the gate of P5 is connected to an output node OUTB, which is used to control the current conduction of P5 according to the voltage of the output node OUTB, and discharge the voltage of the bit line BL through a PMOS in the input circuit, the intermediate node A, and P5 to VSS, so as to cut off N1.

[0058] The source of P6 is connected to another intermediate node B, the drain of P6 is connected to VSS, and the gate of P6 is connected to another output node OUT, which is used to control the current conduction of P6 according to the voltage of the output node OUT, and discharge the voltage of the bit line BLB through a PMOS in the input circuit, the intermediate node B, and P6 to VSS, so as to cut off N2.

[0059] Specifically, when the output node OUT outputs a logic "1" level, P6 in the self-feedback circuit is turned off, and when the output node OUTB continuously discharges to VSS until the voltage is lower than the set threshold, P5 is turned on, so that the intermediate node A can discharge to VSS through P5, so that N1 is cut off, and the pull-down path of the output node OUT with a logic "1" level output is cut off, thereby reducing power consumption.

[0060] When the output node OUTB outputs a logic "1" level, P5 in the self-feedback circuit is turned off, and when the output node OUT continuously discharges to VSS until the voltage is lower than the set threshold, P6 is turned on, so that the intermediate node A can discharge to VSS through P5, so that N1 is cut off, and the pull-down path of the output node OUT with a logic "1" level output is cut off, thereby reducing power consumption.

[0061] Further, the voltage threshold for P6 to turn on is VDD - Vthp6, where Vthp6 represents the threshold voltage of P6; the voltage threshold for P5 to turn on is VDD - Vthp5, where Vthp5 represents the threshold voltage of P5.

[0062] Furthermore, since the voltages transmitted by the intermediate node A and the intermediate node B pass through a PMOS in the input circuit, when the intermediate node A or the intermediate node B discharges to VSS through P5 or P6 in the self-feedback circuit, their voltages pass through two PMOSs. By setting the stacked structure of the two PMOSs, the static power consumption of the bit line discharging to VSS can be reduced, thereby further reducing the overall circuit power consumption.

[0063] When the self-feedback upper cross-coupled sense amplifier circuit provided by the embodiment of the present invention is not working, the output node OUT and the output node OUTB are pre-charged to a high level through VDD. P5 and P6 in the self-feedback circuit are turned off, the enable signal SAE is at a low level, P3 and P4 in the input circuit are turned on, the bit line BL transfers its voltage to the intermediate node A, the bit line BLB transfers its voltage to the intermediate node B, and the intermediate node A and the intermediate node B transfer the voltage to N1 and N2 in the input circuit, making N1 and N2 turned on.

[0064] When the self-feedback upper cross-coupled sense amplifier circuit provided by the embodiment of the present invention is working, the enable signal SAE is at a high level, P3 and P4 in the input signal are turned off, and N3 is turned on, thus conducting the line between the node C and VSS, enabling the output node OUT to discharge to VSS through N1 and N3, and the output node OUTB to discharge to VSS through N2 and N3.

[0065] When the potential of the bit line BL is higher than that of the bit line BLB, the discharge speed of the output node OUT is greater than that of the output node OUTB, thereby controlling the voltage of the output node OUT to be less than the voltage of the output node OUTB; using the upper cross-coupled circuit to amplify the voltage difference between the two output nodes, turning on P2, controlling VDD to charge the output node OUTB, charging the voltage of the output node OUTB to VDD to output a logic "1" level; the output node OUT continuously discharges to VSS until it is lower than the set threshold, controlling the current of P6 connected to OUT in the self-feedback circuit to conduct, causing the intermediate node B to discharge to VSS, so as to cut off N2 in the input circuit, thereby cutting off the DC conduction path between the output node OUTB and VSS.

[0066] When the potential of the bit line BL is lower than that of the bit line BLB, the discharge speed of the output node OUT is less than that of the output node OUTB, thereby controlling the voltage of the output node OUT to be greater than the voltage of the output node OUTB; using the upper cross-coupled circuit to amplify the voltage difference between the two output nodes, turning on P1, controlling VDD to charge the output node OUT, charging the voltage of the output node OUT to VDD to output a logic "1" level. The output node OUTB continuously discharges to VSS until it is lower than the set threshold; controlling the current of P5 connected to OUTB in the self-feedback circuit to conduct, causing the intermediate node A to discharge to the VSS, so as to cut off N1 in the input circuit, thereby cutting off the DC conduction path between the output node OUT and VSS.

[0067] As Figure 4As shown in the figure, in the embodiment of the present invention, before 400 ps, the enable signal SAE is set to a low level, that is, the sense amplifier circuit does not perform amplification work, and the output nodes OUT and OUTB are pre-charged to a high level by VDD. At 400 ps, the enable signal SAE is set to a high level, and the potential of the bit line BLB is higher than that of the bit line BL, so that the discharge speed of the output node OUT is less than that of the output node OUTB. The voltage of the output node OUTB rapidly drops to 0, while the voltage of the output node OUT first drops and then rises through the self-feedback circuit and outputs 1 in a short time, thereby generating an output signal and completing data amplification.

[0068] As Figure 5 shown, it is a comparison diagram of the offset voltages of UCSA, CLSA, and the improved The proposed SA in the embodiment of the present invention under different process corners in the CMOS process. The simulation conditions are VDD = 0.6V and temperature = 25°C. From Figure 5 it can be seen that at the 4 process corners other than SS, the offset voltage of CLSA is more than 50% larger than that of the improved The proposed SA, and the offset voltage of UCSA is also greater than that of the improved The proposed SA. This is because an important reason for the incorrect amplification result of CLSA is the size mismatch of the NMOS transistors participating in the feedback in the cross-coupled structure. The influence of size mismatch means that the pair of transistors with the same size in the original design are affected by the process, resulting in the mismatch of the sizes of the actually manufactured pair of transistors, thus affecting the operation of the overall circuit. The circuit of the improved The proposed SA is mainly affected by the size mismatch of the input transistors, and the size mismatch of the pull-up P transistors has a small impact on the offset voltage of the overall sense amplifier. At the same time, compared with the structurally similar UCSA, the self-feedback structure added to the improved The proposed SA further reduces the offset voltage of the circuit.

[0069] As Figure 6 shown, it is a comparison diagram of the amplification delays of UCSA, CLSA, and the improved The proposed SA in the embodiment of the present invention under different process corners in the CMOS process. The simulation conditions are VDD = 0.6V, temperature = 25°C, bit line capacitance = 50 fF, and bit line difference = 50 mV. From Figure 6 it can be seen that the amplification delay of the improved The proposed SA is slightly larger than that of UCSA and smaller than that of CLSA. This is because the NMOS stacking structure in CLSA reduces the on-current, resulting in the largest amplification delay. Compared with UCSA, the improved The proposed SA has an additional pair of PMOS as extra transmission transistors to isolate the influence of the parasitic capacitance of the bit line on the self-feedback structure during the operation of the sense amplifier, so its delay is slightly larger than that of UCSA.

[0070] As Figure 7 shown, it is a comparison chart of the Energy Consumption Delay Product (EDP) of UCSA, CLSA, and the improved The proposed SA in the embodiments of the present invention under different process corners in the CMOS process. The simulation conditions are VDD = 0.6V, temperature = 25°C, bitline capacitance = 50fF, and bitline difference = 50mV. It can be seen from Figure 7 that, under 4 process corners except for FS, the energy consumption delay product of the improved The proposed SA is less than that of CLSA. Compared with UCSA with a DC path, although the delay of the improved The proposed SA is greater than that of UCSA, the EDP is reduced by more than 75%. Moreover, for The proposed SA in the related technology, due to the setting of more inverters and a larger number of transistors, the power consumption of the amplifier circuit will also increase, and there are still multiple DC paths between the output node with an output of 1 and VSS. This means that the improved The proposed SA can cut off the DC path between the output node with an output of 1 and VSS by adding a self-feedback design, and is provided with a PMOS stacked structure and an NMOS stacked structure, effectively solving the problem of the DC path existing in the upper cross-coupled sense amplifier, and significantly reducing the comprehensive performance index of the energy consumption delay product.

[0071] Generally speaking, the improved The proposed SA in the embodiments of the present invention has a significant improvement in the performance indicators of offset voltage and power consumption.

[0072] As Figure 8 shown, Embodiment 2 of the present invention provides a self-feedback upper cross-coupled sense amplifier circuit module, which is applied to the self-feedback upper cross-coupled sense amplifier circuit in Embodiment 1 and includes: 7 pins. Among them, the first pin is used to connect the sources of P1 and P2 to VDD. The second pin is used to connect the sources of N3, P5, and P6 to VSS. The third pin is used to connect the gates of P3, P4, and N3 to SAE. The fourth pin is used to connect the source of P3 to BL. The fifth pin is used to connect the source of P4 to BLB. The sixth pin is used to connect to the output node OUT. The seventh pin is used to connect to the output node OUTB.

[0073] The sense amplifier circuit module provided by the embodiments of the present invention adopts a modular packaging mode, which is more conducive to the popularization and application of the above SRAM sense amplifier circuit.

[0074] Embodiment 3 of the present invention provides a control method for a self-feedback upper cross-coupled sensitive amplifier circuit, which is applied to the self-feedback upper cross-coupled sensitive amplifier circuit in Embodiment 1, and includes the following steps:

[0075] Step S01, when the enable signal is at a low level, pre-charge the two output nodes to a high level, control the conduction of two PMOSs in the input circuit, transmit the voltages of the two bit lines to the intermediate node A and the intermediate node B respectively, and transmit the voltages from the intermediate node A and the intermediate node B to the gates of two NMOSs in the input circuit to enable the currents of the two NMOSs to conduct;

[0076] Step S02, when the enable signal is at a high level, control the two PMOSs in the input circuit to turn off;

[0077] Step S03, when there is a potential difference between the two bit lines, use the upper cross-coupled circuit to amplify the voltage difference between the two output nodes, and control VDD to charge the output node with a higher voltage, while the other output node continues to discharge to VSS through an NMOS;

[0078] Step S04, when the output node discharges to a voltage lower than the set threshold, control the current of the PMOS connected to the output node in the self-feedback circuit to conduct, discharge to VSS through the intermediate node connected to the PMOS, so as to cut off an NMOS in the input circuit.

[0079] In a preferred but non-limiting embodiment of the present invention, in step S02, when the enable signal is at a high level, controlling the two PMOSs in the input circuit to turn off includes:

[0080] When the enable signal is at a high level, conduct the line between node C and VSS, so that the two output nodes discharge to VSS through the two NMOSs in the input circuit; wherein, node C is connected to the sources of the two NMOSs in the input circuit, and the drains of the two NMOSs are respectively connected to an output node OUT and an output node OUTB.

[0081] Further, step S03 includes:

[0082] When the potential of bit line BL is higher than that of bit line BLB, control the voltage of output node OUT to be lower than the voltage of output node OUTB; use the upper cross-coupled circuit to amplify the voltage difference between the two output nodes, and control VDD to charge output node OUTB, charge the voltage of output node OUTB to VDD to output a logic "1" level; output node OUT continues to discharge to VSS;

[0083] When the potential of bit line BL is lower than that of bit line BLB, control the voltage of output node OUT to be greater than the voltage of output node OUTB; use the upper cross-coupled circuit to amplify the voltage difference between the two output nodes, and control VDD to charge the output node OUT, charging the voltage of the output node OUT to VDD to output a logic "1" level; the output node OUTB continues to discharge to VSS.

[0084] Step S04 includes:

[0085] When the output node OUT outputs a logic "1" level, the output node OUTB continuously discharges to VSS until it is lower than the set threshold; control the current conduction of P5 connected to OUTB in the self-feedback circuit, so that the intermediate node A discharges to VSS, so as to cut off N1 in the input circuit, thereby cutting off the DC conduction path between the output node OUT and VSS;

[0086] When the output node OUTB outputs a logic "1" level, the output node OUT continuously discharges to VSS until it is lower than the set threshold; control the current conduction of P6 connected to OUT in the self-feedback circuit, so that the intermediate node B discharges to VSS, so as to cut off N2 in the input circuit, thereby cutting off the DC conduction path between the output node OUTB and VSS.

[0087] A control method for a self-feedback upper cross-coupled sensitive amplifier circuit provided by the present invention provides a complete control step for cutting off the DC line between the output node with an output of 1 and VSS in the sensitive amplifier circuit, thereby being able to reduce the power consumption and offset voltage of the amplifier circuit.

[0088] It should be noted that the term "including" and its variants used in the embodiments of the present invention are open-ended, that is, "including but not limited to". The term "based on" is "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The modifications of "one" and "multiple" mentioned in the embodiments of the present invention are illustrative rather than restrictive, and those skilled in the art should understand that unless clearly stated otherwise in the context, it should be understood as "one or more".

[0089] The term "embodiment" in this specification means that the specific features, structures or characteristics described in connection with the embodiments may be included in at least one embodiment of the present invention. The phrase appears in various positions in the specification does not necessarily mean the same embodiment, nor does it mean being independent or alternative to other embodiments and mutually exclusive. The embodiments in this specification are all described in a related manner, and the same or similar parts among the embodiments are cross-referred to each other. In particular, for the embodiments of devices, equipment, and systems, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts refer to the partial description of the method embodiments.

[0090] The above-described embodiments only represent several implementation manners of the present invention, and the description thereof is relatively specific and detailed, but it should not be construed as a limitation of the protection scope. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the appended claims.

Claims

1. A self-feedback upper cross-coupled sensitive amplifier circuit, characterized in that, Comprising: An input circuit, including two NMOSs, two intermediate nodes, and two PMOSs. Each of the NMOSs is connected between an output node and VSS, and the current conduction of the NMOS is controlled by an intermediate node. Wherein, each of the intermediate nodes controls the voltage of a bit line to be transmitted according to an enable signal through a PMOS; An upper cross-coupling circuit, including two other PMOSs. The two PMOSs in the upper cross-coupling circuit are cross-connected between the two output nodes and VDD, and are used to control the charging of VDD to one of the output nodes according to the voltage magnitude between the two output nodes; A self-feedback circuit, including two other PMOSs. Each of the PMOSs in the self-feedback circuit is connected between an intermediate node and VSS, and its current conduction is controlled by an output node to cut off one of the NMOSs in the input circuit. Wherein, the output node turns on the PMOS when the voltage is lower than a set threshold; 2. The self-feedback upper cross-coupling sense amplifier circuit according to claim 1, wherein: The two NMOSs of the input circuit are respectively denoted as N1 and N2; The source of N1 is connected to node C, and the drain of N1 is connected to an output node OUT. The gate of N1 is connected to an intermediate node A, and the intermediate node A is used to connect a PMOS in the input circuit; The source of N2 is connected to node C, and the drain of N2 is connected to another output node OUTB. The gate of N2 is connected to another intermediate node B, and the intermediate node B is used to connect another PMOS in the input circuit; The node C is connected to VSS, and the current conduction of node C is controlled by an enable signal to make the line between node C and VSS connected; 3. The self-feedback upper cross-coupling sense amplifier circuit according to claim 2, wherein: The two PMOSs of the input circuit are respectively denoted as P3 and P4; The source of P3 is connected to a bit line BL, and the drain of P3 is connected to an intermediate node A; The source of P4 is connected to another bit line BLB, and the drain of P4 is connected to another intermediate node B; The gates of P3 and P4 are both connected to the enable signal, and are used to control the transmission of the voltage of bit line BL or bit line BLB to intermediate node A or intermediate node B according to the enable signal, the potentials of bit line BL and bit line BLB; 4. The self-feedback upper cross-coupled sensitive amplifier circuit according to claim 2, characterized in that, The circuit further includes: an enable circuit; The enable circuit includes: another NMOS, denoted as N3; The source of N3 is connected to VSS, the drain of N3 is connected to node C, and the gate of N3 is connected to the enable signal. The current conduction of N3 is controlled by the enable signal to make the line between node C and VSS connected; 5. The self-feedback upper cross-coupling sense amplifier circuit according to any one of claims 1-4, wherein: The upper cross-coupling circuit includes: two other PMOSs, respectively denoted as P1 and P2; The source of P1 is connected to VDD, the drain of P1 is connected to an output node OUT; the gate of P1 is connected to another output node OUTB; The source of P2 is connected to VDD, the drain of P2 is connected to the output node OUTB; the gate of P2 is connected to the output node OUT, and is used to control the charging of VDD to the output node with a higher voltage according to the voltage between the output node OUT and the output node OUTB.

6. The self-feedback cross-coupled sense amplifier circuit according to any one of claims 2-4, wherein: The two PMOSs of the self-feedback circuit are denoted as P5 and P6; The source of P5 is connected to an intermediate node A, the drain of P5 is connected to VSS, and the gate of P5 is connected to an output node OUTB, and is used to control the current conduction of P5 according to the voltage of the output node OUTB, and discharge the voltage of the bit line BL through a PMOS in the input circuit, the intermediate node A, and P5 to VSS, so as to cut off N1; The source of P6 is connected to another intermediate node B, the drain of P6 is connected to VSS, and the gate of P6 is connected to another output node OUT, and is used to control the current conduction of P6 according to the voltage of the output node OUT, and discharge the voltage of the bit line BLB through a PMOS in the input circuit, the intermediate node B, and P6 to VSS, so as to cut off N2.

7. A control method for a self-feedback upper cross-coupled sensitive amplifier circuit, applied to the self-feedback upper cross-coupled sensitive amplifier circuit according to any one of claims 1-6, characterized in that, Including the following steps: When the enable signal is at a low level, pre-charge the two output nodes to a high level, control the conduction of the two PMOSs in the input circuit, transfer the voltages of the two bit lines to the intermediate node A and the intermediate node B respectively, and transfer the voltages from the intermediate node A and the intermediate node B to the gates of the two NMOSs in the input circuit to make the currents of the two NMOSs conductive; When the enable signal is at a high level, control the two PMOSs in the input circuit to turn off; When there is a potential difference between the two bit lines, use the cross-coupled circuit to amplify the voltage difference between the two output nodes, and control VDD to charge the output node with a higher voltage, while the other output node continues to discharge to VSS through an NMOS; When the output node discharges to a voltage lower than the set threshold, control the current conduction of the PMOS connected to this output node in the self-feedback circuit, and discharge to VSS through the intermediate node connected to the PMOS, so as to cut off an NMOS in the input circuit.

8. The control method of the self-feedback upper cross-coupled sensitive amplifier circuit according to claim 7, characterized in that When the enable signal is at a high level, controlling the two PMOSs in the input circuit to turn off includes: When the enable signal is at a high level, conduct the line between node C and VSS, so that the two output nodes discharge to VSS through the two NMOSs in the input circuit; wherein, node C is connected to the sources of the two NMOSs in the input circuit, and the drains of the two NMOSs are respectively connected to an output node OUT and an output node OUTB.

9. The control method of the self-feedback upper cross-coupled sensitive amplifier circuit according to claim 8, characterized in that, When there is a potential difference between two bit lines, the upper cross-coupled circuit is used to amplify the voltage difference between the two output nodes, and control the VDD to charge the output node with a higher voltage, while the other output node continues to discharge to the VSS through an NMOS, including: When the potential of the bit line BL is higher than that of the bit line BLB, control the voltage of the output node OUT to be less than the voltage of the output node OUTB; use the upper cross-coupled circuit to amplify the voltage difference between the two output nodes, and control the VDD to charge the output node OUTB, charging the voltage of the output node OUTB to the VDD to output a logic "1" level; the output node OUT continues to discharge to the VSS; When the potential of the bit line BL is lower than that of the bit line BLB, control the voltage of the output node OUT to be greater than the voltage of the output node OUTB; use the upper cross-coupled circuit to amplify the voltage difference between the two output nodes, and control the VDD to charge the output node OUT, charging the voltage of the output node OUT to the VDD to output a logic "1" level; the output node OUTB continues to discharge to the VSS.

10. The control method of the self-feedback upper cross-coupled sensitive amplifier circuit according to claim 9, characterized in that, When the output node discharges to a voltage lower than the set threshold, control the current of the PMOS connected to the output node in the self-feedback circuit to conduct, and discharge to the VSS through the intermediate node connected to the PMOS to cut off an NMOS in the input circuit, including: When the output node OUT outputs a logic "1" level, the output node OUTB continuously discharges to the VSS until it is lower than the set threshold; control the current of the PMOS connected to the OUTB in the self-feedback circuit to conduct, so that the intermediate node A discharges to the VSS to cut off N1 in the input circuit, thereby cutting off the DC conduction path between the output node OUT and the VSS; When the output node OUTB outputs a logic "1" level, the output node OUT continuously discharges to the VSS until it is lower than the set threshold; control the current of the PMOS connected to the OUT in the self-feedback circuit to conduct, so that the intermediate node B discharges to the VSS to cut off N2 in the input circuit, thereby cutting off the DC conduction path between the output node OUTB and the VSS.

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