Memory device

Abstract

A memory device is provided. The memory device includes: a memory cell array; a plurality of page buffer units connected to the memory cell array and commonly connected to the combined sensing node; and a plurality of cache latches respectively corresponding to the plurality of page buffer units, the plurality of cache latches including a first cache latch and a second cache latch commonly connected to a combined sensing node. In a first period of a data dump operation on the first cache latch, a first tri-state inverter and a second tri-state inverter in the first cache latch are enabled to transmit data to the first cache latch, and a third tri-state inverter and a fourth tri-state inverter in the second cache latch are disabled. In a second period of the data dump operation, the third tri-state inverter and the fourth tri-state inverter are sequentially enabled to recover data previously stored in the second cache latch.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2023-0178746, filed with the Korean Intellectual Property Office on December 11, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This application relates to storage, and more particularly, to a memory device. Background Art

[0003] With the demand for high-capacity and scaled-down memory devices, three-dimensional (3D) memory devices have been developed in which a memory cell array and a peripheral circuit are arranged in a vertical direction. As semiconductor processes have advanced, as the number of stacked word lines increases in the memory cell array, the area of the memory cell array decreases. Accordingly, there is a need to reduce the area of the peripheral circuit. In particular, there is an increasing need to reduce the size of a page buffer circuit, which occupies a significantly large area in the peripheral circuit. Summary of the Invention

[0004] Disclosed is a memory device capable of reducing the area of a page buffer circuit by reducing the number of transistors included in the page buffer circuit.

[0005] According to an aspect of the disclosure, there is provided a memory device including: a memory cell array; a plurality of page buffer units connected to the memory cell array and commonly connected to a combined sense node; and a plurality of cache latches respectively corresponding to the plurality of page buffer units, the plurality of cache latches including a first cache latch and a second cache latch commonly connected to the combined sense node, wherein, during a first period of a data dump operation of the first cache latch, a first tri-state inverter and a second tri-state inverter included in the first cache latch are enabled to transfer data to the first cache latch, and a third tri-state inverter and a fourth tri-state inverter included in the second cache latch are disabled, and, during a second period of the data dump operation of the first cache latch, the third tri-state inverter and the fourth tri-state inverter are sequentially enabled to restore data previously stored in the second cache latch.

[0006] According to another aspect of the disclosure, there is provided a memory device including: a memory cell array; a plurality of page buffer units connected to the memory cell array and commonly connected to a combined sense node; and a plurality of cache latches respectively corresponding to the plurality of page buffer units, the plurality of cache latches being commonly connected to the combined sense node, wherein the plurality of cache latches include: a first cache latch including a first tri-state inverter and a second tri-state inverter; and a second cache latch including a third tri-state inverter and a fourth tri-state inverter, wherein, during a first period of a data dump operation of the first cache latch, the first tri-state inverter is enabled to transfer data to the first cache latch, and the second tri-state inverter to the fourth tri-state inverter are disabled, and, during a second period of the data dump operation of the first cache latch, the third tri-state inverter and the fourth tri-state inverter are sequentially enabled to restore data previously stored in the second cache latch.

[0007] According to another aspect of the disclosure, there is provided a memory device including: a memory cell array; a plurality of page buffer units connected to the memory cell array, wherein the plurality of page buffer units are commonly connected to a combined sense node; and a plurality of cache latches respectively corresponding to the plurality of page buffer units, the plurality of cache latches being commonly connected to the combined sense node, wherein the plurality of cache latches include: a first cache latch including a first tri-state inverter and a second tri-state inverter; and a second cache latch including a third tri-state inverter and a fourth tri-state inverter, wherein the first tri-state inverter to the fourth tri-state inverter are disabled during a first period of a data dump operation of the first cache latch, and, during a second period of the data dump operation of the first cache latch, after enabling the first tri-state inverter and the fourth tri-state inverter, the second tri-state inverter and the third tri-state inverter are enabled, and data previously stored in the second cache latch is restored. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be understood more clearly from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram of a memory device according to some embodiments; Figure 2 is a circuit diagram of a memory block according to some embodiments; Figure 3 shows the connection of a memory cell array to a page buffer circuit according to some embodiments; Figure 4 is a circuit diagram of a page buffer according to some embodiments; Figure 5is a detailed circuit diagram of a page buffer according to some embodiments; Figure 6 is a detailed circuit diagram of a page buffer according to some embodiments; Figure 7 is a timing diagram of voltage levels of transmission control signals in a core operation sequence according to some embodiments; Figure 8 illustrates a multi - level structure of a page buffer circuit according to some embodiments; Figure 9 illustrates the connection from a main latch to a cache latch according to some embodiments; Figure 10 is a circuit diagram of a first cache latch according to some embodiments; Figure 11 is a circuit diagram of a first cache latch according to some embodiments; Figure 12 is a circuit diagram of multiple cache latches according to some embodiments; Figure 13 illustrates a data dump operation according to some embodiments; Figure 14A is a timing diagram of control operations on selected cache latches in a data dump operation according to some embodiments; Figure 14B is a timing diagram of control operations on unselected cache latches in a data dump operation according to some embodiments; Figure 15 illustrates a discharge operation according to some embodiments; Figure 16 is according to some embodiments Figure 14A and Figure 14B detailed timing diagram of a data dump operation; Figure 17A is a timing diagram of control operations on selected cache latches in a data dump operation according to some embodiments; Figure 17B is a timing diagram of control operations on unselected cache latches in a data dump operation according to some embodiments; Figure 18 is according to some embodiments Figure 17A and Figure 17B detailed timing diagram of a data dump operation; Figure 19A is a timing diagram of control operations on selected cache latches in a data dump operation according to some embodiments; Figure 19Bis a timing diagram of control operations for unselected cache latches in a data dump operation according to some embodiments; Figure 20 is according to some embodiments Figure 19A and Figure 19B detailed timing diagram of a data dump operation; Figure 21A is a timing diagram of control operations for selected cache latches in a data dump operation according to some embodiments; Figure 21B is a timing diagram of control operations for unselected cache latches in a data dump operation according to some embodiments; Figure 22 illustrates a discharge operation according to some embodiments; Figure 23A is a timing diagram of control operations for selected cache latches in a data dump operation according to some embodiments; Figure 23B is a timing diagram of control operations for unselected cache latches in a data dump operation according to some embodiments; Figure 24A is a timing diagram of control operations for selected cache latches in a data dump operation according to some embodiments; Figure 24B is a timing diagram of control operations for unselected cache latches in a data dump operation according to some embodiments; Figure 25 illustrates the structure of a memory device according to some embodiments; and Figure 26 is a cross-sectional view of a B-VNAND structure according to some embodiments. Detailed Embodiments

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used to denote the same elements in the drawings, and the repeated description thereof is omitted.

[0010] Figure 1 is a block diagram of a memory device 100 according to some embodiments. Referring to Figure 1 , the memory device 100 includes a memory cell array 110 and a peripheral circuit PECT, and the peripheral circuit PECT includes a page buffer circuit 120, a control logic circuit 130, a voltage generator 140, and a row decoder 150. As used herein, the memory device 100 may be referred to as a "non-volatile memory device".

[0011] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz (z is a positive integer), and each of the plurality of memory blocks BLK1 to BLKz includes memory cells. For example, the memory cells may be flash memory cells. Hereinafter, an embodiment in which the memory cells are NAND flash memory cells will be described in detail. However, the disclosure is not limited thereto. In some embodiments, the memory cells may include resistive memory cells (such as resistive RAM (ReRAM) cells), phase change RAM (PRAM) cells, or magnetic RAM (MRAM) cells).

[0012] The page buffer circuit 120 includes page buffers PB. Each of the page buffers PB can be connected to the memory cells of the memory cell array 110 through its corresponding bit line BL. The page buffer circuit 120 can select some of the bit lines BL in response to the column address Y_ADDR received from the control logic circuit 130. Each of the page buffers PB can operate as a write driver or a sense amplifier. For example, during a programming operation, each of the page buffers PB can store the data DATA in the memory cells by applying a voltage corresponding to the data DATA to be programmed to the bit line BL. For example, during a program verify operation or a read operation, each of the page buffers PB can sense the programmed data DATA by sensing the current or voltage of the bit line BL.

[0013] According to some embodiments, the page buffer PB may be arranged to have a multi-level structure, and each of the page buffers PB may have a page buffer unit-cache latch separation structure, in which the page buffer unit (such as Figure 4 PBU in Figure 4 including a main latch (such as M_LAT in Figure 4 )) is separated from the cache latch (such as CL in Figure 4 ). In the multi-level structure, a plurality of cache latches arranged in a row can share a combined sense node (such as SOC in Figure 4 ), and thus, the page buffer circuit 120 can be implemented as a shared SOC structure. To reduce the area of the page buffer circuit 120, the number of transistors included in the cache latch of each of the page buffers PB can be reduced compared to the number of transistors included in a typical cache latch. In this case, various control operations of the page buffer PB are described in detail with reference to Figures 7 to 24B .

[0014] The control logic circuit 130 may output a voltage control signal CTRL_vol, a row address X_ADDR, and a column address Y_ADDR based on, for example, a command CMD, an address ADDR, and a control signal CTRL received from a memory controller to perform a memory operation (e.g., a programming operation, a read operation, and / or an erase operation) on the memory cell array 110. The voltage generator 140 may generate a word line voltage VWL for performing the memory operation based on the voltage control signal CTRL_vol. In response to the row address X_ADDR received from the control logic circuit 130, the row decoder 150 may select one of the memory blocks BLK1 to memory blocks BLKz, select one of the word lines WL of the selected memory block, and select one of the string select lines SSL.

[0015] Figure 2 is a circuit diagram of a memory block BLK according to some embodiments. Referring to Figure 2 , the memory block BLK may correspond to Figure 1 one of the memory blocks BLK1 to memory blocks BLKz of

[0016] The memory block BLK includes NAND strings NS11 to NS33. Each of the NAND strings NS11 to NS33 (e.g., NS11) includes a series-connected string select transistor SST, a memory cell MC, and a ground select transistor GST. The string select transistors SST, the ground select transistors GST, and the memory cells MC included in each of the NAND strings NS11 to NS33 may be stacked on a substrate in a vertical direction.

[0017] A suitable configuration of a three-dimensional memory cell array is disclosed by reference to the following patent documents incorporated herein by reference, in which the three-dimensional memory cell array is configured as multiple layers using word lines and / or bit lines shared between the layers: U.S. Patent No. 7,679,133; U.S. Patent No. 8,553,466; U.S. Patent No. 8,654,587; U.S. Patent No. 8,559,235; and U.S. Patent Publication No. 2011 / 0233648.

[0018] Figure 3 Shows the connection of the memory cell array 110 to the page buffer circuit 120 according to some embodiments. Refer to Figure 3 , the memory cell array 110 includes first to (n + 1)th NAND strings NS0 to NSn, and each of the first to (n + 1)th NAND strings NS0 to NSn includes a ground selection transistor GST connected to a ground selection line GSL, memory cells MC respectively connected to word lines WL0 to WLm, and a string selection transistor SST connected to a string selection line SSL (each of n and m is a positive integer).

[0019] The page buffer circuit 120 includes first to (n + 1)th page buffer units PBU0 to PBUn. The first page buffer unit PBU0 can be connected to the first NAND string NS0 through a first bit line BL0, and the (n + 1)th page buffer unit PBUn can be connected to the (n + 1)th NAND string NSn through an (n + 1)th bit line BLn. The page buffer circuit 120 may further include first to (n + 1)th cache latches CL0 to CLn, and the first to (n + 1)th cache latches CL0 to CLn respectively correspond to the first to (n + 1)th page buffer units PBU0 to PBUn. For example, n may be 7, and the page buffer circuit 120 may have a structure in which the page buffer units PBU0 to PBU7 are arranged in a row in eight stages and the cache latches CL0 to CL7 are arranged in a row in eight stages.

[0020] The corresponding sense nodes of the first to (n + 1)th page buffer units PBU0 to PBUn can be commonly connected to a combined sense node SOC, and the first to (n + 1)th cache latches CL0 to CLn can also be commonly connected to the combined sense node SOC. Therefore, the first to (n + 1)th page buffer units PBU0 to PBUn can be connected to the first to (n + 1)th cache latches CL0 to CLn through the combined sense node SOC.

[0021] Figure 4 Is a circuit diagram of a page buffer PB according to some embodiments. Refer to Figure 4 , the page buffer PB can correspond to Figure 1 An example of the page buffer PB. The page buffer PB includes a page buffer unit PBU and a cache latch CL. Since the cache latch CL is connected to a data input / output (I / O) line, the cache latch CL can be adjacent to the data I / O line. Therefore, the page buffer unit PBU and the cache latch CL can be separated from each other, and the page buffer PB can have a structure in which the page buffer unit PBU is separated from the cache latch CL.

[0022] The page buffer unit PBU includes a main latch M_LAT, a bit line cut-off transistor NM, a precharge transistor PM, and a transfer transistor TR. The bit line cut-off transistor NM can be connected to the bit line BL and can be driven in response to a bit line cut-off signal BLSHF. When the bit line cut-off transistor NM is turned on, the sense node SO can be connected to the bit line BL. The precharge transistor PM can be driven in response to a load signal LOAD, and the sense node SO can be precharged when the precharge transistor PM is turned on. The transfer transistor TR can be driven in response to a transfer control signal SO_PASS. When the transfer transistor TR is turned on, the sense node SO can be connected to a first terminal SOC_U and a second terminal SOC_D.

[0023] Figure 5 is a detailed circuit diagram of a page buffer PB according to some embodiments. Referring to Figure 5 , the page buffer PB includes a page buffer unit PBU and a cache latch CL, and the cache latch CL includes a latch (C-LATCH) C_LAT. The page buffer PB can correspond to Figure 4 an example of the page buffer PB. The page buffer unit PBU includes a main unit MU. The page buffer unit PBU may further include a bit line selection transistor TR_hv, which is connected to the bit line BL and is driven in response to a bit line selection signal BLSLT. The bit line selection transistor TR_hv can be implemented as a high-voltage transistor and is located in a different well region (i.e., a high-voltage unit HVU) from the main unit MU.

[0024] The main unit MU includes a sense latch (S-LATCH) SL, a force latch (F-LATCH) FL, a high-order latch (M-LATCH) ML, and a low-order latch (L-LATCH) LL. Figure 4 The main latch M_LAT of

[0025] During a read operation or a program verify operation, the sense latch SL may store the data stored in the memory cell or the sensing result of the threshold voltage of the memory cell. During a program operation, the sense latch SL may be used to apply a program bit line voltage or a program inhibit voltage to the bit line BL. The force latch FL may store force data and be used to improve the threshold voltage distribution during a program operation. The high-order latch ML, the low-order latch LL, and the cache latch CL may be used to store external input data during a program operation. During a read operation, the cache latch CL may receive the data read from the memory cell from the sense latch SL, and output the received data to the outside through the data I / O line.

[0026] The precharge circuit PC may control the precharge operation of the bit line BL or the sense node SO based on the bit line clamp control signal BLCLAMP. The transistor PM' may be driven in response to the bit line setup signal BLSETUP, the transistor NM5 may be driven in response to the bit line cut-off signal BLSHF, and the transistor NM6 may be driven in response to the bit line connection control signal CLBLK. The precharge transistor PM may be connected to the sense node SO, be driven in response to the load signal LOAD, and precharge the sense node SO during a precharge period (section) (e.g., Figure 18 PRECH).

[0027] The main unit MU may further include a pair of transfer transistors (e.g., a first transfer transistor TR and a second transfer transistor TR'), and the pair of transfer transistors are connected to the sense node SO. The first transfer transistor TR and the second transfer transistor TR' may be driven in response to the transfer control signal SO_PASS. The first transfer transistor TR may be connected between the first terminal SOC_U and the sense node SO, and the second transfer transistor TR' may be connected between the sense node SO and the second terminal SOC_D. For example, when the page buffer unit PBU is Figure 8 the second page buffer unit PBU1, the first terminal SOC_U may be connected to one end of the transfer transistor included in the first page buffer unit PBU0, and the second terminal SOC_D may be connected to one end of the transfer transistor included in the third page buffer unit. Therefore, the sense node SO may be electrically connected to the combined sense node SOC through the transfer transistors respectively included in the third page buffer unit to the (n + 1)-th page buffer unit.

[0028] Figure 6 is a detailed circuit diagram of a page buffer PB' according to some embodiments. Referring to Figure 6 the page buffer PB' includes a page buffer unit PBU' and a cache latch CL, and the page buffer unit PBU' includes a main unit MU' and a high voltage unit HVU. The page buffer PB' may correspond toFigure 5 An example of modification of the page buffer PB. Figure 5 The page buffer unit PBU includes a first transfer transistor TR and a second transfer transistor TR', while the page buffer unit PBU' according to some embodiments may include one transfer transistor TR''. The transfer transistor TR' may be driven in response to a transfer control signal SO_PASS and is connected between a first terminal SOC_U and a second terminal SOC_D. For example, the source of the transfer transistor TR'' may be connected to the first terminal SOC_U, and the drain of the transfer transistor TR'' may be connected to the sense node SO and the second terminal SOC_D. However, the disclosure is not limited thereto, and the source of the transfer transistor TR'' may be connected to the first terminal SOC_U and the sense node SO, and the drain of the transfer transistor TR'' may be connected to the second terminal SOC_D.

[0029] Figure 7 A timing diagram showing an example of the voltage level of the transfer control signal in the core operation sequence according to some embodiments. Referring together to Figure 4 and Figure 7 , the core operation sequence may indicate the operation of the page buffer PB. For example, the core operation sequence includes a data sensing period 71 in which a data sensing operation is performed and a data dump period 72 in which a data dump operation or a data transfer operation is performed.

[0030] During the data sensing period 71, the transfer control signal SO_PASS may be disabled, and the transfer transistor TR may be turned off. Thus, the page buffer unit PBU may not be electrically connected to the combined sense node SOC, and the page buffer unit PBU may not be electrically connected to the cache latch CL. In addition, the page buffer unit PBU may not be electrically connected to an adjacent page buffer unit. For example, the data sensing period 71 may include a precharging period in which the voltage of the bit line BL or the sense node SO is precharged to a precharging level, a developing period in which the voltage of the sense node SO is developed by electrically connecting the bit line BL to the sense node SO, and a sensing period in which the voltage of the sense node SO is sensed.

[0031] During the data dump period 72, the transmission control signal SO_PASS may be enabled, and the transmission transistor TR may be turned on. Accordingly, the page buffer unit PBU may be electrically connected to the combined sense node SOC, and the page buffer unit PBU may be electrically connected to the cache latch CL. In addition, the page buffer unit PBU may be electrically connected to an adjacent page buffer unit. For example, the data dump period 72 may include a period in which an operation of dumping read data stored in the main latch M_LAT to the cache latch CL is performed, a period in which an operation of dumping programmed data stored in the cache latch CL to the main latch M_LAT is performed, or a period in which data stored in the cache latch CL is transferred to the data I / O circuit.

[0032] Figure 8 Shows a multi-stage structure of the page buffer circuit 120 according to some embodiments.

[0033] Referring Figure 8 , the page buffer circuit 120 includes a first page buffer unit PBU0 to an eighth page buffer unit PBU7 and a first cache latch CL0 to an eighth cache latch CL7. Each of the first page buffer unit PBU0 to the eighth page buffer unit PBU7 may include at least one transmission transistor, and the transmission transistor may be driven in response to the transmission control signal SO_PASS[7:0]. For example, the first page buffer unit PBU0 includes a first transmission transistor TRa connected to the first sense node SO0, the second page buffer unit PBU1 includes a second transmission transistor TRb connected to the second sense node SO1, and the eighth page buffer unit PBU7 includes an eighth transmission transistor TRc connected to the eighth sense node SO7. When the transmission control signal SO_PASS[7:0] is enabled, the first transmission transistor TRa to the eighth transmission transistor TRc may be turned on. Accordingly, the first transmission transistor TRa to the eighth transmission transistor TRc may be connected in series with each other, and the first sense node SO0 to the eighth sense node SO7 may be connected to each other.

[0034] The page buffer circuit 120 may further include a transfer transistor TRd. The transfer transistor TRd may be driven in response to a transfer control signal SOC_PASS, and when the transfer transistor TRd is turned on, the combined sense node SOC may be connected to the first sense node SO0 to the eighth sense node SO7. When the first transfer transistor TRa to the eighth transfer transistor TRc and the transfer transistor TRd are turned on, the first sense node SO0 to the eighth sense node SO7 and the combined sense node SOC may be connected to each other to form a "data transmission line". As described above, according to some embodiments, the page buffer circuit 120 may not need to separately include eight data transmission lines configured to connect the first page buffer unit PBU0 to the eighth page buffer unit PBU7 to the first cache unit CU0 to the eighth cache unit CU7, respectively, and signal lines corresponding to the sense nodes included in each of the first page buffer unit PBU0 to the eighth page buffer unit PBU7 may be used as data transmission lines. As a result, the number of metal lines required for the wiring of the page buffer circuit 120 may be reduced, and thus, the size of the page buffer circuit 120 may be reduced.

[0035] Each of the first cache latch CL0 to the eighth cache latch CL7 may include a monitor transistor, and the monitor transistor may be driven in response to a cache monitor signal MON_C[7:0]. For example, the first cache latch CL0 includes a first monitor transistor NMa, the second cache latch CL1 includes a second monitor transistor NMb, and the eighth cache latch CL7 includes an eighth monitor transistor NMc. The first monitor transistor NMa to the eighth monitor transistor NMc included in the first cache latch CL0 to the eighth cache latch CL8 may be connected in parallel with each other and commonly connected to the combined sense node SOC. Specifically, the respective sources of the first monitor transistor NMa to the eighth monitor transistor NMc may be commonly connected to the combined sense node SOC.

[0036] The first page buffer unit PBU0 to the eighth page buffer unit PBU7 may also include precharge transistors PMa to PMc, respectively. For example, in the first page buffer unit PBU0, the precharge transistor PMa may be connected between a precharge terminal to which a voltage having a precharge level is applied and a first sense node SO0, and have a gate to which a load signal LOAD is applied. The precharge transistor PMa may precharge the voltage of the first sense node SO0 to the precharge level in response to the load signal LOAD. The page buffer circuit 120 may also include a precharge transistor PMd. The precharge transistor PMd may be connected between the precharge terminal and a combined sense node SOC, and have a gate to which a load signal LOAD is applied. The precharge transistor PMd may precharge the voltage of the combined sense node SOC to the precharge level in response to the load signal LOAD.

[0037] Figure 9 Shows the connection of the master latch to the cache latch according to some embodiments.

[0038] Referring to Figure 9 , the page buffer circuit 120a may include a plurality of master latches and a plurality of cache latches. The plurality of master latches include a first master latch M0 to a fourth master latch M3, and the plurality of cache latches include a first cache latch C0 to a fourth cache latch C3. Although the first master latch M0 to the fourth master latch M3 and the first cache latch C0 to the fourth cache latch C3 are shown for simplicity, the page buffer circuit 120a may be implemented as an eight-stage structure, in which the first master latch to the eighth master latch and the first cache latch to the eighth cache latch are arranged in a row as shown in Figure 8 . However, the disclosure is not limited thereto. For example, the page buffer circuit 120a may be implemented in various stages (such as a four-stage structure or a six-stage structure).

[0039] The transfer transistor TRd may be between the first master latch M0 to the fourth master latch M3 and the first cache latch C0 to the fourth cache latch C3. The transfer transistor TRd may be driven in response to a transfer control signal SOC_PASS, and corresponds to, for example, Figure 8 the transfer transistor TRd. For example, the transfer transistor TRd may be turned off during the data sensing period 71 of Figure 7 . For example, during the data dump period 72 of Figure 7 , the transfer transistor TRd may be turned on, and the combined sense node SOC may be connected to the corresponding sense nodes of the first master latch M0 to the fourth master latch M3.

[0040] The first master latch M0 to the fourth master latch M3 can be commonly connected to the combinational sense node SOC through transfer transistors TRd. Each of the first master latch M0 to the fourth master latch M3 can correspond to, for example, Figure 4 the master latch LT or Figure 5 and Figure 6 the sense latch SL, the forced latch FL, the high-order latch ML, or the low-order latch LL. The first cache latch C0 to the fourth cache latch C3 can be commonly connected to the combinational sense node SOC. In addition, the first cache latch C0 to the fourth cache latch C3 can be respectively connected to the first transistor TR0 to the fourth transistor TR3. For example, the first cache latch C0 and the first transistor TR0 can correspond to Figure 4 , Figure 5 and Figure 6 the cache latch CL or Figure 8 the first cache latch CL0.

[0041] The gate of each of the first transistor TR0 to the fourth transistor TR3 can be connected to the combinational sense node SOC, and the first transistor TR0 to the fourth transistor TR3 can be turned on or off according to the voltage of the combinational sense node SOC. For example, during the data dump operation of the first cache latch C0, that is, when data is transferred from the first master latch M0 to the first cache latch C0, the first cache latch C0 can be the selected cache latch, and the remaining cache latches including the second cache latch C1 to the fourth cache latch C3 can be the unselected cache latches. For example, when the voltage of the combinational sense node SOC is at a high level, the first transistor TR0 to the fourth transistor TR3 can all be turned on, and thus, the data previously stored in the unselected second cache latch C1 to the fourth cache latch C3 can be corrupted.

[0042] Figure 10 is the circuit diagram of the first cache latch C0 according to some embodiments. Referring to Figure 10 , the first cache latch C0 can correspond to Figure 9 the first cache latch C0. The configuration of the first cache latch C0 described below can also be applied to include Figure 9The other cache latches of the second cache latch C1 to the fourth cache latch C3. The first cache latch C0 includes a first tri-state inverter INV1 and a second tri-state inverter INV2, and the first tri-state inverter INV1 and the second tri-state inverter INVT2 can be cross-coupled to each other between a first node ND1 and a second node ND2. The first tri-state inverter INV1 can generate an output signal by inverting an input signal received from the first node ND1, and provide the generated output signal to the second node ND2. The second tri-state inverter INV2 can generate an output signal by inverting an input signal received from the second node ND2, and provide the generated output signal to the first node ND1. Therefore, the first tri-state inverter INV1 and the second tri-state inverter INV2 cross-coupled to each other can form a latch (e.g., Figure 5 C_LAT in

[0043] The first tri-state inverter INV1 includes a PMOS transistor PM1, a PMOS transistor PM2, and an NMOS transistor NM11, and the PMOS transistor PM1, the PMOS transistor PM2, and the NMOS transistor NM11 are connected in series. The PMOS transistor PM1 can include a gate configured to receive a reset control signal nCRST and a source configured to receive a power supply voltage. The PMOS transistor PM2 can include a gate connected to the first node ND1 and a drain connected to the second node ND2. The NMOS transistor NM11 can include a gate connected to the first node ND1, a source configured to receive a ground voltage, and a drain connected to the second node ND2. The first tri-state inverter INV1 can be driven in response to the reset control signal nCRST. For example, when the reset control signal nCRST is at an active level, the first tri-state inverter INV1 can be enabled and perform an inversion operation. For example, when the reset control signal nCRST is at an inactive level, the first tri-state inverter INV1 can be disabled and not perform an inversion operation.

[0044] The second tri-state inverter INV2 includes PMOS transistor PM3, PMOS transistor PM4, and NMOS transistor NM12, and PMOS transistor PM3, PMOS transistor PM4, and NMOS transistor NM12 are connected in series. PMOS transistor PM3 may include a gate configured to receive a set control signal nCSET and a source configured to receive a power supply voltage. PMOS transistor PM4 may include a gate connected to the second node ND2 and a drain connected to the first node ND1. NMOS transistor NM12 may include a gate connected to the second node ND2, a source configured to receive a ground voltage, and a drain connected to the first node ND1. The second tri-state inverter INV2 may be driven in response to the set control signal nCSET. For example, when the set control signal nCSET is at an active level, the second tri-state inverter INV2 may be enabled and perform an inversion operation. For example, when the set control signal nCSET is at an inactive level, the second tri-state inverter INV2 may be disabled and may not perform an inversion operation.

[0045] The configurations of the first tri-state inverter INV1 and the second tri-state inverter INV2 may vary according to some embodiments. For example, the number of PMOS transistors and / or the number of NMOS transistors in each of the first tri-state inverter INV1 and the second tri-state inverter INV2 may vary according to some embodiments. The modified embodiments of the first tri-state inverter INV1 and the second tri-state inverter INV2 will be described in more detail with reference to Figure 11 Modify the embodiments of the first tri-state inverter INV1 and the second tri-state inverter INV2.

[0046] The first cache latch C0 may further include a first monitoring transistor NMa. The first monitoring transistor NMa may be driven in response to a cache monitoring signal MON_C and control the connection between the combined sense node SOC and the first node ND1. However, the disclosure is not limited thereto. For example, as Figure 5 and Figure 6 In the embodiments shown, the first monitoring transistor NMa may be defined as a component external to the first cache latch C0. In this case, the first monitoring transistor NMa may control the connection between the combined sense node SOC and the first cache latch C0.

[0047] The first cache latch C0 may further include a set transistor NM13 and a reset transistor NM14. The set transistor NM13 may be driven in response to a set signal or a data signal DI, and the reset transistor NM14 may be driven in response to a reset signal or a data inverted signal nDI. The voltage levels of the first node ND1 and the second node ND2 may be determined according to the data signal DI and the data inverted signal nDI.

[0048] Figure 11is a circuit diagram of a first cache latch C0' according to some embodiments. Referring to Figure 11 , the first cache latch C0' may correspond to Figure 10 a modified example of the first cache latch C0 of Figure 10 , and the descriptions provided above with reference to

[0049] may also be applied to the illustrated embodiments. The first cache latch C0' includes a first tri-state inverter INV1' and a second tri-state inverter INV2'. As compared with the first tri-state inverter INV1, the first tri-state inverter INV1' may further include an NMOS transistor NM11'. The NMOS transistors NM11 and NM11' may be connected in series with each other. The NMOS transistor NM11 may include a gate connected to a first node ND1 and a drain connected to a second node ND2. The NMOS transistor NM11' may include a gate configured to receive a control signal CONa and a source configured to receive a ground voltage. In this case, the control signal CONa may correspond to a conduction voltage for turning on the NMOS transistor NM11'.

[0050] Figure 12 is a circuit diagram of a plurality of cache latches according to some embodiments. Referring to Figure 12 , the first cache latch C0 may correspond to Figure 10 the first cache latch C0 of Figure 10 and Figure 11 , and the descriptions provided above with reference to

[0051] When the reset control signal nCRST[0] is at the active level, the first tri-state inverter INV1 can be enabled and output the second node data LAT_C0 to the second node ND2 by inverting the voltage of the first node ND1 (i.e., the first node data LAT_nC0). In addition, when the reset control signal nCRST[0] is at the inactive level, the first tri-state inverter INV1 can be disabled, the second node data LAT_C0 can be maintained at the previous value without being affected by the first node data LAT_nC0, and the voltage of the second node ND2 can be maintained at the previous voltage level.

[0052] When the set control signal nCSET[0] is at the active level, the second tri-state inverter INV2 can be enabled and output the first node data LAT_nC0 to the first node ND1 by inverting the voltage of the second node ND2 (i.e., the second node data LAT_C0). When the set control signal nCSET[0] is at the inactive level, the second tri-state inverter INV2 can be disabled, the first node data LAT_nC0 can be maintained at the previous value without being affected by the second node data LAT_C0, and the voltage of the first node ND1 can be maintained at the previous voltage level.

[0053] The second cache latch C1 includes a third tri-state inverter INV3 and a fourth tri-state inverter INV4, which are cross-coupled to each other between the third node ND3 and the fourth node ND4. The third tri-state inverter INV3 can be driven in response to the reset control signal nCRST[1], and the fourth tri-state inverter INV4 can be driven in response to the set control signal nCSET[1]. The second monitoring transistor NMb can be driven in response to the cache monitoring signal MON_C[1] and control the connection between the combined sense node SOC and the third node ND3. The set transistor NM13' can be driven in response to the set signal or the data signal DI, and the reset transistor NM14' can be driven in response to the reset signal or the data inverted signal nDI.

[0054] When the reset control signal nCRST[1] is at the active level, the third tri-state inverter INV3 can be enabled and output the fourth node data LAT_C1 to the fourth node ND4 by inverting the voltage of the third node ND3 (i.e., the third node data LAT_nC1). When the reset control signal nCRST[1] is at the inactive level, the third tri-state inverter INV3 can be disabled, the fourth node data LAT_C1 can be maintained at the previous value without being affected by the third node data LAT_nC1, and the voltage of the fourth node ND4 can be maintained at the previous voltage level.

[0055] When the set control signal nCSET[1] is at the active level, the fourth tri-state inverter INV4 can be enabled and output the third node data LAT_nC1 to the third node ND3 by inverting the voltage of the fourth node ND4 (i.e., the fourth node data LAT_C1). When the set control signal nCSET[1] is at the inactive level, the fourth tri-state inverter INV4 can be disabled, the third node data LAT_nC1 can be maintained at the previous value without being affected by the fourth node data LAT_C1, and the voltage of the third node ND3 can be maintained at the previous voltage level.

[0056] Conventionally, each cache latch may further include a dump transistor. For example, a dump transistor may be arranged between the first transistor TR0 and the set transistor NM13, and a dump transistor may be arranged between the second transistor TR1 and the set transistor NM13'. In this case, by turning on the dump transistor included in the selected cache latch and turning off the dump transistor included in the unselected cache latch, only the selected cache latch can be discharged, and the unselected cache latch cannot be discharged. However, according to some embodiments, each cache latch may not include a dump transistor, and by separately controlling the tri-state inverters (e.g., INV1 and INV2) included in the selected cache latch (e.g., C0) and the tri-state inverters (e.g., INV3 and INV4) included in the unselected cache latch (e.g., C1), a data dump operation for the selected cache latch can be supported. Therefore, according to some embodiments, the implementation area of each cache latch can be reduced, and thus, the area of the page buffer circuit can be reduced.

[0057] Figure 13 Shows a data dump operation according to some embodiments.

[0058] Referring to Figure 13 , the data dump operation may include an operation of transferring data from the selected page buffer unit or the selected master latch to the selected cache latch, and may be performed, for example, during Figure 7 the data dump period 72. For example, the selected cache latch may be the first cache latch C0, and the unselected cache latches may be the remaining cache latches including the second cache latch C1 to the fourth cache latch C3.

[0059] A data dump operation can be performed during a time period including a first period and a second period. In the first period of the data dump operation, a discharging operation can be performed on a plurality of cache latches including a first cache latch C0 to a fourth cache latch C3 commonly connected to a combined sense node SOC. Accordingly, the first period can be referred to as a "discharge period DISCHARGE". In the first period, first transistors TR0 to fourth transistors TR3 can all be turned on according to the voltage level of the combined sense node SOC, and thus, the plurality of cache latches can be discharged.

[0060] In the second period of the data dump operation (that is, in the second period after the first period), a sensing operation can be performed on the data transmitted from the selected first cache latch C0, and a recovery operation or a repair operation (i.e., a data recovery operation) can be performed on the corrupted data in the unselected second cache latch C1 to fourth cache latch C3. Accordingly, the second period can be referred to as a "recovery period RCY". In the second period, the operation of controlling the first cache latch C0 can be different from the operation of controlling the second cache latch C1 to fourth cache latch C3 as described in detail below with reference to Figures 14A to 24B the operation of controlling the second cache latch C1 to fourth cache latch C3 as described in detail below with reference to

[0061] Figure 14A is a timing diagram of a control operation of a selected cache latch in a data dump operation according to some embodiments. Figure 14B is a timing diagram of a control operation of an unselected cache latch in a data dump operation according to some embodiments.

[0062] Referring together to Figure 13 、 Figure 14A and Figure 14B , for example, in an eight-stage page buffer structure, eight cache latches can be commonly connected to a combined sense node SOC. When a data dump operation is performed on the selected first cache latch C0, the control operation of a tri-state inverter included in the selected first cache latch C0 can be different from the control operation of a tri-state inverter included in each of the unselected cache latches (e.g., the second cache latch to the eighth cache latch).

[0063] In the data dump operation of the selected first cache latch C0, the set control signal nCSET[0] and the reset control signal nCRST[0] applied to the selected first cache latch C0 may be at an active level (e.g., low level). Thus, the first tri-state inverter INV1 and the second tri-state inverter INV2 included in the first cache latch C0 may be enabled. Further, at the first time point T1, the set control signal nCSET[7:1] and the reset control signal nCRST[7:1] applied to the unselected cache latches may transition from the active level to the inactive level (e.g., high level). Thus, the tri-state inverters (e.g., the third tri-state inverter INV3 and the fourth tri-state inverter INV4 included in the second cache latch C1) included in each of the unselected cache latches may be disabled.

[0064] At the second time point T2, the set signal or the data signal DI may transition from the inactive level to the active level (e.g., high level). Thus, the period during which the set signal or the data signal DI is maintained at the active level may be defined as the "discharge period", and the discharge period may correspond to Figure 13 the first period DISCHARGE. During the discharge period or the first period, the first cache latch C0 to the fourth cache latch C3 may be discharged. Hereinafter, the discharge operation of the cache latches during the discharge period will be described with reference to Figure 15 FIGS.

[0065] Figure 15 FIGS. 11A to 11C illustrate a discharge operation according to some embodiments.

[0066] Referring together to Figure 14A FIG. Figure 14B 11A Figure 15 FIG. 11B and FIG. 11C, at the second time point T2, when the set signal or the data signal DI reaches the active level, the set transistors NM13 and NM13' may be turned on. When the voltage of the combined sense node SOC is at the high level H, both the first transistor TR0 and the second transistor TR1 may be turned on. Thus, in the selected first cache latch C0, a discharge path may be generated through the first transistor TR0 and the set transistor NM13, and the voltage of the first node ND1 (i.e., the first node data LAT_nC0) may reach the low level L. In this case, since the set control signal nCSET[0] and the reset control signal nCRST[0] are at the active level, the first tri-state inverter INV1 and the second tri-state inverter INV2 may all be enabled and each perform an inversion operation. Thus, due to the inversion operation of the first tri-state inverter INV1, the second node data LAT_C0 may reach the high level H, and due to the inversion operation of the second tri-state inverter INV2, the first node data LAT_nC0 may be maintained at the low level L.

[0067] In addition, in the unselected second cache latch C1 that is about to be, a discharge path can also be generated by the second transistor TR1 and the set transistor NM13', and the voltage of the third node ND3 (i.e., the third node data LAT_nC1) can reach the low level L. In this case, since the set control signal nCSET[1] and the reset control signal nCRST[1] are at the disabled level, both the third tri-state inverter INV3 and the fourth tri-state inverter INV4 can be disabled and do not perform an inversion operation. Therefore, although the third node data LAT_nC1 is damaged, the fourth node data LAT_C1 can be maintained at the previous value, and the voltage of the fourth node ND4 can be maintained at, for example, the low level L.

[0068] At the third time point T3, the set control signal nCSET[7:1] applied to the unselected cache latch can transition from the disabled level to the enabled level (e.g., low level). Therefore, the tri-state inverters included in each of the unselected cache latches (e.g., the fourth tri-state inverter INV4 included in the second cache latch C1) can be enabled. As a result, the fourth tri-state inverter INV4 can change or restore the third node data LAT_nC1 to the high level by inverting the undamaged fourth node data LAT_C1.

[0069] At the fourth time point T4, the reset control signal nCRST[7:1] applied to the unselected cache latch can transition from the disabled level to the enabled level (e.g., low level). Therefore, the tri-state inverters included in each of the unselected cache latches (e.g., the third tri-state inverter INV3 included in the second cache latch C1) can be enabled. As a result, the third tri-state inverter INV3 can invert the restored third node data LAT_nC1, and thus, the fourth node data LAT_C1 can be maintained at the previous value, and the voltage of the fourth node ND4 can be maintained at, for example, the low level L.

[0070] According to some embodiments, after the discharge period of the data dump operation, the set control signal nCSET[7:1] and the reset control signal nCRST[7:1] applied to the unselected cache latch can sequentially transition to the enabled level. Therefore, the tri-state inverters included in the unselected cache latches can be sequentially enabled. For example, enabling the fourth tri-state inverter INV4 included in the second cache latch C1 can be followed by enabling the third tri-state inverter INV3. By sequentially enabling the fourth tri-state inverter INV4 and the third tri-state inverter INV3, the data previously stored in the second cache latch C1 can be restored.

[0071] Since a data recovery operation is performed on unselected cache latches after the third time point T3, the period after the third time point T3 can be defined as a "recovery period", and the recovery period can correspond to Figure 13 the second period RCY. Since a sensing operation is performed on the data transferred to the selected first cache latch after the third time point T3, the period after the third time point T3 can be defined as a "sensing period", and the sensing period can correspond to Figure 13 the second period RCY. Therefore, the recovery period and the sensing period can correspond to the same time period (e.g., the data recovery period DATA_RCY).

[0072] Figure 16 is according to some embodiments Figure 14A and Figure 14B detailed timing diagram of the data dump operation.

[0073] Refer together to Figure 8 、 Figure 15 and Figure 16 , for example, in an eight-stage page buffer structure, eight cache latches can be commonly connected to a combined sensing node SOC. The data dump operation can be performed during a time period including a precharge period PRECH, a discharge period DISCH, and a recovery period RCY. The precharge period PRECH can correspond to the time period from the first time point t1 to the second time point t2, the discharge period DISCH can correspond to the time period from the fourth time point t4 to the sixth time point t6, and the recovery period RCY can correspond to the time period after the sixth time point t6. For example, the discharge period DISCH can correspond to Figure 13 the first period DISCHARGE, and the recovery period RCY can correspond to Figure 13 the second period RCY. Hereinafter, the control signals applied to the page buffer circuit in the data dump operation are described in detail.

[0074] At a first time point t1, the load signal LOAD can transition to a low level as an enabling level. At a second time point t2, the load signal LOAD can transition to a high level as a disabling level. During a precharge period PRECH, the load signal LOAD can be maintained at the enabling level. Accordingly, the precharge transistors PMa to PMd can be turned on, and thus, the first sense nodes SO0 to the eighth sense nodes SO7 and the combined sense node SOC can be precharged. The transfer control signal SOC_PASS can transition to a high level as an enabling level during the precharge period PRECH, and transition to a low level as a disabling level at a seventh time point t7. When the transfer control signal SOC_PASS is maintained at the enabling level, the transfer transistor TRd can be turned on, and thus, the combined sense node SOC can be connected to the first sense nodes SO0 to the eighth sense nodes SO7.

[0075] At a third time point t3, the set control signals nCSET[7:1] and the reset control signals nCRST[7:1] applied to the unselected cache latches can transition to a high level as a disabling level. As a result, the tri-state inverters (e.g., the third tri-state inverter INV3 and the fourth tri-state inverter INV4 included in the second cache latch C1) included in the unselected cache latches can be disabled. At a fourth time point t4, the set signal or the data signal DI can transition to a high level as an enabling level. At a fifth time point t5, the set signal or the data signal DI can transition to a low level as a disabling level.

[0076] When the data signal DI transitions to the enabling level, a discharge operation can be performed in the cache latches CL0 to CL7 connected to the combined sense node SOC. In this case, due to the inverting operation of the enabled first tri-state inverter INV1, the first node data LAT_nC0 of the first cache latch CL0 can reach a low level, and the second node data LAT_C0 can reach a high level. In addition, the third node data LAT_nC_unsel of the unselected cache latch (e.g., the third node data LAT_nC1 of the second cache latch C1) can reach a low level, while the tri-state inverters included in the unselected cache latches can remain disabled. Accordingly, the fourth node data LAT_C_unsel of the unselected cache latch (e.g., the fourth node data LAT_C1 of the second cache latch C1) can be maintained at a low level without being damaged.

[0077] At the sixth time point t6, the set control signal nCSET[7:1] applied to the unselected cache latch may be transformed to an enable level. For example, the fourth tri-state inverter INV4 included in the second cache latch CL1 may be enabled, and the enabled fourth tri-state inverter INV4 may restore the third node data LAT_nC1 to a high level by inverting the fourth node data LAT_C1. At the seventh time point t7, the reset control signal nCRST[7:1] applied to the unselected cache latch may be transformed to an enable level. For example, the third tri-state inverter INV3 included in the second cache latch CL1 may be enabled, and the enabled third tri-state inverter INV3 may maintain the fourth node data LAT_C1 at a low level by inverting the third node data LAT_nC1.

[0078] According to some embodiments, the set control signal nCSET[7:1] and the reset control signal nCRST[7:1] applied to the unselected cache latches may be sequentially transitioned to an enable level, and the tri-state inverters included in the unselected cache latches may be sequentially enabled. As a result, data damaged by discharging the unselected cache latches may be restored to data previously stored in each of the unselected cache latches.

[0079] Figure 17A is a timing diagram of control operations on selected cache latches in a data dump operation according to some embodiments. Figure 17B FIG. 1 is a timing diagram of a control operation of an unselected cache latch in a data dump operation according to some embodiments. Figure 13 , Figure 17A and Figure 17B , some embodiments may correspond to Figure 14A and Figure 14B A modified example of Figures 14A to 16 The description provided is also applicable to the illustrated embodiment. Because the illustrated embodiment differs from the embodiment in terms of the control operation of the selected cache latch Figure 14A The present invention is an embodiment shown in FIG. 1 , so the following description will focus on the control operation of the selected cache latch.

[0080] In the data dump operation of the selected first cache latch C0, the reset control signal nCRST[0] may be at a low level as the enabling level, and the first tri-state inverter INV1 included in the first cache latch C0 may be enabled. At the first time point T1, the set control signal nCSET[0] may transition to a high level as the disabling level, and the second tri-state inverter INV2 may be disabled. Therefore, the power consumption of the first cache latch C0 can be reduced during the data dump operation. At the second time point T2, when the set signal or the data signal DI reaches the enabling level, the set transistor NM13 may conduct, and the first node data LAT_nC0 may reach the low level L. In this case, since the reset control signal nCRST[0] is at the enabling level, the first tri-state inverter INV1 may be enabled and perform an inversion operation. Through the inversion operation of the enabled first tri-state inverter INV1, the second node data LAT_C0 may reach the high level H.

[0081] At the first time point T1, the set control signals nCSET[7:1] and the reset control signals nCRST[7:1] may transition to a high level. At the second time point T2, when the set signal or the data signal DI reaches the enabling level, the set transistor NM13' may conduct, and the third node data LAT_nC1 may reach the low level L. At the third time point T3, when the set control signal nCSET[7:1] transitions to a low level, the fourth tri-state inverter INV4 may be enabled. Therefore, the fourth tri-state inverter INV4 may invert the undamaged fourth node data LAT_C1, and thus, the third node data LAT_nC1 may be restored to the high level. At the fourth time point T4, the reset control signal nCRST[7:1] may transition to a low level, and the third tri-state inverter INV3 may be enabled. As a result, the third tri-state inverter INV3 may invert the restored third node data LAT_nC1, and the fourth node data LAT_C1 may be maintained at the low level.

[0082] Figure 18 is according to some embodiments Figure 17A and Figure 17B a detailed timing diagram of the data dump operation. Referring together to Figure 8 、 Figure 15 and Figure 18 , some embodiments may correspond to Figure 16 a modified example of Figure 16 and the description provided above with reference to Figure 16 may also be applied to the illustrated embodiments. The following description will focus on the differences between the illustrated embodiments and

[0083] In the data dump operation of the selected first cache latch C0, the reset control signal nCRST[0] may be maintained at a low level, and therefore, the first tri-state inverter INV1 may be enabled. By the inversion operation of the enabled first tri-state inverter INV1, the second node data LAT_C0 may be transformed to a high level. At the third time point t3, the set control signal nCSET[0] may be transformed to a high level, and therefore, the second tri-state inverter INV2 may be disabled. As a result, the power consumption of the first cache latch C0 may be reduced. At the sixth time point t6, the set control signal nCSET[0] may be transformed to a low level, and therefore, the second tri-state inverter INV2 may be enabled. By the inversion operation of the enabled second tri-state inverter INV2, the first node data LAT_nC0 may be maintained at a low level.

[0084] Figure 19A is a timing diagram of control operations on selected cache latches in a data dump operation according to some embodiments. Figure 19B FIG. 1 is a timing diagram of a control operation of an unselected cache latch in a data dump operation according to some embodiments. Figure 13 , Figure 19A and Figure 19B , some embodiments may correspond to Figure 14A and Figure 14B A modified example of Figures 14A to 16 The description provided is also applicable to the illustrated embodiment. Because the illustrated embodiment differs from the embodiment in terms of the control operation of the selected cache latch Figure 14A The present invention is an embodiment shown in FIG. 1 , so the following description will focus on the control operation of the selected cache latch.

[0085] In the data dump operation of the selected first cache latch C0, at the first time point T1, the set control signal nCSET[0] and the reset control signal nCRST[0] may be transformed to a high level as a disable level, and thus, the first tri-state inverter IVN1 and the second tri-state inverter INV2 may be disabled. At the second time point T2, when the set signal or the data signal DI reaches the enable level, the set transistor NM13 may be turned on, and the first node data LAT_nC0 may reach a low level. In this case, because the set control signal nCSET[0] and the reset control signal nCRST[0] are at the disable level, both the first tri-state inverter INV1 and the second tri-state inverter INV2 may be disabled and may not perform an inversion operation. Therefore, the second node data LAT_C0 may be maintained at a previous level (e.g., a low level).

[0086] At the third time point T3, when the reset control signal nCRST[0] transitions to a low level as the enabling level, the first tri-state inverter INV1 can be enabled. The enabled first tri-state inverter INV1 can invert the first node data LAT_nC0, and thus, the second node data LAT_C0 can transition to a high level. At the fourth time point T4, the set control signal nCSET[0] can transition to a low level as the enabling level, and thus, the second tri-state inverter INV2 included in the first cache latch C0 can be enabled. The second tri-state inverter INV2 can invert the second node data LAT_C0, and thus, the first node data LAT_nC0 can be maintained at a low level.

[0087] According to some embodiments, during the discharge period, the reset control signal nCRST[0] and the set control signal nCSET[0] can transition to a disabling level. After the discharge period, the reset control signal nCRST[0] and the set control signal nCSET[0] can sequentially transition to an enabling level. Thus, the first tri-state inverter INV1 and the second tri-state inverter INV2 can be sequentially enabled. For example, enabling the second tri-state inverter INV2 can follow enabling the first tri-state inverter INV1. By sequentially enabling the first tri-state inverter INV1 and the second tri-state inverter INV2, the first cache latch C0 can store the data received from the master latch. In this case, since the first tri-state inverter INV1 and the second tri-state inverter INV2 are disabled during the discharge period, the power consumption of the first cache latch C0 can be reduced during the data dump operation.

[0088] In addition, at the first time point T1, the set control signals nCSET[7:1] and the reset control signals nCRST[7:1] can transition to a high level. At the second time point T2, when the set signal or the data signal DI reaches the enabling level, the set transistor NM13' can conduct, and the third node data LAT_nC1 can reach a low level L. At the third time point T3, the set control signal nCSET[7:1] can transition to a low level, and the fourth tri-state inverter INV4 can be enabled. As a result, the fourth tri-state inverter INV4 can restore the third node data LAT_nC1 to a high level by inverting the intact fourth node data LAT_C1. At the fourth time point T4, the reset control signal nCRST[7:1] can transition to a low level, and the third tri-state inverter INV3 can be enabled. Thus, the third tri-state inverter INV3 can invert the restored third node data LAT_nC1, and the fourth node data LAT_C1 can be maintained at a low level.

[0089] Figure 20 is according to some embodiments Figure 19A and Figure 19BDetailed timing diagram of the data dump operation. Refer to together Figure 8 , Figure 15 and Figure 20 , some embodiments may correspond to Figure 16 's modified examples, and the descriptions provided above with reference to Figure 16 can also be applied to the illustrated embodiments. The following description will focus on the differences between the illustrated embodiments and Figure 16 the embodiments shown in

[0090] In the data dump operation of the selected first cache latch C0, at the third time point t3, the set control signal nCSET[0] and the reset control signal nCRST[0] may transition to high level. Therefore, the first tri-state inverter INV1 and the second tri-state inverter INV2 may be disabled, thereby reducing the power consumption of the first cache latch C0. At the sixth time point t6, the reset control signal nCRST[0] may transition to low level, and thus, the first tri-state inverter INV1 may be enabled. Through the inversion operation of the enabled first tri-state inverter INV1, the second node data LAT_C0 may transition to high level. At the seventh time point t7, the set control signal nCSET[0] may transition to low level, and thus, the second tri-state inverter INV2 may be enabled. Through the inversion operation of the enabled second tri-state inverter INV2, the first node data LAT_nC0 may be maintained at low level.

[0091] Figure 21A is a timing diagram of the control operation of the selected cache latch in the data dump operation according to some embodiments. Figure 21B is a timing diagram of the control operation of the unselected cache latch in the data dump operation according to some embodiments. Figure 22 Illustrates the discharge operation according to some embodiments.

[0092] Refer to together Figures 21A to 22 , some embodiments may correspond to Figure 14A and Figure 14B 's modified examples, and the descriptions provided above with reference to Figures 14A to 16 can also be applied to the illustrated embodiments. In the Figures 14A to 16 illustrated embodiments, a discharge path for the first node ND1 may be generated by controlling the set signal or the data signal DI, while in the illustrated embodiments, a discharge path for the second node ND2 may be generated by controlling the reset signal or the data inverted signal nDI.

[0093] In a data dump operation on a selected first cache latch C0, the set control signal nCSET[0] and the reset control signal nCRST[0] applied to the selected first cache latch C0 may be at a low level as an active level. Accordingly, a first tri-state inverter INV1 and a second tri-state inverter INV2 included in the first cache latch C0 may be enabled. In addition, at a first time point T1, the set control signals nCSET[7:1] and the reset control signals nCRST[7:1] applied to unselected cache latches may transition to a high level. Accordingly, tri-state inverters (e.g., a third tri-state inverter INV3 and a fourth tri-state inverter INV4 included in a second cache latch C1) included in each of the unselected cache latches may be disabled.

[0094] At a second time point T2, a reset signal or a data inversion signal nDI may transition to a high level as an active level. As described above, a period during which the reset signal or the data inversion signal nDI is maintained at the active level may be defined as a "discharge period", and the discharge period may correspond to Figure 13 a first period DISCHARGE. During the discharge period or the first period, a discharge operation may be performed on the selected first cache latch C0.

[0095] At the second time point T2, when the reset signal or the data inversion signal nDI reaches the active level, a reset transistor NM14 and a reset transistor NM14' may be turned on. When the voltage of a combined sense node SOC is at a high level H, both a first transistor TR0 and a second transistor TR1 may be turned on. Accordingly, in the selected first cache latch C0, a discharge path may be generated through the first transistor TR0 and the reset transistor NM14, and the voltage of a second node ND2 (i.e., second node data LAT_C0) may reach a low level L. In this case, since the set control signal nCSET[0] and the reset control signal nCRST[0] are at the active level, the first tri-state inverter INV1 and the second tri-state inverter INV2 may all be enabled and each perform an inversion operation. Due to the inversion operation of the second tri-state inverter INV2, the first node data LAT_nC0 may reach a high level H, and due to the inversion operation of the first tri-state inverter INV1, the second node data LAT_C0 may be maintained at the low level L.

[0096] In the unselected second cache latch C1, a discharge path can be generated through the second transistor TR1 and the reset transistor NM14', and the voltage of the fourth node ND4 (i.e., the fourth node data LAT_C1) can reach the low level L. In this case, since the set control signal nCSET[1] and the reset control signal nCRST[1] are at the disabled level, both the third tri-state inverter INV3 and the fourth tri-state inverter INV4 can be disabled and do not perform an inversion operation. Therefore, although the fourth node data LAT_C1 is damaged, the third node data LAT_nC1 can be maintained at the previous level (e.g., low level).

[0097] At the third time point T3, the reset control signal nCRST[7:1] applied to the unselected cache latch can transition to the low level, and the tri-state inverters included in each of the unselected cache latches (e.g., the third tri-state inverter INV3 included in the second cache latch C1) can be enabled. The enabled third tri-state inverter INV3 can restore the fourth node data LAT_C1 to the high level by inverting the undamaged third node data LAT_nC1.

[0098] At the fourth time point T4, the set control signal nCSET[7:1] applied to the unselected cache latch can transition to the low level, and the tri-state inverters included in each of the unselected cache latches (e.g., the fourth tri-state inverter INV4 included in the second cache latch C1) can be enabled. The enabled fourth tri-state inverter INV4 can invert the restored fourth node data LAT_C1, and thus, the third node data LAT_nC1 can be maintained at the previous level (e.g., low level).

[0099] According to some embodiments, after the discharge period of the data dump operation, the set control signal nCSET[7:1] and the reset control signal nCRST[7:1] applied to the unselected cache latch can sequentially transition to the enabled level. Therefore, the tri-state inverters included in the unselected cache latches can be sequentially enabled. For example, enabling the third tri-state inverter INV3 included in the second cache latch C1 can be followed by enabling the fourth tri-state inverter INV4. By sequentially enabling the third tri-state inverter INV3 and the fourth tri-state inverter INV4, the data previously stored in the second cache latch C1 can be restored.

[0100] Figure 23A is a timing diagram of the control operation of the selected cache latch in the data dump operation according to some embodiments. Figure 23BIt is a timing diagram of the control operation of unselected cache latches in a data dump operation according to some embodiments. Referring together Figures 22 to 23B , some embodiments may correspond to Figure 17A and Figure 17B modification examples of, and the description provided above with reference to Figures 17A to 18 can also be applied to the illustrated embodiments. In addition, some embodiments may correspond to Figure 21A and Figure 21B modification examples of, and the description provided above with reference to Figures 21A to 22 can also be applied to the illustrated embodiments.

[0101] In the data dump operation of the selected first cache latch C0, the set control signal nCSET[0] may be at a low level, and the second tri-state inverter INV2 may be enabled. At the first time point T1, the reset control signal nCRST[0] may transition to a high level, and the first tri-state inverter INV1 may be disabled. At the second time point T2, when the reset signal or the data inverse signal nDI reaches the enable level, the reset transistor NM14 may conduct, and the second node data LAT_C0 may reach the low level L. In this case, since the set control signal nCSET[0] is at the enable level, the second tri-state inverter INV2 may be enabled and perform an inversion operation. Through the inversion operation of the enabled second tri-state inverter INV2, the first node data LAT_nC0 may reach the high level H. At the third time point T3, when the reset control signal nCRST[0] transitions to a low level, the first tri-state inverter INV1 may be enabled. The enabled first tri-state inverter INV1 may invert the first node data LAT_nC0, and thus, the second node data LAT_C0 may be maintained at the low level L.

[0102] At the first time point T1, the set control signals nCSET[7:1] and the reset control signals nCRST[7:1] may transition to a high level. At the second time point T2, when the reset signal or the data inverse signal nDI reaches the enable level, the reset transistor NM14' may conduct, and the fourth node data LAT_C1 may reach the low level L. At the third time point T3, when the reset control signals nCRST[7:1] transition to a low level, the third tri-state inverter INV3 may be enabled. The enabled third tri-state inverter INV3 may invert the intact third node data LAT_nC1, and thus, the fourth node data LAT_C1 may be restored to the high level. At the fourth time point T4, the set control signals nCSET[7:1] may transition to a low level, and the fourth tri-state inverter INV4 may be enabled. The enabled fourth tri-state inverter INV4 may invert the restored fourth node data LAT_C1, and the third node data LAT_nC1 may be maintained at the low level.

[0103] Figure 24A is a timing diagram of control operations for selected cache latches in a data dump operation according to some embodiments. Figure 24B is a timing diagram of control operations for unselected cache latches in a data dump operation. Referring together Figure 22 , Figure 24A and Figure 24B , some embodiments may correspond to Figure 19A and Figure 19B modified examples of, and the description provided above with reference to Figures 19A to 20 may also apply to the illustrated embodiments. Moreover, some embodiments may correspond to Figure 21A and Figure 21B modified examples of, and the description provided above with reference to Figures 21A to 22 may also apply to the illustrated embodiments.

[0104] In a data dump operation for a selected first cache latch C0, at a first time point T1, the set control signal nCSET[0] and the reset control signal nCRST[0] may transition to a high level as a disabled level, and thus, the first tri-state inverter IVN1 and the second tri-state inverter INV2 may be disabled. At a second time point T2, when the reset signal or the data inverse signal nDI reaches the enabled level, the reset transistor NM14 may conduct, and the second node data LAT_C0 may reach a low level L. In this case, since the set control signal nCSET[0] and the reset control signal nCRST[0] are at the disabled level, both the first tri-state inverter INV1 and the second tri-state inverter INV2 may be disabled and may not perform an inversion operation. Accordingly, the first node data LAT_nC0 may be maintained at the previous level (e.g., a low level).

[0105] At a third time point T3, when the set control signal nCSET[0] transitions to a low level as an enabled level, the second tri-state inverter INV2 may be enabled. The enabled second tri-state inverter INV2 may invert the second node data LAT_C0, and thus, the first node data LAT_nC0 may transition to a high level H. At a fourth time point T4, when the reset control signal nCRST[0] transitions to a low level, the first tri-state inverter INV1 may be enabled. The enabled first tri-state inverter INV1 may invert the first node data LAT_nC0, and thus, the second node data LAT_C0 may be maintained at the low level.

[0106] At a first time point T1, the set control signals nCSET[7:1] and the reset control signals nCRST[7:1] may transition to a high level. At a second time point T2, when the reset signal or the data inverted signal nDI reaches an enabling level, the reset transistor NM14' may conduct, and the data at the fourth node LAT_C1 may reach a low level L. At a third time point T3, the reset control signals nCRST[7:1] may transition to a low level, and the third tri-state inverter INV3 may be enabled. The enabled third tri-state inverter INV3 may invert the uncorrupted data at the third node LAT_nC1, and thus, the data at the fourth node LAT_C1 may be restored to a high level. At a fourth time point T4, the set control signals nCSET[7:1] may transition to a low level, and the fourth tri-state inverter INV4 may be enabled. The enabled fourth tri-state inverter INV4 may invert the restored data at the fourth node LAT_C1, and the data at the third node LAT_nC1 may be maintained at a low level.

[0107] Figure 25 Shows the structure of a memory device 100 according to some embodiments. Referring together Figure 1 and Figure 25 , the memory device 100 includes a first semiconductor layer L1 and a second semiconductor layer L2, and the first semiconductor layer L1 may be stacked on the second semiconductor layer L2 in a vertical direction Z. Specifically, the second semiconductor layer L2 may be below the first semiconductor layer L1 in the vertical direction Z. In some embodiments, the memory cell array 110 may be formed in the first semiconductor layer L1, and the peripheral circuit PECT may be formed in the second semiconductor layer L2. Thus, the memory device 100 may have a structure in which the memory cell array 110 is disposed on the peripheral circuit PECT (i.e., a cell-on-peripheral (COP) structure or a bonded VNAND (B-VNAND) structure).

[0108] In the first semiconductor layer L1, bit lines BL may extend in a first direction Y, and word lines WL may extend in a second direction X. The second semiconductor layer L2 may include a substrate. By forming semiconductor devices (e.g., transistors) and patterns for wiring the semiconductor devices on the substrate, a peripheral circuit PECT may be formed on the second semiconductor layer L2. In some embodiments, when the memory device 100 has a COP structure, after forming the peripheral circuit PECT on the second semiconductor layer L2, a first semiconductor layer L1 including a memory cell array 110 may be formed, and a pattern configured to electrically connect the word lines WL and bit lines BL of the memory cell array 110 to the peripheral circuit PECT formed on the second semiconductor layer L2 may be formed. In some embodiments, when the memory device 100 has a B-VNAND structure, the peripheral circuit PECT and a lower bonding pad may be formed on the second semiconductor layer L2, and the memory cell array 110 and an upper bonding pad may be formed on the first semiconductor layer L1. Thereafter, the upper bonding pad on the first semiconductor layer L1 may be connected to the lower bonding pad on the second semiconductor layer L2 by using a bonding method.

[0109] Figure 26 is a view showing a memory device 500 according to some embodiments of the disclosure.

[0110] Referring to Figure 26 , the memory device 500 may have a chip-to-chip (C2C) structure. At least one upper chip including a cell region and a lower chip including a peripheral circuit region PERI may be manufactured separately, and then, the at least one upper chip and the lower chip may be connected to each other by a bonding method to implement the C2C structure. For example, the bonding method may refer to a method of electrically connecting or physically connecting a bonding metal pattern formed in the topmost metal layer of the upper chip to a bonding metal pattern formed in the topmost metal layer of the lower chip. For example, when the bonding metal pattern is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. Alternatively, the bonding metal pattern may be formed of aluminum (Al) or tungsten (W).

[0111] The memory device 500 may include at least one upper chip including a cell region. For example, as Figure 26As shown in [Fig.], the memory device 500 may include two upper chips. However, the number of upper chips is not limited thereto. In the case where the memory device 500 includes two upper chips, the first upper chip including the first cell region CELL1, the second upper chip including the second cell region CELL2, and the lower chip including the peripheral circuit region PERI may be manufactured separately, and then, the first upper chip, the second upper chip, and the lower chip may be connected to each other by a bonding method to manufacture the memory device 500. The first upper chip may be flipped and then connected to the lower chip by a bonding method, and the second upper chip may also be flipped and then connected to the first upper chip by a bonding method. Hereinafter, the upper and lower portions of each of the first upper chip and the second upper chip will be defined based on before flipping each of the first upper chip and the second upper chip. In other words, in Figure 26 , the upper portion of the lower chip may represent the upper portion defined based on the +Z axis direction, and the upper portion of each of the first upper chip and the second upper chip may represent the upper portion defined based on the -Z axis direction. However, the disclosed embodiments are not limited thereto. In a specific embodiment, one of the first upper chip and the second upper chip may be flipped and then connected to the corresponding chip by a bonding method.

[0112] Each of the peripheral circuit region PERI, the first cell region CELL1, and the second cell region CELL2 of the memory device 500 includes an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0113] The peripheral circuit region PERI includes a first substrate 210 and a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210. An interlayer insulating layer 215 including one or more insulating layers may be disposed on the plurality of circuit elements 220a, 220b, and 220c, and a plurality of metal lines electrically connected to the plurality of circuit elements 220a, 220b, and 220c may be disposed in the interlayer insulating layer 215. For example, the plurality of metal lines includes first metal lines 230a, 230b, and 230c connected to the plurality of circuit elements 220a, 220b, and 220c, and second metal lines 240a, 240b, and 240c formed on the first metal lines 230a, 230b, and 230c. The plurality of metal lines may be formed of at least one of various conductive materials. For example, the first metal lines 230a, 230b, and 230c may be formed of tungsten having a relatively high resistivity, and the second metal lines 240a, 240b, and 240c may be formed of copper having a relatively low resistivity.

[0114] In some embodiments, first metal lines 230a, 230b, and 230c and second metal lines 240a, 240b, and 240c are shown and described. However, the disclosed embodiments are not limited thereto. In a particular embodiment, at least one additional metal line may be formed on the second metal lines 240a, 240b, and 240c. In this case, the second metal lines 240a, 240b, and 240c may be formed of aluminum, and at least some of the additional metal lines formed on the second metal lines 240a, 240b, and 240c may be formed of copper having a resistivity lower than that of aluminum of the second metal lines 240a, 240b, and 240c.

[0115] An interlayer insulating layer 215 may be disposed on the first substrate 210 and may include an insulating material such as silicon oxide and / or silicon nitride.

[0116] Each of a first unit region CELL1 and a second unit region CELL2 may include at least one memory block. The first unit region CELL1 may include a second substrate 310 and a common source line 320. A plurality of word lines 330 (331 to 338) may be stacked on the second substrate 310 in a direction perpendicular to the top surface of the second substrate 310 (i.e., the Z-axis direction). A string selection line and a ground selection line may be disposed above and below the word lines 330, and the plurality of word lines 330 may be between the string selection line and the ground selection line. Similarly, the second unit region CELL2 includes a third substrate 410 and a common source line 420, and a plurality of word lines 430 (431 to 438) may be stacked on the third substrate 410 in a direction perpendicular to the top surface of the third substrate 410 (i.e., the Z-axis direction). Each of the second substrate 310 and the third substrate 410 may be formed of at least one of various materials and may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a substrate having a single crystal epitaxial layer grown on a single crystal silicon substrate. A plurality of channel structures CH may be formed in each of the first unit region CELL1 and the second unit region CELL2.

[0117] In some embodiments, as shown in region "A1" which is an alternative embodiment of region "A", the channel structure CH may be disposed in a bit line bonding region BLBA and may extend in a direction perpendicular to the top surface of the second substrate 310 to penetrate the word lines 330, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected to a first metal line 350c and a second metal line 360c in the bit line bonding region BLBA. For example, the second metal line 360c may be a bit line and may be connected to the channel structure CH through the first metal line 350c. The bit line 360c may extend in a first direction (e.g., the Y-axis direction) parallel to the top surface of the second substrate 310.

[0118] In some embodiments, as shown in region "A2" which is an alternative embodiment of region "A", the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process of forming the lower channel LCH and a process of forming the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the top surface of the second substrate 310 to penetrate the common source line 320 and the lower word lines 331 and 332. The lower channel LCH may include a data storage layer, a channel layer, and a filling insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 333 to 338. The upper channel UCH may include a data storage layer, a channel layer, and a filling insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 350c and the second metal line 360c. As the length of the channel increases, due to the characteristics of the manufacturing process, it may be difficult to form a channel with a substantially uniform width. The memory device 500 according to some embodiments may include a channel having improved width uniformity due to the lower channel LCH and the upper channel UCH formed by sequentially executed processes.

[0119] Meanwhile, in the case where the channel structure CH includes the lower channel LCH and the upper channel UCH as shown in region "A2", the word lines near the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. For example, the word lines 332 and 333 adjacent to the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. In this case, data may not be stored in the memory cells connected to the dummy word lines. Alternatively, the number of pages corresponding to the memory cells connected to the dummy word lines may be less than the number of pages corresponding to the memory cells connected to the general word lines. The level of the voltage applied to the dummy word lines may be different from the level of the voltage applied to the general word lines, and thus it is feasible to reduce the influence of the non-uniform channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device.

[0120] At the same time, in region "A2", the number of the lower word lines 331 and 332 penetrated by the lower channel LCH may be less than the number of the upper word lines 333 to 338 penetrated by the upper channel UCH. However, the disclosed embodiments are not limited thereto. In a specific embodiment, the number of the lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of the upper word lines penetrated by the upper channel UCH. Additionally, the structural features and connection relationships of the channel structure CH provided in the second cell region CELL2 may be substantially the same as the structural features and connection relationships of the channel structure CH provided in the first cell region CELL1. For example, the channel structure CH provided in the second cell region CELL2 may include a data storage layer, a channel layer, and a filling insulating layer, and the channel layer may be electrically connected to the first metal wiring 450c and the second metal wiring 460c in the bit line bonding area BLBA.

[0121] In the bit line bonding region BLBA, a first through electrode THV1 can be disposed in the first cell region CELL1, and a second through electrode THV2 can be disposed in the second cell region CELL2. As Figure 26 shown, the first through electrode THV1 can penetrate the common source line 320 and multiple word lines 330. In a particular embodiment, the first through electrode THV1 can also penetrate the second substrate 310. The first through electrode THV1 can include a conductive material. Optionally, the first through electrode THV1 can include a conductive material surrounded by an insulating material. The second through electrode THV2 can have the same shape and structure as the first through electrode THV1.

[0122] In some embodiments, the first through electrode THV1 and the second through electrode THV2 can be electrically connected to each other through a first through metal pattern 372d and a second through metal pattern 472d. The first through metal pattern 372d can be formed at the bottom end of the first upper chip including the first cell region CELL1, and the second through metal pattern 472d can be formed at the top end of the second upper chip including the second cell region CELL2. The first through electrode THV1 can be electrically connected to the first metal line 350c and the second metal line 360c. A lower via 371d can be formed between the first through electrode THV1 and the first through metal pattern 372d, and an upper via 471d can be formed between the second through electrode THV2 and the second through metal pattern 472d. The first through metal pattern 372d and the second through metal pattern 472d can be connected to each other through a bonding method.

[0123] In addition, in the bit line bonding region BLBA, an upper metal pattern 252 can be formed in the uppermost metal layer of the peripheral circuit region PERI, and an upper metal pattern 392 having the same shape as the upper metal pattern 252 can be formed in the uppermost metal layer of the first cell region CELL1. The upper metal pattern 392 in the first cell region CELL1 and the upper metal pattern 252 in the peripheral circuit region PERI can be electrically connected to each other through a bonding method. In the bit line bonding region BLBA, the bit line 360c can be electrically connected to a page buffer included in the peripheral circuit region PERI. For example, some of the circuit elements 220c in the peripheral circuit region PERI can constitute a page buffer, and the bit line 360c can be electrically connected to the circuit elements 220c constituting the page buffer through the upper bonding metal pattern 370c in the first cell region CELL1 and the upper bonding metal pattern 270c in the peripheral circuit region PERI.

[0124] Continue to refer to Figure 26, in the word line bonding area WLBA, the word line 330 of the first cell area CELL1 may extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the second substrate 310 and may be connected to a plurality of cell contact plugs 340 (plugs 341 to 347). The first metal line 350b and the second metal line 360b may be sequentially connected to the cell contact plugs 340 connected to the word line 330. In the word line bonding area WLBA, the cell contact plugs 340 may be connected to the peripheral circuit area PERI through the upper bonding metal pattern 370b of the first cell area CELL1 and the upper bonding metal pattern 270b of the peripheral circuit area PERI.

[0125] The cell contact plugs 340 may be electrically connected to a row decoder included in the peripheral circuit area PERI. For example, some of the circuit elements 220b in the peripheral circuit area PERI may constitute a row decoder, and the cell contact plugs 340 may be electrically connected to the circuit elements 220b constituting the row decoder through the upper bonding metal pattern 370b of the first cell area CELL1 and the upper bonding metal pattern 270b of the peripheral circuit area PERI. In some embodiments, the operating voltage of the circuit elements 220b constituting the row decoder may be different from the operating voltage of the circuit elements 220c constituting the page buffer. For example, the operating voltage of the circuit elements 220c as components of the page buffer may be greater than the operating voltage of the circuit elements 220b as components of the row decoder.

[0126] Similarly, in the word line bonding area WLBA, the word line 430 of the second cell area CELL2 may extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the third substrate 410 and may be connected to a plurality of cell contact plugs 440 (441 to 447). The cell contact plugs 440 may be connected to the peripheral circuit area PERI through the upper metal pattern of the second cell area CELL2 and the lower metal pattern, upper metal pattern, and cell contact plug 348 of the first cell area CELL1.

[0127] In the word line bonding area WLBA, the upper bonding metal pattern 370b may be formed in the first cell area CELL1, and the upper bonding metal pattern 270b may be formed in the peripheral circuit area PERI. The upper bonding metal pattern 370b of the first cell area CELL1 and the upper bonding metal pattern 270b of the peripheral circuit area PERI may be electrically connected to each other by a bonding method. The upper bonding metal pattern 370b and the upper bonding metal pattern 270b may be formed of aluminum, copper, or tungsten.

[0128] In the external pad bonding region PA, the lower metal pattern 371e may be formed in the lower part of the first cell region CELL1, and the upper metal pattern 472a may be formed in the upper part of the second cell region CELL2. The lower metal pattern 371e of the first cell region CELL1 and the upper metal pattern 472a of the second cell region CELL2 may be connected to each other in the external pad bonding region PA by a bonding method. Similarly, the upper metal pattern 372a may be formed in the upper part of the first cell region CELL1, and the upper metal pattern 272a may be formed in the upper part of the peripheral circuit region PERI. The upper metal pattern 372a of the first cell region CELL1 and the upper metal pattern 272a of the peripheral circuit region PERI may be connected to each other by a bonding method.

[0129] Common source line contact plugs 380 and 480 may be disposed in the external pad bonding region PA. The common source line contact plugs 380 and 480 may be formed of a conductive material such as metal, metal compound, and / or doped polysilicon. The common source line contact plug 380 of the first cell region CELL1 may be electrically connected to the common source line 320, and the common source line contact plug 480 of the second cell region CELL2 may be electrically connected to the common source line 420. The first metal line 350a and the second metal line 360a may be sequentially stacked on the common source line contact plug 380 of the first cell region CELL1, and the first metal line 450 and the second metal line 460a may be sequentially stacked on the common source line contact plug 480 of the second cell region CELL2.

[0130] Input / output pads 205, 405, and 406 may be disposed in the external pad bonding region PA. Referring to Figure 26 , the lower insulating layer 201 may cover the bottom surface of the first substrate 210, and the first input / output pad 205 may be formed on the lower insulating layer 201. The first input / output pad 205 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through the first input / output contact plug 203, and may be separated from the first substrate 210 through the lower insulating layer 201. In addition, a side insulating layer may be disposed between the first input / output contact plug 203 and the first substrate 210 to electrically isolate the first input / output contact plug 203 from the first substrate 210.

[0131] An upper insulating layer 401 covering the top surface of the third substrate 410 may be formed on the third substrate 410. The second input / output pad 405 and / or the third input / output pad 406 may be disposed on the upper insulating layer 401. The second input / output pad 405 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through the second input / output contact plug 403 and 303, and the third input / output pad 406 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through the third input / output contact plug 404 and 304.

[0132] In some embodiments, the third substrate 410 may not be disposed in the region where the input / output contact plugs are provided. For example, as shown in the region "B", the third input / output contact plug 404 may be separated from the third substrate 410 in a direction parallel to the top surface of the third substrate 410, and may penetrate the interlayer insulating layer 415 of the second unit region CELL2 to be connected to the third input / output pad 406. In this case, the third input / output contact plug 404 may be formed by at least one of various processes.

[0133] In some embodiments, as shown in the region "B1" which is an alternative embodiment of the region "B", the third input / output contact plug 404 may extend in the third direction (e.g., the Z-axis direction), and the diameter of the third input / output contact plug 404 may gradually increase toward the upper insulating layer 401. In other words, the diameter of the channel structure CH described in the region "A1" may gradually decrease toward the upper insulating layer 401, but the diameter of the third input / output contact plug 404 may gradually increase toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed after joining the second unit region CELL2 and the first unit region CELL1 to each other by a bonding method.

[0134] In a specific embodiment, as shown in the region "B2" which is an alternative embodiment of the region "B", the third input / output contact plug 404 may extend in the third direction (e.g., the Z-axis direction), and the diameter of the third input / output contact plug 404 may gradually decrease toward the upper insulating layer 401. In other words, like the channel structure CH, the diameter of the third input / output contact plug 404 may gradually decrease toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed together with the unit contact plug 440 before the second unit region CELL2 and the first unit region CELL1 are joined to each other.

[0135] In a specific embodiment, the input / output contact plug may be stacked with the third substrate 410. For example, as shown in region "C", the second input / output contact plug 403 may penetrate the interlayer insulating layer 415 of the second unit region CELL2 in the third direction (e.g., the Z-axis direction), and may be electrically connected to the second input / output pad 405 through the third substrate 410. In this case, the connection structure between the second input / output contact plug 403 and the second input / output pad 405 may be implemented by various methods.

[0136] In some embodiments, as shown in region "C1" which is an alternative embodiment of region "C", an opening 408 may be formed to penetrate the third substrate 410, and the second input / output contact plug 403 may be directly connected to the second input / output pad 405 through the opening 408 formed in the third substrate 410. In this case, as shown in region "C1", the diameter of the second input / output contact plug 403 may gradually increase toward the second input / output pad 405. However, the disclosed embodiments are not limited thereto, and in a specific embodiment, the diameter of the second input / output contact plug 403 may gradually decrease toward the second input / output pad 405.

[0137] In a specific embodiment, as shown in region "C2" which is an alternative embodiment of region "C", an opening 408 penetrating the third substrate 410 may be formed, and a contact 407 may be formed in the opening 408. One end of the contact 407 may be connected to the second input / output pad 405, and the other end of the contact 407 may be connected to the second input / output contact plug 403. Accordingly, the second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the contact 407 in the opening 408. In this case, as shown in region "C2", the diameter of the contact 407 may gradually increase toward the second input / output pad 405, and the diameter of the second input / output contact plug 403 may gradually decrease toward the second input / output pad 405. For example, the second input / output contact plug 403 may be formed together with the unit contact plug 440 before the second unit region CELL2 and the first unit region CELL1 are joined to each other, and the contact 407 may be formed after the second unit region CELL2 and the first unit region CELL1 are joined to each other.

[0138] In a specific embodiment, as shown in region "C3" which is an alternative embodiment of region "C", compared to the embodiment of region "C2", a stopper 409 may also be formed on the bottom end of the opening 408 of the third substrate 410. The stopper 409 may be a metal line formed in the same layer as the common source line 420. Optionally, the stopper 409 may be a metal line formed in the same layer as at least one of the word lines 430. The second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the contact 407 and the stopper 409.

[0139] Similar to the second input / output contact plug 403 and the third input / output contact plug 404 of the second cell region CELL2, the diameter of each of the second input / output contact plug 303 and the third input / output contact plug 304 in the first cell region CELL1 may gradually decrease or gradually increase toward the lower metal pattern 371e.

[0140] Meanwhile, in some embodiments, a slit 411 may be formed in the third substrate 410. For example, the slit 411 may be formed at a specific position in the external pad bonding region PA. For example, as shown in region "D", when observed in a plan view, the slit 411 may be located between the second input / output pad 405 and the cell contact plug 440. Optionally, when observed in a plan view, the second input / output pad 405 may be located between the slit 411 and the cell contact plug 440.

[0141] In some embodiments, as shown in region "D1" which is an alternative embodiment of region "D", the slit 411 may be formed to penetrate the third substrate 410. For example, when the opening 408 is formed, the slit 411 may be used to prevent the third substrate 410 from cracking slightly. However, the disclosed embodiments are not limited thereto, and in a specific embodiment, the slit 411 may be formed to have a depth ranging from about 60% to about 70% of the thickness of the third substrate 410.

[0142] In a specific embodiment, as shown in region "D2" which is an alternative embodiment of region "D", a conductive material 412 may be formed in the slit 411. For example, the conductive material 412 may be used to release leakage current generated when driving circuit elements in the external pad bonding region PA to the outside. In this case, the conductive material 412 may be connected to an external ground wire.

[0143] In a particular embodiment, as shown by region "D3" which is an alternative embodiment of region "D", an insulating material 413 may be formed in the slit 411. For example, the insulating material 413 may be used to electrically isolate the second input / output pad 405 and the second input / output contact plug 403 disposed in the external pad bonding region PA from the word line bonding region WLBA. Since the insulating material 413 is formed in the slit 411, it is possible to prevent the voltage provided through the second input / output pad 405 from affecting the metal layer on the third substrate 410 disposed in the word line bonding region WLBA.

[0144] Meanwhile, in a particular embodiment, the first input / output pad 205, the second input / output pad 405, and the third input / output pad 406 may be selectively formed. For example, the memory device 500 may be implemented to include only the first input / output pad 205 disposed on the first substrate 210, only the second input / output pad 405 disposed on the third substrate 410, or only the third input / output pad 406 disposed on the upper insulating layer 401.

[0145] In some embodiments, at least one of the second substrate 310 of the first cell region CELL1 and the third substrate 410 of the second cell region CELL2 may be used as a sacrificial substrate and may be completely or partially removed before or after the bonding process. Additional layers may be stacked after removing the substrate. For example, the second substrate 310 of the first cell region CELL1 may be removed before or after the bonding process between the peripheral circuit region PERI and the first cell region CELL1, and then, an insulating layer covering the top surface of the common source line 320 or a conductive layer for connection may be formed. Similarly, the third substrate 410 of the second cell region CELL2 may be removed before or after the bonding process between the first cell region CELL1 and the second cell region CELL2, and then, the upper insulating layer 401 covering the top surface of the common source line 420 or a conductive layer for connection may be formed.

[0146] Although this disclosure contains many specific implementation details, these should not be construed as limitations on the scope that can be claimed. The specific features described in the context of separate embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. In addition, although the features may be described above as acting in a particular combination, in some cases one or more features from the combination may be excluded from the combination, and the combination may involve a sub-combination or a variation of the sub-combination.

[0147] Although the disclosure has been specifically shown and described with reference to the disclosed embodiments, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A memory device, comprising: a memory cell array; a plurality of page buffer units connected to the memory cell array and to a combined sensing node; as well as a plurality of cache latches respectively corresponding to the plurality of page buffer units, the plurality of cache latches including a first cache latch and a second cache latch connected to a combined sensing node, wherein the first cache latch comprises a first three-state inverter and a second three-state inverter, and the second cache latch comprises a third three-state inverter and a fourth three-state inverter, wherein, during a first period of a data dump operation to the first cache latch, the first tri-state inverter and the second tri-state inverter are enabled to transfer data to the first cache latch, and the third tri-state inverter and the fourth tri-state inverter are disabled, and, During a second period of the data dump operation on the first cache latch, the third tri-state inverter and the fourth tri-state inverter are sequentially enabled to restore data previously stored in the second cache latch.

2. The memory device according to claim 1, wherein: The first tri-state inverter and the second tri-state inverter are cross-coupled with each other between the first node and the second node, and, During the first period, voltages of the first node and the second node are changed according to the voltage of the combined sensing node.

3. The memory device according to claim 2, wherein: During the first period, the voltage of the first node is discharged and transitions to a low level, and the voltage of the second node transitions to a high level in response to an inversion operation of the enabled first tri-state inverter.

4. The memory device according to claim 2, wherein: The third three-state inverter and the fourth three-state inverter are cross-coupled with each other between the third node and the fourth node. During the first period, the voltage of the third node is discharged and transitions to a low level, and the voltage of the fourth node is maintained at a previous level by disabling the third tri-state inverter and the fourth tri-state inverter, and, During the second period, the fourth three-state inverter is enabled, and the voltage of the third node is restored to a high level in response to an inversion operation of the enabled fourth three-state inverter.

5. The memory device according to claim 4, wherein: During the second period, the third tri-state inverter is enabled based on the voltage of the third node being restored to a high level, and the voltage of the fourth node is maintained at a low level in response to an inversion operation of the enabled third tri-state inverter.

6. The memory device according to claim 4, wherein: The first cache latch also includes a first set transistor connected to the first node, The second cache latch also includes a second set transistor connected to the third node, The first setting transistor and the second setting transistor are turned on during a first period, and The first setting transistor and the second setting transistor are turned off during the second period.

7. The memory device according to claim 2, wherein: The third three-state inverter and the fourth three-state inverter are cross-coupled with each other between the third node and the fourth node. During the first period, the voltage of the fourth node is discharged and transitions to a low level, and the voltage of the third node is maintained at a previous level, and During the second period, the third three-state inverter is enabled, and the voltage of the fourth node is restored to a high level in response to an inversion operation of the enabled third three-state inverter.

8. The memory device according to claim 7, wherein: During the second period, the fourth three-state inverter is enabled based on the voltage of the fourth node being restored to a high level, and the voltage of the third node is maintained at a low level in response to an inversion operation of the enabled fourth three-state inverter.

9. The memory device according to claim 7, wherein: The first cache latch also includes a first reset transistor connected to the second node, The second cache latch also includes a second reset transistor connected to the fourth node, The first reset transistor and the second reset transistor are turned on during a first period, and The first reset transistor and the second reset transistor are turned off during the second period.

10. The memory device of claim 1, further comprising: a first transistor having a first gate connected to the combined sense node, the first transistor connected to the first cache latch; as well as a second transistor having a second gate connected to the combined sense node, the second transistor connected to the second cache latch, During the first period, the first transistor and the second transistor are turned on according to the voltage of the combined sensing node.

11. The memory device according to claim 1, wherein: Each of the plurality of page buffer units includes a sensing node and a pass transistor connected to the sensing node, and, In a data dump operation, sensing nodes respectively included in the plurality of page buffer units are electrically connected to each other through series connection of pass transistors respectively included in the plurality of page buffer units, and, In a data sensing operation, the transfer transistor is turned off, and the sensing nodes are not electrically connected to each other.

12. The memory device according to claim 11, wherein: The plurality of page buffer units include: a first page buffer unit including a first sensing node, a first transfer transistor connected to the first sensing node, and a first master latch, wherein the first page buffer unit corresponds to a first cache latch; and a second page buffer unit including a second sensing node, a second transmission transistor connected to the second sensing node, and a second master latch, wherein the second page buffer unit corresponds to a second cache latch, The data is transferred from the first master latch to the first cache latch in a data dump operation.

13. A memory device comprising: a memory cell array; a plurality of page buffer units connected to the memory cell array and to a combined sensing node; as well as a plurality of cache latches, corresponding to the plurality of page buffer units, respectively, the plurality of cache latches being connected to a combined sensing node, Wherein, the plurality of cache latches include: a first cache latch comprising a first tri-state inverter and a second tri-state inverter; and a second cache latch including a third three-state inverter and a fourth three-state inverter, wherein, during a first period of a data dump operation on the first cache latch, the first tri-state inverter is enabled to transfer data to the first cache latch, and the second to fourth tri-state inverters are disabled, and, During a second period of the data dump operation on the first cache latch, the third tri-state inverter and the fourth tri-state inverter are sequentially enabled to restore data previously stored in the second cache latch.

14. The memory device according to claim 13, wherein: The first tri-state inverter and the second tri-state inverter are cross-coupled with each other between the first node and the second node, and, During the first period, voltages of the first node and the second node are changed according to the voltage of the combined sensing node.

15. The memory device of claim 14, wherein: During the first period, the voltage of the first node is discharged and transitions to a low level, and the voltage of the second node transitions to a high level by an inversion operation of the first tri-state inverter, and, During the second period, the second tri-state inverter is enabled, and the voltage of the first node is maintained at a low level by an inversion operation of the second tri-state inverter.

16. The memory device of claim 14, wherein: The third three-state inverter and the fourth three-state inverter are cross-coupled with each other between the third node and the fourth node. During the first period, the voltage of the third node is discharged and transitions to a low level, and the voltage of the fourth node is maintained at a previous level by disabling the third tri-state inverter and the fourth tri-state inverter, and, During the second period, the fourth three-state inverter is enabled, and the voltage of the third node is restored to a high level in response to an inversion operation of the enabled fourth three-state inverter.

17. The memory device of claim 16, wherein: During the second period, the third tri-state inverter is enabled based on the voltage of the third node being restored to a high level, and the voltage of the fourth node is maintained at a low level in response to an inversion operation of the enabled third tri-state inverter.

18. The memory device of claim 16, wherein: The first cache latch also includes a first set transistor connected to the first node, The second cache latch also includes a second set transistor connected to the third node, The first setting transistor and the second setting transistor are turned on during a first period, and The first setting transistor and the second setting transistor are turned off during the second period.

19. A memory device comprising: a memory cell array; a plurality of page buffer units connected to the memory cell array, wherein the plurality of page buffer units are connected to a combined sensing node; and a plurality of cache latches, respectively corresponding to the plurality of page buffer units, wherein the plurality of cache latches are connected to a combined sensing node, Wherein, the plurality of cache latches include: a first cache latch comprising a first tri-state inverter and a second tri-state inverter; and a second cache latch including a third three-state inverter and a fourth three-state inverter, wherein the first to fourth tri-state inverters are disabled in a first period of a data dump operation on the first cache latch, and, During a second period of the data dump operation to the first cache latch, enabling the first and fourth tri-state inverters is followed by enabling the second and third tri-state inverters, and data previously stored in the second cache latch is restored.

20. The memory device of claim 19, wherein: The third three-state inverter and the fourth three-state inverter are cross-coupled with each other between the third node and the fourth node. During the first period, the voltage of the third node is discharged and transitions to a low level, and the voltage of the fourth node is maintained at a previous level by disabling the third tri-state inverter and the fourth tri-state inverter, and, During the second period, the fourth three-state inverter is enabled, and the voltage of the third node is restored to a high level in response to an inversion operation of the enabled fourth three-state inverter.

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