Access error correction for content addressable memory

Abstract

The invention provides access error correction for content addressable memory. Examples of the disclosed technology provide a method for detecting and correcting errors (i.e., 'access' error correction) in a summed content addressable memory (sigma-CAM) when the sigma-CAM performs a compute task. The method involves adding redundant columns to a sigma-CAM for storing a task-driven matrix (i.e., a matrix having a value conforming to a computational task). Examples may utilize an encoder to calculate redundancy values for redundant columns such that the sigma-CAM stores codewords for linear codes (C) in each row. Examples also modify a linear code (C) used to calculate redundancy values. That is, examples modify the linear code (C) such that it includes an omni-vector. By this modification, the system of the present technology may detect and correct errors in the output vector from the sigma-CAM based on this modified / specific linear code (C).

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 609,652, filed on December 13, 2023, the content of which is incorporated herein by reference in its entirety. Background of the Invention

[0003] A content - addressable memory (“CAM”) is a computational memory in which stored data is searched by content rather than by location. When a “word” is input to the CAM, the CAM searches for that word in its content. If the CAM finds the word (i.e., “returns a match”), then the CAM returns the address of the location where the found word is located. The individual cells of the CAM (referred to herein as CAM cells) can be arranged in rows and columns to form the CAM. Depending on the configuration, the corresponding CAM rows or columns connecting the outputs from the constituent CAM cells may be referred to as match lines.

[0004] A sum CAM (Σ - CAM) (sometimes referred to as a Hamming - distance CAM) is a special type of CAM that is configured to sum the outputs from CAM cells arranged along corresponding columns. In other words, a Σ - CAM can refer to a CAM consisting of an l×n array of CAM cells, where for some internal state values each CAM cell (i,j) ∈ [l>×[n> implements a function The programmed internal state of the Σ - CAM can be represented as an array (matrix) where a i represents row i and A j (=(A) {j} ) represents column j. The input to the Σ - CAM can include a row vector (e.g., a search key) where x i serves as the input to all CAM cells along row i. The corresponding column j of the Σ - CAM (corresponding to the match line) can compute the integer sum of the outputs of the CAM cells arranged along the corresponding column j (i.e., c j =∑ i∈[l> N(x i ,a i,j ) = w(x - A j )) The integer sums form the output row vector of the Σ - CAM, i.e., c=(c j ) j∈[n> ∈[0:l] n . Thus, the Σ - CAM computes the Hamming distance between the input vector and the content of the CAM cells along each of the n columns in the Σ - CAM. Brief Description of the Drawings

[0005] In accordance with one or more various examples, the present disclosure is described in detail with reference to the following drawings. The drawings are provided for illustrative purposes only and depict only examples.

[0006] Figure 1 An example truth table in accordance with a technical example of the present disclosure is described.

[0007] Figure 2 An encoding mapping algorithm in accordance with a technical example of the present disclosure is described.

[0008] Figure 3 An example value table in accordance with a technical example of the present disclosure is described.

[0009] Figure 4 An example value table in accordance with a technical example of the present disclosure is described.

[0010] Figure 5 An example value table in accordance with a technical example of the present disclosure is described.

[0011] Figure 6 An example CAM cell in accordance with a technical example of the present disclosure is described.

[0012] Figure 7 An example CAM-based circuit in accordance with a technical example of the present disclosure is described.

[0013] Figure 8 An example graph in accordance with a technical example of the present disclosure is described, which shows a comparison between a threshold voltage and a voltage output of a match line associated with a column of a CAM cell of a sum CAM.

[0014] Figure 9 A block diagram of an example computer system in which various examples described herein may be implemented is described.

[0015] The drawings are not exhaustive and do not limit the present disclosure to the exact forms disclosed. Detailed Description

[0016] Examples of the present disclosure provide a method for detecting and correcting errors in a Σ-CAM (i.e., "on-access" error correction) when the Σ-CAM performs a computing task.

[0017] The "access" error correction method of the present disclosure can improve the "offline" error detection / correction method. Such an "offline" error detection / correction method typically involves a detection program that can interfere with the normal operation of the hardware accelerator during a computing task, and thus it must be executed "offline". For example, another method for detecting errors in a CAM may involve applying a test vector sequence to the CAM to detect programming errors and other circuit-based errors. Applying the test vector may be independent of the computing task that the CAM is being used to perform, or it will interfere with the computing task. Therefore, this method will be executed "offline". In contrast, the error detection and correction method of the present disclosure involves correcting the output vector generated by the Σ-CAM when the Σ-CAM performs a specified computing task. Therefore, compared with other "offline" error detection and correction methods, this method can be more computationally efficient (i.e., consume fewer processing resources, time, and power consumption).

[0018] The example realizes the advantages provided by "access" error detection and correction by leveraging the insightful observation that the Σ-CAM operates similarly to a vector matrix multiplier (sometimes referred to as a dot product engine). Using such an insight, the example uniquely adapts the error correction method for a vector matrix multiplier to the Σ-CAM. The adapted method involves adding redundant columns to the Σ-CAM that has already been used to store a task-driven matrix (i.e., a matrix with values that conform to the computing task). The example can use one or more processing resources (such as an encoder) to calculate the redundant values of the redundant columns so that the Σ-CAM stores the codewords of a linear code (C) in each row. To further adapt the method for a new / specific type of hardware accelerator (i.e., the Σ-CAM), the example modifies the linear code (C) used to calculate the redundant values. That is, the example modifies the linear code (C) to include an all-one vector. By this modification, the system of the present disclosure technology can detect and correct errors in the output vector from the Σ-CAM based on this modified / specific linear code (C).

[0019] For example, the system of the present disclosure technology may include: a) a Σ-CAM including CAM cells arranged in a number (l) of rows and a number (n) of columns, where the Σ-CAM is configured to sum the outputs from the number (l) of CAM cells connected along the corresponding columns in the number (n) of columns; and b) one or more processing resources for programming the CAM cells to store a matrix (A) having a dimension (l x n), where: i) each row of the matrix (A) includes a codeword of a linear code (C), and ii) the linear code (C) includes an all-one vector having a dimension of (n) as a codeword.

[0020] In the above system, the CAM units connected along the k-th column among the n columns of numbers may include task-driven CAM units. Correspondingly, the CAM units connected along the (n-k)-th column among the n columns of numbers may include redundant CAM units. Thus, each row of the Σ-CAM includes k task-driven CAM units and (n-k) redundant CAM units. Therefore, programming the Σ-CAM to store a matrix (A) with dimensions (l×n) may include: a) programming the k task-driven CAM units of each row to store task-driven values that conform to a computing task; b) calculating redundant values of the (n-k) redundant CAM units of each row based on the programmed task-driven values and the linear code (C); and c) programming the (n-k) redundant CAM units of each row to store the calculated redundant values such that each row stores a codeword of the linear code (C). In some implementations, calculating the redundant values of the (n-k) redundant CAM units of each row may include calculating the redundant values of the (n-k) redundant CAM units of each row such that the task-driven values and the redundant values include a sequence of ones and zeros specified by the linear code (C).

[0021] In the above system, one or more processing resources may further be used to detect and correct one or more errors in the output vector (c) from the Σ-CAM based on the linear code (C). In some embodiments, the output vector (c) may have a dimension of n. Correspondingly, the output vector (c) may include a concatenation of a task-driven output vector (c') and a redundant output vector (c"). Here, the task-driven output vector (c') may have a dimension of k and correspond to the sum between: (1) the vector-matrix product between the transformation of the input vector (x) with dimension l received by the Σ-CAM and the task-driven storage matrix (A') with dimensions (l×k) stored by the task-driven CAM units of the Σ-CAM; and (2) the vector product between the all-ones vector with dimension n and a constant value (e.g., see Equation 4 below). Correspondingly, the redundant output vector (c") may have a dimension of (n-k) and correspond to the sum between: (1) the vector-matrix product between the transformation of the input vector (x) and the redundant storage matrix (A") with dimensions (l×(n-k)) stored by the redundant CAM units of the Σ-CAM; and (2) the vector product between the all-ones vector with dimension n and a constant value (e.g., see Equation 4 below). Additionally, one or more processing resources may detect and correct one or more errors in the task-driven output vector (c') based on (e.g., by comparing) the linear code (C) and the redundant output vector (c").

[0022] In some embodiments of the above system, the corresponding CAM units of the Σ-CAM may include one or more programmable memristors. Here, programming the corresponding CAM units may include programming the conductance of one or more programmable memristors.

[0023] Examples of the disclosed technology will be described in more detail below. It should be understood that the following description provides only illustrative examples and should not limit the principles disclosed herein.

[0024] Several coding schemes for access correction of error Σ-CAMs are presented herein. These schemes can be applied to binary Σ-CAMs (sometimes referred to herein as Σ-BCAMs) and ternary Σ-CAMs (sometimes referred to herein as Σ-TCAMs). Each of the various schemes requires allocating rows of the Σ-CAM for redundancy so that when an input vector is applied to the Σ-CAM, errors in the output vector can be corrected provided that their number (measured by the Hamming metric or the L 1 -metric) does not exceed a specified value. In the case of a Σ-BCAM, the operation of the Σ-BCAM is similar to that of a discrete vector matrix (V-M) multiplier. Thus, the error correction scheme of the disclosed technology for Σ-BCAMs builds on the schemes proposed for such multipliers. Due to the presence of wildcards (sometimes referred to as "don't care" symbols), adapting such schemes to Σ-TCAMs may be more complex. Thus, the scheme of the disclosed technology for Σ-TCAMs uses a special type of positional binary representation of pairs of integers, where the representations of the two integers in any pair do not share a 1 in the same position.

[0025] Examples of the disclosed technology will be described in more detail in conjunction with Parts I through VIII below.

[0026] Part I: Symbol Introduction

[0027] Hereafter, this application uses the following symbols. For This application uses [y:z] to denote the subset of integers and uses [y:z> to denote the set [y:z - 1]. This application will use the shorthand notation [z> to denote [0:z> and use to denote [2>. For an integer vector x, this application uses w(x) and ∥x∥ to denote its Hamming weight and L 1 -norm, respectively. For an l×n matrix A (or, if l = 1, a row n-vector) and a subset this application lets (A)X denote the l×|X| submatrix of A formed by the columns indexed by X. For z > 0, the symbol y MOD z denotes the remainder in [z> when y is divided by z. The ring of integers modulo q is denoted by ​

[0028] Let be the inequality test (XOR) function, which for each is defined by:

[0029]

[0030] where denotes the Iverson bracket (which evaluates to 1 if its argument is true and 0 otherwise). As described above, a Σ-CAM can refer to a device consisting of an l×n CAM cell array, where for some internal state values each CAM cell (i,j) ∈ [l]×[n] implements the function This application represents the internal state as an array (matrix) where a i denotes row i and A j (=(A) {j} ) denotes column j. The input to the Σ-CAM can include a row vector (e.g., a "search key") where x i serves as the input to all CAM cells along row i. Each column (corresponding to a match line) j in the Σ-CAM computes the integer sum of the outputs of the CAM cells along that column,

[0031] c j = ∑ i∈[l> N(x i , a i，j ) = w(x - A j ). Equation 2

[0032] These integer sums form the output row vector c = (c j ) j∈[n> ∈ [0:l] n . Thus, the Σ-CAM computes the Hamming distance between the input vector and the contents of the CAM cells along each of the n columns in the Σ-CAM.

[0033] Thereafter, this application uses the symbol S(x,A) to denote the vector in [0:l] n whose entries are given by the right-hand side of Equation 2. That is, when the input vector x is applied to a Σ-CAM programmed with the matrix A as the internal state, S(x,A) is the computed result c. The 0 entries in c = S(x,A) are called "matches", and a regular binary CAM (BCAM) can be regarded as a quantized Σ-CAM whose output is a binary n-vector (which indicates the columns where matches occur).

[0034] Σ-CAM is a model of an accelerator proposed for calculating Hamming distances in various applications, and there are various designs for its CAM cells (using CMOS as well as resistive technologies) and the circuitry for calculating Hamming distances along each column. In these designs, typically, the value N(x i ,a i,j ) = 1 is achieved by setting the CAM cell (i,j) to some high conductance. When N(x i ,a i,j ) = 0, the CAM cell is effectively open (i.e., has 0 conductance). One way to obtain the Hamming distance is by fixing the voltage level of the match lines and measuring the current flowing through each column of the CAM. This current is typically proportional to the number of high-conductance CAM cells along the column. In various applications of interest, the matrix is modified much less frequently than the input vector x.

[0035] Inaccuracies during programming of CAM cells, manufacturing defects, and noise during reading of the output vector are all example factors that can cause the actually read row vector to be different from the correct vector c = S(x,A). The error vector can be defined as the following vector in

[0036] e = (e j ) j∈[n> = y - c

[0037] In the case where a faulty CAM cell produces an incorrect output and that output is still within , then the output at the column containing that CAM cell will be a change of ±1. This application refers to such an event as an L 1 -error. Then, there is a lower bound on the number of L 1 -errors under the L 1 -norm ∥e∥, where the equality holds if all faulty CAM cells along the same column occur in the same direction. A focus of this application is this situation, in which one of the design parameters of this disclosure will be the maximum L 1 -norm τ of tolerable e, which (when not considering the internal state in matrix A) can serve as a proxy for the maximum number τ or faulty CAM cells that can be tolerated. However, this application will also consider the situation where faulty CAM cells may have a large impact on the output of the column, in which case τ will represent the maximum Hamming weight of tolerable e. Hereafter, depending on the context, the "number of errors" in this application can refer to ∥e∥ or w(e).

[0038] An object of the present disclosure technology is to provide an encoding scheme for access error correction in Σ-CAM (and in its variants to be given below). To this end, the present disclosure technology adapts the framework for integer vector matrix (V-M) multipliers to Σ-CAM, due to the close relationship between the functions of these two devices. Specifically, as can be seen from Equation 2

[0039]

[0040] where 1 n represents a full row n-vector. Next is

[0041]

[0042] where, u ∈ {±1} l .

[0043] That is, up to an additive multiple of the all-one vector, Σ-CAM performs the multiplication of a vector in {±1} l by a matrix in .

[0044] Taking this into account, an example programming matrix A of the present disclosure technology is such that the first k (<n) terms in c = S(x, A) will carry the target computation of Σ-CAM, while the remaining n-k terms of c will contain redundant symbols, which can be used to detect or correct computational errors. Thus, the programmed l×n matrix A will have the structure

[0045] A = (A′|A"), Equation 5

[0046] where A′ = (A) [k> and A″ = (A) [k:n> . The output row vector of the computation of the input vector will be c = S(x, A) = (c′∣c″), where c′ = (c) [k> = S(x, A′) is the target computation and c″ = (c) [k:n> = S(x, A″) is the redundant part.

[0047] Given positive integers l, n, and k < n, the Σ-CAM encoding scheme is a pair where

[0048] · is an encoding mapping such that for each the image A = ε(A′) for some has the form of Equation 5, and

[0049] · is a decoding mapping (where "e" indicates decoding failure).

[0050] Set

[0051]

[0052] is a code induced by ε and its members are called codewords. That is, and its codewords are all possible output vectors that can be obtained when A′ ranges over all possible l×k matrices and x ranges over all possible 2 input vectors in . This application takes n and k as the length and dimension of the coding scheme respectively. For the row vectors that appear in the combined coding scheme l this application uses the symbols z′ and z″ to represent its k-prefix (z) and (n-k)-suffix (z) [k> respectively. This symbol specification is also extended to l×n matrices. [n-k>

[0053] Given l, k, and a specified number of errors τ (measured by the L 1 -metric or Hamming metric), the goal is to have a coding scheme with the smallest possible n such that for each and the k-prefix c′ of the corresponding codeword c = S(x, ε(A′)) = (c′∣c″) in n can be correctly recovered in the presence of τ or fewer errors. That is, for each read vector y ∈ [0:l]

[0054]

[0055] (alternatively, n can be given and k will be maximized). Note that a decoding map may not be required to recover the redundant part c″.

[0056] More generally, given non-negative integers τ and σ, if the following condition holds for each computed output vector and the corresponding read vector y ∈ [0:l] n then the coding scheme is considered to be able to correct τ errors and detect τ+σ errors (in the L 1 -metric or Hamming metric).

[0057] · If ∥y - c∥ ≤ τ, then

[0058] · Otherwise, if ∥y - c∥ ≤ τ+σ, then ​

[0059] The minimum distance (denoted as ) is defined as the minimum L 1 / Hamming distance between any two codewords in

[0060]

[0061] with different k-prefixes:

[0062] Proposition 1. Let be the encoding mapping and let τ and σ be non-negative integers such that

[0063]

[0064] Then there exists a decoding mapping such that the coding scheme can correct τ errors and detect τ + σ errors.

[0065] Unless otherwise specified, ε will be separable, i.e., for each row index i ∈ [l>, the content of row i in ε(A′) will be a function only of row i in A′ (and not of other rows in A′), will be the same for all i, and will not depend on l. In the case of a separable encoder, this application assumes that the domain and range of ε are and

[0066] Let be the set of all images of (separable) ε. From Equation 3 (or Equation 4), it follows that

[0067]

[0068] In particular, for each c ∈ Im(ε), and when l is even Thus, the example uses the coding scheme where Im(ε) is a subset of n with the ambient module containing 1 n with the ambient module and is a subset of the intersection of such that For simplicity, this application generally assumes σ = 0 hereafter.

[0069] For the matrix in For special cases above, such a coding scheme can be obtained by modifying the construction of the vector matrix multiplier. Those modifications may require some mild conditions on the length n, but there is no loss in redundancy. This application will start to describe the scheme in Part II, which is derived from the modification of the Hamming metric construction of the vector matrix multiplier. As a general construction, this construction is perhaps the simplest and it conforms to both the L 1 -metric and the Hamming metric. When τ is small enough compared to n, there are other (albeit more complex) constructions for the L 1 -metric. These constructions are discussed in Parts VI and VII of this application.

[0070] In Part III (and subsequent parts), this application will consider a variant of the Σ-CAM based on the cells of a ternary content addressable memory (TCAM). TCAM is an extension of the ordinary binary CAM, where the internal state values of the CAM cells and the inputs to the CAM cells are allowed to use a third "wildcard" symbol *, sometimes called the "don't care" or "always match" symbol. Thus, both the input and state alphabets of the CAM cells are and each CAM cell implements Figure 1 the function defined in the truth table 100 of (the restrictions of the truth table 100 on its last two rows and two columns are consistent with the function N(·,·) in Equation 1).

[0071] The introduction of the symbol wildcard * has an important impact on the encoding scheme of this disclosure. In particular, the examples utilize a positional binary representation of a special type of integer pair, where the representations of the two integers in any pair do not share a 1 in the same position. This representation, called a bi-spanner in this application, can be of independent interest and its properties will be presented in Part IV. Compared with the Σ-CAM, the construction for the Σ-TCAM of this disclosure increases the redundancy by approximately 60%.

[0072] This application will conclude with the discussion in Part VIII.

[0073] II. Construction Based on Hamming-Metric Codes

[0074] This application presents a (separable) construction of the vector matrix multiplier with modifications for the Σ-CAM. For the purpose of this construction, the set of allowable error patterns is characterized by two parameters: the maximum number τ of columns in A that include faulty CAM cells c and the maximum number τ of L 1 -errors ("internal errors") per column i . That is, τ c and τ iBounded above by the Hamming weight of the error vector e and the L ∞ -norm, respectively. Thus, (τ c , τ i ) = (τ, 1) corresponds to the case where at most τ L 1 -errors can occur and at most one such error can occur in each column. Taking (τ c , τ i ) = (τ, τ) will cover the case where the total number of L 1 -errors is at most τ. Finally, taking (τ c , τ i ) = (τ, n) will correspond to the Hamming metric where at most τ columns can be in error without further assuming the number of L 1 -errors in each column.

[0075] Given the number of columns n, an upper bound τ c on the number of error columns, and an upper bound τ 1 on the number of L i -errors in each column, let p > 2τ i be an odd prime and let Example selection on the corresponding Hamming metric linear τ c -error correcting code C, which is assumed to satisfy the following three conditions.

[0076] a) It contains the all-one codeword.

[0077] b) It is systematic, i.e., there exists a one-to-one mapping such that for each the image E(u) has u as its k-prefix.

[0078] c) It has an efficient bounded-distance decoder for the received word the decoder returns the true error vector provided that

[0079] the parameters n and are related as

[0080]

[0081] This application next describes the (separable) encoder of the proposed coding scheme by its action on a given row Take a′ as a vector in which is first extended by the systematic encoder of C to a codeword of C,

[0082] ​

[0083] Among them Now, in the next step of constructing the vector matrix multiplier, for each redundant symbol can be extended to its base-2 representation That is

[0084]

[0085] Among them

[0086] ω m =(1 2 2 2 ...2 m-1 ).

[0087] Here, instead of Equation 7, the example will represent Set to in the vector such that

[0088]

[0089] Among them is obtained by changing its last term to 2 m-1 -1 from ω m . Since (2 m -2) / 2 < p ≠ 2 m -2, so the multiplier 2 m -2 in Equation 8 is invertible modulo p. Since p ≤ 2 m -1, so the extension in Equation 8 is indeed always possible (sometimes with two different representations of the m-vector ). In addition, for the example can take (even if another representation is possible, it will be chosen).

[0090] Finally, like the vector matrix multiplier, the image of a' under ε 0 is defined as:

[0091] ε 0 (a') = a = (a'|a"),

[0092] Among them

[0093]

[0094] Figure 2 The encoding mapping algorithm 200 in 0 (1 k ) = 1 n And on Im(ε0 ) has a linear span over the module To understand the properties of this module, define to map each vector

[0095]

[0096] where y′ = (y) [k> and map to the following image

[0097]

[0098] (where the MOD p operation is applied component - by - component). λ is homomorphic and it maps to C. In turn, this means that the example can (efficiently) decode any into the correct codeword in C, provided that the number of error symbols in y (and thus in ) does not exceed τ c . Further, if the number of L 1 -errors in each term of y′ does not exceed τ i , then from the inequality p > 2τ i , the example can correct all these errors.

[0099] Specifically, in the case where C is a normalized extended primitive BCH code over which satisfies the above conditions a) - c), and so do some of its abbreviations. The upper bound on the redundancy obtained by the example is bounded by

[0100]

[0101] where equality holds when (which is a case of interest). Since therefore the redundancy behaves as

[0102]

[0103] (where the constant multiplier in the O(τ c ) term is proportional to log 2 p ≈ log 2 τ i ).

[0104] Example 1. For the case where τ i = 1, where each column can tolerate at most one L 1 -error, the example takes p = 3. Accordingly

[0105]

[0106] In particular, for τ c = 1, the example gives n - k = (2 / log 2 3)log 2 n + O(1) ≈ 1.26log 2 n, and when τ c = 2, it can be obtained twice (i.e., 2.52log 2 n). However, for τ c = 2, it can be done better by replacing the BCH code example with a Preparata code that is linear in . The resulting redundancy is only 2log 2 n. The example can also obtain a similar redundancy with the construction of Part VI, with the additional benefit that two L 1 -errors can also occur in the same column of the array.

[0107] Example 2. For the case of τ i = 2, the example can take p = 5, in which case the example obtains the following approximation of the ratio between the redundancy and τ c ·log 2 n:

[0108]

[0109] However, due to the rounding in the term in Equation 9, if the example selects p = 7, then the example will obtain a smaller redundancy:

[0110]

[0111] For large τ i , the (p - 1) / p term in Equation 9 actually becomes 1, and the expression for the redundancy approximately becomes (2τ c - 1)·log 2 n.

[0112] Recall that the normalized extended primitive BCH code C over (for some which has length ) includes the all-one codeword, so it satisfies condition a). This condition also applies to any code obtained by shortening C on the 0-entries of any non-0 codeword of C (possibly after rescaling the coordinates). For example, for any proper divisor s > 2τ h of p c - 1, the code C contains t = (p h - 1) / s codewords c i, for \(i\in[t]\), each has a Hamming weight of \(s + 1\), and their supports overlap only on the coordinates corresponding to the code locator \(0\). Moreover, all their other non - zero terms are \(1\). Thus, for any \(w\in[0:t]\), the Hamming weight of the codeword \(\sum\) of \(C\) i∈[w> c i is \(s\cdot w\) (if \(p\) divides \(w\)) or \(s\cdot w+1\) (otherwise). That is, while satisfying condition a), all these code lengths can be achieved by shortening \(C\). For the actual range of parameters, \(p\) h - 1 has enough divisors (in particular, it is always divisible by \(2\) and \(p - 1\)). For example, when \(\tau\) i = 1, an example can take \(p = 3\). In this case, for \(h = 4,5,6\), the values are \(80=2\) 4 \(\cdot5\), \(242 = 2\cdot11\) 2 and \(728 = 2\) 3 \(\cdot7\cdot13\). Or when \(\tau\) i = 2, an example can take \(p = 5\), in which case \(5\) 4 - 1 = 624 = 2\) 4 \(\cdot3\cdot13\).

[0113] III. Extension to \(\sum\) - TCAM

[0114] This section describes the access error - correction problem in \(\sum\) - TCAM, that is, \(\sum\) - CAM based on TCAM cells (i.e., a specific type of CAM cell). If the entry \(x i ) i∈[l> of the input vector \(x=(x i )\) is the wildcard symbol \(*\), then the TCAM cell along row \(i\) in \(\sum\) - TCAM will produce an all - zero vector, which will thus not affect the output vector. Therefore, in the following discussion, it can be assumed that the input vector \(x\) is in .

[0115] For \(i\in[l]\), this application uses the notation to denote the internal state vector in an \(l\times n\sum\) - TCAM (on ). For this application makes denote the vector in which the entry is the output of the TCAM cell along row \(i\) when the input symbol is \(x\). Thus, and for and any \(j\in[n]\):

[0116]

[0117] In short,

[0118]

[0119] wherein Then, Equation 3 becomes

[0120]

[0121] Note that due to the *-cells (i.e., CAM cells programmed to store wildcards), the following relationship no longer holds:

[0122] Equation 11 indicates that the Σ-TCAM performs the following multiplication operation of the vector in by the 2l×n matrix on

[0123]

[0124] where A (0) and A (1) are l×n matrices, whose rows are respectively and However, it should be noted that the vectors and must be disjoint, i.e., they cannot have 1 at the same position. Now, if the example applies the separable encoder ε to the (non-intersecting) then the example can finally obtain rows that intersect on their redundant parts (a (0) )″ and (a (1) )″

[0125] a (0) = ((a (0) )′ | (a (0) )") and a (1) = ((a (1) )′ | (a (1) )")

[0126] Therefore, if the l×n array of TCAM cells is regarded as the 2l×n matrix in Equation 12, then the coding scheme for Σ-TCAM itself may not be separable. However, the dependency relationship between the rows in the matrix can be limited to the row pairs corresponding to the same row i of the TCAM cells in the physical array, i.e., and On the other hand, different from the setting in Part II, due to the relationship no longer holds, the example can remove the requirement that the all-one vector is a codeword in the induced code (is a codeword in the ambient module containing the induced code).

[0127] Therefore, the construction of the vector matrix multiplier adapted for Σ-TCAM may be different from that described in Part II. Specifically, let C, D, and E be the same as defined in Part II, except that m will be chosen differently below, and the example may no longer require condition a) (which requires C to include all-one codewords). Given two vectors representing the outputs of the first k cells along a given row in the Σ-TCAM (as in Equation 10), the example may apply the systematic encoder of C to both of these two vectors as in Equation 6,

[0128] and to produce codewords of C and However, the extension of Equation 7 will become

[0129]

[0130] where and are non-intersecting in , ρ is a fixed integer vector in such that for any pair Equation 13 can be satisfied. A simple choice for such vectors is

[0131] ρ = (ω m′ | ω m′ ),

[0132] where Here, In addition, the example can choose (correspondingly, ) such that its first (correspondingly, last) m′ terms are all zero. However, as described above, the redundancy of the scheme is This means that this simple choice of ρ can double the redundancy compared to the ∑-CAM in the second part. One goal is to do better than this simple scheme, and for this purpose, the example introduces the following definitions.

[0133] Let be an Abelian group, and let be a subset of . A bi-spanner of over is a multiset of elements of such that for every pair there exist non-intersecting subsets and of

[0134]

[0135] Equivalently, taking written as the vector There exist two non - intersecting vectors such that

[0136] ξ (0) = a (0) · ρ T and ξ (1) = a (1) · ρ T , Equation 15

[0137] The representation in Equation 13 corresponds to the case where and where q is a prime p (although in later examples values of q that are not necessarily prime will be considered). For m ≥ 2, let q m be the largest integer such that for any q ≤ qm has a bi - spanner of size m on . Figure 3 The right - most column in Table 300 of m lists several values of q that were found by an exhaustive computer search. For a given q = p, the example chooses m to be the minimum value such that qm ≥ q, thus allowing Equation 13 to be satisfied for any

[0138] Example 3. Referring to the parameters in Example 1, for p = 3 = q 3 the example can take m = 3 (whereas the simple construction would require taking m = 2m' = 4). The vector ρ=(1 1 2) is a on bi - spanner. Figure 4 Table 400 of shows the elements of (0) (as in Equation 15) and the corresponding representation of the values of the contents of the TCAM cells (due to symmetry, only pairs where ξ (1) ≥ ξ (0) need to be listed (ξ (1) ). The remaining pairs switch between a (0) and a (1) and are respectively between 0 and 1 in θ). As in Example 1 (where the example takes ) compared with the Σ-CAM structure, the Σ-TCAM structure increases the redundancy by 3 / 2 times.

[0139] Example 4. Referring to the parameters in Example 2, if the example selects p = 5, then, since q 4 = 6, so the example can take m = 4 (instead of taking m = 3 as in Example 3). In this case, compared with Σ-CAM, the redundancy of Σ-TCAM only increases by 4 / 3:

[0140]

[0141] The vector ρ = (1 2 3) is on a bi-spanner of Figure 5 and Table 500 of

[0142] shows the corresponding content of the TCAM cell.

[0143]

[0144] IV. Properties of Bi-Spanner

[0145] In this part, this application will present some properties of the sequence (q m ) m defined in Part III. In particular, the application shows that the sequence (log 2 q m ) / m converges to a limit greater than 0.622. Therefore, for a given q = p, the strategy for choosing m is to choose the smallest one such that q m ≥ q results in the redundancy of Σ-TCAM, which is (asymptotically) less than 1 / 0.622 < 1.607 times the redundancy of the corresponding Σ-CAM (while the simple method mentioned above would double the redundancy).

[0146] For and for some positive integer r

[0147] in the case of, the construction of the bi-spanner can have an additional requirement that the terms of ρ are all positive and ∑ v∈[m> ρ v = ||ρ|| = r. For any Let ξ (*) = r - ξ (0) - ξ (1) , and for disjoint subsets Let Under the condition that ||ρ|| = r, the example can rewrite Equation 14 as:

[0148]

[0149] Since max{ξ (0) , ξ (1) , ξ (*)} can be made as small as Also, since ρ is assumed to be all positive, the example can then derive from Equation 16 that for each v ∈ [m In particular

[0150]

[0151] Conversely, starting with and satisfying the equality of Equation 17 for all m > 1 in an infinite sequence generates a sequence of integers

[0152]

[0153] each of which is the largest For this largest r there is a fully positive bi - spanner ρ of size m such that ∥ρ∥ = r. From Equation 17 (when expressed with equality) and Equation 18 the example obtains

[0154]

[0155] And by induction on m, it is easy to obtain and both scale by approximately (3 / 2) m . That is, the growth rate of these sequences is

[0156]

[0157] Figure 3 Table 300 of shows the first few values of

[0158] Now, for any positive integer and on any bi - spanner ρ of (when taken modulo q, component - by - component modulo q) is also a bi - spanner of on. Thus In fact, if ρ could also have negative terms, even though the example still requires the sum of the terms in ρ to equal r, the example could do better. Denote the largest integer by r m ​ For this maximum integer r, has a bi - spanner such that ∑ v∈[m> ρ v = r, and the example has and for large enough m, the inequality is strict. (See Proposition 2 and Equation 22 below; for m = 6, the example already has ).

[0159] The example can be taken further and look at the bi - spanner of the set [q> on 2 =[q>×[q>. Let z m denote the maximum integer q for which [q> 2 has a bi - spanner of size m on . The sequences (r m ) m and (z m ) m are related by

[0160]

[0161] .

[0162] In fact, any bi - spanner of on is also a bi - spanner of [q> 2 . Moreover, any bi - spanner of the latter is also a bi - spanner of and can be made to sum to 0 by adding at most one element.

[0163] The sequence (z m ) m is non - decreasing and it is super - multiplicative, i.e.,

[0164]

[0165] For any if ρ and are bi - spanners of [q> and 2 on respectively, then

[0166]

[0167] is The bi-spanner of. Thus, according to the example of Fekete's lemma, we have:

[0168]

[0169] The limit in the last equation (which is the growth rate of (z m ) m and (r m ) m will hereafter be denoted by The lower and upper bounds on the first few values of z m found by computer search are shown in in Figure 3 Table 300. Specifically, the example gives

[0170]

[0171] Here, is strictly greater than 's growth rate. In the next proposition, the application shows that is also the growth rate of (q m ) m .

[0172] Proposition 2.

[0173]

[0174] Proof. When taking modulo q, any bi-spanner on [q> 2 is a bi-spanner of on . Thus, q m ≥ z m , and

[0175]

[0176] Conversely, given let q = q m and assume that ρ 1 is a bi-spanner of size m on . The example can regard ρ 1 as an integer vector in [q> m . Let ρ 2 be the smallest bi-spanner of [m> on 2 and let v m denote its size. Note that (The equality obtained when constructing a bi - spanner simply). Thus

[0177] ρ=(ρ 1 |-q·ρ 2 ), Equation 24

[0178] is on [q> 2 of the bi - spanner. In fact, given any (ξ (0) , ξ (1) ) ∈ [q> 2 , there exists such that

[0179]

[0180] This means there exists β (0) , β (1) ∈ [m> such that

[0181]

[0182] Since ρ 2 is a bi - spanner of [m> 2 , there exists such that

[0183]

[0184] The last two equations imply that ρ in Equation 24 is on of size m + v m of [q> 2 bi - spanner. Therefore, So

[0185]

[0186] The result is obtained from Equation 23 and Equation 25.

[0187] Therefore, the example can draw the conclusion that

[0188]

[0189] where the last inequality is obtained from a simple counting argument. Specifically

[0190]

[0191] V. Single L 1 - error correction in Σ - CAM and Σ - TCAM

[0192] This section describes the case when τ = 1 (where there is at most one L throughout the array1 - error). This situation corresponds to the parameters in Part II (τ c , τ i ) = (1, 1). Where the construction of Σ-CAM results in a redundancy of approximately 1.26 log 2 n (see Example 1), and the application of Σ-TCAM in Part II leads to an increase in redundancy by 3 / 2 to approximately 1.89 log 2 n (see Example 3).

[0193] This part presents the construction of Σ-CAM with a redundancy of m = [log 2 (2n + 1)]. The corresponding construction of Σ-TCAM will have the minimum redundancy m such that q m ≥ 2n + 1. In particular, for sufficiently large n, this redundancy may be less than 1.607 · log 2 (2n + 1) (see Proposition 2 and Equation 22).

[0194] Given the code length n, let it be the redundancy of the construction such that k = n - m, and let

[0195] α = (α j ) j∈[n> = (a′|α″)

[0196] be the vector of code locators in [k> where α′ = (α) [k:n> and α″ = (α)

[0197] i) The terms of α are non-zero elements in [2n + 1>.

[0198] ii) For any two different indices i, j ∈ [n> (unless both are in [k:n>):

[0199] α i ≠ α j and α i + α j ≠ 2n + 1

[0200] iii) α″ = ω m = (1 2 2 2 … 2 m-1 ).

[0201] Such a vector α can be constructed for each n > 4.

[0202] Single-L 1 - error correcting encoder will map such that

[0203]

[0204] (i.e., a″ is the binary representation of the left - hand side of Equation 26). Thus, the code induced by ε 1 is a subset of the following module over :

[0205]

[0206] Therefore, under the conditions i) - iii), any change of ±1 in any of the first k coordinates of any vector occurring in this module can always be corrected.

[0207] For this scheme to be applicable to Σ - CAM, it only requires This application shows that when n>9 is not a power of 2 (i.e., n≠2 m-2 ), it can always be achieved by appropriately choosing the code locator.

[0208] The example first adopts a code locator such that α′=(α j ) j∈[k> whose terms form the set

[0209] {α j} j∈{k> ={j + 1} j∈[n> \({2 j} j∈[m-1) ∪{2n + 1-2 m-1})

[0210] and α″=(α j ) j∈[k：n> =ω m (Note that 2 m-1 >n, and according to condition (ii), this requires excluding 2n + 1-2 m-1 from α′). Assume that the terms of α′ are in increasing order, α k-1 =n, unless when n = 2 m-1 -1, in which case α k-1 =n - 1. Let μ 1 denote the first moment (mod 2n + 1) of the code locator:

[0211] μ 1 =1 n ·α T MOD(2n + 1), Equation 27

[0212] If μ 1 =0, the example ends (but this case rarely occurs). By negating α k-1 (∈{n,n - 1}), the example can obtain μ1 , such that

[0213]

[0214] in this case there are Ω(k 2 ) index pairs (i, j) such that i and j are distinct in [k] and α i + α j = (μ 1 / 2) MOD (2n + 1). When both α i and α j are negated, the first moment μ 1 can then make modulo 2n + 1 equal to 0. For each n > 9, the Ω(k 2 )-terms can be positive.

[0215] Taking n to be odd in the above construction and adding an extra parity bit, the example can also detect two L 1 -errors (corresponding to (τ, σ) = (1, 1)), and the extended module will contain the vector 1 n+1 .

[0216] The modification of the construction of the vector matrix multiplier for ∑-TCAM is similar in spirit to what was done in the example in Section II. That is, the example changes condition iii) to:

[0217] iii) * α″ = ρ, where ρ is on 's bi-spanner.

[0218] Therefore, m should be chosen such that q m ≥ 2n + 1 to ensure such a bi-spanner. To detect two L 1 -errors, the example uses two extra bits to record the two possible values of the parity bit.

[0219] Example 5. Suppose a single L 1 -error correction coding scheme is sought for a ∑-CAM with k = 100. The example can choose the redundancy m to be the minimum such that

[0220] 2 m ≥ 2n + 1 = 2(k + m)+1 = 201 + 2m

[0221] The result is m = 8.

[0222] For ∑-TCAM, the example can choose m to be the minimum such that

[0223] q m≥2n + 1 = 2(k + m) + 1 = 201 + 2m

[0224] Figure 3 Table 300 of Figure 3 stops at a smaller value of qm, but the example can use the general recursion of (which is Equation 17 with an equality relation) to obtain explicit expressions for feasible m and ρ. Specifically, for m = 12, 13, 14, the example obtains 158, 237 respectively. Accordingly, the example can take m = 14, because

[0225]

[0226] Alternatively, the example can use the superproduct from Equations 20 and 21. It can be seen from Table 300 that

[0227] z 13 ≥z 2 ·z 11 ≥2·115 = 230 ≥ 227 = 201 + 2·13

[0228] This means the example can take m = 13.

[0229] VI. Double L 1 - Error correction

[0230] This part describes the case of τ = 2 (i.e., at most two Ls in the entire array 1 - errors), which includes the case of (τ c , τ i ) = (2, 1) in the construction of Part II. As pointed out in Example 1, the construction of ∑-CAM has a redundancy of approximately 2.521og 2 n, while the construction in this part has a redundancy of 2·log 2 n + O(1).

[0231] Let p > 3 be a prime number and define n 1 = (p - 1) / 2, k = n 1 - m, n 2 = n 1 + m, and n = n 2 + 1. The (separable) coding scheme has dimension k, length n, and thus redundancy n - k = 2m + 1. For this construction, the example can use the vector of code locators that satisfy conditions i)-iii) in Part V This application defines the coding mapping that maps the vector to the vector The following four conditions are satisfied.

[0232] (a) [k> = a′, Equation 28

[0233]

[0234] By applying the encoder ε in Equation 26 1 to a′, Equation 29 can be achieved (replacing n therein with n 1 = (p - 1) / 2). Equation 30 implies forming the binary representation. Equation 31 implies that the last term in a is the parity bit. The induced code of ε 2 is a subset of the module consisting of all vectors (using c instead of a in the expression) that satisfy the conditional equations 29 - 31. It can be noted here that that is, it can correct up to two +1 changes in any pattern within the first k coordinates (possibly in the same coordinate) of any vector in .

[0235] As described in Part V, by ensuring that 1 n belongs to Example adapts the encoding scheme of the vector matrix multiplier to ∑-CAM. Repeating what was described in Part V, it can be assumed that α is such that there are Ω(k 2 ) index pairs (i, j) such that i and j are distinct in [k> and α i + α j = (μ 1 / 2) MOD p, where μ 1 is the first moment of the code locator defined in Equation 27. Using

[0236] μ 3 = 1 n ·(α [3] ) T MOD p

[0237] represents the third moment of the code locator, which can be non-zero modulo p (and zero first moment). A method for obtaining such a code locator is described below.

[0238] Suppose (i, j) and (i′, j′) are two of the above Ω(k 2 ) index pairs, where

[0239] α i + α j ≡ αi′ +α j′ ≡μ 1 / 2 (mod p)

[0240] The example may not be able to obtain

[0241]

[0242] Conversely, this may mean that for at least one pair in the pair, say (i, j), once the example negates α i and α j , then μ 1 will become zero (mod p), while μ 3 may be non - zero. In fact, otherwise there would exist two different vectors in 1 with L -norm 2, and these two vectors would be in the same coset of the module : one has 1 at positions {i, j} (0 otherwise), and the other has 1 at positions {i′, j′}. However, this would mean This is a contradiction.

[0243] Now assume μ 3 ≠0, the example modifies equation 30 in two ways. First, the example replaces the vector ω with the vector m , where the vector is obtained by changing the last term of ω m to 2 m-1 - 1 (as shown in equation 8). Second, the example multiplies the right - hand side of equation 30 by the following (non - zero and) well - defined constant

[0244]

[0245] Since p > 2 m-1 , p does not divide 2 m - 2. Thus, equation 30 becomes

[0246]

[0247] (Compare with equation 8). It can be shown that the resulting module still has 2 - L 1 - error correction and 1 n satisfies equations 29 and 32. In addition, it also satisfies equation 31 when m is odd, in which case

[0248] When m is even, the example can further modify the construction to have an extra redundant bit (i.e., set n = n 2(+2) and replace equation 31 with, for example

[0249]

[0250] (such that ).

[0251] In the case of ∑-TCAM, the currently disclosed modifications to the vector matrix multiplier scheme are similar to those described in Sections III and V. Specifically, the example selects m as the minimum value such that q m ≥ 2n + 1. The example sets k = n 1 - m, n 2 = n 1 + m, and n = n 2 + 2. The example also takes α such that is on of the bi-spanner ρ (see condition (iii) in Section V). Equations 28 - 31 now become, for each

[0252] (a (x) ) [k> = (a (x) )′

[0253]

[0254] where a (0) and a (1) are disjoint (in particular, note that two bits are assigned to the parity check in the last equation).

[0255] VII. Multiple L 1 - Error Correction

[0256] This section describes the correction of any number τ of L 1 - Errors.

[0257] Given the number τ of correctable L 1 - Errors of a design, let p > 2τ be a prime number and define n 1 = (p - 1) / 2 and Furthermore, let α be an integer vector in that satisfies conditions (i) - (iii) in Section V. For denote the integer vector by α [i] and let H = H Ber = H Ber (α, τ) denote the τ × n 1Integer matrix with rows α [2i+1] , i ∈ [τ>. That is, when considered as a matrix over , H Ber is the parity-check matrix of the Berlekamp code C over Ber . Let P be any τ × τ integer matrix such that and define the following module over :

[0258]

[0259] When p > 2τ, it is known that the minimum Lee distance of C Ber is at least 2τ + 1. Thus, =

[0260]

[0261] For any coset of in the above equation also holds.

[0262] Let be the encoder in Part V (where n is replaced by n 1 ), and let a = (a′|a″) ∈ Im(ε 1 ) (where a′ = (a) [k> ). An example can compute the following syndrome vector of a

[0263]

[0264] Furthermore, if the example selects P such that its first column is the standard unit vector (1 0 0 …) T , then the example (from a ∈ Im(ε 1 )) obtains The example can expand each term in to its binary-based representation

[0265]

[0266] Now consider the coding mapping defined as follows

[0267]

[0268] where

[0269]

[0270] If y = ε(a)+e, where ||e|| ≤ τ, then, according to Equation 33 and Proposition 1, under the assumption that the (τ - 1)m-suffix of y is error-free, the example can recover a′ from y. This assumption can be ensured by applying the (second) encoder of a linear τ-L 1 -error correcting code of dimension (τ - 1)m. The example can continue this process recursively, but if the example makes only (2τ + 1)-overlaps in the second step, then the example can end up with the following total redundancy

[0271]

[0272] where n is the final code length. Thus, for n compared to τ, most of the redundancy is due to the first encoding stage.

[0273] To make this scheme applicable to Σ-CAM, the example selects α as in Section VI, and as done therein, the example replaces the vector ω in Equation 34 with . Consider the syndrome of the all-one vector in m . :

[0274]

[0275] where the first column in P is the standard unit vector. Recall

[0276] while

[0277]

[0278] It can be seen that while by appropriately choosing P, the example can have

[0279]

[0280] In this case, the example obtains that the image of under ε in Equation 35 is the all-one vector This argument applies to any subsequent recursive encoding step, especially when the step is just a repetition. Thus, this application shows that under the choice of parameters as in Section VI, the all-one vector can be guaranteed to be a codeword of the induced code. This argument applies to any subsequent recursive encoding step, especially when the step is just a repetition. Thus, this application shows that under the choice of parameters as in Section VI, the all-one vector can be guaranteed to be a codeword of the induced code.

[0281] Comparing Equation 36 with the redundancy of the construction in Section II, if the example replaces τ in Equation 9 with c = τ, then the value obtained by the example is less than the value obtained in Equation 36 in many cases (even when v iwhen >1). This is because the O(·) term in Equation 36 becomes non-negligible when τ is not small enough compared to n.

[0282] Finally, for Σ-TCAM, the example uses on the bi-spanner of to replace ω in Equation 34 m .

[0283] VIII. Ordinary BCAM and TCAM

[0284] Although this application relates to error correction schemes for Σ-CAM and Σ-TCAM, such schemes are also useful for more general BCAM and TCAM (which can be regarded as Σ-CAM / Σ-TCAM, where the integer sum of the outputs of the CAM cells along each column is replaced by the complement of their logical "OR"). By replicating each column 2τ + 1 times, the example can recover from any τ errors in the array, but the redundancy is excessive.

[0285] The error correction problem of BCAM has been explored in many papers. The currently proposed solutions involve hardware modifications to the sense amplifiers along each match line: "matching" is redefined to mean that the (integer) sum of the outputs of the CAM cells along a column does not exceed a specified threshold (therefore, the improved device is actually a quantized Σ-CAM; ordinary BCAM corresponds to t = 0). In such a device, the example can encode the content of each column using a t-error correcting binary code and encode the input vector accordingly. Then, the readout will be the same / similar to that of a BCAM without errors, provided that the number of errors in each column does not exceed t. For TCAM, it can be shown that this method will require at least a simple (2t + 1)-fold redundancy of the content of each column (resulting in excessive redundancy).

[0286] Figure 6 An example CAM cell 600 according to an example of the technology of the present disclosure is described.

[0287] As mentioned above, CAM can be divided into "binary" or "ternary". A binary CAM ("BCAM") composed of BCAM cells operates on (and stores data) input patterns of binary bits containing "0" and "1". A ternary CAM ("TCAM") composed of TCAM cells operates on (and stores data) input patterns of binary bits containing "0", "1", and "X" values. The "X" value is sometimes referred to as a "don't care" value or a "wildcard" value. When searching for an input pattern in TCAM, "X" will return a match for either a "0" bit or a "1" bit. Thus, a search for the input pattern "10X1" will return a match for the bit "1001" or "1011".

[0288] As mentioned above, the CAM-based circuits of the disclosed technology may utilize BCAM / BCAM cells or TCAM / TCAM cells, depending on the implementation.

[0289] CAM cell 600 illustrates an example of a 4-transistor-2-memristor (4T2M) TCAM cell that may be used in the CAM-based circuits of the disclosed technology. For example, CAM cell 600 may illustrate an example task-driven CAM cell programmed to store task-driven values that conform to a computing task. CAM cell 600 may also illustrate an example redundant CAM cell programmed to store redundant values.

[0290] As shown, CAM cell 600 includes a switching transistor T1 connected to data line SL and a switching transistor T2 connected to an inverted data line As described above, the voltage across data line SL and the inverted data line may correspond to the value / item (e.g., voltage signal) of the input vector applied to the CAM, where CAM cell 600 is part of the CAM. For example, the voltage across data line SL may correspond to the value / item (e.g., logic one) of the input vector, while the voltage across the inverted data line may correspond to the negated version of the value / item of the input vector (e.g., logic zero). Memristor M2 is connected to switching transistor T1, and memristor M1 is connected to switching transistor T2. As shown, the gate terminals of switching transistors T1 and T2 are connected to word line WL, which biases switching transistors T1 and T2. Immediately before and during a search / match operation, the voltage of word line WL may be raised above a threshold to activate switching transistors T1 and T2. When switching transistor T1 is activated, switching transistor T1 may provide an electrical connection between data line SL and memristor M2. In contrast, when switching transistor T1 is not activated (i.e., when the voltage across word line WL is below the threshold), data line SL may be electrically disconnected from memristor M2. Similarly, when switching transistor T2 is activated, switching transistor T2 may provide an electrical connection between the inverted data line and memristor M1. In contrast, when switching transistor T2 is not activated (i.e., the voltage across word line WL is below the threshold), the inverted data line may be electrically disconnected from memristor M1. Thus, including switching transistors T1 and T2 may ensure that memristors M1 and M2 are disconnected from the data lines of CAM cell 600 when a search / match operation is not being performed, which may reduce the overall power consumption of CAM cell 100.

[0291] As shown, memristors M1 and M2 are connected in series to form a resistive voltage divider 602. The output voltage of the resistive voltage divider 602 (i.e., the voltage at the common node G) is applied to the gate of the match line transistor T4 to control the activation of the match line transistor T4. When the match line transistor T4 is activated, it can discharge (i.e., "pull down") the voltage of the match line ML. For example, if the voltage applied to the gate of the match line transistor T4 exceeds a threshold, then the match line transistor T4 will activate and discharge (i.e., "pull down") the voltage across the match line ML - returning a mismatch. In contrast, when the voltage applied to the gate of the match line transistor T4 is less than or equal to the threshold, the match line transistor T4 may not be activated. Thus, the match line transistor T4 will not discharge (i.e., "pull down") the voltage across the match line ML - thus returning a match. Although "pull down" logic is described in the specific example of Figure 6 , it should be understood that in other examples, the CAM cell 600 can implement "pull up" logic.

[0292] As described above, the CAM cell 600 can be programmed to store task-driven values or redundant values by programming the conductances of the memristors M1 and M2. Although the conductances of the programmed memristors M1 and M2 generally remain unchanged (unless reprogrammed), the output voltage of the resistive voltage divider 602 (i.e., the voltage at the common node G) will change based on the values of the voltages received by the memristors M2 and M1 from the data line SL and the inverted data line respectively. For example, the memristors M1 and M2 can be programmed to a first conductance state (e.g., a logic zero conductance state that can correspond to a negative literal), i.e., when the voltages received from the data line SL and the inverted data line represent a logic one, this state causes the output voltage of the resistive voltage divider to be high (e.g., exceed the threshold), thereby activating the match line transistor T4 and returning a mismatch when the voltages across the data line SL and the inverted data line represent a logic 1. In contrast, the memristors M1 and M2 can be programmed to a second conductance state (e.g., a logic 1 conductance state that can correspond to a non-negative literal), i.e., when the voltages received from the data line SL and the inverted data line represent a logic zero, this state causes the output voltage of the resistive voltage divider to be high (e.g., exceed the threshold), thereby activating the match line transistor T4 and returning a mismatch when the voltages across the data line SL and the inverted data line represent a logic zero. In various examples, the memristors M1 and M2 can be programmed to a third conductance state (e.g., a wildcard conductance state), i.e., regardless of whether the voltages received from the data line SL and the inverted data line represent a logic zero or a logic one, this state can cause the output voltage of the resistive voltage divider to remain low (e.g., below the threshold), thereby ensuring that the match line transistor T4 remains deactivated and when the voltages across the data line SL and the inverted data line Returns a match when the voltage represents a logical zero or a logical one.

[0293] As shown, the service line transistor T3 can work in cooperation with the switch transistor T1 and / or the switch transistor T2 to use the service line SX to program the conductances of the memristors M1 and M2.

[0294] It should be understood that the CAM cell 600 is only an example of a CAM cell that can be included in the CAM-based circuits of the present technology. In other embodiments, the CAM cell 600 can include a BCAM cell or a TCAM cell with a different configuration, such as a CMOS-based CAM cell, a 6-transistor-2-memristor (6T2M) CAM cell, a 3-terminal CAM cell, a 16-transistor (16T) TCAM cell, etc.

[0295] Figure 7 An example CAM-based circuit 700 according to an example of the present disclosed technology is described.

[0296] As shown, the CAM-based circuit 700 can include a Σ-CAM 710 and one or more processing resources (not shown for simplicity) for programming the CAM cells of the Σ-CAM 710 and detecting one or more errors in the output vector (c) from the Σ-CAM 700. As shown, the output vector (c) can be composed of the constituent values c 0 -c n-1 composed.

[0297] As described above, a Σ-CAM (sometimes also referred to as a Hamming distance CAM) is a special type of CAM that is configured to sum the outputs from CAM cells arranged along corresponding columns. In other words, a Σ-CAM can refer to a CAM composed of an l×n array of CAM cells, where for some internal state values each CAM cell (i,j)∈[l>×[n> implements the function The programmed internal state of the Σ-CAM can be represented as an array (matrix) where a i represents row i and A j (=(A) {j} ) represents column j. The input to the Σ-CAM can include a row vector (e.g., a search key) where x i serves as the input to all CAM cells along row i. The corresponding column (corresponding to the matching row) j of the Σ-CAM can compute the integer sum of the outputs of the CAM cells arranged along the corresponding column j, i.e., c j =∑ i∈[l> N(x i ,a i,j )=w(x - A j)。These integers form the output row vector of the Σ-CAM, i.e., c = (c j ) j∈[n> ∈ [0:l] n . Thus, the Σ-CAM calculates the Hamming distance between the input vector and the content of the CAM cells along each of the n columns in the Σ-CAM.

[0298] As an illustrative example, the Σ-CAM 710 includes a number (n) of columns, i.e., from Figure 7 the leftmost column 0 to Figure 7 the rightmost column n-1 . The Σ-CAM 710 also includes a number (l) of rows, i.e., from Figure 7 the top row 0 to Figure 7 the bottom row l-1 .

[0299] For ease of reference, the CAM cells arranged along the columns 0 and rows 0 can be referred to as CAM cell 0,0 . Similarly, the CAM cells arranged along the columns n-1 and rows l-1 can be referred to as CAM cell n-1,l-1 , and so on.

[0300] The constituent CAM cells of the Σ-CAM 710 can include various types of CAM cells, including BCAM cells or TCAM cells (e.g., Figure 6 the exemplary CAM cell 600 in

[0301] As shown, the CAM cells arranged along the common rows of the Σ-CAM 710 are electrically connected along a common data line. For example, the CAM cells of row 0 are electrically connected along the first data line, and accordingly each CAM cell can receive an input value x 0 . Similarly, the CAM cells of row l-1 are electrically connected along the l th th data line, and accordingly each CAM cell can receive an input value x l-1 . Here, the input values x 0 -x l-1 can include the constituent values of the input vector (x).

[0302] As shown, the CAM cells arranged along the common columns of the Σ-CAM 710 are electrically connected along a common match line. For example, the CAM cells connected along column 0 are electrically connected along the match line ML 0 . Similarly, the CAM cells connected along column n-1 are electrically connected along the match line ML n-1 .

[0303] As shown (and as described above), the Σ-CAM 710 can be configured to sum the outputs from CAM cells arranged along corresponding columns. The final sum can be output on a match line associated with the corresponding column.

[0304] For example (as described above in connection with Figure 6 ), when a CAM cell (e.g., CAM cell 600) returns a mismatch, the CAM cell can be configured to pull down the voltage of the match line to which the CAM cell is connected. Thus, the Σ-CAM 710 can effectively sum / count the number of mismatches (or conversely, matches) returned by the CAM cells of the corresponding column by reading the final voltage output of the match line associated with the corresponding column.

[0305] For conceptual illustration, Figure 8 Example graph 800 is described, which shows a comparison between a threshold voltage and the voltage output of a match line associated with a corresponding column of the Σ-CAM 710. As shown, the threshold voltage is 0.9 a.u. volts, and the match line voltage is compared to the threshold voltage at three discrete times: t = 10.00 a.u. seconds; t = 10.25 a.u. seconds; t = 10.50 a.u. seconds. If the match line returns three matches (as shown by curve 802), the match line voltage will exceed the threshold voltage three times. If the match line returns two match points (as shown by curve 804), the match line voltage will exceed the threshold voltage two times. If the match line returns one match (as shown by curve 806), the match line voltage will exceed the threshold voltage once. If the match line returns zero matches (as shown by curve 808), the match line voltage will exceed the threshold voltage zero times. Here, the threshold voltage and the sensing / comparison times can be strategically selected to fit this relationship.

[0306] As described above, the CAM-based circuit 700 can detect and correct errors in the Σ-CAM 710 (i.e., "access" error correction) while the Σ-CAM 710 is performing computational tasks.

[0307] This "access" error correction method can improve the "offline" error detection / correction method. Such "offline" error detection / correction methods typically involve test programs that can interfere with the normal operation of the hardware accelerator during a computing task and thus must be performed "offline". For example, another method for detecting errors in a CAM can involve applying a sequence of test vectors to the CAM to detect programming errors and other circuit-based errors. Applying the test vectors can be independent of the computing task that the CAM is being used to perform, or else it would disrupt the computing task. Thus, this method will be performed "offline". In contrast, the CAM-based circuit 700 can correct the output vectors generated by the Σ-CAM 710 while the Σ-CAM 710 is performing a specified computing task. Thus, compared to other "offline" error detection and correction methods, this method can be computationally more efficient (i.e., consume fewer processing resources, time, power consumption, etc.).

[0308] The CAM-based circuit 700 realizes the advantages provided by "access" error detection and correction by leveraging the insightful observation that the Σ-CAM operates similar to a vector matrix multiplier (sometimes referred to as a dot product engine). Leveraging such an observation, the CAM-based circuit 700 uniquely adapts the error correction method for a vector matrix multiplier to the Σ-CAM. The adapted method involves adding redundant columns to the Σ-CAM 710. The CAM-based circuit 700 can utilize one or more processing resources (such as an encoder) to calculate the redundant values of the redundant columns such that the Σ-CAM 710 stores the codewords of a linear code (C) in each row. To further adapt the method for a new / specific type of hardware accelerator (i.e., the Σ-CAM 710), the CAM-based circuit 700 can modify the linear code (C) used to calculate the redundant values. That is, the CAM-based circuit 700 can modify the linear code (C) to include an all-ones vector. By this modification, the CAM-based circuit 700 can detect and correct errors in the output vectors from the Σ-CAM 710 based on this modified / specialized linear code (C).

[0309] For example (and as described above), the CAM-based circuit 700 can include: a) the Σ-CAM 710, which includes CAM cells arranged in a number (l) of rows and a number (n) of columns, where the Σ-CAM 710 is configured to sum the outputs from the number (l) of CAM cells connected along the respective columns of the number (n) of columns; and b) one or more processing resources for programming the CAM cells to store a matrix (A) having dimensions (l x n), where: i) each row of the matrix (A) includes a codeword of a linear code (C), and ii) the linear code (C) includes an all-ones vector of dimension (n) as a codeword.

[0310] In the Σ-CAM 710, the CAM cells connected along the k-th column among the n columns of numbers may include task-driven CAM cells. Correspondingly, the CAM cells connected along the (n-k)-th column among the n columns of numbers may include redundant CAM cells. Thus, each row of the Σ-CAM 710 includes k task-driven CAM cells and (n-k) redundant CAM cells. Therefore, programming the Σ-CAM 710 to store a matrix (A) with dimensions (l×n) may include: a) programming the k task-driven CAM cells of each row to store task-driven values that conform to a computing task; b) calculating redundant values of the (n-k) redundant CAM cells of each row based on the programmed task-driven values and a linear code (C); and c) programming the (n-k) redundant CAM cells of each row to store the calculated redundant values such that each row stores a codeword of the linear code (C). In some implementations, calculating the redundant values of the (n-k) redundant CAM cells of each row may include calculating the redundant values of the (n-k) redundant CAM cells of each row such that the task-driven values and the redundant values include a sequence of ones and zeros specified by the linear code (C).

[0311] In the CAM-based circuit 700, one or more processing resources may further be used to detect and correct one or more errors in an output vector (c) from the Σ-CAM 710 based on a linear code (C). In some embodiments, the output vector (c) may have dimensions (n). Correspondingly, the output vector (c) may include a concatenation of a task-driven output vector (c') and a redundant output vector (c"). Here, the task-driven output vector (c') may have dimensions (k) and correspond to the sum between: (1) the vector-matrix product between the transformation of an input vector (x) with dimensions (l) received by the Σ-CAM 710 and a task-driven storage matrix (A') with dimensions (l×k) stored by the task-driven CAM cells of the Σ-CAM 710; and (2) the vector product between a vector of all ones with dimensions (n) and a constant value (e.g., see Equation 4 below). Correspondingly, the redundant output vector (c") may have dimensions (n-k) and correspond to the sum between: (1) the vector-matrix product between the transformation of the input vector (x) and a redundant storage matrix (A") with dimensions (l×(n-k)) stored by the redundant CAM cells of the Σ-CAM 710; and (2) the vector product between a vector of all ones with dimensions (n) and a constant value (e.g., see Equation 4 above). Additionally, one or more processing resources may detect and correct one or more errors in the task-driven output vector (c') based on (e.g., by comparing) the linear code (C) and the redundant output vector (c").

[0312] Figure 9A block diagram of an example computer system 900 is described, in which various examples described herein can be implemented. The computer system 900 can also be used to calculate redundancy values and detect / correct errors in the output vectors from a Σ-CAM (e.g., Σ-CAM 710).

[0313] The computer system 900 includes a bus 912 or other communication mechanism for conveying information, and one or more hardware processors 904 coupled to the bus 912 for processing information. The hardware processors 904 can be, for example, one or more general-purpose microprocessors.

[0314] The computer system 900 also includes a main memory 906 coupled to the bus 912 for storing information and instructions to be executed by the processor 904, such as random access memory (RAM), cache, and / or other dynamic storage devices. The main memory 906 can also be used to store temporary variables or other intermediate information during the execution of instructions by the processor 904. When stored in a storage medium accessible by the processor 904, such instructions cause the computer system 900 to become a special-purpose machine customized to perform the operations specified in the instructions.

[0315] The computer system 900 also includes a read-only memory (ROM) 908 or other static storage device coupled to the bus 902 for storing static information and instructions for the processor 904. A storage device 910, such as a magnetic disk, optical disk, or USB thumb drive (flash drive), is provided and coupled to the bus 902 for storing information and instructions.

[0316] The computer system 900 can be coupled via the bus 902 to a display 912, such as a liquid crystal display (LCD) (or touch screen), for displaying information to a computer user. An input device 914, including alphanumeric keys and other keys, is coupled to the bus 902 for conveying information and command selections to the processor 904. Another type of user input device is a cursor control 916, such as a mouse, trackball, or cursor direction keys, for conveying direction information and command selections to the processor 904 and for controlling cursor movement on the display 912. In some embodiments, the same direction information and command selections as those of the cursor control can be implemented via receiving touches on a touch screen without a cursor.

[0317] The computing system 900 can include a user interface module to implement a GUI, which can be stored as executable software code executed by the computing device in a mass storage device. By way of example, such and other modules can include components such as software components, object-oriented software components, class components, and task components, processes, functions, attributes, procedures, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables.

[0318] Generally, as used herein, words such as "component", "engine", "system", "database", "data storage", etc. can refer to logic embodied in hardware or firmware, or to a collection of software instructions written in a programming language (such as Java, C, or C++) that may have entry and exit points. Software components can be compiled and linked into an executable program, installed in a dynamic link library, or can be written in an interpreted programming language, such as BASIC, Perl, or Python. It will be understood that software components can be callable from other components or from themselves and / or can be called in response to detected events or interrupts. Software components configured to execute on a computing device can be provided on a computer-readable medium, such as a compact disc, digital video disc, flash drive, disk, or any other tangible medium, or as a digital download (and can initially be stored in a compressed or installable format that requires installation, decompression, or decryption before execution). Such software code can be stored, in whole or in part, on the memory device of the executing computing device for execution by the computing device. Software instructions can be embedded in firmware, such as an EPROM. It will also be understood that hardware components can be composed of connected logic units, such as gates and flip-flops, and / or can be composed of programmable units, such as programmable gate arrays or processors.

[0319] Computer system 900 can implement the techniques described herein using custom hardwired logic, one or more ASICs or FPGAs, firmware, and / or program logic, the custom hardwired logic, one or more ASICs or FPGAs, firmware, and / or program logic combined with the computer system causing the computer system 900 to be a special-purpose machine or programming the computer system 900 as a special-purpose machine. According to one embodiment, the techniques herein are performed by computer system 900 in response to one or more sequences of one or more instructions contained in main memory 906 being executed by processor 904. These instructions can be read into main memory 906 from another storage medium, such as storage device 910. Execution of the sequence of instructions included in main memory 906 causes processor 904 to perform the processing steps described herein. In alternative embodiments, hardwired circuitry can be used in place of or in combination with software instructions.

[0320] As used herein, the term "non-transitory medium" and like terms refer to any medium that stores data and / or instructions that cause a machine to operate in a particular manner. Such non-transitory media can include non-volatile media and / or volatile media. Non-volatile media includes, for example, optical or magnetic disks, such as storage device 910. Volatile media includes dynamic memory, such as main memory 906. Common forms of non-transitory media include, for example, floppy disks, flexible disks, hard disks, solid state disks, magnetic tape, or any other magnetic data storage media, CD-ROM, any other optical data storage media, any physical media with hole patterns, RAM, PROM, and EPROM, FLASH-EPROM, NVRAM, any other memory chip or cartridge, and networked versions thereof.

[0321] Non-transitory media is different from transmission media but can be used in combination with transmission media. Transmission media participates in transferring information between non-transitory media. For example, transmission media includes coaxial cables, copper wire, and fiber optics, including the wires that make up bus 902. Transmission media can also take the form of acoustic or light waves, such as those generated during radio wave and infrared data communications.

[0322] Computer system 900 also includes a communication interface 918 coupled to bus 902. Network interface 918 provides two-way data communication coupling to one or more network links connected to one or more local networks. For example, communication interface 918 can be an Integrated Services Digital Network (ISDN) card, cable modem, satellite modem, or a modem that provides a data communication connection to a corresponding type of telephone line. As another example, network interface 918 can be a local area network (LAN) card that provides a data communication connection to a compatible LAN (or a WAN component communicating with a WAN). A wireless link can also be implemented. In any such implementation, network interface 918 transmits and receives electrical, electromagnetic, or optical signals that carry digital data streams representing various types of information.

[0323] Network links typically provide data communication to other data devices through one or more networks. For example, a network link can provide a connection through a local network to a host computer or to a data device operated by an Internet Service Provider (ISP). The ISP in turn provides data communication services through the global packet data communication network now commonly referred to as the "Internet". Both local networks and the Internet use electrical, electromagnetic, or optical signals that carry digital data streams. Signals through various networks and on network links, as well as signals through communication interface 918 (which carry digital data to and from computer system 900), are example forms of transmission media.

[0324] The computer system 900 can send messages and receive data, including program code, via a network, network link, and communication interface 918. In an Internet example, a server can send the requested code for an application via the Internet, an ISP, a local network, and communication interface 918.

[0325] The received code can be executed by the processor 904 when it is received and / or stored in the storage device 910 or other non-volatile memory for later execution.

[0326] Each of the processes, methods, and algorithms described in the previous sections can be embodied in code components executed by one or more computer systems or computer processors including computer hardware and be fully or partially automated. One or more computer systems or computer processors can also operate to support the execution of related operations in a "cloud computing" environment or as "software as a service" (SaaS). The processes and algorithms can be implemented partially or fully in dedicated circuitry. The various features and processes described above can be used independently of each other or can be combined in various ways. Different combinations and sub-combinations are intended to fall within the scope of this disclosure, and in some embodiments, certain method or process blocks can be omitted. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states associated therewith can be executed in a suitable other sequence or can be executed in parallel or in some other manner. Blocks or states can be added to or removed from the disclosed example embodiments. The execution of certain operations or processes can be distributed among computer systems or computer processors, not only residing within a single machine but also deployed across multiple machines.

[0327] As used herein, a circuit can be implemented using any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, ASICs, PLAs, PALs, CPLDs, FPGAs, logic components, software routines, or other mechanisms can be implemented to form a circuit. In an implementation, the various circuits described herein can be implemented as discrete circuits, or the described functions and features can be shared partially or fully in one or more circuits. Although the elements of various features or functions can be described independently or claimed as independent circuits, these features and functions can be shared in one or more common circuits, and such a description does not require or imply the need for independent circuits to implement such features or functions. In cases where software is used to implement a circuit in whole or in part, such software can be implemented to operate with a computing or processing system capable of performing the described functions, such as the computer system 900.

[0328] As used herein, the term "or" can be understood in an inclusive or exclusive sense. Further, the description of the singular form of a resource, operation, or structure should not be construed as excluding a plural form. Unless expressly stated otherwise, or otherwise understood in the context in which it is used, conditional language such as "can", "could", "may", or "might" generally is intended to convey that certain implementations include, while other implementations do not include, certain features, elements, and / or steps.

[0329] Unless expressly stated otherwise, the terms and phrases used herein and their variants should be construed as open-ended rather than limiting. Adjectives such as "conventional", "traditional", "normal", "standard", "known", and terms of similar import should not be construed to limit the item described to a given time period or to items available at a given time, but rather should be read to cover conventional, traditional, normal, or standard techniques that may be available or known now or at any time in the future. In some instances, the presence of expansive words and phrases such as "one or more", "at least", "but not limited to", or other similar phrases should not be construed as implying that a narrower case is intended or required in instances where such expansive phrases may be absent.

Claims

1. A system comprising: a summing content addressable memory (CAM), the summing content addressable memory comprising CAM cells arranged in a number (l) of rows and a number (n) of columns, wherein the summing CAM is configured to sum outputs from a number (l) of CAM cells connected along corresponding ones of the number (n) of columns; as well as one or more processing resources operable to program the CAM cell to store a matrix (A) having dimensions (l x n), wherein: Each row of the matrix (A) comprises a codeword of a linear code (C), and The linear code (C) includes all-one vectors of dimension (n) as codewords.

2. The system of claim 1, wherein: The CAM cells connected along number (k) of the number (n) of columns include task-driven CAM cells; and CAM cells connected along number (nk) of the number (n) columns include redundant CAM cells such that the corresponding row of the summing CAM includes number (k) task-driven CAM cells and number (nk) redundant CAM cells.

3. The system of claim 2, wherein programming the summation CAM to store the matrix (A) having dimensions (lxn) comprises: programming the number (k) of task-driven CAM cells of the corresponding row to store task-driven values ​​consistent with a computing task; calculating redundancy values ​​of the number (nk) of redundant CAM cells of the corresponding row based on the programmed task-driven value and the linear code (C); as well as The number (nk) of redundant CAM cells of the corresponding row are programmed to store the calculated redundant values ​​such that the corresponding row stores a codeword of the linear code (C).

4. The system of claim 3 , wherein calculating the redundancy values ​​of the number (nk) of redundant CAM cells of the corresponding row based on the programmed task-driven values ​​and the linear code (C) comprises: The redundant values ​​of the number (nk) of redundant CAM cells of the corresponding row are calculated such that the task driven values ​​and the redundant values ​​comprise a sequence of ones and zeros specified by the linear code (C).

5. The system of claim 2, wherein the one or more processing resources are operable to: One or more errors in an output vector (c) from the summing CAM are detected and corrected based on the linear code (C).

6. The system of claim 5, wherein: The output vector (c) has dimension (n); The output vector (c) comprises a cascade of a task-driven output vector (c') and a redundant output vector (c"); The task driven output vector (c') has dimension (k) and corresponds to the sum between: The transformation of the input vector (x) of dimension (l) received by the summation CAM is the same as the transformation of the input vector (x) of dimension (l) received by the summation CAM. a vector-matrix product between a task-driven storage matrix (A') of dimension (lxk) stored by said task-driven CAM unit of the CAM, and the vector product between the all-ones vector of dimension (n) and a constant value; The redundant output vector (c") has dimension (nk) and corresponds to the sum between: a vector-matrix product between said transformation of said input vector (x) and a redundant storage matrix (A") of dimension (lx(nk)) stored by said redundant CAM cells of said summing CAM, and a vector product between the all-ones vector of dimension (n) and the constant value; and Detecting and correcting one or more errors in the output vector (c) from the summing CAM based on the linear code (C) includes detecting and correcting the one or more errors in the task-driven output vector (c') based on the linear code (C) and the redundant output vector (c").

7. The system of claim 1, wherein: The corresponding CAM cells of the summing CAM include one or more programmable memristors; and Programming the corresponding CAM cells includes programming the conductance of the one or more programmable memristors.

8. A system comprising: One or more processing resources, the one or more processing resources being operable to: A summed content addressable memory (CAM) is programmed to store a matrix (A) having dimensions (lxn) where: Each row of the matrix (A) comprises a codeword of a linear code (C), and The linear code (C) comprises an all-one vector of dimension (n) as a codeword; and One or more errors in an output vector (c) from the summing CAM are detected and corrected based on the linear code (C).

9. The system of claim 8, further comprising the summing CAM.

10. The system of claim 9, wherein: The summing CAM includes CAM cells arranged in a number (l) of rows and a number (n) of columns; and The summing CAM is configured to sum outputs from a number (l) of CAM cells connected along corresponding columns of the number (n) columns.

11. The system of claim 10, wherein the one or more processing resources are operable to: programming the number (k) of task-driven CAM cells of the corresponding row to store task-driven values ​​consistent with the computing task; calculating redundancy values ​​of the number (nk) of redundant CAM cells of the corresponding row based on the programmed task-driven value and the linear code (C); as well as The number (nk) of redundant CAM cells of the corresponding row are programmed to store the calculated redundant values ​​such that the corresponding row stores a codeword of the linear code (C).

12. The system of claim 11 , wherein calculating the redundancy values ​​of the number (nk) of redundant CAM cells of the corresponding row based on the programmed task-driven values ​​and the linear code (C) comprises: The redundant values ​​of the number (nk) of redundant CAM cells of the corresponding row are calculated such that the task driven values ​​and the redundant values ​​comprise a sequence of ones and zeros specified by the linear code (C).

13. The system of claim 11, wherein: The output vector (c) has dimension (n); The output vector (c) comprises a cascade of a task-driven output vector (c') and a redundant output vector (c"); The task driven output vector (c') has dimension (k) and corresponds to the sum between: The transformation of the input vector (x) of dimension (l) received by the summation CAM is the same as the transformation of the input vector (x) of dimension (l) received by the summation CAM. a vector-matrix product between a task-driven storage matrix (A') of dimension (lxk) stored by said task-driven CAM unit of the CAM, and the vector product between the all-ones vector of dimension (n) and a constant value; The redundant output vector (c") has dimension (nk) and corresponds to the sum between: a vector-matrix product between said transformation of said input vector (x) and a redundant storage matrix (A") of dimension (lx(nk)) stored by said redundant CAM cells of said summing CAM, and a vector product between the all-ones vector of dimension (n) and the constant value; and Detecting and correcting one or more errors in the output vector (c) from the summing CAM based on the linear code (C) includes detecting and correcting the one or more errors in the task-driven output vector (c') based on the linear code (C) and the redundant output vector (c").

14. The system of claim 8, wherein: The corresponding CAM cells of the summing CAM include one or more programmable memristors; and Programming the corresponding CAM cells includes programming the conductance of the one or more programmable memristors.

15. A method comprising: A summed content addressable memory (CAM) is programmed to store a matrix (A) having dimensions (lxn) where: Each row of the matrix (A) comprises a codeword of a linear code (C), and The linear code (C) comprises an all-one vector of dimension (n) as a codeword; and One or more errors in an output vector (c) from the summing CAM are detected and corrected based on the linear code (C).

16. The method of claim 15, wherein: The summing CAM includes CAM cells arranged in a number (l) of rows and a number (n) of columns; and The summing CAM is configured to sum outputs from a number (l) of CAM cells connected along corresponding columns of the number (n) columns.

17. The method of claim 16, wherein programming the summation CAM to store the matrix (A) having dimensions (l xn) comprises: programming the number (k) of task-driven CAM cells of the corresponding row to store task-driven values ​​consistent with the computing task; calculating redundancy values ​​of the number (nk) of redundant CAM cells of the corresponding row based on the programmed task-driven value and the linear code (C); as well as The number (nk) of redundant CAM cells of the corresponding row are programmed to store the calculated redundant values ​​such that the corresponding row stores a codeword of the linear code (C).

18. The method of claim 17, wherein calculating the redundancy values ​​of the number (nk) of redundant CAM cells of the corresponding row based on the programmed task-driven values ​​and the linear code (C) comprises: The redundant values ​​of the number (nk) of redundant CAM cells of the corresponding row are calculated such that the task driven values ​​and the redundant values ​​comprise a sequence of ones and zeros specified by the linear code (C).

19. The method of claim 17, wherein: The output vector (c) has dimension (n); The output vector (c) comprises a cascade of a task-driven output vector (c') and a redundant output vector (c"); The task driven output vector (c') has dimension (k) and corresponds to the sum between: The transformation of the input vector (x) of dimension (l) received by the summation CAM is the same as the transformation of the input vector (x) of dimension (l) received by the summation CAM. a vector-matrix product between a task-driven storage matrix (A') of dimension (lxk) stored by said task-driven CAM unit of the CAM, and the vector product between the all-ones vector of dimension (n) and a constant value; The redundant output vector (c") has dimension (nk) and corresponds to the sum between: a vector-matrix product between said transformation of said input vector (x) and a redundant storage matrix (A") of dimension (lx(nk)) stored by said redundant CAM cells of said summing CAM, and a vector product between the all-ones vector of dimension (n) and the constant value; and Detecting and correcting one or more errors in the output vector (c) from the summing CAM based on the linear code (C) includes detecting and correcting the one or more errors in the task-driven output vector (c') based on the linear code (C) and the redundant output vector (c").

20. The method of claim 15, wherein: The corresponding CAM cells of the summing CAM include one or more programmable memristors; and Programming the corresponding CAM cells includes programming the conductance of the one or more programmable memristors.

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