Semiconductor dielectric structure and preparation method thereof

Abstract

The invention discloses a semiconductor dielectric structure and a preparation method thereof. The preparation method comprises the following steps: providing a substrate with a trench structure in a dielectric layer; performing constant-speed deposition on an insulating material in an atmosphere environment with catalytic gas and performing differential deposition in an atmosphere environment without catalytic gas in the groove structure to form a liner layer with the thickness gradually reduced in a first direction extending from the groove opening of the groove structure to the groove bottom; the surface of the liner layer is cleaned, and a target liner layer with the thickness gradually increased in the first direction is formed; and filling the trench structure with the target liner layer with a metal material to form a conductive structure. The liner layer with the thick upper part and the thin lower part is formed through constant-speed deposition and differential-speed deposition of the insulating material, so that the preparation efficiency is improved, the top of the liner layer is prevented from being etched through in the surface cleaning process to damage the groove structure, the accuracy of the contour of the groove structure is improved, the time-dependent breakdown performance in the middle-section manufacturing process of a semiconductor is improved, and the yield of the semiconductor is improved. And the dielectric property and the reliability of the semiconductor dielectric structure are greatly improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor dielectric structure and a method for preparing the same. Background Art

[0002] Semiconductor devices have extremely high requirements for processing precision. Especially when processing each contact hole module in the semiconductor middle-end process (MEOL) of a semiconductor substrate, a large number of processes such as etching, grooving, and filling need to be performed on the substrate to form various patterned structures on the substrate, so as to manufacture semiconductor devices with precise structures and excellent performances. However, the efficiency and preparation yield during the processing are often difficult to achieve a harmonious unity.

[0003] Among them, the groove structure formed in the substrate is very difficult to maintain the accuracy of the contour in subsequent processing steps. In order to prevent the groove structure from expanding outward, a barrier material is often coated in the groove structure as a liner for isolation in the prior art to prevent the side walls of the groove structure from being etched. And in order to improve production capacity, the forming speed of the barrier material is generally relatively fast, which easily leads to the difficulty in controlling the morphological contour of the liner. In subsequent processing processes such as etching or filling, the liner is prone to the phenomenon of non-uniform etching through, resulting in the exposure of the side walls of the groove structure. If the material of the substrate comes into contact with the etching environment, it will be quickly corroded, and irreversible damage will occur to the side walls of the groove structure. The loss amount of the groove opening of the groove structure is much larger than that of the groove bottom, so that the distance between the side walls of the groove structure, especially the top side walls of the groove structure, expands, and the shape accuracy of the groove structure cannot be maintained. The distance between the edge of the conductive structure filled in the groove structure and the adjacent gate will also decrease, which is likely to induce Time Dependence Dielectric Breakdown (TDDB) failure, greatly damaging or even invalidating the performance of the finally formed semiconductor dielectric structure. Summary of the Invention

[0004] In order to solve the problems of the prior art, embodiments of this application provide a semiconductor dielectric structure and a method for preparing the same. The technical solutions are as follows:

[0005] On the one hand, this application provides a method for preparing a semiconductor dielectric structure, including:

[0006] Providing a substrate having a groove structure in a dielectric layer;

[0007] A buffer layer is formed by depositing an insulating material within the trench structure. The buffer layer covers the inner wall of the trench structure, and along a first direction extending from the notch of the trench structure towards the bottom of the trench, the thickness of the buffer layer gradually decreases; during the formation of the buffer layer, isochronous deposition of the insulating material within the trench structure is performed in an atmosphere environment with a catalytic gas, and differential deposition of the insulating material within the trench structure is performed in an atmosphere environment without a catalytic gas, so that the thickness difference of the buffer layer formed on the sidewall of the trench structure reaches a preset value;

[0008] The surface of the buffer layer is cleaned to thin the buffer layer until the bottom wall of the trench structure is exposed, and a target buffer layer is formed on the sidewall of the trench structure; the thickness of the target buffer layer gradually increases along the first direction;

[0009] The trench structure having the target buffer layer is filled with a metal material to form a conductive structure.

[0010] In some exemplary embodiments, forming the buffer layer by depositing an insulating material within the trench structure includes:

[0011] In an atmosphere environment with the catalytic gas, an insulating material is deposited within the trench structure to form a first initial buffer layer;

[0012] In an atmosphere environment without the catalytic gas, an insulating material is deposited on the first initial buffer layer until the thickness difference of the insulating material on the sidewall of the trench structure along the first direction reaches the preset value, obtaining the buffer layer.

[0013] In some exemplary embodiments, forming the buffer layer by depositing an insulating material within the trench structure includes:

[0014] In an atmosphere environment without the catalytic gas, an insulating material is deposited within the trench structure until the thickness difference of the insulating material on the sidewall of the trench structure along the first direction reaches the preset value, forming a second initial buffer layer;

[0015] In an atmosphere environment with the catalytic gas, an insulating material is deposited on the second initial buffer layer, obtaining the buffer layer.

[0016] In some exemplary embodiments, forming the buffer layer by depositing an insulating material within the trench structure includes:

[0017] During the formation of the buffer layer, the catalytic gas is intermittently introduced to perform the deposition of the insulating material until the thickness difference of the insulating material on the sidewall of the trench structure along the first direction reaches the preset value, obtaining the buffer layer.

[0018] Further, the preparation method satisfies at least one of the following characteristics:

[0019] The deposition duration for forming the liner layer is 1.6 min to 12 min;

[0020] During the formation of the liner layer, the duration of a single introduction of the catalytic gas is 6 s to 15 s;

[0021] The time interval between two adjacent introductions of the catalytic gas is 10 s to 20 s;

[0022] The number of times of intermittently introducing the catalytic gas in the step of forming the liner layer is 6 to 20 times.

[0023] Further, the preset value is the thickness difference between the thickness of the liner layer on the sidewall of the notch and the thickness of the liner layer on the sidewall of the bottom of the notch, and the preset value is 1 nm to 2 nm.

[0024] Further, the deposition rate of the insulating material in the atmosphere environment with the catalytic gas is 1.0 to 1.5 nm / min, and the deposition rate of the insulating material in the atmosphere environment without the catalytic gas is 0.3 to 0.8 nm / min.

[0025] Further, in the environment without the catalytic gas, the ratio of the deposition rate of the insulating material to the depth of the trench structure is 0.10 to 0.04 min -1 .

[0026] Further, the preparation method satisfies at least one of the following characteristics:

[0027] The deposition temperature adopted during the formation of the liner layer in the trench structure is 300 to 400 °C;

[0028] The radio frequency power adopted during the formation of the liner layer in the trench structure is 200 to 400 W;

[0029] The deposition pressure adopted during the formation of the liner layer in the trench structure is 60 to 80 Pa.

[0030] Further, the insulating material includes at least one of silicon nitride, silicon oxynitride, and silicon carbide.

[0031] Further, the thickness of the liner layer on the sidewall of the trench structure is 6 nm to 9 nm.

[0032] Further, the width difference between the inner diameter at the top and the inner diameter at the bottom of the inner cavity of the trench structure with the target liner layer is 2 to 4 nm.

[0033] Further, filling a metal material in the trench structure having the target liner layer to form a conductive structure includes:

[0034] Forming a conductive isolation layer in the trench structure having the target liner layer;

[0035] Filling a metal material in the trench structure having the conductive isolation layer to form a metal filling structure, thereby obtaining the conductive structure.

[0036] On the other hand, the present application also provides a semiconductor dielectric structure, the semiconductor dielectric structure includes a substrate having a trench structure, and an electrode structure is provided below the trench structure;

[0037] A conductive structure is provided in the trench structure, and the conductive structure is in contact with the bottom wall of the trench structure;

[0038] A target liner layer is provided between the side wall of the trench structure and the conductive structure, and the thickness of the target liner layer gradually increases in a first direction extending from the notch of the trench structure to the bottom of the trench structure.

[0039] In the process of forming the liner layer in the present application, isochronous deposition of an insulating material is performed in an atmosphere environment having a catalytic gas, and differential deposition of the insulating material is performed in an atmosphere environment without a catalytic gas. The two cooperate to form a liner layer with a thicker upper part and a thinner lower part in the trench structure, greatly improving the preparation efficiency. At the same time, the liner layer is more resistant to etching than the substrate material, so that the liner layer with a thicker upper part and a thinner lower part is not easily etched through during the subsequent surface cleaning process, especially preventing the top of the liner layer from being etched through and damaging the side wall of the trench structure, effectively improving the accuracy of the shape profile of the trench structure and the preparation yield; moreover, the precise control of the shape of the trench structure is beneficial to improving the shape accuracy of the conductive structure subsequently formed in the trench structure and the accuracy of the critical dimension between the conductive structure and the adjacent gate, which is beneficial to improving the TDDB performance in the middle process of the semiconductor, and greatly improving the dielectric performance and reliability of the semiconductor dielectric structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0041] Figure 1 It is a cross-sectional view of a semiconductor dielectric structure provided by an embodiment of the present application;

[0042] Figure 2 It is a cross-sectional view of a substrate having a trench structure provided by an embodiment of the present application;

[0043] Figure 3 Schematic diagram of deposition state during isodeposition of insulating material;

[0044] Figure 4 Schematic cross-sectional view of trench structure after surface cleaning during only isodeposition of insulating material;

[0045] Figure 5 Schematic diagram of deposition state during differential deposition of insulating material;

[0046] Figure 6 Schematic diagram of principle of catalytic gas promoting growth and deposition of insulating material;

[0047] Figure 7 Flowchart of a preparation method for forming a buffer layer provided by an embodiment of the present application;

[0048] Figure 8 Flowchart of another preparation method for forming a buffer layer provided by an embodiment of the present application;

[0049] Figure 9 Flowchart of a preparation method for forming a buffer layer provided by a preferred embodiment of the present application;

[0050] Figure 10 Schematic diagram of state where catalytic gas intermittently exists over time in some embodiments of the present application;

[0051] Figure 11 Cross-sectional view of a trench structure with a target buffer layer provided by an embodiment of the present application;

[0052] Figure 12 Cross-sectional view of a trench structure with an electrically insulating layer provided by an embodiment of the present application;

[0053] Figure 13 Cross-sectional view of a semiconductor dielectric structure with a conductive structure provided by an embodiment of the present application.

[0054] Among them, the reference numerals are: 100 - substrate, 110 - trench structure, 111 - notch, 112 - bottom of trench, 120 - electrode structure, 130 - dielectric layer, 140 - epitaxial layer, 200 - buffer layer, 201 - target buffer layer, 202 - first initial buffer layer, 203 - second initial buffer layer, 300 - conductive structure, 310 - conductive isolation layer, 320 - metal filling structure, 400 - gate. Detailed implementation manners

[0055] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0056] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific object or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or server including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0057] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as the second element, component, region, layer, or part. And when discussing the second element, component, region, layer, or part, it does not mean that the present application necessarily has a first element, component, region, layer, or part.

[0058] In the manufacturing process of semiconductor devices, it is necessary to perform operations such as grooving and filling on structures such as substrates to form semiconductor devices with target structures. Among them, the size of the groove structure is extremely small. When the groove structure on the substrate is subjected to preparation steps such as surface cleaning and filling, the corrosion rate of the substrate material is relatively fast, and the etching degree is difficult to control, which easily causes excessive corrosion to the side walls of the groove structure. In the method of protecting the groove structure by a liner, the rate of forming the liner in the groove structure is also very fast, and it is difficult to ensure that the liner effectively protects the groove structure, resulting in a large change in the shape of the groove structure, especially the inner cavity spacing at the top of the groove structure, which in turn has an adverse effect on the semiconductor dielectric structure, and even causes the final semiconductor device to fail, thereby reducing the preparation yield of the semiconductor device and the life of the semiconductor device.

[0059] In semiconductor devices, precise control of the shape of the trench structure can effectively improve the overall performance of the semiconductor device. Among them, the control of the critical dimension between the source / drain contact and the gate can effectively reduce the breakdown risk during the operation of the semiconductor device and improve the TDDB performance of the gate oxide layer. TDDB is a time-dependent dielectric breakdown. Improving the TDDB performance is beneficial to extending the service life of the semiconductor device. The critical dimension refers to the critical distance between the source / drain contact and the gate at which the source / drain contact can work stably under normal operating voltage and is not easily broken down. When the distance between the source / drain contact and the gate is smaller than the adjacent dimension, breakdown is more likely to occur, resulting in TDDB failure of the gate oxide layer.

[0060] To solve the problems that it is difficult to balance the preparation efficiency and the preparation yield, it is difficult to accurately maintain the shape of the trench structure, and TDDB is prone to failure in the middle process of semiconductor manufacturing, this application provides a semiconductor dielectric structure and a preparation method thereof. The preparation method includes providing a substrate 100 with a trench structure 110 in a dielectric layer 130; forming a liner layer 200 in the trench structure 110 by depositing an insulating material, the liner layer 200 covering the inner wall of the trench structure 110, and along a first direction extending from the trench opening 111 of the trench structure 110 to the trench bottom 112, the thickness of the liner layer 200 gradually decreasing; performing surface cleaning on the liner layer 200 to thin the liner layer 200 until the bottom wall of the trench structure 110 is exposed, and forming a target liner layer 201 on the side wall of the trench structure 110; filling a metal material in the trench structure 110 with the target liner layer 201 to form a conductive structure 300. During the formation of the liner layer 200, isochronous deposition of the insulating material in the trench structure 110 is carried out in an atmosphere environment with a catalytic gas, and differential deposition of the insulating material in the trench structure 110 is carried out in an atmosphere environment without a catalytic gas. By the mutual cooperation of the two deposition processes, the liner layer 200 is formed in a shape with a thicker upper part and a thinner lower part on the side wall of the trench structure 110, and the thickness difference of the liner layer 200 formed on the side wall of the trench structure 110 reaches a preset value. Then, during the subsequent surface cleaning process, by utilizing the characteristic that the insulating material is more resistant to etching, the thicker liner layer 200 at the top of the trench structure 110 can effectively play a blocking role, offsetting the larger etching damage amount at the top, avoiding the liner layer 200 from being etched through and causing the top of the side wall of the trench structure 110 to be over-etched. Furthermore, the shape profile of the trench structure 110 can be effectively maintained, greatly improving the accuracy and reliability of the shape of the trench structure 110 during the preparation process, avoiding the diffusion of the conductive structure 300 formed in the subsequent trench structure 110 during the filling of the metal material, being beneficial to maintaining the spacing between the conductive structure 300 and the adjacent gate 400, that is, being beneficial to maintaining the reliability of the critical dimension of the source / drain contact, greatly improving the TDDB performance, and enhancing the performance and reliability of the semiconductor dielectric structure.

[0061] A semiconductor dielectric structure provided by an embodiment of this application is as Figure 1As shown, the semiconductor dielectric structure includes a substrate 100 having a trench structure 110, and an electrode structure 120 is disposed below the trench structure 110; a conductive structure 300 is disposed in the trench structure 110, and the conductive structure 300 is in contact with the bottom wall of the trench structure 110; a target liner layer 201 is disposed between the side wall of the trench structure 110 and the conductive structure 300, and the thickness of the target liner layer 201 gradually increases in a first direction extending from the notch 111 of the trench structure 110 to the bottom 112; wherein, the conductive structure 300 has a conductive isolation layer 310 and a metal filling structure 320, the conductive isolation layer 310 is disposed on the inner wall of the target liner layer 201 and the bottom wall of the trench structure 110, and the metal filling structure 320 is disposed in the inner cavity of the conductive isolation layer 310; the shape profile of the trench structure 110 of the semiconductor dielectric structure is accurate and excellent, and the diameter of the inner cavity of the trench structure 110 is precise, so that the critical dimension between the conductive structure 300 and the adjacent gate 400 is also precisely controlled, and its TDDB performance is greatly improved.

[0062] The following will be combined with Figure 1-12 to describe in detail the manufacturing method of the semiconductor dielectric structure of the embodiment of the present application.

[0063] Refer to Figure 2 , and provide a substrate 100 having a trench structure 110 in the dielectric layer; an electrode structure 120 is formed below the trench structure 110.

[0064] Among them, as Figure 1 shown, there may be a plurality of trench structures 110 on the substrate 100. The substrate 100 includes an insulating dielectric layer 130 (ILD) and an epitaxial layer 140 (EPI) located below the dielectric layer 130. The trench structure 110 is opened in the dielectric layer 130 and stops on the epitaxial layer 140, and is used to fill a metal material in the trench structure 110 in subsequent processing steps to form a conductive structure 300, so that the interlayer connection is realized through the conductive structure 300 and the electrode structure 120 below; at the same time, the dielectric layer 130 forms a good electrical isolation, effectively reducing the parasitic capacitance between the conductive structure 300 and the epitaxial layer 140 or the substrate 100; in some exemplary embodiments, the dielectric material of the dielectric layer 130 is silicon oxide, which has good electrical insulation and is also easy to be etched to form the trench structure 110, which is beneficial to reducing the difficulty and cost of semiconductor processing.

[0065] In some exemplary embodiments, the electrode structure 120 may be an active region, and the conductive structure 300 is located on and in contact with the active region, enabling the active region to perform multi-layer interconnection upward through the conductive structure 300; in some other exemplary embodiments, the electrode structure 120 may also be the metal material of the lower layer, so that the conductive structure 300 can perform multi-layer interconnection downward through the metal material of the lower layer until it is connected and conducted with the active region, realizing multi-layer interconnection.

[0066] Specifically, the trench structure 110 is formed by patterning and etching a photoresist and / or a hard mask formed above the dielectric layer 130; in some exemplary embodiments, the trench structure 110 is obtained by all in one etch (AIO), which refers to a process in which the three steps of via etching, photoresist removal, and trench etching are completed in the same step, so as to reduce the pattern defects generated during the formation of the trench structure 110 and greatly improve the processing efficiency of the semiconductor dielectric structure.

[0067] Next, a liner layer 200 is formed in the trench structure 110 by depositing an insulating material. The liner layer 200 covers the inner wall of the trench structure 110, and along the first direction extending from the notch 111 of the trench structure 110 to the bottom 112, the thickness of the liner layer 200 gradually decreases, that is, the liner layer 200 has a structure with a thicker top and a thinner bottom, so that the top and middle parts of the liner layer 200 are less likely to be completely etched compared to the bottom during the subsequent surface cleaning process, which can effectively prevent the surface cleaning from damaging the trench structure 110 and prevent the top sidewall of the trench structure 110 from being over-etched during the subsequent surface cleaning process, which is beneficial to maintaining the accuracy and stability of the shape of the trench structure 110 during the preparation of the semiconductor dielectric structure.

[0068] During the formation of the liner layer 200, isodeposition of the insulating material in the trench structure 110 is performed in an atmosphere environment with a catalytic gas, and differential deposition of the insulating material in the trench structure 110 is performed in an atmosphere environment without a catalytic gas. The deposition rate of the insulating material is affected by the catalytic gas and the depth of the trench structure 110, so that the thickness difference of the liner layer 200 formed on the sidewall of the trench structure 110 reaches a preset value. On the one hand, the preparation efficiency of the liner layer 200 is improved, and on the other hand, the forming accuracy of the formed liner layer 200 is improved, which is beneficial to the liner layer 200 effectively and reliably protecting the shape of the trench structure 110 during the subsequent processing, taking into account both the preparation efficiency and the preparation yield of the semiconductor dielectric structure.

[0069] Among them, such as Figure 3As shown, in an atmosphere environment with a catalytic gas, the degree to which the deposition rate of the insulating material is affected by the catalytic action of the catalytic gas is much greater than the degree to which it is affected by the depth of the trench structure 110. That is, in an atmosphere environment with a catalytic gas, the deposition rate of the insulating material is mainly affected by the catalytic action, the deposition rate is greatly accelerated, and the deposition rates on the inner walls of each part of the trench structure 110 are almost equal, so that an insulating material with an equal thickness is deposited in the trench structure 110; but as Figure 4 shown, the corrosion rate of the insulating material with an equal thickness during the subsequent surface cleaning process is affected by the depth of the trench structure 110. The loss amount of the insulating material at the notch 111 of the trench structure 110 is greater than the loss amount of the insulating material at the bottom 112 of the trench. It is very likely that when the insulating material at the bottom 112 still has a certain thickness, the insulating material at the notch 111 has been completely lost. Even the dielectric layer 130 material on the side wall of the trench structure 110 is corroded and lost, resulting in an increase in the inner cavity spacing at the top and even the middle of the trench structure 110. Correspondingly, the metal filling structure 320 filled in the trench structure 110 will show an outward expansion phenomenon, which is extremely prone to time-dependent dielectric breakdown failure, seriously reducing the TDDB performance and even causing the entire semiconductor dielectric structure to fail.

[0070] And as Figure 5 shown, in an atmosphere environment without a catalytic gas, the deposition rate is easily affected by the depth of the trench structure 110, making the deposition rate of the insulating material at the notch 111 greater than its deposition rate at the bottom 112, so as to show a differential deposition trend in the first direction, making the deposition thickness of the insulating material at the notch 111 greater than the deposition thickness of the insulating material at the bottom 112. And during the subsequent surface cleaning process, the etching rate of the insulating material at the notch 111 is greater than the etching rate of the insulating material at the bottom 112. That is, the insulating material with a larger deposition thickness at the notch 111 corresponds to a faster etching rate, and the insulating material with a smaller deposition thickness at the bottom 112 corresponds to a slower etching rate, so that a certain thickness of the insulating material can still remain at the notch 111 after surface cleaning, forming a reliable protection for the shape of the trench structure 110; through the cooperation of the two atmosphere environments, a liner layer 200 with a thicker upper part and a thinner lower part and a thickness difference in the first direction being a preset value is formed in the trench structure 110, taking into account the preparation efficiency and the shape accuracy of the trench structure 110 during the entire preparation process.

[0071] Specifically, the preset value is the thickness difference between the thickness of the liner layer 200 on the sidewall of the notch 111 and the thickness of the liner layer 200 on the sidewall of the bottom of the notch 112. In some exemplary embodiments, the preset value is 1 nm to 2 nm; it can be understood that the preset value can be any point value within 1 nm to 2 nm; for example, the preset value can be 1 nm, 1.2 nm, 1.3 nm, 1.5 nm, 1.7 nm, 1.8 nm, 2.0 nm, etc.; in this way, it can be ensured that a certain thickness can still be retained at the top and middle parts of the target liner layer 201 after surface cleaning, avoiding the situation of being completely etched through, making the shape of the trench structure 110 after surface cleaning accurate, the cross-section excellent, and the spacing from the gate 400 large enough, and the TDDB performance in the middle semiconductor manufacturing process has been greatly improved.

[0072] Specifically, the thickness of the liner layer 200 on the sidewall of the trench structure 110 is 6 nm to 9 nm, and the preset value of the thickness difference is always maintained within the range of 1 nm to 2 nm; it can be understood that the thickness can be any point value within 6 nm to 9 nm, and will not be enumerated here; in this way, it can form a stable and effective protection for the sidewall of the trench structure 110, avoiding damage to the trench structure 110 caused by the liner layer 200 being etched through during the subsequent surface cleaning process, so that the trench structure 110 can still maintain precise boundaries and excellent contours after subsequent processing, and the TDDB performance in the middle semiconductor manufacturing process has been greatly improved; in some preferred embodiments, the thickness of the liner layer 200 on the sidewall of the trench structure 110 is 7 nm to 8 nm. The thickness of the liner layer 200 is appropriate and further thins after subsequent surface cleaning treatment, avoiding adverse effects on the dielectric properties of the semiconductor dielectric structure caused by the target liner layer 201 being too thick, which is beneficial to improving the structural reliability and performance stability of the semiconductor dielectric structure.

[0073] Specifically, the insulating material used for the liner layer 200 has better etching resistance than the material of the dielectric layer 130, so as to reduce the loss amount during the subsequent surface cleaning process and prevent damage to the shape profile of the trench structure 110 from expanding; in some alternative embodiments, the insulating material used in the process of forming the liner layer 200 includes at least one of silicon nitride, silicon nitride compound, and silicon carbide. This insulating material has a lower etching rate than silicon oxide and is more resistant to etching during the subsequent surface cleaning process to avoid the liner layer 200 being etched through and losing its blocking effect during the subsequent surface cleaning process; in some exemplary embodiments, the insulating material used to form the liner layer 200 in the trench structure 110 is silicon nitride, which is easy to obtain and has low cost.

[0074] Specifically, during the formation of the liner layer 200, the insulating material is deposited in the trench structure 110 by at least one of physical vapor deposition, atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), and plasma enhanced chemical vapor deposition (PECVD); in some exemplary embodiments, silicon nitride is deposited in the trench structure 110 by plasma enhanced chemical vapor deposition, and the raw materials of the insulating material used to deposit silicon nitride in the trench structure 110 during the formation of the liner layer 200 include: The liner layer 200 is formed by reacting diiodosilane with nitrogen to generate silicon nitride which is deposited in the trench structure 110 to form the liner layer 200. Diiodosilane, as a silicon source for chemical vapor deposition, can generate more active silicon radicals under plasma enhancement, which is beneficial to accelerate the deposition rate of silicon nitride and improve the processing efficiency. In addition, the deposition temperature and deposition pressure are less required in the process of depositing silicon nitride by using diiodosilane and nitrogen, so that the deposition temperature and deposition pressure of the deposition process are controllable, which is beneficial to reduce the processing difficulty.

[0075] In some exemplary embodiments, the gas flow ratio of diiodosilane and nitrogen is 20 / 60 to 20 / 140; it is understandable that the gas flow ratio can be any point value between 20 / 60 and 20 / 140; exemplarily, the gas flow ratio can be 20 / 60, 20 / 70, 20 / 80, 20 / 90, 20 / 100, 20 / 120, 20 / 140, etc.; within this gas flow ratio range, the deposition rate of silicon nitride is precisely controllable, so that silicon nitride can be stably and reliably deposited in the groove structure 110 to form the liner layer 200, which is also beneficial to precisely control the shape, thickness, thickness difference in the first direction, etc. of the liner layer 200 during the entire process of forming the liner layer 200, with high accuracy.

[0076] Specifically, in some exemplary embodiments, the catalytic gas is a gas capable of providing hydrogen atoms to promote the growth of the insulating material on the inner wall of the trench structure 110; illustratively, the catalytic gas includes hydrogen; Figure 6 As shown, during the process of forming the liner layer 200, hydrogen atoms can form Si-H bonds with silicon atoms in the insulating material raw material, greatly accelerating the deposition of the insulating material. In addition, hydrogen can also inhibit oxidation reactions to protect silicon atoms from being oxidized, and can also promote the growth and deposition of the insulating material.

[0077] Specifically, in some exemplary embodiments, the gas flow ratio of catalytic gas hydrogen to nitrogen is 1:1 to 1:2; it can be understood that this gas flow ratio can be any point value within 1:1 to 1:2, and will not be enumerated here; within this gas flow ratio range, hydrogen can play a catalytic role, effectively accelerating the deposition of the insulating material, making the deposition rates of the insulating material at the top and bottom of the trench structure equal, while avoiding waste of hydrogen gas.

[0078] Specifically, the deposition rate of the insulating material in an atmosphere environment with catalytic gas is greater than that in an atmosphere environment without catalytic gas; in some embodiments, the deposition rate of the insulating material in an atmosphere environment with catalytic gas is 1.0 to 1.5 nm / min, and the deposition rate of the insulating material in an atmosphere environment without catalytic gas is 0.3 to 0.8 nm / min; it can be understood that the deposition rate in an atmosphere environment with catalytic gas can be any point value within 1.0 to 1.5 nm / min, and the deposition rate in an atmosphere environment without catalytic gas can be any point value within 0.3 to 0.8 nm / min; exemplarily, the deposition rate in an atmosphere environment with catalytic gas can be 1.0 nm / min, 1.1 nm / min, 1.2 nm / min, 1.3 nm / min, 1.5 nm / min, etc.; through the coordinated cooperation between the deposition rate in an atmosphere environment with catalytic gas and the deposition rate in an atmosphere environment without catalytic gas, the forming efficiency of the liner layer 200 can be greatly accelerated, and it is convenient to control the shape and thickness of the liner layer 200, improving the structural compactness, insulation and etching resistance of the liner layer 200.

[0079] Specifically, during the differential deposition process in an atmosphere environment without catalytic gas, the deposition rate of the insulating material is related to the depth of the trench structure 110. Among them, on the sidewall of the trench structure 110 with a deeper depth, the deposition rate of the insulating material is slower; in some exemplary embodiments, during the process of forming the liner layer 200 in the trench structure 110, the ratio between the deposition rate of the insulating material and the depth of the trench structure 110 in an atmosphere environment without catalytic gas is 0.10 to 0.04 min -1 , so that the insulating material forms a shape with a thicker upper part and a thinner lower part in the trench structure 110. Combining with the isometric deposition step in an atmosphere environment with catalytic gas, the thickness difference between the thickness of the insulating material at the trench opening 111 and the thickness of the insulating material at the trench bottom 112 is gradually and precisely controlled, so that the thickness of the insulating material at the trench opening 111 always remains slightly greater than the thickness of the insulating material at the trench bottom 112, which is beneficial to improving the structural accuracy of the formed liner layer 200 and ensuring the reliability of the liner layer 200 to protect the sidewall of the trench structure 110 in subsequent steps.

[0080] Specifically, in some exemplary embodiments, the liner layer 200 is formed by successively providing an atmosphere environment with a catalytic gas and an atmosphere environment without a catalytic gas, as Figure 7 shown, the formation of the liner layer by depositing an insulating material in the trench structure 110 includes:

[0081] In an atmosphere environment with a catalytic gas, deposit an insulating material in the trench structure 110 to form a first initial liner layer 202;

[0082] In an atmosphere environment without a catalytic gas, deposit an insulating material on the first initial liner layer 202 until the thickness difference of the insulating material along the first direction on the sidewalls of the trench structure 110 reaches a preset value, obtaining the liner layer 200.

[0083] Among them, as Figure 7 shown, first, in an atmosphere environment with a catalytic gas, the insulating material is deposited at a constant speed, greatly improving the deposition rate to form the first initial liner layer 202. At this time, the thickness of each part of the first initial liner layer 202 is equal; then, the catalytic gas in the environment is removed to form an atmosphere environment without a catalytic gas, and differential deposition of the insulating material is carried out in this atmosphere environment, so that the deposition rate of the insulating material at the notch 111 is greater than the deposition rate of the insulating material at the bottom 112 of the trench. Then, the thickness of the insulating material in the trench structure 110 further thickens to different degrees on the basis of the first initial liner layer 202. Finally, when the thickness difference between the insulating material on the sidewall of the notch 111 and the insulating material on the sidewall of the bottom 112 reaches the preset value, a liner layer 200 with a thicker top and a thinner bottom is obtained. The thickness of the top of the liner layer 200 is slightly greater than the thickness of the bottom of the liner layer 200. On the one hand, it reduces the change in the original shape of the trench structure 110, and on the other hand, it plays an effective blocking role in subsequent steps to prevent the trench structure 110 from expanding undesirably.

[0084] Specifically, in some other exemplary embodiments, the liner layer 200 is formed by successively providing an atmosphere environment without a catalytic gas and an atmosphere environment with a catalytic gas, as Figure 8 shown, the formation of the liner layer by depositing an insulating material in the trench structure 110 includes:

[0085] In an atmosphere environment without the catalytic gas, deposit an insulating material in the trench structure until the thickness difference of the insulating material along the first direction on the sidewalls of the trench structure reaches the preset value, forming a second initial liner layer;

[0086] In an atmosphere environment with the catalytic gas, deposit an insulating material on the second initial liner layer to obtain the liner layer.

[0087] Among them, as Figure 8As shown, in an atmosphere environment without catalytic gas, a second initial cushion layer 203 with a thicker upper part and a thinner lower part is first formed in the trench structure 110 by differential deposition of an insulating material. During this differential deposition process, there is already a certain thickness difference between the top and bottom thicknesses of the second initial cushion layer 203. Until the thickness difference of the formed second initial cushion layer 203 reaches a preset value, that is, the second initial cushion layer 203 and the subsequently formed cushion layer 200 have the same thickness difference in the first direction, then only the second initial cushion layer 203 needs to be thickened during the subsequent isodeposition process, greatly reducing the operation difficulty of the preparation process; thereafter, catalytic gas is introduced to form an atmosphere environment with catalytic gas, and isodeposition of the insulating material is further carried out in this atmosphere environment to increase the thickness of the insulating material, so that the formed cushion layer 200 has sufficient thickness to offset the structural loss caused by the subsequent surface cleaning process, avoiding irreversible damage to the shape of the trench structure 110, greatly improving the contour accuracy of the trench structure 110 and the subsequent metal filling structure 320 filled therein, and effectively reducing the risk of TDDB failure.

[0088] In some exemplary embodiments, the deposition duration of the isodeposition step is 3 min to 5 min, and the deposition duration of the differential deposition step is 5 min to 7 min; thus, an insulating material with a certain thickness can be deposited on the sidewall of the trench structure 110, and it is not easy to expose the sidewall of the trench structure 110 after subsequent surface cleaning, and it is even less likely to cause the sidewall of the trench structure 110 to be over-corroded or the subsequent filling structure to abnormally diffuse, greatly improving the reliability of maintaining the precise shape of the trench structure 110, being beneficial to improving the preparation yield, and improving the TDDB performance of the semiconductor dielectric structure; it can be understood that the deposition duration of the isodeposition step can be any point value within 3 min to 5 min, and the deposition duration of the differential deposition step can be any point value within 5 min to 7 min, which will not be enumerated here.

[0089] Specifically, in some preferred embodiments, forming the cushion layer 200 in the trench structure 110 by depositing an insulating material includes:

[0090] During the formation of the cushion layer, catalytic gas is intermittently introduced to deposit the insulating material until the thickness difference of the insulating material on the sidewall of the trench structure in the first direction reaches the preset value to obtain the cushion layer.

[0091] Among them, the cushion layer is obtained by depositing an insulating material by intermittently providing an atmosphere environment in which a catalytic gas is present or intermittently providing an atmosphere environment in which a catalytic gas is absent. Intermittent operation can be achieved by intermittently introducing a catalytic gas or by intermittently removing the catalytic gas. The two are the same operation. In addition, the step of isochronous deposition by introducing a catalytic gas can be carried out as an initial sub-step for forming the cushion layer, and then intermittent operation is carried out. Alternatively, the step of differential deposition in an atmosphere environment without a catalytic gas can be used as the initial sub-step of the step of forming the cushion layer, and then intermittent operation is carried out, which has good flexibility.

[0092] In some exemplary embodiments, such as Figure 9 and Figure 10 shown, taking two rounds of intermittent operation as an example for illustration. First, introduce a catalytic gas to form a first initial cushion layer 202 with an equal thickness in an atmosphere environment with a catalytic gas. Then, remove the catalytic gas and perform differential deposition of the insulating material in an atmosphere environment without a catalytic gas to thicken the thickness of the insulating material on the first initial cushion layer 202 and form a structural prototype with a thicker upper part and a thinner lower part. After that, introduce the catalytic gas again for isochronous deposition to further thicken the thickness of the insulating material. Then, remove the catalytic gas again and continue differential deposition in an atmosphere environment without a catalytic gas to further thicken the insulating material. And, relative to the thickness difference formed by the insulating material after the first differential deposition step, the thickness difference formed by the insulating material in the first direction after the second differential deposition step is further increased, but still does not reach the preset value. Then, repeat the above isochronous deposition step and differential deposition step until the thickness difference formed by the insulating material in the first direction accumulates to the preset value, and a cushion layer 200 with a specific thickness and a preset thickness difference is obtained. The isochronous deposition step and the differential deposition step are alternately carried out, so that the deposition shape and deposition thickness of the insulating material during the preparation process can be controlled flexibly and precisely, and the forming accuracy of the cushion layer 200 is high.

[0093] Specifically, in some exemplary embodiments, during the process of intermittently introducing a catalytic gas (or intermittently removing the catalytic gas) to form the cushion layer 200, the deposition duration for forming the cushion layer 200 is 1.6 min to 12 min. It can be understood that the deposition duration can be any point value within 1.6 min to 12 min, which will not be enumerated here. In this way, the thickness of the cushion layer 200 and its thickness difference in the first direction can be effectively controlled to reach the preset value, and the etching damage can be effectively neutralized during the subsequent surface cleaning process, avoiding the cushion layer 200 from being etched through and damaging the trench structure 110. Preferably, the deposition duration for forming the cushion layer 200 is 8 min to 12 min.

[0094] Specifically, in some embodiments, during the formation of the liner layer 200, the duration of a single introduction of the catalytic gas during the intermittent introduction of the catalytic gas is 6 s to 15 s; it can be understood that the duration of a single introduction of the catalytic gas can be any point value within 6 s to 15 s; exemplarily, the duration of a single introduction of the catalytic gas can be 6 s, 8 s, 10 s, 11 s, 12 s, 15 s, etc.

[0095] Specifically, in some embodiments, during the intermittent introduction of the catalytic gas, the time interval between two adjacent introductions of the catalytic gas is 10 s to 20 s; it can be understood that the time interval between two adjacent introductions of the catalytic gas can be any point value within 10 s to 20 s; exemplarily, the time interval between two adjacent introductions of the catalytic gas can be 10 s, 11 s, 13 s, 15 s, 16 s, 19 s, 20 s, etc.

[0096] Specifically, in some embodiments, the number of times of the step of intermittently introducing the catalytic gas for forming the liner layer is 6 to 20 times; it can be understood that the number of times can be any point value within 6 to 20 times; exemplarily, the number of times can be 6 times, 8 times, 10 times, 13 times, 15 times, 17 times, 20 times, etc.

[0097] Within the above ranges of the duration of a single introduction of the catalytic gas, the time interval between two adjacent introductions of the catalytic gas, and the number of times of the step of intermittently introducing the catalytic gas, the forming efficiency and forming accuracy of the liner layer 200 can be synergistically improved. Among them, through the alternation of multiple rounds of isovelocity deposition and differential deposition, the gradual accumulation of the insulating material on the inner wall of the trench structure 110 is realized until the liner layer 200 with a preset thickness difference is formed. At the same time, the liner layer 200 has a certain thickness, and the liner layer 200 can provide enough thickness to be etched and damaged during the subsequent surface cleaning process. The shape with a thicker upper part and a thinner lower part can effectively prevent the top of the liner layer 200 from being etched through and damaging the trench structure 110, avoid the outward expansion of the trench structure 110 during the subsequent processing, and the preset value is small, and the thickness of the liner layer 200 is also small, avoiding the influence of the liner layer 200 on the edge profiles of the original trench structure 110 and the subsequently formed metal filling structure 320, which is beneficial to improving the performance of the finally formed semiconductor dielectric structure.

[0098] Specifically, the deposition temperature used in the process of forming the liner layer 200 within the trench structure 110 is 300 to 400 °C; it can be understood that this deposition temperature can be any point value within 300 to 400 °C; exemplarily, this deposition temperature can be 300 °C, 330 °C, 350 °C, 360 °C, 380 °C, 400 °C, etc.; in this way, it can enable the insulating material to be stably deposited in the trench structure 110, with good deposition reliability, and is also beneficial to improving the performance of the liner layer 200, reducing the internal stress of the formed liner layer 200, making the structure dense, improving the etching resistance of the liner layer 200, so that the liner layer 200 can effectively protect the trench structure 110 and prevent the trench structure 110 from diffusing during subsequent processing. In addition, at this deposition temperature, it is also beneficial to improving the insulation performance of the liner layer 200, reducing charge traps, enhancing the breakdown voltage resistance, improving the TDDB performance of the semiconductor dielectric structure in this middle process, and greatly improving the electrical performance of the finally formed semiconductor dielectric structure.

[0099] Specifically, the radio frequency power used in the process of forming the liner layer 200 within the trench structure 110 is 200 to 400 W; it can be understood that this radio frequency power can be any point value within 200 to 400 W, and will not be enumerated here; at this radio frequency power, the reaction gas can be fully ionized to provide the ions, neutral atomic groups, and plasma required for the deposition of the insulating material, so as to promote the deposition of the insulating material and improve the reliability of the deposition of the insulating material. At the same time, it can improve the uniformity and density of the internal structure of the liner layer 200, reduce the occurrence of holes in the liner layer 200, and also enhance the corrosion resistance of the liner layer 200.

[0100] Specifically, the deposition pressure used in the process of forming the liner layer 200 within the trench structure 110 is 60 to 80 Pa; it can be understood that this deposition pressure can be any point value within 60 to 80 Pa, and will not be enumerated here; in this way, the deposition rate of the insulating material can be effectively adjusted, and the uniformity of the internal structure of the formed liner layer 200 can be improved.

[0101] In addition, during the process of forming the liner layer 200, in some exemplary embodiments, the specific set values of the preparation process can always be maintained as the same parameter values, and the parameter values include those affecting the deposition effect such as temperature, pressure, gas flow ratio, and duration, etc., so as to make the preparation process precise and orderly, and the shape of the formed liner layer 200 is within the expected shape range; in other exemplary embodiments, the specific set values during the entire process of forming the liner layer 200 can also be selected as different parameter values, that is, it can be flexibly adjusted during the preparation process to flexibly control the thickness of the insulating material on the sidewalls of the trench structure 110, form a liner layer 200 with a preset thickness difference, have good preparation flexibility and fault tolerance, and can also be flexibly applied to the preparation processes of various different semiconductor dielectric structures, meeting the preparation requirements of various different semiconductor dielectric structures, and having good applicability.

[0102] By effectively controlling parameters such as deposition temperature, deposition pressure, RF power, deposition rate, and deposition duration during the process of forming the liner layer 200, the deposition process of the insulating material is synergistically controlled to form a liner layer 200 with a certain shape and a preset thickness difference, greatly improving the forming accuracy of the liner layer 200, being beneficial to enhancing the reliability of the trench structure 110 with this liner layer 200 to maintain its own structural shape unchanged in subsequent processing steps, reducing the risk of TDDB failure during the processing, and thus being beneficial to enhancing the preparation yield and the performance of the semiconductor dielectric structure.

[0103] Next, refer to Figure 11 , the surface of the liner layer 200 is cleaned to thin the liner layer 200 until the bottom wall of the trench structure 110 is exposed, and a target liner layer 201 is formed on the sidewalls of the trench structure 110; wherein, the loss rate of the liner layer 200 during the surface cleaning process is also related to the depth of the trench structure 110, such that the loss amount of the top of the liner layer 200 etched is greater than the loss amount of the bottom of the liner layer 200 etched. Then, at the same depth of the trench structure 110, the thickness of the target liner layer 201 obtained after surface cleaning is less than or equal to the thickness of the liner layer 200 formed in the previous step, but the insulating material will not be completely lost. Finally, the thickness of the target liner layer 201 gradually increases along the first direction, forming a shape with a thinner top and a thicker bottom, and can still play a certain role in protecting the sidewall profile of the trench structure 110; the liner layer 200 and the target liner layer 201 are insulated. While maintaining the accuracy of the shape of the trench structure 110, the target liner layer 201 can further increase the critical dimension between the subsequent formed conductive structure 300 and the adjacent gate 400, further improving the TDDB performance and extending the life of the semiconductor dielectric structure.

[0104] In some exemplary embodiments, the surface cleaning may employ an etching process, which can be carried out by methods such as dry etching or wet etching. Among them, the dry etching process can be reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method can also be used, or more than one etching method can be used.

[0105] In some other exemplary embodiments, the surface cleaning can also adopt a plasma surface treatment process. On the one hand, it can reduce the thickness of the liner layer 200 on the sidewalls of the trench structure 110, but does not completely remove the thickness of the liner layer 200 on the sidewalls of the trench structure 110. At the same time, it reduces the insulating material of the liner layer 200 located at the bottom wall of the trench structure 110, so that the bottom of the liner layer 200 is completely removed until the bottom wall of the trench structure 110 is exposed, enabling the conductive structure 300 formed by subsequent filling of the metal material to be in contact and conduct with the electrode structure 120 below the bottom wall of the trench structure 110, facilitating current flow. On the other hand, it can also physically and chemically modify the insulating material in the liner layer 200, improve the surface adhesion of the formed target liner layer 201, facilitate the subsequent filling of the metal material, and enhance the stability and reliability of the formed conductive structure 300.

[0106] Specifically, the width difference between the inner diameter at the top and the inner diameter at the bottom of the inner cavity of the trench structure 110 with the target liner layer 201 is 2 - 4 nm. It can be understood that this width difference can be any point value within 2 - 4 nm. Exemplarily, this width difference can be 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, etc. In this way, the change in the profile of the trench structure 110 is small, greatly maintaining the accuracy of the cross-sectional profile of the trench structure 110, and also avoiding the outward expansion of the trench structure 110, greatly improving the critical dimension between the conductive structure 300 formed subsequently in the trench structure 110 and the adjacent gate 400, improving the TDDB performance in the middle section process of the semiconductor, and being beneficial to improving the final preparation yield and performance reliability of the semiconductor dielectric structure.

[0107] Finally, refer to Figure 12 And Figure 13 , fill the trench structure 110 with the target liner layer 201 with a metal material to form a conductive structure 300, and connect it to the electrode structure 120 below the trench structure 110 through the exposed bottom wall in the trench structure 110. Among them, the metal material is used to form the conductive structure 300, and the metal material can include one or more of aluminum metal, copper metal, silver metal, tungsten metal, and cobalt metal to form metal contacts (source / drain contacts) in the trench structure 110 of the substrate 100 to transfer current or signals.

[0108] Specifically, in some exemplary embodiments, filling a metal material in the trench structure 110 having the target liner layer 201 to form the conductive structure 300 includes:

[0109] Forming a conductive isolation layer 310 in the trench structure 110 having the target liner layer 201;

[0110] Filling a metal material in the trench structure 110 having the conductive isolation layer 310 to form a metal filling structure 320, thereby obtaining the conductive structure 300.

[0111] Among them, as Figure 12 shown, the conductive isolation layer 310 is deposited on the inner wall of the target liner layer 201 and the bottom wall of the trench structure 110. As Figure 13 shown, the metal filling structure 320 is deposited in the inner cavity of the trench structure 110 having the conductive isolation layer 310 and the target liner layer 201, which can further protect the side walls of the trench structure 110, reduce the possible damage to the side walls of the trench structure 110 during the subsequent process of filling the metal material, so that the shortest distance between the edge of the finally formed conductive structure 300 and the adjacent gate 400 is greater than or equal to the critical dimension, thereby effectively improving the TDDB performance in the middle process of the semiconductor and extending the service life of the semiconductor dielectric structure in the working state; at the same time, the bottom wall of the trench structure 110 is exposed, and a semiconductor material can be formed between the metal material of the conductive isolation layer 310 and the non-metal material of the dielectric layer 130 or the epitaxial layer 140 exposed on the bottom wall of the trench structure 110, thereby reducing the contact resistance between the conductive structure 300 and the electrode structure 120; in some exemplary embodiments, the material of the conductive isolation layer 310 includes at least one of TI and TIN, which can form a semiconductor amorphous silicide with the silicon oxide material, greatly reducing the contact resistance and improving the contact quality.

[0112] The embodiment of the present application further provides a semiconductor device, including any one of the semiconductor dielectric structures described in the embodiment of the present application.

[0113] The embodiment of the present application further provides an electronic device. The electronic device includes any one of the semiconductor devices described in the embodiment of the present application. The electronic device can be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, etc., or an intermediate product having the semiconductor device, for example: a device main board having the semiconductor device, etc.; the electronic device adopts the semiconductor device, thereby correspondingly improving the working performance of the electronic device.

[0114] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for preparing a semiconductor dielectric structure, characterized in that, comprising: providing a substrate having a trench structure in a dielectric layer; forming a liner layer within the trench structure by depositing an insulating material, the liner layer covering the inner wall of the trench structure, and along a first direction extending from the notch of the trench structure to the bottom of the trench, the thickness of the liner layer gradually decreasing; during the formation of the liner layer, isochronous deposition of the insulating material within the trench structure is performed in an atmosphere environment having a catalytic gas, and differential deposition of the insulating material within the trench structure is performed in an atmosphere environment without a catalytic gas, so that the thickness difference of the liner layer formed on the sidewall of the trench structure reaches a preset value; performing surface cleaning on the liner layer to thin the liner layer to expose the bottom wall of the trench structure and form a target liner layer on the sidewall of the trench structure; the thickness of the target liner layer gradually increases along the first direction; filling a metal material within the trench structure having the target liner layer to form a conductive structure.

2. The preparation method according to claim 1, characterized in that, the forming of the liner layer by depositing an insulating material within the trench structure comprises: depositing an insulating material within the trench structure in an atmosphere environment having the catalytic gas to form a first initial liner layer; depositing an insulating material on the first initial liner layer in an atmosphere environment without the catalytic gas until the thickness difference of the insulating material on the sidewall of the trench structure along the first direction reaches the preset value to obtain the liner layer.

3. The preparation method according to claim 1, characterized in that, the forming of the liner layer by depositing an insulating material within the trench structure comprises: depositing an insulating material within the trench structure in an atmosphere environment without the catalytic gas until the thickness difference of the insulating material on the sidewall of the trench structure along the first direction reaches the preset value to form a second initial liner layer; depositing an insulating material on the second initial liner layer in an atmosphere environment having the catalytic gas to obtain the liner layer.

4. The preparation method according to claim 1, characterized in that, the forming of the liner layer by depositing an insulating material within the trench structure comprises: during the formation of the liner layer, intermittently introducing a catalytic gas to perform deposition of the insulating material until the thickness difference of the insulating material on the sidewall of the trench structure along the first direction reaches the preset value to obtain the liner layer.

5. The preparation method according to claim 4, characterized in that, the preparation method satisfies at least one of the following characteristics: the deposition duration for forming the liner layer is 1.6 min to 12 min; during the formation of the liner layer, the duration of each single introduction of the catalytic gas is 6 s to 15 s; the time interval between adjacent two introductions of the catalytic gas is 10 s to 20 s; the number of times of intermittently introducing the catalytic gas steps performed for forming the liner layer is 6 to 20 times.

6. The preparation method according to any one of claims 1-5, characterized in that, The preset value is the thickness difference between the thickness of the liner layer on the sidewall of the notch and the thickness of the liner layer on the sidewall of the bottom of the groove, and the preset value is 1 nm to 2 nm.

7. The preparation method according to any one of claims 1-5, wherein, the deposition rate of the insulating material in the atmosphere environment with the catalytic gas is 1.0 to 1.5 nm / min, and the deposition rate of the insulating material in the atmosphere environment without the catalytic gas is 0.3 to 0.8 nm / min.

8. The preparation method according to any one of claims 1-5, wherein, In an environment without the catalytic gas, the ratio between the deposition rate of the insulating material and the depth of the trench structure is 0.10 to 0.04 min -1 .

9. The preparation method according to any one of claims 1-5, wherein, the preparation method satisfies at least one of the following characteristics: the deposition temperature used in the process of forming the liner layer in the trench structure is 300 to 400 °C; the radio frequency power used in the process of forming the liner layer in the trench structure is 200 to 400 W; the deposition pressure used in the process of forming the liner layer in the trench structure is 60 to 80 Pa.

10. The preparation method according to any one of claims 1-5, wherein, the insulating material includes at least one of silicon nitride, silicon nitride compound, and silicon carbide.

11. The preparation method according to any one of claims 1-5, wherein, the thickness of the liner layer on the sidewall of the trench structure is 6 nm to 9 nm.

12. The preparation method according to any one of claims 1-5, wherein, the width difference between the inner diameter at the top and the inner diameter at the bottom of the inner cavity of the trench structure having the target liner layer is 2 to 4 nm.

13. The preparation method according to any one of claims 1-5, wherein, filling the trench structure having the target liner layer with a metal material to form a conductive structure includes: forming a conductive isolation layer in the trench structure having the target liner layer; filling the trench structure having the conductive isolation layer with a metal material to form a metal filling structure, and obtaining the conductive structure.

14. A semiconductor dielectric structure, wherein, the semiconductor dielectric structure includes a substrate having a trench structure, and an electrode structure is provided below the trench structure; a conductive structure is provided in the trench structure, and the conductive structure is in contact with the bottom wall of the trench structure; a target liner layer is provided between the sidewall of the trench structure and the conductive structure, and the thickness of the target liner layer gradually increases in the first direction extending from the notch to the bottom of the trench structure.

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