Silicon-based through hole etching method and system without bottom groove effect, and medium
By preparing a patterned metal layer on the back of the silicon substrate, the problems of large helium leakage and groove effect when etching high-deep TSV through holes are solved, and through hole etching without bottom groove effect is achieved, which improves the reliability and etching rate of the silicon adapter plate.
Patent Information
- Application Number
- CN202510336907.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-21
- Publication Date
- 2025-06-13
AI Technical Summary
In the prior art, when etching high-deep TSV through-holes, the etching machine is suspended due to the large helium leakage rate on the back of the silicon wafer, and the use of non-conductive or whole-side conductive support layer materials will cause a groove effect, affecting the reliability and etching rate of the silicon adapter plate.
A patterned metal layer is prepared on the back of the silicon substrate, covering only the conductive material at the through-hole position, and the influence on the power of the etching device is reduced by patterning the metal layer, and the occurrence of groove effects is avoided.
Through-hole etching without bottom groove effect is achieved, etching machine suspension caused by large helium leakage rate is avoided, and the reliability and etching rate of silicon adapter plates are improved, and the requirements of high thickness, high reliability, high precision and high integration TSV adapter plates are met.
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Figure CN120149172A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of TSV (Through-Silicon Via) substrate manufacturing, and in particular to a silicon-based through-hole etching method, system and medium without bottom groove effect. Background Art
[0002] There are two main forms of TSV (Through-Silicon Via) adapter board production: one is TSV production process based on blind holes, and the other is TSV production process based on through holes. Silicon substrates with thickness requirements, such as high heat dissipation substrates with integrated microfluidics, require a certain thickness to form the flow channel, while also carrying the upper and lower interconnected electrical paths. Therefore, the TSV adapter board needs to have a high thickness. Usually, a TSV adapter board based on through-hole technology is used. The formation of high-depth TSV through holes is the difficulty in making this type of adapter board.
[0003] The electrical interconnection of the TSV adapter plate is achieved by interconnection holes with a high aspect ratio (>5:1). The formation of through holes is the primary element in the production of TSV adapter plates, and is usually achieved by the Bosch process that alternates etching / protection. For through holes with high depth, due to the limitations of the equipment, conventional etching equipment uses back helium heat dissipation. By introducing helium as a cooling medium on the back of the silicon wafer, the high thermal conductivity and low density of helium are used to achieve efficient thermal management. Hole penetration will increase the helium leakage rate, and the equipment alarm will cause the etcher to pause. Etching usually needs to be performed after the carrier is attached. In the prior art, a support layer is prepared on the back of the silicon wafer to solve the problem that the etcher cannot operate due to the large helium leakage rate on the back of the silicon wafer during etching. However, the use of non-conductive support layer materials will cause lateral etching due to the groove effect, affecting the reliability of the silicon adapter plate; and the use of conductive support layer materials on the entire surface will shield the lower electrode power of the etching equipment, affecting the etching rate and uniformity.
[0004] Therefore, achieving through-hole etching without bottom groove effect without affecting the power loading of the equipment is a technical problem that needs to be solved urgently when making through-holes in TSV adapter boards. Summary of the invention
[0005] In order to solve the problems of the prior art and realize through hole etching without bottom groove effect without affecting the power loading of the equipment, the present application provides a silicon-based through hole etching method without bottom groove effect.
[0006] In a first aspect, a silicon-based through-hole etching method without a bottom groove effect is provided, which adopts the following technical solution:
[0007] Cleaning silicon substrates;
[0008] Prepare a patterned metal layer on the back side of the silicon substrate: Deposit a metal layer on the back side of the silicon substrate first, then perform backside lithography, then pattern the metal layer, and finally remove the photoresist layer on the back side of the silicon substrate;
[0009] Perform front-side lithography on the silicon substrate;
[0010] Etch the vias;
[0011] Remove the photoresist layer on the front side of the silicon substrate;
[0012] Remove the patterned metal layer.
[0013] Further, when cleaning the silicon substrate, the following method is adopted: First, use SC-1 cleaning solution to remove surface particles; second, use SC-2 cleaning solution to remove metal contaminants; then, use SC-3 cleaning solution to remove organic contaminants; finally, rinse with deionized water.
[0014] Further, the composition and volume ratio of the SC-1 cleaning solution is NH 4 OH:H 2 O 2 :H 2 O = 1:1:5, the composition and volume ratio of the SC-2 cleaning solution is HCl:H 2 O 2 :H 2 O = 1:1:6, the composition and volume ratio of the SC-3 cleaning solution is H 2 SO 4 :H 2 O 2 = 5:1.
[0015] Further, when preparing the patterned metal layer on the back side of the silicon substrate, the metal used is single metal or composite metal.
[0016] Further, when preparing the patterned metal layer on the back side of the silicon substrate, the thickness of the metal layer is greater than 1 μm.
[0017] Further, when depositing the metal layer on the back side of the silicon substrate, evaporation or sputtering is used.
[0018] Further, when performing backside lithography, the pattern of the metal layer mask plate corresponds to the hole pattern of the TSV, and the diameter of the pattern of the metal layer mask plate is more than 1.5 times the diameter of the TSV hole.
[0019] Further, when etching the vias, the Bosch process of alternating etching / protection is used for via etching, specifically as follows: During the protection process, the protection gas is C 4 F 8, the flow rate is 150 sccm and the protection time is 1.5 s; the etching process includes Etch1 and Etch2. During the Etch1 process, the etching gas is SF 6 , the gas flow rate is 200 sccm, the power of the lower electrode loaded is 80 W, and the etching time is 1 s; during the Etch2 process, the etching gas is SF 6 , the gas flow rate is 200 sccm, the power of the lower electrode loaded is 30 W, and the etching time is 1.5 s.
[0020] In a second aspect, a silicon-based through-hole etching system without bottom groove effect is provided. The system includes a memory, a processor, and a computer program stored on the memory. The computer program is configured to implement the steps of the method described in the first aspect when called by the processor.
[0021] In a third aspect, a computer-readable storage medium is provided. The computer-readable storage medium stores a computer program, and the computer program is configured to implement the steps of the method described in the first aspect when called by a processor.
[0022] The beneficial effects of the present invention are as follows:
[0023] In the prior art, by preparing a support layer on the back of the silicon wafer, the situation that the etching machine cannot operate due to the large helium leakage rate on the back of the silicon wafer during through-etching is solved. However, when using a non-conductive support layer material, lateral etching will occur due to the groove effect, affecting the reliability of the silicon interposer; while using a whole-surface conductive support layer material will shield the power of the lower electrode of the etching equipment, affecting the etching rate and uniformity.
[0024] In this application, a patterned metal layer is prepared on the back of the silicon substrate, and the patterned position corresponds to the position of the TSV holes. By patterning the metal layer, only the area corresponding to the position of the through-holes is retained. The influence of the metal layer on the power loading of the etching equipment is extremely low, and it has almost no influence on the etching rate and etching uniformity.
[0025] Due to the blocking of the patterned metal layer at the etching end point, no helium leakage phenomenon will occur, and single-chip direct etching can be realized; moreover, the patterned metal layer can absorb and consume charged particles, inhibit the groove phenomenon during bottom-through etching, avoid lateral etching at the bottom of the holes, reduce etching damage, improve the reliability of the silicon-based interposer, meet the requirements of high-thickness, high-reliability, high-precision, and high-integration TSV interposers, and meet the packaging requirements of new active sub-arrays / components silicon-based interposers. Description of the Drawings
[0026] Figure 1 is a flowchart of the silicon-based through-hole etching method without bottom groove effect according to an embodiment of the present invention;
[0027] Figure 2 is a flowchart of fabricating a patterned metal layer on the back side of a silicon substrate according to an embodiment of the present invention;
[0028] Figure 3 is a schematic structural diagram of the silicon substrate after cleaning according to an embodiment of the present invention;
[0029] Figure 4 is a schematic structural diagram of the silicon substrate after depositing a metal layer on the back side according to an embodiment of the present invention;
[0030] Figure 5 is a schematic structural diagram of the silicon substrate after lithography on the back side according to an embodiment of the present invention;
[0031] Figure 6 is a schematic structural diagram of the silicon substrate after patterning the metal layer on the back side according to an embodiment of the present invention;
[0032] Figure 7 is a schematic structural diagram of the silicon substrate after lithography of the TSV hole etching mask on the front side according to an embodiment of the present invention;
[0033] Figure 8 is a schematic structural diagram of the silicon substrate after etching the through hole on the front side according to an embodiment of the present invention;
[0034] Figure 9 is a schematic structural diagram of the silicon substrate after removing the photoresist layer on the front side according to an embodiment of the present invention;
[0035] Figure 10 is a schematic structural diagram of the silicon substrate after etching the patterned metal layer according to an embodiment of the present invention. Detailed implementation manners
[0036] The present invention will be further described below.
[0037] The present invention provides a silicon-based through hole etching method without bottom groove effect. The flowchart is as Figure 1 shown and includes the following steps:
[0038] S10. Clean the silicon substrate
[0039] Remove contaminants such as organic contamination, particles, and metal contamination on the surface of the silicon substrate to ensure the cleanliness of the silicon substrate surface and provide a good foundation for subsequent process steps. In this embodiment, the RCA cleaning process is adopted.
[0040] The present invention is described using a 400-μm-thick silicon substrate. In actual use, silicon substrates with different thicknesses can be used according to design requirements. First, use SC-1 cleaning solution (NH 4 OH:H 2 O 2 :H 2O = 1:1:5) Heat in a water bath (95 °C) for 10 minutes to oxidize and micro-etch for undercutting and removing surface particles; secondly, use SC-2 cleaning solution (HCl:H 2 O 2 :H 2 O = 1:1:6) to remove metal contaminants; then use SC-3 cleaning solution (H 2 SO 4 :H 2 O 2 = 5:1) to remove organic contaminants; finally, rinse with DI water (Deionized Water) to complete the cleaning. The schematic diagram of the silicon substrate structure after cleaning is as shown in Figure 3 shown.
[0041] The cleaning of the silicon substrate can also use dilute hydrofluoric acid cleaning, ozone water cleaning, megasonic cleaning, plasma cleaning, brush cleaning, and supercritical fluid cleaning, etc. The appropriate cleaning method can be selected according to the pollution type of the silicon wafer and process requirements, or multiple cleaning processes can be used in combination.
[0042] S20. Prepare a patterned metal layer on the back of the silicon substrate
[0043] Deposit a metal layer on the back of the silicon substrate first, then perform backside lithography, then pattern the metal layer, and finally remove the photoresist layer, so that a metal layer can be covered at the position corresponding to the TSV holes on the back of the silicon substrate. Since the metal layer on the back of the silicon substrate has been patterned and is no longer a whole-surface conductive material, but only a conductive material is covered at the position corresponding to the TSV holes, it will not affect the device power loading, and thus will not affect the etching rate and uniformity; moreover, the metal layer absorbs and consumes charged particles, enabling through-hole etching without a groove effect. The process of preparing a patterned metal layer on the back of the silicon substrate is as shown in Figure 2 shown, and the specific steps are as follows:
[0044] S201. Deposit a metal layer on the back of the silicon substrate
[0045] Form a metal layer on the back of the silicon substrate by evaporation, sputtering, etc. The thickness of the metal layer is greater than 1 μm. The metal layer can be a single metal or a composite metal. The schematic diagram of the structure after depositing the metal layer on the back of the silicon substrate is as shown in Figure 4 shown.
[0046] Evaporation method:
[0047] Put the metal material (such as aluminum, copper, etc.) into the evaporation source (such as tungsten wire or electron beam evaporation source), heat the metal material in a vacuum environment to make it evaporate, and the metal vapor deposits on the back of the silicon substrate to form a uniform metal layer.
[0048] Sputtering method:
[0049] Install a metal target (such as titanium, copper, etc.) on the target holder of the sputtering equipment. Introduce an inert gas (such as argon) in a vacuum environment, apply a high-voltage electric field to generate plasma, bombard the surface of the target, and metal atoms are sputtered from the surface of the target and deposited on the surface of the silicon substrate.
[0050] S202, Backside lithography
[0051] The specific operations are as follows:
[0052] Fabricate a metal layer mask plate. The pattern of the metal layer mask plate corresponds to the hole pattern of the TSV. The diameter of the metal layer pattern is more than 1.5 times the diameter of the TSV hole to ensure that the metal layer completely covers the TSV hole.
[0053] Spin-coat a photoresist on the backside of the silicon substrate. The recommended photoresist model is AZ4620, and the maximum spin-coating speed is 3000 rpm / s. The thickness of the photoresist layer on the backside of the silicon substrate is greater than 4 μm.
[0054] Pre-bake to remove the solvent in the photoresist and improve the adhesion and stability of the photoresist layer. The temperature is 90°C - 110°C, and the time is adjusted according to the thickness of the photoresist, which can be 1 - 2 minutes.
[0055] Exposure to ensure precise alignment of the mask plate pattern and the TSV hole pattern. Use an ultraviolet light exposure machine and adjust according to the photoresist thickness and the light source intensity of the exposure machine.
[0056] Development to form a patterned mask. Immerse the exposed silicon substrate in a TMAH (tetramethylammonium hydroxide) solution, usually for 1 - 2 minutes (the specific time is adjusted according to the photoresist thickness). Remove the photoresist in the unexposed part to form a patterned mask.
[0057] Hard bake the photoresist by heating on a hot plate or in an oven (120°C - 140°C, 10 - 20 minutes), which can improve the etch resistance, mechanical strength, and adhesion of the photoresist layer to obtain a patterned metal layer etch mask. The schematic diagram of the structure after backside lithography of the silicon substrate is as Figure 5 shown.
[0058] S203, Pattern the metal layer
[0059] According to the different types of metal layers fabricated in step S201, select the corresponding etchant and wet-etch the metal layer not blocked by the photoresist; or use a dry etching method to physically bombard the metal layer not blocked by the photoresist with plasma Ar (argon) gas to pattern the metal layer.
[0060] S204, Remove the photoresist layer on the backside of the silicon substrate
[0061] Use a dedicated photoresist remover or an alkaline solution (such as a NaOH sodium hydroxide solution) to remove the photoresist layer on the back of the silicon substrate, obtaining a silicon substrate after patterning of the metal layer. The schematic structural diagram of the silicon substrate after patterning of the metal layer on the back is as shown in Figure 6 shown.
[0062] S30. Photolithography on the front side of the silicon substrate
[0063] Fabricate a mask for the TSV holes. In this embodiment, a hole diameter of 100 μm is used for illustration. In actual use, different hole diameters can be adopted according to design requirements.
[0064] Spin-coat a photoresist on the front side of the silicon substrate. The recommended photoresist model is AZ4620, and the maximum spin-coating speed is 2000 rpm / s. The thickness of the photoresist layer is greater than 7 μm.
[0065] After pre-baking, perform an exposure process. The exposure time can be adjusted according to the photoresist thickness and the light source intensity of the exposure machine.
[0066] Then, immerse the exposed silicon substrate in a TMAH (tetramethylammonium hydroxide) solution, develop it using a 2.38% concentration of TMAH, and finally perform hard baking on the photoresist to obtain a patterned TSV hole etching mask. The schematic structural diagram of the silicon substrate after photolithography of the TSV hole etching mask on the front side is as shown in Figure 7 shown.
[0067] S40. Through-hole etching
[0068] Place the lithographed silicon substrate into an etching equipment, and perform through-hole etching using the Bosch process with alternating etching / protection. The schematic structural diagram of the silicon substrate after etching through-holes on the front side is as shown in Figure 8 shown.
[0069] During the protection process, the protection gas is C 4 F 8 , with a flow rate of 150 sccm and a protection time of 1.5 s, used to form a polymer protection film on the sidewalls of the through-holes to prevent the sidewalls from being etched;
[0070] The etching process includes Etch1 and Etch2, specifically as follows:
[0071] Etch1: High-power etching, used to etch the main part of the through-hole. The etching gas is SF 6 , with a gas flow rate of 200 sccm, the power of the lower electrode loaded is 80 W, and the etching time is 1 s;
[0072] Etch2: Low-power etching, used to perform fine etching at the bottom of the through-hole. The etching gas is SF 6 , with a gas flow rate of 200 sccm, the power of the lower electrode loaded is 30 W, and the etching time is 1.5 s.
[0073] Taking a silicon substrate with a thickness of 400 μm as an example, in a process chamber with a chamber pressure of 40 mT (millitorr), the total number of cycles for etching through-holes is 420 times, and each cycle includes 1 protection and 2 etching steps (1 Etch1 and 1 Etch2).
[0074] In addition to using the Bosch process, a low-temperature deep silicon etching process can also be used. In a process chamber with a chamber pressure of 10 mT to 100 mT (millitorr) and a temperature of -100 °C to -150 °C, SF 6 and O 2 mixed gas is used, that is, SF 6 :O 2 = 1:1 to 2:1 (volume ratio), and the radio frequency power is 100 W to 500 W for through-hole etching.
[0075] S50. Remove the photoresist layer on the front side of the silicon substrate.
[0076] Use a special photoresist stripper or an alkaline solution (such as NaOH sodium hydroxide solution) to remove the photoresist layer on the front side of the silicon substrate. The schematic structural diagram of the silicon substrate after removing the front-side photoresist layer is as shown in Figure 9 shown.
[0077] S60. Remove the patterned metal layer.
[0078] According to the different types of metal layers fabricated in step S201, select the corresponding etching solution to wet-etch the remaining metal layer, and finally form a silicon-based adapter plate with a through-hole structure. The schematic structural diagram of the silicon substrate after etching the patterned metal layer is as shown in Figure 10 shown.
[0079] The present invention also provides a silicon-based through-hole etching system without bottom groove effect. The system includes a memory, a processor, and a computer program stored on the memory. The computer program is configured to implement the steps of the silicon-based through-hole etching method without bottom groove effect when called by the processor.
[0080] The present invention also provides a computer-readable storage medium storing a computer program, and the computer program is configured to implement the steps of the silicon-based through-hole etching method without bottom groove effect when called by the processor.
[0081] Although the present invention has been disclosed above with preferred embodiments, the embodiments are not used to limit the present invention. Any equivalent changes or modifications made without departing from the spirit and scope of the present invention also belong to the protection scope of the present invention. Therefore, the protection scope of the present invention should be defined by the content defined in the claims of this application.
Claims
1. A silicon-based through-hole etching method without bottom groove effect, characterized in that: The steps include: Cleaning silicon substrates; Preparing a patterned metal layer on the back side of the silicon substrate: first depositing a metal layer on the back side of the silicon substrate, then performing backside photolithography, then patterning the metal layer, and finally removing the photoresist layer on the back side of the silicon substrate; Silicon substrate front lithography; Through hole etching; removing the photoresist layer on the front side of the silicon substrate; The patterned metal layer is removed.
2. The silicon-based through hole etching method without bottom groove effect according to claim 1, characterized in that: When cleaning the silicon substrate, the method used is as follows: first use SC-1 cleaning solution to remove surface particles; secondly use SC-2 cleaning solution to remove metal contaminants; then use SC-3 cleaning solution to remove organic contaminants; and finally rinse with deionized water.
3. The silicon-based through hole etching method without bottom groove effect according to claim 2, characterized in that: The composition and volume ratio of the SC-1 cleaning solution are NH4OH:H2O2:H2O=1:1:5, the composition and volume ratio of the SC-2 cleaning solution are HCl:H2O2:H2O=1:1:6, and the composition and volume ratio of the SC-3 cleaning solution are H2SO4:H2O2=5:
1.
4. The silicon-based through hole etching method without bottom groove effect according to claim 1, characterized in that: When a patterned metal layer is prepared on the back side of a silicon substrate, the metal used is a single metal or a composite metal.
5. The silicon-based through hole etching method without bottom groove effect according to claim 4, characterized in that: When the patterned metal layer is prepared on the back side of the silicon substrate, the thickness of the metal layer is greater than 1 μm.
6. The silicon-based through hole etching method without bottom groove effect according to claim 5, characterized in that: When depositing the metal layer on the back side of the silicon substrate, evaporation or sputtering is used.
7. The silicon-based through hole etching method without bottom groove effect according to claim 1, characterized in that: During backside photolithography, the pattern of the metal layer mask plate is made to correspond to the hole pattern of the TSV, and the diameter of the pattern of the metal layer mask plate is more than 1.5 times the diameter of the TSV hole.
8. The silicon-based through hole etching method without bottom groove effect according to claim 1, characterized in that: When etching the through hole, the Bosch process of alternating etching / protection is used for through hole etching, as follows: during the protection process, the protective gas is C4F8, the flow rate is 150sccm, and the protection time is 1.5s; the etching process includes Etch1 and Etch2, wherein the etching gas in the Etch1 process is SF6, the gas flow rate is 200sccm, the loaded lower electrode power is 80W, and the etching time is 1s; during the Etch2 process, the etching gas is SF6, the gas flow rate is 200sccm, the loaded lower electrode power is 30W, and the etching time is 1.5s.
9. A silicon-based through-hole etching system without bottom groove effect, characterized in that: The system comprises a memory, a processor and a computer program stored in the memory, wherein the computer program is configured to implement the steps of the method according to any one of claims 1 to 8 when called by the processor.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is configured to implement the steps of any one of claims 1-8 when called by a processor.