Chip identification and selection device and method
By identifying the mark point of the wafer to be solid on the solid crystal machine and setting the shielding area, and identifying qualified chips outside the solid crystal shielding area, the bad problems of the wafer LED chips in solid crystal operation are solved, and product yield and solid crystal operation efficiency are improved.
Patent Information
- Application Number
- CN202510229703.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2025-06-13
AI Technical Summary
The chip LED chip has problems such as poor appearance, poor cutting, and poor electrical properties in solid crystal operations, which leads to a decrease in product yield. After improving the solid crystal PR recognition score, the solid crystal operation efficiency is reduced and the production capacity loss is serious.
A chip identification and selection method is provided, through the solid crystal machine, the mark point of the wafer to be solidified, the chip position is positioned, and the shielding area is set, and qualified chips outside the shielding area are identified to perform solid crystal operations.
This method is simple to operate, accurate identification and selection of qualified chips, effectively improve product yield, avoid adverse chips affecting product quality, and at the same time, the solid crystal operating efficiency is basically not affected.
Smart Images
Figure CN120149200A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a chip identification and selection device and method. Background Art
[0002] Wafer LED chips are chips that do not undergo full testing and sorting. Defective chips are not screened and removed and still remain on the blue film. Compared with square LED chips that undergo full-point testing and sorting, the production cost of wafer LED chips is relatively low and can be applied to products with low requirements for luminous color.
[0003] Due to factors such as stress, adhesion, thermal cycling, and wet cleaning, problems such as poor appearance, poor cutting, and poor electrical performance may occur in the crystal edge area of wafer LED chips. If directly die-bonded, the product yield will be reduced by 1% - 3%. Chips with poor appearance are prone to clogging the suction nozzle during die-bonding operations and clogging the ceramic nozzle during wire bonding operations, resulting in a reduction in die-bonding operation efficiency and an increase in auxiliary material loss. In addition, a small number of defective chips can be normally die-bonded, resulting in unstable product quality. If the die-bonding PR recognition score is adjusted from 50% to 85%, the die-bonding operation efficiency will be reduced by approximately 30%, and the die-bonding operation production capacity will be severely lost. Moreover, by increasing the die-bonding PR recognition score, approximately 0.5% of defective chips will be normally die-bonded, and approximately 1% of good chips will be misjudged and missed suction, resulting in an increase in chip loss. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide a chip identification and selection device and method, which is simple to operate, accurately identifies and selects qualified chips, and can effectively improve the product yield.
[0005] To solve the above problems, the present invention discloses a chip identification and selection method, including the following steps:
[0006] Place the wafer to be die-bonded on the die-bonding machine table, and the die-bonding machine table identifies the Mark points of the wafer to be die-bonded to locate the positions of each chip in the wafer to be die-bonded;
[0007] Set a fixed position Mark point as the pick-up origin, and at the same time set the number of defective chip circles as the shielding area, and identify and die-bond the qualified chips outside the shielding area.
[0008] As an improvement of the above technical solution, the method for setting the shielding area includes:
[0009] Provide a standard wafer, and after point testing, obtain the chip distribution template Mapping diagram of the standard wafer;
[0010] Provide the wafer to be die-bonded, and after scanning, map the chip positions of the wafer to be die-bonded to the chip distribution template Mapping diagram to generate the chip distribution diagram of the wafer to be die-bonded.
[0011] Define the number of turns of the chips in the chip distribution map as S. The range of N turns from the center of the circle to the circumference is the qualified area. The N turns of chips in the qualified area are qualified chips, and the remaining (S - N) turns of the range are the shielding area. The (S - N) turns of chips in the shielding area are defective chips, where S > N.
[0012] As an improvement to the above technical solution, 1 ≤ S - N ≤ 3.
[0013] As an improvement to the above technical solution, the method for generating the chip distribution map includes:
[0014] Align the direction of the wafer to be fixed with the direction of the chip distribution template Mapping diagram. After scanning, map the chip positions of the wafer to be fixed with the chip distribution template Mapping Figure 1 to obtain the chip distribution map of the wafer to be fixed.
[0015] As an improvement to the above technical solution, identify the Mark points of the wafer to be fixed to align the direction of the wafer to be fixed with the direction of the chip distribution template Mapping diagram.
[0016] As an improvement to the above technical solution, the Mark points are arranged in the qualified area; the number of Mark points is 4 to 8.
[0017] As an improvement to the above technical solution, in the horizontal direction, the number of qualified chips between two adjacent Mark points is 50 to 100; and / or, in the vertical direction, the number of qualified chips between two adjacent Mark points is 50 to 100.
[0018] As an improvement to the above technical solution, the figure formed by the connection lines of the Mark points is symmetrically distributed with respect to the diameter of the wafer to be fixed.
[0019] As an improvement to the above technical solution, reference patterns are provided at the positions of the pick-up origin and the Mark points, and the reference pattern at the position of the pick-up origin is different from the reference pattern at the position of the Mark points.
[0020] Correspondingly, the present method also discloses a chip identification and selection device, including:
[0021] A die bonder stage, which is provided with a wafer stage for fixing a standard wafer or a wafer to be fixed;
[0022] A chip distribution template Mapping diagram generation module for point-measuring the standard wafer to obtain the chip distribution template Mapping diagram of the standard wafer;
[0023] A chip distribution map generation module, configured to scan the chip positions of the wafer to be fixed and map them to the chip distribution template Mapping map, so as to generate the chip distribution map of the wafer to be fixed;
[0024] An identification and selection module, configured to identify and select qualified chips outside the shielding area for die bonding operations.
[0025] Implementing the present invention has the following beneficial effects:
[0026] The present invention first identifies and locates the positions of each chip in the wafer to be fixed, and sets the shielding area of the wafer to be fixed. By identifying and selecting qualified chips outside the shielding area for die bonding operations, compared with direct die bonding and improving the PR recognition score, the method provided by the present invention is simple to operate, the identification and selection of qualified chips are accurate, and the product yield can be effectively improved. Description of the Drawings
[0027] Figure 1 is a schematic flow chart of the chip identification and selection method provided by an embodiment of the present invention;
[0028] Figure 2 is a schematic flow chart of the shielding area setting method provided by an embodiment of the present invention. Detailed Embodiments
[0029] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below.
[0030] See Figure 1 and Figure 2 , the present invention provides a chip identification and selection method, including the following steps:
[0031] S100. Place the wafer to be fixed on the die bonder, and the die bonder identifies the Mark points of the wafer to be fixed to locate the positions of each chip in the wafer to be fixed.
[0032] S200. Set the selected fixed position Mark point as the pick-up origin, and at the same time set the number of turns of defective chips as the shielding area, and identify and select qualified chips outside the shielding area for die bonding operations.
[0033] In a preferred embodiment, the method for setting the shielding area includes:
[0034] S201. Provide a standard wafer, and obtain the chip distribution template Mapping map of the standard wafer after spot measurement.
[0035] It can be understood that since the chips on the wafers to be fixed have not been tested, there is no actual corresponding Mapping diagram for each wafer to be fixed. However, since both the wafer size and the chip size have standard specifications, such as the wafer size is generally 4 inches or 6 inches, and the single-chip size of the same model of chip products is the same, such as 8 mil × 22 mil, 12 mil × 20 mil, etc. Therefore, after the wafers to be fixed are cut, the distribution of chip grains is the same as the chip distribution template Mapping of the standard wafers of the same model and the same size. Figure 1 In the present invention, first, a standard wafer is provided for testing to obtain the chip distribution template Mapping diagram of the standard wafer, which is used to simulate the chip distribution position information. In the actual application process, according to the wafer size and the chip size of the wafer, the chip distribution template Mapping diagrams of multiple standard wafers can be obtained for the wafers to be fixed with different wafer sizes and chip sizes to make a comparison.
[0036] S202: Provide the wafers to be fixed, and after scanning, map the chip positions of the wafers to be fixed to the chip distribution template Mapping diagram to generate the chip distribution diagram of the wafers to be fixed.
[0037] In a preferred embodiment, the direction of the wafers to be fixed is kept consistent with the direction of the chip distribution template Mapping diagram. After scanning, the chip positions of the wafers to be fixed are mapped one by one with the chip distribution template Mapping to obtain the chip distribution diagram of the wafers to be fixed. Figure 1 Among them, the direction of the wafers to be fixed is kept consistent with the direction of the chip distribution template Mapping diagram by identifying the Mark points on the wafers to be fixed.
[0038] Specifically, the preparation steps of the Mark points are as follows: Provide an etching template provided with positioning points to etch and form the wafers to be fixed provided with Mark points. After production, each wafer to be fixed has Mark points at the same position, which are used for chip positioning identification and etching direction identification.
[0039]
[0040] S203: Define the number of circles of the chips in the chip distribution diagram as S, the range of N circles from the center of the circle to the circumference is the qualified area, the N circles of chips in the qualified area are qualified chips, and the remaining (S - N) circle range is the shielding area, and the (S - N) circles of chips in the shielding area are defective chips, where S > N.
[0041] The determination of the number of circles of the chips includes the following steps: Define a pick-up origin on the chip distribution diagram, and position the position of each chip in the wafers to be fixed through the position of the pick-up origin; each circle of chips in the chip distribution diagram includes all chips with the same distance from the center of the circle.
[0042] Using the method provided by the present invention, first establish a chip distribution template Mapping diagram of a standard wafer, scan the wafer to be fixed, and then obtain and map it to the chip distribution template Mapping Figure 1 A mapped chip distribution diagram, so as to obtain the chip distribution position information of the wafer to be fixed, identify and select qualified chips in the qualified area for die bonding, and defective chips in the shielding area are shielded and do not participate in die bonding.
[0043] In a preferred embodiment, 1 ≤ S - N ≤ 3, that is, shield 1 - 3 outermost circles of defective chips. More preferably, S - N = 2.
[0044] In a preferred embodiment, the number of Mark points is 4 - 8. The figure formed by connecting the Mark points is symmetrically distributed with respect to the diameter of the wafer to be fixed. For example, the connection of 6 Mark points is a hexagon symmetric with respect to the diameter of the wafer to be fixed, which can accurately identify and locate the placement position of the wafer to be fixed.
[0045] More preferably, in the horizontal direction, the number of qualified chips between two adjacent Mark points is 50 - 100; and / or, in the vertical direction, the number of qualified chips between two adjacent Mark points is 50 - 100, thereby improving the recognition efficiency.
[0046] It can be understood that the size and shape of the Mark points can be selected according to the actual situation, and the Mark points cover at least the area of one chip.
[0047] Exemplarily, if the number of chip circles in the chip distribution diagram is 20 circles, the inner N circles can be set as good chips, named Bin 1 chips, and the outer (20 - N) circles of chips are defective chips, named Bin 0 chips. The number of outermost defective chip circles is set according to the actual cutting defective circles. Set to pick up the inner N circles of Bin 1 chips for die bonding operation, and the operation of shielding the outer defective Bin 0 chips can be realized.
[0048] Correspondingly, the present invention also provides a chip identification and selection device, including:
[0049] A die bonding base, the die bonding base is provided with a wafer stage, and the wafer stage is used to fix a standard wafer or a wafer to be fixed;
[0050] A chip distribution template Mapping diagram generation module, used to point - measure the standard wafer to obtain the chip distribution template Mapping diagram of the standard wafer;
[0051] A chip distribution diagram generation module, used to scan the chip positions of the wafer to be fixed and map them to the chip distribution template Mapping diagram to generate the chip distribution diagram of the wafer to be fixed;
[0052] An identification and selection module is used to identify and select qualified chips outside the shielding area for die bonding operations.
[0053] Through the above devices and methods, the shielding of defective chips on the outer ring of the wafer to be die bonded is realized, avoiding the adverse effects of defective chips on product yield, process operations, and product quality. At the same time, the die bonding operation efficiency is basically not affected, the sorting yield is increased by 1% - 3%, and the benefits of wafer chip operations are maximized.
[0054] The above is the preferred embodiment of the invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements are also regarded as the protection scope of the present invention.
Claims
1. A chip identification and selection method, characterized in that: The following steps are involved: Placing the wafer to be bonded on a bonding machine, and the bonding machine identifies the mark points of the wafer to be bonded to locate the position of each chip in the wafer to be bonded; Set the fixed position Mark point as the picking origin, and set the number of defective chip circles as the shielding area, and identify qualified chips outside the shielding area for die bonding.
2. The chip identification and selection method according to claim 1, characterized in that: The method for setting the shielding area includes: Providing a standard wafer, and obtaining a chip distribution template Mapping diagram of the standard wafer after spot measurement; Providing a wafer to be fixed, and mapping the chip positions of the wafer to be fixed to the chip distribution template Mapping map after scanning, so as to generate a chip distribution map of the wafer to be fixed; The number of circles of chips in the chip distribution diagram is defined as S, the N-circle range from the center to the circumference is the qualified area, the N-circle chips in the qualified area are qualified chips, the remaining (SN) circle range is the shielding area, the (SN) circle chips in the shielding area are bad chips, S>N.
3. The chip identification and selection method according to claim 2, characterized in that: 1≤SN≤3.
4. The chip identification and selection method according to claim 2, characterized in that: The method for generating the chip distribution map includes: The direction of the wafer to be fixed is made consistent with the direction of the chip distribution template Mapping map. After scanning, the chip positions of the wafer to be fixed are mapped one by one with the chip distribution template Mapping map to obtain the chip distribution map of the wafer to be fixed.
5. The chip identification and selection method according to claim 2, characterized in that: The Mark point of the wafer to be fixed is identified so that the direction of the wafer to be fixed is consistent with the direction of the chip distribution template Mapping diagram.
6. The chip identification and selection method according to claim 5, characterized in that: The Mark points are set in the qualified area; the number of the Mark points is 4 to 8.
7. The chip identification and selection method according to claim 6, characterized in that: In the horizontal direction, the number of qualified chips between two adjacent Mark points is 50 to 100; and / or, in the vertical direction, the number of qualified chips between two adjacent Mark points is 50 to 100.
8. The chip identification and selection method according to claim 7, characterized in that: The figure formed by the lines connecting the Mark points is symmetrically distributed relative to the diameter of the wafer to be fixed.
9. The chip identification and selection method according to claim 6, characterized in that: Reference patterns are provided at the positions of the pickup origin and the Mark point, and the reference pattern at the position of the pickup origin is different from the reference pattern at the position of the Mark point.
10. A chip identification and selection device, characterized in that: include: A crystal bonding machine, wherein the crystal bonding machine is provided with a wafer carrier, and the wafer carrier is used to fix a standard wafer or a wafer to be bonded; A chip distribution template Mapping diagram generating module is used for spot-measuring the standard wafer to obtain a chip distribution template Mapping diagram of the standard wafer; A chip distribution map generating module is used to scan the chip positions of the wafer to be fixed and map them to the chip distribution template Mapping map to generate a chip distribution map of the wafer to be fixed; The identification and selection module is used to identify and select qualified chips outside the shielding area for die bonding operations.