Direct-current solid-state circuit breaker with voltage-limiting protection circuit and control method of direct-current solid-state circuit breaker

Abstract

The invention discloses a direct-current solid-state circuit breaker with a voltage limiting protection circuit and a control method thereof. The direct-current solid-state circuit breaker comprises a solid-state switch module, the solid-state switch module comprises a first sub-module and a second sub-module which are the same, and each of the first sub-module and the second sub-module comprises a SiC JFET device J, capacitors C, Cgd and Cgs, a comparator U, an MOSFET device Q, a resistor Rg and resistors ra and rb; the first end of Rg is used for receiving a driving signal, and the second end of Rg is connected to the grid electrode of J after being connected with the first end of C, the second end of Cgd and the first end of Cgs; the second end of ra and the first end of rb are connected as a comparison voltage sampling point; the first end of ra is connected to the first end of Cgd and the drain electrode of J; the second end of the rb is connected to the second end of the Cgs, the source electrode of the Q and the source electrode of the J; the second end of C is connected to the drain electrode of Q; the output end of U is connected to the grid electrode of Q; the anode input of U is comparison voltage, and the cathode input is reference voltage; the source electrode of the first sub-module J is connected to the drain electrode of the second sub-module J.

Description

Technical Field

[0001] The present invention relates to the technical field of DC distribution system protection, and particularly to a DC solid-state circuit breaker with a voltage-limiting protection circuit and its control method. Background Art

[0002] In recent years, DC microgrids have attracted much attention due to their ability to efficiently integrate distributed energy and energy storage units. However, the low-impedance characteristic of DC microgrids results in high short-circuit fault current amplitudes and fast rising speeds, making it difficult for traditional mechanical circuit breakers to meet the fast protection requirements of DC microgrids due to their millisecond-level turn-off delays. In contrast, the SSCB (Solid-State Circuit Breaker) based on power semiconductor devices has become an ideal solution due to its fast response and arc-free characteristics.

[0003] Currently, wide-bandgap semiconductors (such as SiC devices) are widely used in SSCBs due to their low conduction losses and high junction temperature tolerance. However, limited by manufacturing processes, the voltage withstand capabilities of commercial SiC discrete devices are insufficient, and the overall voltage withstand level needs to be improved by series connection. However, factors such as parasitic parameter differences between series devices will cause voltage imbalance during the turn-off process, leading to local overvoltage and seriously threatening device reliability. Existing passive voltage equalization schemes (such as RC buffer circuits) can alleviate some problems, but they are insufficient in adapting to the dynamic turn-off process and are difficult to effectively suppress transient overshoots.

[0004] Therefore, there is an urgent need for a new technical solution to solve the technical problem of how to limit the voltage overshoot of series switching devices. Summary of the Invention

[0005] The present invention provides a DC solid-state circuit breaker with a voltage-limiting protection circuit and its control method to solve the technical problem of how to limit the voltage overshoot of series switching devices.

[0006] To achieve the above object, the present invention provides a DC solid-state circuit breaker with a voltage-limiting protection circuit, including a solid-state switch module; The solid-state switch module includes a first sub-module and a second sub-module. The structures of the first sub-module and the second sub-module are the same, and both include SiC JFET discrete devices , capacitors , and , comparators , low-voltage MOSFET devices , drive resistors , and sampling resistors , and ; The first end of is used to receive a drive signal, The second end of The second end of is connected to the first end of and then connected to the gate of The second end of is connected to the first end of The first end of is connected to the first end of and the drain of The second end of is connected to the second end of the source of and the source of The second end of is connected to the drain of The output end of is connected to the gate of The negative input of is the comparison voltage, and the positive input is the preset reference voltage; In the first sub-module, the source of is connected to the drain of in the second sub-module; the DC bus current flows into from the drain of in the first sub-module and flows out from the source of

[0007] Preferably, it further includes a sampling module, an isolation module, an FPGA module, and a driving module; The sampling module is used to sample the current information flowing into the solid-state switch module, and send the current information to the FPGA module through the isolation module; the FPGA module is used to control the driving module to send a driving signal to the solid-state switch module according to the current information.

[0008] Preferably, it further includes a switch protection module, and the switch protection module includes a metal oxide varistor and an RC buffer absorption circuit; the metal oxide varistor and the RC buffer absorption circuit are connected in parallel and then connected in parallel across both ends of the solid-state switch module.

[0009] The present invention also provides a control method for a DC solid-state circuit breaker with a voltage-limiting protection circuit. Based on the DC solid-state circuit breaker of the present invention, it includes: When it is determined that a DC bus fault occurs, the FPGA module is used to control the driving module to send a driving signal to the solid-state switch module, and control the SiC JFET discrete devices of the first sub-module and the second sub-module to turn off; When an overvoltage situation occurs in the first sub-module or the second sub-module, the sub-module with the overvoltage situation is recorded as the faulty sub-module; the comparator of the faulty sub-module outputs a low level to control the low-voltage MOSFET device of the faulty sub-module Conduct, and at this time, the capacitor in the faulty sub-module is connected to the gate and source of the SiC JFET discrete device .

[0010] Preferably, when there is no overvoltage situation in the solid-state switch module, the comparators of the first sub-module and the second sub-module both output high levels to control the low-voltage MOSFET devices of the first sub-module and the second sub-module to turn off, and the SiC JFET discrete devices of the first sub-module and the second sub-module both maintain the normal turn-off speed.

[0011] Preferably, when the DC solid-state circuit breaker is connected to the DC bus, it includes: When there is a difference in the magnitudes of the driving resistors between the first sub-module and the second sub-module , it will cause an overvoltage situation in the sub-module with the smaller driving resistor, which becomes the faulty sub-module; the normal sub-module is denoted as the normal sub-module; When the DC solid-state circuit breaker is connected to the DC bus, it includes seven consecutive stages of time: Stage 1: When there is no fault in the DC bus, the DC solid-state circuit breaker does not operate; Stage 2: When a fault occurs in the DC bus, the bus current starts to rise, and the DC solid-state circuit breaker does not operate; Stage 3: When the bus current rises to a preset threshold, the SiC JFET discrete devices of the first sub-module and the second sub-module receive a turn-off signal, and the gate-source voltages both start to decline; Stage 4: The gate-source voltage of the SiC JFET discrete device in the faulty sub-module reaches the Miller platform voltage; the in the faulty sub-module stops reverse charging, starts charging, the SiC JFET discrete device starts to turn off, and the comparison voltage starts to rise; Stage 5: The gate-source voltage of the SiC JFET discrete device in the normal sub-module reaches the Miller platform voltage; the in the normal sub-module stops reverse charging, starts charging, the SiC JFET discrete device starts to turn off, and the comparison voltage starts to rise; Stage 6: The Miller platform of the SiC JFET discrete device in the faulty sub-module ends, the charging of the faulty sub-module ends, and starts reverse charging; ​ Stage Seven: Normal Sub-module SiC JFET Discrete Device The Miller plateau of the normal sub-module ends, and the charging of the normal sub-module ends, and reverse charging begins; the SiC JFET discrete devices of the faulty sub-module and the normal sub-module both continue to turn off. Since the driving resistance of the faulty sub-module is smaller and the turn-off speed is faster, the comparison voltage of the faulty sub-module is higher than that of the normal sub-module, which in turn causes the comparison voltage of the faulty sub-module to be higher than the preset reference voltage. The comparator of the faulty sub-module outputs a low level, connecting the capacitor to the gate and source of the SiC JFET discrete device to slow down the turn-off speed of the SiC JFET discrete device in the faulty sub-module .

[0012] Preferably, Stage Three includes: Since the gate-source voltages of the SiC JFET discrete devices in the first sub-module and the second sub-module have not reached the Miller plateau voltage, the DC solid-state circuit breaker has not turned off the fault current yet; the comparison voltages of the SiC JFET discrete devices in the faulty sub-module and the normal sub-module are both 0, the outputs of the comparators are both high level, and the low-voltage MOSFET devices are both turned off. The capacitors and are both reversely charged through the corresponding driving resistors . According to Kirchhoff's voltage law (KVL), there is: ; wherein, and respectively represent the driving resistors of the normal sub-module and the faulty sub-module; and respectively represent the capacitors of the normal sub-module and the faulty sub-module ; and respectively represent the gate-source voltages of the SiC JFET discrete devices in the normal sub-module and the faulty sub-module , that is, the voltages across and ; and respectively represent the driving signals received by the driving resistors in the normal sub-module and the faulty sub-module; Therefore, due to the driving resistance of the faulty sub-module Smaller, the rate of decrease in the gate-source voltage of the faulty sub-module in stage three is greater than that of the normal sub-module.

[0013] The present invention has the following beneficial effects: For the DC solid-state circuit breaker with a voltage-limiting protection circuit of the present invention, when a short-circuit fault occurs, it can realize the connection and disconnection of the capacitor on the driving side of the switching device through a closed-loop control method, thereby adjusting the turn-off speed of the switching device, slowing down the voltage change rate of the device with a faster turn-off speed, and limiting the voltage overshoot of the switching device. By connecting SiC JFETs in series, the capacity, withstand voltage, and power rating of the DC solid-state circuit breaker are effectively improved. Compared with the topological structure using a passive voltage-limiting control method, the addition of active devices in the present invention greatly reduces the voltage overshoot degree of the series-connected switching devices. When the DC solid-state circuit breaker responds to a line short-circuit fault, it can promptly cut off the short-circuit fault; and within the fault-cutting stage of the DC solid-state circuit breaker, if the device voltage undergoes an overvoltage situation, it can promptly adjust the voltage turn-off rate and limit the unevenness degree of the branch voltage.

[0014] The control method of the DC solid-state circuit breaker with a voltage-limiting protection circuit of the present invention, based on the DC solid-state circuit breaker of the present invention, has the same beneficial effects as the method of the present invention.

[0015] In addition to the purposes, features, and advantages described above, the present invention has other purposes, features, and advantages. The following will refer to the accompanying drawings to further elaborate on the present invention in detail. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments and descriptions thereof of the present invention are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings: Figure 1 is a schematic structural diagram of the solid-state switch module of the preferred embodiment of the present invention.

[0017] Figure 2 is a schematic structural diagram of the DC solid-state circuit breaker with a voltage-limiting protection circuit of the preferred embodiment of the present invention.

[0018] Figure 3 is the theoretical waveform diagram of the voltages on the capacitors and during the seven stages of the turn-off process in the preferred embodiment of the present invention.

[0019] Figure 4 is a schematic diagram of the simulation circuit topology of the preferred embodiment of the present invention.

[0020] Figure 5 is a schematic diagram of the simulation result diagram using voltage-limiting control in the preferred embodiment of the present invention.

[0021] Figure 6 It is a schematic diagram of simulation results of unlimited pressure control of a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0022] The embodiments of the present invention are described in detail below with reference to the accompanying drawings, but the present invention can be implemented in many different ways as defined and covered by the claims.

[0023] See also Figure 1 , In a preferred embodiment of the present invention, there is provided a DC solid-state circuit breaker including a voltage limiting protection circuit, comprising a solid-state switch module; The solid-state switch module includes a first submodule and a second submodule. The first submodule and the second submodule have the same structure and both include SiC JFET discrete devices. ,capacitance and , Comparator , low voltage MOSFET devices , drive resistance And the sampling resistor and .exist Figure 1 In the above device, the sampling resistors of the first submodule and the second submodule are and They are and as well as and The remaining components are all denoted by the subscript 1 to indicate that they are from the first submodule, and are denoted by the subscript 2 to indicate that they are from the second submodule.

[0024] and They are SiC JFET discrete devices Parasitic capacitance between internal gate drain and gate source. SiC JFET discrete device There is also a capacitor between the drain and source. .

[0025] The first end is used to receive a driving signal, The second end of The first end The second end and The first end is connected to The gate of The second end and The first end of is connected as a sampling point of the comparison voltage; The first end is connected to The first end and The drain; The second terminal of is connected to the second terminal of the source of and the source of The second terminal of is connected to the drain of The output terminal of is connected to the gate of The negative input of is the comparison voltage, and the positive input is the preset reference voltage The comparator is used to adjust the voltage drop rate across the gate-source of the SiC JFET discrete device and control the turn-off speed of the SiC JFET discrete device to limit the turn-off voltage overshoot.

[0026] In a preferred embodiment of the present invention, it is assumed that the first sub-module is a normal sub-module and the second sub-module is a faulty sub-module. In Figure 1 , represents the driving signal received by the driving resistor in the first sub-module, represents the driving signal received by the driving resistor in the second sub-module; represents the drain of the SiC JFET discrete device in the first sub-module, represents the source of the SiC JFET discrete device in the second sub-module; represents the comparison voltage of the first sub-module, represents the comparison voltage of the second sub-module.

[0027] In the first sub-module, the source of is connected to the drain of in the second sub-module; the DC bus current flows into from the drain of in the first sub-module and flows out from the source of

[0028] Referring to Figure 2 , in a preferred embodiment of the present invention, the DC solid-state circuit breaker further includes a sampling module, an isolation module, an FPGA module, a driving module, and a switch protection module.

[0029] The sampling module is used to sample the current information flowing into the solid-state switch module, and send the current information to the FPGA module through the isolation module. The isolation module transmits information through optical fibers to prevent interference between strong and weak currents and ensure the safety of the device. The FPGA module is used to control the driving module to send a driving signal to the solid-state switch module according to the current information. The high-speed FPGA can improve the operation speed of the fault algorithm. The driving module has a negative voltage driving ability and can drive SiC JFET discrete devices well.

[0030] The switch protection module includes a metal oxide varistor (MOV) and an RC buffer absorption circuit; the metal oxide varistor and the RC buffer absorption circuit are connected in parallel and then connected in parallel across both ends of the solid-state switch module. The switch protection module is used to clamp the overvoltage of the device, protect the solid-state switch from damage caused by transient overvoltage, and slow down the dv / dt , and absorb the remaining energy in the line inductance.

[0031] In Figure 2 , represents the DC bus; represents the line current; represents the sampling point; represents the load; represents the metal oxide varistor; and represents the buffer absorption circuit.

[0032] For the DC solid-state circuit breaker with a voltage-limiting protection circuit of the present invention, when a short-circuit fault occurs, it can realize the access and disconnection of the capacitor on the driving side of the switching device through a closed-loop control method, thereby adjusting the turn-off speed of the switching device, slowing down the voltage change rate of the device with a relatively fast turn-off speed, and limiting the voltage overshoot of the switching device. By connecting SiC JFETs in series, the capacity, withstand voltage, and power level of the DC solid-state circuit breaker are effectively improved. Compared with the topology structure using the passive voltage-limiting control method, the addition of active devices in the present invention greatly reduces the voltage overshoot degree of the series switching devices. When the DC solid-state circuit breaker responds to a line short-circuit fault, it can promptly cut off the short-circuit fault; and during the fault-cutting stage of the DC solid-state circuit breaker, if the device voltage has an overvoltage situation, it can promptly adjust the voltage turn-off rate and limit the unevenness degree of the branch voltage.

[0033] In a preferred embodiment of the present invention, a control method for a DC solid-state circuit breaker with a voltage-limiting protection circuit is further provided. Based on the DC solid-state circuit breaker of the present invention, it includes: When it is determined that a fault occurs in the DC bus, the driving module is controlled by the FPGA module to send a driving signal to the solid-state switch module to control the SiC JFET discrete devices of the first sub-module and the second sub-module Turn off.

[0034] When an overvoltage occurs in the first sub-module or the second sub-module, the sub-module where the overvoltage occurs is recorded as a faulty sub-module; the comparator of the faulty sub-module outputs a low level to control the low-voltage MOSFET device of the faulty sub-module to conduct. At this time, the capacitor in the faulty sub-module is connected to the gate and source of the SiC JFET discrete device .

[0035] When no overvoltage occurs in the solid-state switch module, the comparators of the first sub-module and the second sub-module both output a high level to control the low-voltage MOSFET devices of the first sub-module and the second sub-module to turn off, and the SiC JFET discrete devices of the first sub-module and the second sub-module both maintain the normal turn-off speed.

[0036] When the DC solid-state circuit breaker is connected to the DC bus, it includes: When there is a difference in the magnitude between the driving resistors of the first sub-module and the second sub-module , it will cause an overvoltage in the sub-module with the smaller driving resistor, becoming a faulty sub-module; the normal sub-module is recorded as the normal sub-module. Ignoring the delay of the sampling module and the comparator, when the DC solid-state circuit breaker is connected to the DC bus, it includes seven consecutive stages of time: Stage 1 ( ): When no fault occurs in the DC bus, the DC solid-state circuit breaker does not operate. and The theoretical waveforms of the voltages on the capacitors Figure 3 are shown in and respectively represent the voltages on the capacitors in the first sub-module and the second sub-module; and respectively represent the voltages on the capacitors in the first sub-module and the second sub-module; represents the Miller platform voltage; represents the turn-off threshold voltage; represents the final turn-off voltage; Stage 1 ( ): When no fault occurs in the DC bus, the DC solid-state circuit breaker does not operate.

[0037] Stage 2 ( ): When a fault occurs in the DC bus, the bus current starts to rise, and the DC solid-state circuit breaker does not operate.

[0038] In the second stage, the on-resistance of the SiC JFET is very small and can be basically ignored. The current in the circuit rises rapidly. According to the KVL law, we can get: ; where represents the DC bus voltage, represents the line current during a fault, represents the load resistance during a fault, represents the line inductance.

[0039] Under the initial conditions: , , the solution after the first-order Taylor expansion is: ; where represents the rated current.

[0040] That is, the line current is: ; Stage 3 ( ): The bus current rises to the preset threshold, and the SiC JFET discrete devices in the first sub-module and the second sub-module receive the turn-off signal, and the gate-source voltages start to decrease.

[0041] In stage 3: Since the gate-source voltages of the SiC JFET discrete devices in the first sub-module and the second sub-module do not reach the Miller plateau voltage, the DC solid-state circuit breaker has not turned off the fault current yet; the comparison voltages of the SiC JFET discrete devices in the faulty sub-module and the normal sub-module are both 0, and the outputs of the comparators are both high level, and the low-voltage MOSFET devices are all turned off, and the capacitors and are both reversely charged through the corresponding drive resistors . According to the KVL law, there is: ; where and represent the drive resistors of the normal sub-module and the faulty sub-module respectively; and represent the capacitors of the normal sub-module and the faulty sub-module respectively ; and represent the SiC JFET discrete devices in the normal sub-module and the faulty sub-module respectively The gate-source voltage of, that is and the voltage across both ends; and respectively represent the drive signals received by the drive resistors in the normal sub-module and the faulty sub-module; Therefore, due to the smaller drive resistor of the faulty sub-module, the rate of decrease of the gate-source voltage of the faulty sub-module in the third stage is greater than that of the normal sub-module.

[0042] Stage Four ( ): The gate-source voltage of the SiC JFET discrete device in the faulty sub-module reaches the Miller plateau voltage; the in the faulty sub-module stops reverse charging, starts charging, the SiC JFET discrete device starts to turn off, and the comparison voltage starts to rise. However, at this time, the comparison voltage is less than the preset reference voltage. Therefore, the output of the comparator of the faulty sub-module is high level, controlling the low-voltage MOSFET device to turn off, and the drive-side capacitor is not connected to the circuit, and the turn-off speed remains normal. The preset reference voltage is half of the DC bus voltage.

[0043] Stage Five ( ): The gate-source voltage of the SiC JFET discrete device in the normal sub-module reaches the Miller plateau voltage; the in the normal sub-module stops reverse charging, starts charging, the SiC JFET discrete device starts to turn off, and the comparison voltage starts to rise.

[0044] Stage Six ( ): The Miller plateau of the SiC JFET discrete device in the faulty sub-module ends, the charging of the faulty sub-module ends, starts reverse charging.

[0045] Stage Seven ( ): The Miller plateau of the SiC JFET discrete device in the normal sub-module ends, the charging of the normal sub-module ends, starts reverse charging; the SiC JFET discrete devices in both the faulty sub-module and the normal sub-module continue to turn off. Due to the drive resistor Smaller and faster turn-off speed result in a comparison voltage of the faulty sub-module being higher than that of the normal sub-module, which further leads to the comparison voltage of the faulty sub-module being higher than the preset reference voltage, and the comparator of the faulty sub-module outputs a low level, connecting the capacitor to the gate and source of the SiC JFET discrete device to slow down the turn-off speed of the SiC JFET discrete device in the faulty sub-module.

[0046] The control method of the DC solid-state circuit breaker with a voltage-limiting protection circuit according to the present invention is based on the DC solid-state circuit breaker of the present invention and has the same beneficial effects as the method of the present invention.

[0047] Verification part: To verify the effectiveness of the proposed SSCB voltage-limiting control scheme, the feasibility of this topology will be verified through PSpice simulation. The simulation circuit topology is as Figure 4 shown. The solid-state switch module of the present invention is used as the voltage-limiting control topology and connected to the test circuit, and is turned on and off by VPULSE to drive the topology. VPULSE is the VPULSE pulse voltage source inside PSpice, and DC uses the built-in VDC DC voltage source of PSpice. represents the line resistance. Point connects to the first end of the driving resistors of the first sub-module and the second sub-module in the solid-state switch module; Point D connects to the P in the solid-state switch module; Point S connects to the N in the solid-state switch module.

[0048] The device parameters in the simulation circuit are shown in Table 1. The simulation model of the SiC JFET comes from United SiC Company in the United States, and the bus voltage is set to 1200V. A control signal is output through VPULSE to both ends of GS of the voltage-limiting control topology to drive the series JFET to turn off, and by observing the turn-off waveform of the voltage-limiting control topology, the turn-off effect of this topology in the test circuit can be examined to verify the feasibility of this topology circuit.

[0049] Table 1 Simulation circuit device parameter table ; The simulation results of the turn-off process of the voltage-limiting control topology are as Figure 5 、 6 shown. The simulation causes the unevenness of the branch current by adjusting the driving resistors , . Figure 5 is the simulation result diagram with voltage-limiting control, Figure 6 is the simulation result diagram without voltage-limiting control.

[0050] It can be seen that Figure 6 when the driving resistors R g1 and R g2 are not equal, there will be a deviation in the voltage division between the two devices J 1 and J 2 . During the turn-off process, J 2 turns off first, resulting in the voltage division of J 2 exceeding the ideal value. By comparison Figure 5 it can be obtained that after adding the overvoltage control, the turn-off speed of J 2 slows down, and the degree of voltage unevenness is greatly reduced, verifying the feasibility of the overvoltage control method proposed in this paper.

[0051] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A DC solid-state circuit breaker with a voltage limiting protection circuit, characterized in that: Includes solid-state switch module; The solid-state switch module includes a first submodule and a second submodule, the first submodule and the second submodule have the same structure and both include SiC JFET discrete devices. ,capacitance and , Comparator , low voltage MOSFET devices , drive resistance And the sampling resistor and ; The first end is used to receive a driving signal, The second end of The first end The second end and The first end is connected to The gate of The second end and The first end of is connected as a sampling point of the comparison voltage; The first end is connected to The first end and The drain; The second end is connected to The second end The source and The source of The second end is connected to The drain; The output terminal is connected to The gate of The negative input is the comparison voltage, and the positive input is the preset reference voltage; In the first submodule The source of the second submodule is connected to The DC bus current is supplied by the first submodule The drain of the second submodule flows into The source flows out.

2. The DC solid-state circuit breaker with a voltage limiting protection circuit according to claim 1, characterized in that: It also includes a sampling module, an isolation module, an FPGA module and a driver module; The sampling module is used to sample the current information flowing into the solid-state switch module, and send the current information to the FPGA module through the isolation module; the FPGA module is used to control the driving module to send a driving signal to the solid-state switch module according to the current information.

3. The DC solid-state circuit breaker with a voltage limiting protection circuit according to claim 2, characterized in that: It also includes a switch protection module, which includes a metal oxide varistor and an RC buffer absorption circuit; the metal oxide varistor and the RC buffer absorption circuit are connected in parallel and then connected in parallel to the two ends of the solid-state switch module.

4. A control method for a DC solid-state circuit breaker including a voltage limiting protection circuit, based on the DC solid-state circuit breaker according to any one of claims 2 to 3, characterized in that: include: When it is determined that the DC bus fails, the FPGA module controls the drive module to send a drive signal to the solid-state switch module to control the SiC JFET discrete devices of the first submodule and the second submodule. Shut down; When an overvoltage occurs in the first submodule or the second submodule, the submodule in which the overvoltage occurs is recorded as a faulty submodule; the comparator of the faulty submodule Output low level to control the low voltage MOSFET device of the fault submodule The capacitor in the faulty submodule is turned on. Access to SiC JFET discrete devices of the gate and source.

5. The control method of a DC solid-state circuit breaker with a voltage limiting protection circuit according to claim 4, characterized in that: When there is no overvoltage in the solid-state switch module, the comparators of the first submodule and the second submodule Both output high level to control the low voltage MOSFET devices of the first submodule and the second submodule The SiC JFET discrete devices of the first submodule and the second submodule are turned off. Maintain normal shut-off speed.

6. The control method of a DC solid-state circuit breaker with a voltage limiting protection circuit according to claim 5, characterized in that: When the DC solid-state circuit breaker is connected to the DC bus, it includes: When the driving resistance of the first submodule and the second submodule When there is a size difference between them, it will cause the driving resistance The smaller submodule has an overvoltage condition and becomes a faulty submodule; the normal submodule is recorded as a normal submodule; The DC solid-state circuit breaker includes seven time-continuous stages when connected to the DC bus: Stage 1: When the DC bus does not fail, the DC solid-state circuit breaker does not work; Stage 2: When a fault occurs in the DC bus, the bus current starts to rise, and the DC solid-state circuit breaker does not work; Phase 3: The bus current rises to a preset threshold, and the SiC JFET discrete devices of the first and second submodules After receiving the shutdown signal, both the gate-source voltage starts to decrease; Stage 4: Faulty Sub-Module SiC JFET Discrete Device The gate-source voltage of the faulty submodule reaches the Miller platform voltage; Stop reverse charging, Start charging, SiC JFET discrete devices Start shutting down, and the comparison voltage starts to rise; Phase 5: Normal submodule SiC JFET discrete devices The gate-source voltage of the normal submodule reaches the Miller platform voltage; Stop reverse charging, Start charging, SiC JFET discrete devices Start shutting down, and the comparison voltage starts to rise; Stage 6: Faulty Sub-Module SiC JFET Discrete Device The Miller platform ends, the fault submodule Charging is finished. Start reverse charging; Stage 7: Normal Sub-Module SiC JFET Discrete Devices The Miller platform ends, the normal submodule Charging is finished. Reverse charging starts; SiC JFET discrete devices of faulty and normal submodules All continue to shut down, due to the driving resistance of the faulty submodule The smaller the voltage, the faster the shutdown speed, which causes the comparison voltage of the faulty submodule to be higher than the comparison voltage of the normal submodule, and thus causes the comparison voltage of the faulty submodule to be higher than the preset reference voltage. Output low level, the capacitor Access to SiC JFET discrete devices Gate and source to mitigate failures in SiC JFET discrete devices in submodules The shut-off speed.

7. The control method of a DC solid-state circuit breaker with a voltage limiting protection circuit according to claim 6, characterized in that: The Phase 3 includes: Since the SiC JFET discrete devices in the first submodule and the second submodule The gate-source voltage of the DC solid-state circuit breaker has not reached the Miller platform voltage, so the fault current is not cut off temporarily; the SiCJFET discrete devices in the fault submodule and the normal submodule The comparison voltage of the comparator is 0. The outputs are all high level, low voltage MOSFET devices All turned off, capacitor and Through the corresponding drive resistor Reverse charging, according to the KVL law, exists: ； in, and Respectively represent the driving resistance of the normal submodule and the faulty submodule; and Represents the capacitance of normal submodule and faulty submodule respectively ; and Represents the SiC JFET discrete devices in the normal submodule and the faulty submodule respectively The gate-source voltage is and The voltage across the terminals; and Respectively represent the driving resistance in the normal submodule and the faulty submodule a received driving signal; Therefore, due to the driving resistance of the faulty submodule The gate-source voltage drop rate of the faulty submodule in stage three is greater than the gate-source voltage drop rate of the normal submodule.

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