Electrostatic discharge protection circuit, electrostatic discharge protection method

Abstract

The present application provides an electrostatic discharge protection circuit and an electrostatic discharge protection method, wherein the electrostatic discharge protection circuit includes: a current discharge module; the current discharge module includes a first NMOS connected between a power supply and a ground; wherein the first NMOS is used to discharge current of an electrostatic discharge pulse in a conductive state; a driving module; wherein the driving module is used to provide a gate voltage required for the first NMOS to turn on when electrostatic discharge is generated; the driving module includes a first PMOS connected to the power supply and a second PMOS connected in series with the first PMOS; the drain of the second PMOS is connected to the gate of the first NMOS; wherein the size of the first NMOS is larger than the size of the first PMOS or the second PMOS; and a pull-up module; wherein the pull-up module is connected between the power supply and the gate of the first NMOS to pull up the potential of the drain of the second PMOS during the current discharge of the first NMOS. In this way, the risk of gate-drain breakdown of the second PMOS can be effectively reduced, and the reliability of the electrostatic discharge protection circuit can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit technology, and in particular to an electrostatic discharge protection circuit and an electrostatic discharge protection method. Background Art

[0002] Electrostatic discharge (ESD) can generate transient pulses of high voltage and current, causing permanent damage to sensitive integrated circuits and electronic components, leading to device or equipment failure. The risk of ESD is particularly prominent during the manufacturing, transportation, installation, and use of semiconductor devices.

[0003] Currently, through the design and integration of effective electrostatic discharge protection circuits (ESD protection circuits), it is possible to quickly respond and discharge electrostatic energy when electrostatic discharge occurs, thereby protecting the core circuits from damage.

[0004] In related technologies, ESD protection circuits typically consist of an RC network, an inverter (INV), and a large MOS transistor. When an ESD pulse occurs, the large MOS transistor, which is turned on, provides a current path to dissipate the ESD discharge current. However, technicians have found that this ESD protection circuit is prone to failure in practical applications and lacks reliability. Summary of the Invention

[0005] In view of this, multiple embodiments of the present application are dedicated to providing an electrostatic discharge protection circuit and an electrostatic discharge protection method, which can effectively improve the problem of electrostatic discharge protection circuit failure and enhance the reliability of the electrostatic discharge protection circuit.

[0006] One embodiment of the present application provides an electrostatic discharge protection circuit, comprising: a current discharge module; the current discharge module comprises a first NMOS connected between a power supply and a ground; wherein the first NMOS is used to discharge current of an electrostatic discharge pulse in a conducting state; a driving module; the driving module is used to provide the gate voltage required for the first NMOS to be turned on when electrostatic discharge occurs; the driving module comprises a first PMOS connected to a power supply and a second PMOS connected in series with the first PMOS; the drain of the second PMOS is connected to the gate of the first NMOS; wherein the size of the first NMOS is larger than the size of the first PMOS or the second PMOS; a pull-up module; the pull-up module is connected between the power supply and the gate of the first NMOS to pull up the potential of the drain of the second PMOS during the current discharge of the first NMOS.

[0007] Optionally, the pull-up module includes a third PMOS; wherein the source of the third PMOS is connected to a power supply, and the drain is connected to the gate of the first NMOS.

[0008] Optionally, the pull-up module also includes a first RC network connected to the gate of the third PMOS; the first RC network includes a first resistor and a first capacitor; wherein the gate of the third PMOS is connected to the power supply through the first resistor and is grounded through the first capacitor.

[0009] Optionally, the gate of the third PMOS is connected to the source of the second PMOS.

[0010] Optionally, the pull-up module further includes a protection resistor provided between the gate of the third PMOS and the source of the second PMOS.

[0011] Optionally, the pull-up module includes a second NMOS; wherein the drain of the second NMOS is connected to the power supply, and the source is connected to the gate of the first NMOS.

[0012] Optionally, the pull-up module further includes a pull-up resistor provided between the gate of the first NMOS and the drain of the second PMOS.

[0013] Optionally, the gate of the second NMOS has the same potential as the gate of the first PMOS and the gate of the second PMOS.

[0014] Optionally, the electrostatic discharge protection circuit also includes a second RC network; the second RC network includes a second resistor and a second capacitor; the gate of the first PMOS and the gate of the second PMOS are commonly connected to the second RC network; wherein the gate of the first PMOS and the gate of the second PMOS are connected to the power supply through the second resistor and to the ground through the second capacitor.

[0015] An embodiment of the present application provides an electrostatic discharge protection method, which includes: in the event of electrostatic discharge, providing a gate voltage to a first NMOS connected between a power supply and a ground through a driving module, so that the first NMOS is in an on state and discharges the electrostatic discharge pulse; the driving module includes a first PMOS connected to the power supply and a second PMOS connected in series with the first PMOS; the drain of the second PMOS is connected to the gate of the first NMOS; the size of the first NMOS is larger than that of the first PMOS or the second PMOS; wherein, during the current discharge of the first NMOS, the potential of the drain of the second PMOS is pulled up by a pull-up module; the pull-up module is connected between the power supply and the gate of the first NMOS.

[0016] The unexpected effect of the multiple embodiments provided in the present application is that by adding a pull-up module in front of the gate of the large-sized first NMOS, the charging speed of the gate capacitance of the first NMOS can be increased during the current discharge of the electrostatic discharge pulse by the first NMOS, and the drain potential of the second PMOS connected to the gate of the first NMOS can be increased, thereby reducing the potential difference between the gate and drain of the second PMOS, reducing the risk of gate-drain breakdown, and thus improving the problem of failure of the electrostatic discharge protection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of an electrostatic discharge protection circuit in related art.

[0018] Figure 2 Schematic diagram of nanoprobe measurement results for ESD protection circuit failure analysis.

[0019] Figure 3 and Figure 4 Schematic diagram of transmission electron microscopy results for ESD protection circuit failure analysis.

[0020] Figure 5 Schematic diagram of simulation results of an electrostatic discharge protection circuit in related art.

[0021] Figure 6 A schematic diagram of an electrostatic discharge protection circuit provided in accordance with an embodiment of the present application.

[0022] Figure 7 A schematic diagram of simulation results of an electrostatic discharge protection circuit provided in one embodiment of the present application.

[0023] Figure 8 A schematic diagram of an electrostatic discharge protection circuit provided in another embodiment of the present application.

[0024] Figure 9 A schematic diagram of simulation results of an electrostatic discharge protection circuit provided in another embodiment of the present application.

[0025] Figure 10 A schematic diagram of an electrostatic discharge protection circuit provided in yet another embodiment of the present application.

[0026] Figure 11 A schematic diagram of simulation results of an electrostatic discharge protection circuit provided in yet another embodiment of the present application. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0028] In this application, the drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show details of the local features.

[0029] Unless otherwise indicated, all technical and scientific terms used in this application have the same meaning as those generally understood by those skilled in the art in the technical field of this application. The terms used in this application are only for the purpose of describing the specific embodiments and are not intended to limit the scope of this application. The term "and / or" used in this application includes any and all combinations of one or more related listed items. The singular forms of "a", "above" and "the" used in the embodiments of this application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0030] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0031] In the description of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of a simplified description of this application, and do not indicate that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and should not be understood as a limitation to this application.

[0032] In the description of this application, unless otherwise expressly defined, the terms "installed," "connected," "connect," "fixed," and "disposed" should be understood broadly. For example, "connection" can mean fixed, removable, or integrated; it can mean mechanical or electrical; it can mean direct or indirect connection through an intermediary; it can also mean internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0033] See also Figures 1 to 5 . Traditional electrostatic discharge (ESD) protection circuits such as Figure 1As shown in the figure, it consists of an RC network, an inverter INV and a large-size MOS tube NM'. The inverter includes two PMOS transistors connected in series, namely Figure 1 In the example, PM1' and PM2' are connected. The source of PM1' is connected to the power supply, the drain is connected to the source of PM2', and the drain of PM2' is connected to the gate of NM'. The gates of PM1' and PM2' are connected between the power supply and ground via an RC network. When an ESD pulse occurs between the power supply and ground, a voltage drop occurs across resistor R, causing the gate voltage of PM1' and PM2' to fall below the source voltage, causing them to turn on. This, in turn, turns on NM', creating a low-impedance path between the power supply and ground to discharge the current, I_ESD.

[0034] In the related art, the size of NM' is usually large to meet the voltage resistance requirements when discharging current, so NM' has a large gate capacitance. However, the drain of PM2' is connected to the gate of NM', which is equivalent to the drain of PM2' being connected to the gate capacitance of NM'. Since the gate capacitance of NM' is large, its charging speed is relatively slow, resulting in the potential VD2' of the drain of PM2' connected to the gate of NM' being lower than the drain potential VD1' of PM1' when NM' starts to turn on and discharge current. Furthermore, since the gate potentials of PM1' and PM2' are the same, both VG', there is a large voltage difference between the gate potential VG' and the drain potential VD2' of PM2'. When the voltage difference is greater than the breakdown voltage of PM2', it will cause gate-drain breakdown in PM2', and the electrostatic discharge protection circuit will fail.

[0035] The technicians conducted a failure analysis (FA) on the actual product and found that the PM2's nano probe measurement results were as follows: Figure 2 As shown in , there is μA level leakage between the gate and the drain, and the TEM (transmission electron microscopy) results are as follows Figure 3 and Figure 4 As shown in , there is diffusion of NiSi between the gate and the drain, from which it can be seen that PM2' has undergone gate-drain breakdown.

[0036] In addition, the technicians also simulated the opening of the above-mentioned ESD protection circuit under a 2KV ESD pulse. The simulation results are as follows Figure 5 As shown in the figure, an ESD pulse is generated at the power supply at 0.5μs, triggering the ESD protection circuit to activate and discharging the current I_ESD through NM'. Comparing the voltages at various nodes reveals that VD2' remains consistently lower than VD1' and exhibits a significant voltage difference with VG'. The voltage difference reaches a maximum of 4.0V at 1.35μs, potentially leading to gate-drain breakdown.

[0037] Therefore, it is necessary to provide an electrostatic discharge protection circuit that can reduce the risk of gate-drain breakdown and thereby improve the problem of electrostatic discharge protection circuit failure.

[0038] See also Figure 6 and Figure 7 One embodiment of the present application provides an electrostatic discharge protection circuit. Figure 7 As shown, the electrostatic discharge protection circuit may include a current discharge module 11 , a driving module 12 , a pull-up module 13 and a second RC network 14 .

[0039] In this embodiment, the current discharge module 11 is used to provide a low-impedance current path from the power supply to the ground when electrostatic discharge occurs, so as to discharge the electrostatic discharge pulse through the path, thereby realizing the function of protecting the circuit. Specifically, the current discharge module 11 includes a first NMOS connected between the power supply and the ground, that is, Figure 6 In the NM, the first NMOS is used to discharge the electrostatic discharge pulse current when in the on state. The source of the NM is grounded, and the drain is connected to the power supply.

[0040] In this embodiment, the driving module 12 is used to provide the gate voltage required for NM to turn on when electrostatic discharge occurs. Specifically, the driving module 12 includes a first PMOS connected to the power supply and a second PMOS connected in series with the first PMOS, that is, Figure 6 PM1 and PM2 are connected. PM1's source is connected to the power supply, its drain is connected to PM2's source, and PM2's drain is connected to the gate of NM. This allows the potential VD2 of PM2's drain to control the on / off state of NM. The gates of PM1 and PM2 can be connected to the same potential, VG.

[0041] In this embodiment, the driving module 12 may further include two NMOSs connected in series between VD2 and the ground. The two NMOSs and PM1 and PM2 may form an inverter.

[0042] In this embodiment, NM can be a large-size transistor, which can be larger than PM1 or PM2 to meet the voltage withstand requirements of the discharge current. It can be understood that the gate capacitance of NM is larger than the gate capacitance of PM1 or PM2.

[0043] In this embodiment, the pull-up module 13 is used to increase the potential of the drain of PM2 during the current discharge process to reduce the potential difference between the drain potential VD2 and the gate potential VG of PM2, thereby preventing breakdown. Specifically, the pull-up module 13 can be connected between the power supply and the gate of PM1. In this way, the charging speed of the NM gate can be increased during the current discharge process of the NM, thereby increasing the potential of the drain of PM2.

[0044] In this embodiment, the pull-up module 13 may include a third PMOS, namely Figure 6 PM3 is connected to the gate of PM3, and a first RC network including a first resistor R1 and a first capacitor C1. The source of PM3 is connected to the power supply, and the drain is connected to the gate of NM. The gate of PM3 is connected to the power supply via R1 and to ground via C1.

[0045] In this embodiment, when an electrostatic discharge pulse occurs, a voltage drop may be generated across the first resistor R1 of the first RC network, thereby turning on PM3. The current flowing through PM3 may charge the gate of NM, thereby increasing the charging speed of the gate capacitance of NM. At the same time, the gate voltage of node NM is higher, and the potential of VD2 is pulled higher.

[0046] In this embodiment, by providing a first RC network, PM3 can be delayed in responding when an electrostatic discharge pulse is generated, thereby preventing the instantaneous electrostatic discharge energy from causing a significant impact on the circuit. It should be noted that in some embodiments, such as in application scenarios where the ESD voltage is not large, the first RC network may not be provided in the pull-up module 13.

[0047] In this embodiment, the ESD protection circuit may further include a second RC network 14. Specifically, the second RC network 14 may include a second resistor R2 and a second capacitor C2. In this embodiment, the gates of PM1 and PM2 may be connected to the second RC network 14. The gates of PM1 and PM2 are connected to a power supply via R2 and to ground via C2. Similarly, the second RC network 14 can provide a delay in the ESD protection circuit's response, thereby protecting the circuit.

[0048] In this embodiment, an unexpected effect is that, through the pull-up module 13, during the process of the first NMOS discharging the current of the electrostatic discharge pulse, the charging speed of the gate capacitance of the first NMOS can be improved, and the drain potential of the second PMOS connected to the gate of the first NMOS can be increased, thereby reducing the potential difference between the gate and the drain of the second PMOS, reducing the risk of gate-drain breakdown, and thus improving the problem of failure of the electrostatic discharge protection circuit.

[0049] The technicians simulated the opening of the electrostatic discharge protection circuit provided by this embodiment under a 2KV electrostatic discharge pulse. The simulation results are as follows Figure 7As shown in the figure, an ESD pulse is generated at the power supply at 0.5μs, triggering the ESD protection circuit to activate and dissipate current through NM. Comparing the voltages at various nodes reveals a significant decrease in the potential difference between VD2 and VG, reaching a maximum of 2.0V at 1.39μs. This represents a 50% reduction compared to ESD protection circuits in related technologies, mitigating the risk of PM2 breakdown. Furthermore, the potential difference between PM3's source and gate is essentially the same as that of PM1, and the potential difference between its drain and gate is essentially the same as that of PM2, thus minimizing the risk of breakdown.

[0050] Also, please refer again to Figure 5 ,from Figure 5 It can also be seen that in the electrostatic discharge protection circuit in the related art, the current flowing through NM' is basically 0 at 1.6μs, that is, NM' is turned off, but the ESD discharge process lasts about 2μs. Therefore, the electrostatic discharge protection circuit in the related art still has the problem of incomplete current discharge.

[0051] And from Figure 7 It can be seen from the figure that the electrostatic discharge protection circuit provided in this embodiment has a current flowing through NM of substantially zero at 2.0 μs, that is, NM is closed, which is consistent with the entire ESD discharge process. Therefore, the current discharge of the electrostatic discharge protection circuit provided in this embodiment is more complete.

[0052] See also Figure 8 and Figure 9 Another embodiment of the present application provides an electrostatic discharge protection circuit. Figure 8 As shown, the electrostatic discharge protection circuit may include a current discharge module 21, a driver module 22, a pull-up module 23, and a second RC network 24. Unlike the previous embodiment, in this embodiment, the pull-up module 23 is composed of a third PMOS transistor, PM3, and a protection resistor R3 disposed between the gate of PM3 and the source of PM2. The gate of PM3 is connected to the source of PM2 via R3.

[0053] In this embodiment, the functions and effects of the same parts as those in the previous embodiment can be explained with reference to the previous embodiment and will not be repeated here.

[0054] In this embodiment, an unexpected effect is that, while the pull-up module 23 is used to pull up the drain potential of the second PMOS to reduce the potential difference between the gate and the drain of the second PMOS, thereby reducing the risk of gate-drain breakdown, compared with the previous embodiment, fewer electronic components are used, the connection method is simpler, and the integrated circuit layout area occupied is smaller.

[0055] The technicians simulated the opening of the electrostatic discharge protection circuit provided by this embodiment under a 2KV electrostatic discharge pulse. The simulation results are as follows Figure 9 As shown, it can be seen that at 0.5μs, an ESD pulse is generated at the power supply end, the ESD protection circuit is activated, and the current is discharged through NM. Comparing the voltages of various nodes, it can be found that the potential difference between VD2 and VG has been significantly reduced, reaching a maximum of 2.1V at 1.35μs. Compared with the ESD protection circuit in the related art, this potential difference is reduced by 48%, reducing the risk of the second PMOS breakdown. Although the potential difference between the drain and gate of PM3 also reaches 2.7V at 1.35μs, it is also reduced by 33% compared to the 4V potential difference between the gate and drain of PM2' in the ESD protection circuit of the related art, reducing the risk of breakdown.

[0056] In addition, from Figure 9 It can be seen from the figure that the electrostatic discharge protection circuit provided in this embodiment has a current flowing through NM of substantially zero at 2.0 μs, that is, NM is closed, which is consistent with the entire ESD discharge process. Therefore, the current discharge of the electrostatic discharge protection circuit provided in this embodiment is also more complete.

[0057] See also Figure 10 and Figure 11 Another embodiment of the present application provides an electrostatic discharge protection circuit. Figure 10 As shown, the electrostatic discharge protection circuit may include a current discharge module 31, a driving module 32, a pull-up module 33 and a second RC network 34. The difference from the previous embodiment is that in this embodiment, the pull-up module 33 is composed of a second NMOS, i.e. Figure 10 NM1 and a pull-up resistor R4 are placed between NM's gate and PM2's drain. NM1's drain is connected to the power supply, and its source is connected to NM's gate. NM1's bulk terminal can be grounded or connected to its source. NM1's gate can be connected to the same node as PM1 and PM2's gates, ensuring that the gates of NM1, PM1, and PM2 are at the same potential, VG.

[0058] In this embodiment, the pull-up resistor R4 can further increase the drain potential VD2 of PM2 to reduce the potential difference between the gate and drain of the second PMOS when the current flowing through the second NMOS is insufficient to charge the gate of NM. It should be noted that in some embodiments, such as when the second NMOS has a sufficient charging effect on the gate of NM, the pull-up resistor R4 may not be provided. The pull-up resistor R4 can be flexibly configured as needed.

[0059] In this embodiment, the functions and effects of the same parts as those in the aforementioned embodiments can be explained with reference to the aforementioned embodiments and will not be repeated here.

[0060] In this embodiment, an unexpected effect is that while the pull-up module 33 is used to pull up the drain potential of the second PMOS to reduce the potential difference between the gate and the drain of the second PMOS, thereby reducing the risk of gate-drain breakdown, fewer electronic components are used, the connection method is simpler, and the integrated circuit layout area occupied is smaller.

[0061] The technicians simulated the opening of the electrostatic discharge protection circuit provided by this embodiment under a 2KV electrostatic discharge pulse. The simulation results are as follows Figure 11 As shown in the figure, it can be seen that an ESD pulse is generated at the power supply at 0.5μs, the ESD protection circuit is activated, and the current is discharged through NM. Comparing the voltages of various nodes, it can be seen that the potential difference between VD2 and VG has been significantly reduced, reaching a maximum of 2.04V at 1.51μs. Compared with the ESD protection circuit in the related art, this potential difference is reduced by 49%, reducing the risk of breakdown of the second PMOS. At the same time, the potential difference between PM3's source potential VD3 and gate potential VG reaches a maximum of 2.05V at 1.51μs, also reducing the risk of breakdown.

[0062] In addition, from Figure 11 It can be seen from the figure that the electrostatic discharge protection circuit provided in this embodiment has a current flowing through NM of substantially zero at 2.2 μs, that is, NM is closed, which is consistent with the entire ESD discharge process. Therefore, the electrostatic discharge protection circuit provided in this embodiment can also discharge the current completely and effectively.

[0063] An embodiment of the present application provides a method for protecting against electrostatic discharge, the method comprising:

[0064] In the event of electrostatic discharge, a gate voltage is provided to a first NMOS connected between a power supply and a ground through a driving module, so that the first NMOS is in a conductive state and discharges the current of the electrostatic discharge pulse; the driving module includes a first PMOS connected to a power supply and a second PMOS connected in series with the first PMOS; the drain of the second PMOS is connected to the gate of the first NMOS; the size of the first NMOS is larger than that of the first PMOS or the second PMOS; wherein, during the current discharge of the first NMOS, the potential of the drain of the second PMOS is pulled up by a pull-up module; the pull-up module is connected between the power supply and the gate of the first NMOS.

[0065] The functions and effects of each step in the electrostatic discharge protection method can be explained and illustrated with reference to the aforementioned embodiments, and will not be repeated here.

[0066] It should be understood that the specific examples in this article are only intended to help those skilled in the art better understand the embodiments of the present application, and are not intended to limit the scope of the present invention.

[0067] It can be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0068] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0069] Unless otherwise indicated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art in the technical field of the present application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of this application. The term "and / or" used in this application includes any and all combinations of one or more related listed items. The singular forms of "a", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0070] The above description is merely a specific embodiment of the present application, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. An electrostatic discharge protection circuit, characterized in that: include: Current discharge module; The current discharge module includes a first NMOS connected between a power supply and a ground; wherein the first NMOS is used to discharge the current of the electrostatic discharge pulse in a conducting state; A driving module; the driving module is configured to provide a gate voltage required for turning on the first NMOS in the event of electrostatic discharge; the driving module comprises a first PMOS connected to a power supply and a second PMOS connected in series with the first PMOS; the drain of the second PMOS is connected to the gate of the first NMOS; wherein the size of the first NMOS is larger than that of the first PMOS or the second PMOS; A pull-up module; the pull-up module is connected between a power supply and the gate of the first NMOS to pull up the potential of the drain of the second PMOS during the current discharge of the first NMOS; the pull-up module includes a third PMOS; the source of the third PMOS is connected to the power supply, and the drain is connected to the gate of the first NMOS; wherein the gate of the third PMOS is connected to the source of the second PMOS.

2. The electrostatic discharge protection circuit according to claim 1, wherein: The pull-up module further includes a first RC network connected to the gate of the third PMOS; the first RC network includes a first resistor and a first capacitor; wherein the gate of the third PMOS is connected to a power supply through the first resistor and to ground through the first capacitor.

3. The electrostatic discharge protection circuit according to claim 1, wherein: The pull-up module further includes a protection resistor provided between the gate of the third PMOS and the source of the second PMOS.

4. The electrostatic discharge protection circuit according to any one of claims 1 to 3, characterized in that: The electrostatic discharge protection circuit also includes a second RC network; the second RC network includes a second resistor and a second capacitor; the gate of the first PMOS and the gate of the second PMOS are commonly connected to the second RC network; wherein the gate of the first PMOS and the gate of the second PMOS are connected to the power supply through the second resistor and to ground through the second capacitor.

5. An electrostatic discharge protection circuit, characterized in that: include: Current discharge module; The current discharge module includes a first NMOS connected between a power supply and a ground; wherein the first NMOS is used to discharge the current of the electrostatic discharge pulse in a conducting state; A driving module; the driving module is configured to provide a gate voltage required for turning on the first NMOS in the event of electrostatic discharge; the driving module comprises a first PMOS connected to a power supply and a second PMOS connected in series with the first PMOS; the drain of the second PMOS is connected to the gate of the first NMOS; wherein the size of the first NMOS is larger than that of the first PMOS or the second PMOS; A pull-up module; the pull-up module is connected between a power supply and the gate of the first NMOS to pull up the potential of the drain of the second PMOS during the current discharge process of the first NMOS; the pull-up module includes a second NMOS and a pull-up resistor; wherein the drain of the second NMOS is connected to the power supply, and the source is connected to the gate of the first NMOS; the pull-up resistor is arranged between the gate of the first NMOS and the drain of the second PMOS.

6. The electrostatic discharge protection circuit according to claim 5, characterized in that: The gate of the second NMOS has the same potential as the gates of the first PMOS and the second PMOS.

7. The electrostatic discharge protection circuit according to claim 5 or 6, characterized in that: The electrostatic discharge protection circuit also includes a second RC network; the second RC network includes a second resistor and a second capacitor; the gate of the first PMOS and the gate of the second PMOS are commonly connected to the second RC network; wherein the gate of the first PMOS and the gate of the second PMOS are connected to the power supply through the second resistor and to ground through the second capacitor.

8. A method for protecting against electrostatic discharge, characterized in that: The electrostatic discharge protection method includes: In the event of electrostatic discharge, a gate voltage is provided to a first NMOS connected between a power supply and a ground through a driving module, so that the first NMOS is in a conducting state and discharges the current of the electrostatic discharge pulse; the driving module includes a first PMOS connected to the power supply and a second PMOS connected in series with the first PMOS; the drain of the second PMOS is connected to the gate of the first NMOS; the size of the first NMOS is larger than that of the first PMOS or the second PMOS; In which, during the current discharge of the first NMOS, the potential of the drain of the second PMOS is pulled up by the pull-up module; the pull-up module is connected between the power supply and the gate of the first NMOS; the pull-up module includes a third PMOS; the source of the third PMOS is connected to the power supply, and the drain is connected to the gate of the first NMOS; wherein the gate of the third PMOS is connected to the source of the second PMOS; or, the pull-up module includes a second NMOS and a pull-up resistor; wherein the drain of the second NMOS is connected to the power supply, and the source is connected to the gate of the first NMOS; the pull-up resistor is arranged between the gate of the first NMOS and the drain of the second PMOS.

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