Systems, methods, and apparatus for controlling oscillator frequency response

Abstract

A method may include generating, using an oscillator, a first signal having a frequency based on a current; generating a first portion of the current based on the second signal, the first portion of the current having a first frequency characteristic; and generating a second portion of the current based on the second signal, the second portion of the current having a second frequency characteristic. A gain of the first frequency characteristic may vary based on a frequency of the second signal. The first frequency characteristic may include a first gain at a first frequency and a second gain at a second frequency. The first gain may be greater than the second gain, and the second frequency may be greater than the first frequency. A phase of the first frequency characteristic may vary based on a frequency of the second signal.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of U.S. Provisional Patent Application No. 63 / 609,844, filed on December 13, 2023, which is incorporated herein by reference. Technical field

[0003] This disclosure generally relates to oscillators, and more particularly, to systems, methods, and apparatuses for controlling the frequency response of an oscillator. Background art

[0004] An oscillator can generate an output signal at a frequency determined by a control signal. For example, a voltage controlled oscillator (VCO) can generate an output signal that can oscillate at a frequency determined by an input voltage signal. VCOs can be used in various applications such as signal modulation, phase locked loop (PLL), etc.

[0005] The above information disclosed in the background art section is only for enhancing the understanding of the background of the principles of the invention, and thus may include information that does not constitute prior art. Summary of the invention

[0006] A method may include: generating, using an oscillator, a first signal having a current - based frequency; generating a first portion of a current based on a second signal, the first portion of the current having a first frequency characteristic; and generating a second portion of the current based on the second signal, the second portion of the current having a second frequency characteristic. The gain of the first frequency characteristic may be changed based on the frequency of the second signal. The method may further include: controlling the frequency of the second signal; and controlling the gain of the first frequency characteristic based on the frequency of the second signal. The first frequency characteristic may include a first gain at a first frequency and a second gain at a second frequency. The first gain may be greater than the second gain, and the second frequency may be greater than the first frequency. The phase of the first frequency characteristic may be changed based on the frequency of the second signal. The method may further include: controlling the phase of the second signal; and controlling the gain of the first frequency characteristic based on the phase of the second signal. The first frequency characteristic may include a first phase shift at a first frequency and a second phase shift at a second frequency. The first phase shift may be in a first direction, and the second phase shift may be in a second direction.

[0007] A circuit may include: an oscillator; configured to generate a first signal having a current-based frequency; and a current generator, configured to generate a current, wherein the current generator may include: a first path, configured to generate a first portion of the current based on a second signal, the first path having a first frequency characteristic; and a second path, configured to generate a second portion of the current based on the second signal, the second path having a second frequency characteristic. The first path may include a first transistor configured to generate the first portion of the current based on the second signal, and the second path may include a second transistor configured to generate the second portion of the current based on the second signal. The second path may include a filter configured to control the second transistor based on the second signal. The current generator may include a third transistor configured to control the first transistor and the second transistor based on the second signal. The first path may be configured to generate the first portion of the current based on a third signal, the second path may be configured to generate the second portion of the current based on the third signal, and the circuit may include an input stage configured to generate the third signal based on the second signal. The current may be a first current, the third signal may be a second current, and the current generator may include a current mirror configured to: use the first path to generate the first portion of the first current based on the second current; and use the second path to generate the second portion of the first current based on the second current. The input stage may be configured to generate the third signal based on a comparison of the second signal and a fourth signal. The circuit may include a detector circuit configured to generate the second signal based on a comparison of the first signal and the third signal. The circuit may have a loop bandwidth, the first path may have a pole at a pole frequency, and the loop bandwidth may be greater than the pole frequency.

[0008] A circuit may include: an oscillator, configured to generate a first signal having a current-based frequency; a current generator, configured to generate a current; and an input stage, configured to control the current generator based on a comparison of a second signal and a third signal. The second signal may include an input signal, and the third signal may include a reference signal. The input stage may include a first transistor and a second transistor, the first transistor including a first terminal connected to a power supply, a second terminal configured to receive the second signal, and a third terminal connected to the current generator, the second transistor including a first terminal connected to the power supply, a second terminal configured to receive the third signal, and a third terminal connected to the current generator. The second terminal of the first transistor may be connected to the power supply using a first current source, the second terminal of the second transistor may be connected to the power supply using a second current source, and the input stage may include a resistor connected between the first transistor and the second transistor.

[0009] A circuit may include: an oscillator configured to generate an output signal having a frequency based on a first signal; and a signal generator configured to generate the first signal, wherein the signal generator may include: a first path configured to generate a first portion of the first signal based on a second signal, the first path having a first frequency characteristic; and a second path configured to generate a second portion of the first signal based on the second signal, the second path having a second frequency characteristic.

[0010] A circuit may include: an oscillator configured to generate an output signal having a frequency based on a control signal; and an input stage configured to generate the control signal based on a comparison of an input signal and a reference signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings are not necessarily to scale, and for illustrative purposes, in all the drawings, elements or portions thereof having similar structures or functions may generally be represented by reference numerals that end with the same numbers, letters, etc. and / or include the same numbers, letters, etc. The drawings are only intended to facilitate the description of the various embodiments described herein. The drawings do not depict every aspect of the teachings disclosed herein and do not limit the scope of the claims. To prevent the drawings from becoming cluttered, not all components, connections, etc. are shown, and not all components have reference numerals. However, the pattern of component configurations can be readily seen from the drawings. The drawings, together with the specification, illustrate example embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure.

[0012] Figure 1 An embodiment of a voltage-controlled oscillator according to an example embodiment of the present disclosure is shown.

[0013] Figure 2 An example embodiment of the present disclosure is shown Figure 1 A graph of an example frequency characteristic of the voltage-controlled oscillator shown.

[0014] Figure 3 An embodiment of a voltage-controlled oscillator having a current mirror according to an example embodiment of the present disclosure is shown.

[0015] Figure 4 An embodiment of a phase-locked loop according to an example embodiment of the present disclosure is shown.

[0016] Figure 5 An example embodiment of a loop filter according to an example embodiment of the present disclosure is shown.

[0017] Figure 6 An embodiment of a charge pump according to an example embodiment of the present disclosure is shown.

[0018] Figure 7An embodiment of a phase-locked loop expressed in complex frequency according to an example embodiment of the present disclosure is shown.

[0019] Figure 8 An example embodiment of the frequency response characteristics of a phase-locked loop and its components according to an example embodiment of the present disclosure is shown.

[0020] Figure 9 An embodiment of a voltage-controlled oscillator and a calibration scheme according to an example embodiment of the present disclosure is shown.

[0021] Figure 10 An example embodiment of the frequency-voltage characteristics of a voltage-controlled oscillator and an example embodiment of the output voltage-current characteristics of a charge pump according to an example embodiment of the present disclosure are shown.

[0022] Figure 11 An example embodiment of the frequency-voltage characteristics of a voltage-controlled oscillator and the current-voltage characteristics of a charge pump at a reduced operating temperature according to an example embodiment of the present disclosure is shown.

[0023] Figure 12 An example embodiment of the frequency-voltage characteristics of a voltage-controlled oscillator and the current-voltage characteristics of a charge pump at an elevated operating temperature according to an example embodiment of the present disclosure is shown.

[0024] Figure 13 An embodiment of an oscillator with a modified gain coefficient according to an example embodiment of the present disclosure is shown.

[0025] Figure 14 An example embodiment of the frequency response characteristics of a phase-locked loop and its components with a modified gain coefficient according to an example embodiment of the present disclosure is shown.

[0026] Figure 15 An embodiment of an oscillator having one or more frequency characteristics according to an example embodiment of the present disclosure is shown.

[0027] Figure 16 An example embodiment of an oscillator having one or more frequency characteristics according to an example embodiment of the present disclosure is shown.

[0028] Figure 17 An example embodiment of a voltage-controlled oscillator having one or more frequency characteristics according to an example embodiment of the present disclosure is shown.

[0029] Figure 18 An example embodiment of the frequency response characteristics of a voltage-controlled oscillator having a low-pass filter and a phase-locked loop as shown in Figure 17 is shown according to an example embodiment of the present disclosure.

[0030] Figure 19An example embodiment showing the frequency - voltage characteristics of a voltage - controlled oscillator and the current - voltage characteristics of a charge pump at a reduced operating temperature in accordance with an example embodiment of the present disclosure.

[0031] Figure 20 An embodiment of an oscillator having an input stage in accordance with an example embodiment of the present disclosure is shown.

[0032] Figure 21 An example embodiment of a voltage - controlled oscillator having an input stage in accordance with an example embodiment of the present disclosure is shown.

[0033] Figure 22 An example embodiment showing the frequency - voltage characteristics of a voltage - controlled oscillator and the current - voltage characteristics of a charge pump at a reduced operating temperature in accordance with an example embodiment of the present disclosure.

[0034] Figure 23 An embodiment of a voltage - controlled oscillator having one or more frequency characteristics and a cascode scheme in accordance with an example embodiment of the present disclosure is shown.

[0035] Figure 24 An embodiment of a voltage - controlled oscillator having one or more frequency characteristics and a cascode scheme in accordance with an example embodiment of the present disclosure is shown.

[0036] Figure 25 An example embodiment of a low - pass filter having a capacitor and a resistor in accordance with an example embodiment of the present disclosure is shown.

[0037] Figure 26 An example embodiment of a low - pass filter having a capacitor and a resistor based on one or more electronically controllable devices in accordance with an example embodiment of the present disclosure is shown.

[0038] Figure 27 Some example operating characteristics of an embodiment of a transistor operating in the triode region in accordance with an example embodiment of the present disclosure are shown. Detailed Description

[0039] An oscillator (such as a voltage - controlled oscillator (VCO)) can generate an oscillating signal at a frequency determined by an input voltage signal applied to the VCO. The VCO can be used, for example, in a phase - locked loop (PLL) to generate an output signal at a frequency that can be a multiple of the frequency of a reference signal. The dynamic characteristics (e.g., frequency response) of the VCO can affect the stability, capture range, lock - in range, and / or other performance characteristics of the PLL in which the VCO can be used.

[0040] One type of VCO may include a voltage-current converter, a current mirror, and a current-controlled oscillator. The voltage-current converter may convert an input voltage into a first current that may be applied to the current mirror. The current mirror may generate a second current that is a multiple of the first current. For example, the current mirror may have a current ratio of 1:N such that the second current is N times the first current. The second current may be applied to a current-controlled oscillator (e.g., a ring oscillator) that may oscillate based on the frequency of the second current.

[0041] In some embodiments, a relatively high current multiplication ratio may provide a relatively high gain coefficient (K VCO ) for the VCO, which may enable the VCO (and / or a PLL in which the VCO may be used) to operate over a relatively wide frequency range. However, a potential problem with a higher current multiplication ratio is that the noise associated with the current mirror may increase as the multiplication ratio increases. Depending on the implementation details, the noise may limit the available current multiplication, gain coefficient, and / or frequency range. Another potential problem with a higher current multiplication ratio, gain coefficient, etc. is that this may change the dynamic characteristics of the VCO in a way that may reduce the stability of a PLL in which the VCO is used.

[0042] An oscillator (e.g., a VCO) according to an example embodiment of the present disclosure may include a current generator (e.g., a current mirror) that may generate a current having two or more components with different frequency characteristics. For example, the current mirror may include a relatively high-frequency current path that may provide a current component with a relatively large variation based on a change in a control signal (e.g., an input voltage). The current mirror may also include a relatively low-frequency current path that may provide a current component with a relatively small variation based on a change in the control signal. The two components may be combined (e.g., by summing), and the combined current may be applied to the current-controlled oscillator. Using a current with components having different frequency characteristics may reduce or eliminate the noise problems associated with the current mirror, which, depending on the implementation details, may increase the available current multiplication ratio, gain coefficient, frequency range, etc. of the VCO and / or PLL. Additionally or alternatively, using a current with components having different frequency characteristics may reduce or eliminate the stability problems associated with a relatively high current multiplication ratio, gain coefficient, etc.

[0043] In some applications, a VCO may be used in a PLL with a loop filter and a charge pump that may output a positive current (also referred to as an up current or I UP) or a negative current (also referred to as a down current or I DN ). The output current of the charge pump can be applied to a loop filter, and the loop filter can generate a control voltage that can be applied as an input signal to a VCO (which can be referred to as V cont ). The control voltage can be stabilized at a value when the PLL is locked.

[0044] A potential problem with a charge pump PLL is that the relative magnitudes of the positive charge pump current and the negative charge pump current may not be equal, especially under certain operating conditions (e.g., process, voltage, and / or temperature (PVT) conditions, operating frequency, etc.). For example, in some embodiments, when the voltage across the loop filter driven by the positive charge pump stabilizes to a value approximately halfway (also referred to as the midpoint) between the positive supply voltage and the negative supply voltage (e.g., V DD and ground), the positive charge pump current and the negative charge pump current can be equal (e.g., matched). As the voltage across the loop filter moves away from the midpoint (e.g., away from V DD / 2), a mismatch may occur such that the positive charge pump current and the negative charge pump current may become unequal. Depending on the implementation details, the mismatched charge pump currents may cause spurs, jitter, phase noise, etc. in the PLL.

[0045] In addition, some VCOs may include a voltage - current converter, and the voltage - current converter can be configured in such a way that it may cause the voltage across the loop filter to operate or stabilize at a voltage other than the midpoint, thereby causing a mismatch between the positive charge pump current and the negative charge pump current. For example, some voltage - current converters can have a voltage - current conversion ratio that varies with changes in the threshold voltage of the input transistor (which may be sensitive to PVT values), the value of the degeneration resistor for the input transistor, etc.

[0046] An oscillator (e.g., a VCO) according to an example embodiment of the present disclosure can include an input stage (e.g., a voltage - current converter), and the input stage can cause the input signal of the oscillator (e.g., V of the VCO cont ) to operate at or near the midpoint of the supply voltage or at or near other values where the charge pump can generate matched positive and negative currents. For example, the input stage can be implemented using a voltage - current converter having a pair of differential inputs (e.g., a differential input transconductance stage that can be referred to as a G m stage or a g m stage). One of the differential inputs can be connected to receive the input signal of the oscillator (e.g., V cont ), while the other differential input can be connected to a reference signal (e.g., the midpoint or V DD / 2). Thus, the voltage - current converter can operate based on the difference between the input signal and the reference signal (e.g., by comparing the input signal with the reference signal). Depending on the implementation details, this can cause the input control signal of the oscillator to stabilize at a value where the charge pump can generate a matching positive current and negative current when the PLL using the VCO is locked. Additionally or alternatively, depending on the implementation details, using a differential input stage for the oscillator may reduce or eliminate the sensitivity of the input stage to transistor threshold voltages, degradation resistor values, operating temperature, etc. Additionally or alternatively, depending on the implementation details, using a differential input stage for the oscillator may reduce or eliminate the need for one or more types of calibration (e.g., PVT calibration) for the oscillator.

[0047] The present disclosure encompasses many aspects related to oscillators, such as input stages, current generators, etc. The aspects disclosed herein can have independent utility and can be embodied separately, and not every embodiment can utilize every aspect. Additionally, these aspects can also be embodied in various combinations, some of which can amplify some of the benefits of individual aspects in a synergistic manner.

[0048] For illustrative purposes, some embodiments may be described in the context of some specific implementation details, such as a device implemented using a specific type of transistor, filter, charge pump, oscillator, current mirror, number and / or configuration of components, etc. However, the aspects of the present disclosure are not limited to these or any other implementation details.

[0049] Figure 1 An embodiment of a voltage - controlled oscillator according to an example embodiment of the present disclosure is shown. Figure 1 The voltage - controlled oscillator (VCO) 104 shown can generate an oscillating output signal 102, and the frequency f of the oscillating output signal 102 out can be determined by the control voltage v applied as an input 101 to the VCO 104. cont value.

[0050] In some embodiments throughout the present disclosure, and depending on the context, certain markings can be used to indicate signals, aspects of signals (e.g., the frequency, voltage, etc. of a signal), terminals that can carry signals, components, values of components, etc. For example, depending on the context, f out can indicate the output signal 102, the frequency of the output signal 102, and / or the output terminal that can carry the output signal 102 from the VCO 104. As another example, depending on the context, v contIt may indicate the input signal 101, the value of the control voltage applied as the input signal 101, and / or may carry the input signal 101 to the input terminal of the VCO 104. As another example, depending on the context, R or C may respectively indicate a resistor or a capacitor, and / or indicate the value representing the resistor or the capacitor.

[0051] Figure 2 shows an example according to an exemplary embodiment of the present disclosure Figure 1 A graph of the exemplary frequency characteristics of the voltage-controlled oscillator shown. Refer to Figure 2 , in some embodiments, the frequency f of the output signal shown along the vertical axis out may vary proportionally with the magnitude of the control voltage v cont shown along the horizontal axis. For example, f out value may be at the control voltage V 1 of f 1 and at the control voltage V 2 of f 2 . Figure 2 The slope of the frequency characteristics shown may represent the gain coefficient K VCO (which may also be referred to as gain) of the VCO 104. For example, in Figure 2 the embodiment shown, K VCO may be determined as follows:

[0052]

[0053] which may be expressed, for example, in units of Hertz per Volt (Hz / V).

[0054] The value f 0 may indicate the offset of K cont for v VCO = 0, so

[0055] f out = f 0 + K VCO v cont (Equation 2)

[0056] The phase φ out of the output signal 102 may be represented in the time domain as follows:

[0057] φ out (t) = ∫ω out dt = 2π∫f out dt = 2πf 0 t + 2πK VCO ∫v cont dt (Equation 3)

[0058] where ω outThe frequency of the output signal can be expressed in radians per second such that ω out = 2πf out . The voltage v of the output signal 102 out can be represented in the time domain as follows:.

[0059] v out (t) = V 0 cosθ out (t) = V 0 cos(∫ω out dt) = V 0 cos2πft + 2πK 0 t + 2πK VCO ∫v cont dt (Equation 4)

[0060] The phase φ of the output signal 102 in the time domain out can be related to the excess phase Φ in the complex frequency domain (e.g., s-domain) of the output signal 102 as follows:. excess Related:.

[0061]

[0062] Figure 3 FIG. shows an embodiment of a voltage controlled oscillator with a current mirror according to an exemplary embodiment of the present disclosure. Figure 3 The illustrated VCO 304 may include a voltage-to-current (V2I) converter input stage 305, a current mirror 306, and / or a current controlled oscillator (CCO) 307. The input stage 305 may include a transistor Q301 having a gate configured to receive an input signal in the form of a control voltage v cont at an input terminal 301, a source connected to a first power supply (e.g., a ground node) through a degeneration resistor R301, and a drain configured to control a first current I cont based on the control voltage v 302 . Thus, the input stage 305 may have a transconductance G m that can determine the voltage-to-current conversion ratio of the input stage 305.

[0063] The first current I 302 can serve as an input signal to the current mirror 306, which may include transistors Q302 and Q303. The transistor Q302 may have a source connected to a second power supply (e.g., a positive power supply node or V DD ) and be configured to mirror the first current I 302The drain that can flow into the drain of Q301, and the gate connected back to the drain (e.g., diode-connected). The transistor Q303 can have a source connected to the second power supply, a gate connected to the gate of Q302, and is configured to generate a second current I 303 As the drain of the output of the current mirror 306.

[0064] The second current I 303 Can serve as the input signal of the current-controlled oscillator 307. The current-controlled oscillator 307 can be implemented, for example, using a ring oscillator (e.g., a delay chain) with multiple stages arranged in a ring (e.g., an odd number of inverter stages) to generate an oscillating output signal with a frequency of f at the output terminal 302 out Of the oscillating output signal. The frequency f of the output signal out Can vary, for example, in proportion to the value of the second current I 303 Therefore, depending on the implementation details, the output frequency f out May vary in proportion to the value of the control voltage v cont In this implementation, the second current I 303 Can be referred to as I VCO , and the gain coefficient K of the current-controlled oscillator 307 ICO Can be determined as follows:

[0065]

[0066] Which can be expressed, for example, in hertz per ampere (Hz / A).

[0067] The transistors Q302 and Q303 can be configured to provide current multiplication, for example, at a ratio of 1:N, such that the output current I 303 Can have a value N times that of the input current I 302 . In some embodiments, the value of N can be any positive real number, and a value greater than 1 can provide current gain. The current ratio can be implemented, for example, by fabricating transistors Q302 and Q303 with a device geometry ratio (e.g., the ratio of channel area, channel width, channel length, etc.) of 1:N and / or by using N parallel replicas of Q303, each replica having the same geometry as Q302. Additionally or alternatively, the current multiplication ratio 1:N can be implemented using an adjustable value of N (as shown by arrow 379) by selectively connecting N replicas of Q303 in parallel using one or more switches.

[0068] Depending on the implementation details, Figure 3 The VCO 304 shown may provide a relatively high gain coefficient K VCOAccordingly, the PLL including the VCO 304 can cover a relatively wide frequency range. For example, using a relatively high N value can enable the current mirror 306 to generate a relatively high current I 303 to drive the current-controlled oscillator 307 while saving power by maintaining a relatively low current through Q302 and / or Q301 (e.g., I 302 = I 303 / N). The N value can be determined based on, for example, one or more of the operating frequency of the current mirror 306, the gain coefficient of the VCO 304 (e.g., K VCO ), and the gain of the voltage-current converter 305. Additionally, in some embodiments of low-voltage circuits, using a relatively high K VCO may be beneficial.

[0069] However, Figure 3 a potential problem with the illustrated embodiment is that the current multiplication provided by the N value may also increase noise (e.g., the noise sensitivity may increase). For example, in some embodiments, the transistor Q302 may be the main source of noise. Depending on the implementation details, the noise caused by Q302 in the transistor Q303 may increase by N 2 times. Therefore, increasing K VCO by increasing N can cause an unacceptable increase in phase noise and / or jitter in the output signal f out . Thus, in a practical implementation, the N value can be limited to a relatively low value.

[0070] Figure 3 Another potential problem with the illustrated embodiment is that the voltage-current conversion ratio of the input stage 305 (e.g., G m ) may depend on the resistance of R301. Yet another potential problem is that the voltage of the input signal v cont received at the gate of Q301 (e.g., the stable value of v cont when the PLL is locked) may also depend on the value of R301 as well as the threshold voltage of Q301 and / or other PVT values. The stable voltage of the input signal v cont can be particularly problematic because, as described above, this can cause the charge pump to operate at an output voltage where the positive and negative charge pump currents may be mismatched, resulting in additional spurs, jitter, phase noise, etc. in the PLL. Any one or all of these potential problems may also reduce the flexibility of the input stage 305 by restricting the values and / or other parameters that can be selected for the various components.

[0071] Figure 4 An embodiment of a phase-locked loop according to an example embodiment of the present disclosure is shown. Figure 4The illustrated embodiments may include a VCO 404, a frequency divider 412, a phase frequency detector (PFD) 413, a charge pump (CP) 414, and / or a loop filter (LF) 415.

[0072] For example, the VCO 404 may be implemented using any one of the VCOs disclosed herein. The frequency divider 412 may generate a feedback signal having a phase φ div , where the phase φ div may be related to the phase φ div of the output of the VCO 404 according to φ VCO = φ DIV / N, where the frequency divider 412 may perform an operation of dividing by N. VCO The phase frequency detector 413 may generate an UP signal and a DN signal in response to a phase difference and / or a frequency difference between the feedback signal φ DIV and a reference signal φ div . For example, the phase frequency detector 413 may generate UP and DN as pulse digital signals having a pulse width proportional to the phase error between φ ref and φ div . ref

[0073] The charge pump 414 may generate a charge pump current I cp that may be applied to the loop filter 415. The charge pump current I cp may be a positive (source) current having a specific amplitude during the pulses in the UP signal from the phase frequency detector 413 and a negative (sink) current having the same or a similar amplitude during the pulses in the DN signal from the phase frequency detector 413. The loop filter 415 may integrate or otherwise process the positive current pulses and / or the negative current pulses in the charge pump current I cp to generate a control signal v cont that may be applied as an input to the VCO 404.

[0074] Figure 5 An example embodiment of a loop filter according to an example embodiment of the present disclosure is shown. For example, Figure 5 the illustrated embodiments may be used with any one of the PLLs, VCOs, etc. disclosed herein. For example, Figure 5 the illustrated embodiments may be used to implement Figure 4 the loop filter 415 shown. The loop filter 515 may receive the charge pump current I cp at an input terminal 516 and output the control signal v cont at an output terminal 501.。In this example, the input terminal 516 can be connected to the output terminal 501 at node 517, but in other embodiments, one or more components can be connected between the input terminal 516 and the output terminal 501.

[0075] The loop filter 515 can include a first capacitor C 1 , a resistor R 1 and / or a second capacitor C 2 . The first capacitor C 1 can have a first terminal connected to a first power supply (e.g., ground or GND) and a second terminal connected to node 517 through the resistor R 1 . The second capacitor C 2 can have a first terminal connected to the first power supply (e.g., GND) and a second terminal connected to node 517. The transfer function of the loop filter 515 can be expressed in various forms. For example, the transfer function (which can be referred to as v cont / I cp (s) or Z(s)) can be expressed as follows in the complex frequency domain (e.g., s-domain) using one or more poles and / or zeros:

[0076]

[0077] where T 1 can represent a zero, T 2 can represent a pole, and the transfer function can include an additional pole at the origin (e.g., s = 0).

[0078] As another example, the transfer function can be expressed as follows using the values of R 1 , C 1 and C 2 :

[0079]

[0080] As yet another example, the transfer function can be expressed as follows using the zero frequency and the pole frequency:

[0081]

[0082] where Z dc can represent the DC impedance, ω z can represent the frequency of the zero, ω p can represent the frequency of the pole, and the additional s in the denominator can represent an additional pole at the origin (e.g., s = 0).

[0083] In some embodiments, the first capacitor C 1 can be for the charge pump current I cpIntegrate (e.g., average). However, C 1 may introduce a pole (e.g., at the origin), which may cause instability in the PLL due to a very small phase margin or no phase margin (especially in combination with the pole at the origin that may be introduced by the VCO 404). Therefore, the resistor R 1 can be in series with C 1 to introduce a zero that can increase the phase margin and / or stabilize the PLL. A second capacitor C 2 can be included to reduce spurs, sidebands, jitter, etc., for example, by filtering out voltage pulses that may appear across R cp due to positive and / or negative pulses in the charge pump current I 1 . Depending on implementation details, the second capacitor C 2 may introduce another pole, and thus, the value of C 2 can be selected to be higher than (e.g., much higher than) the loop bandwidth of the PLL to maintain the phase margin and / or the stability of the PLL.

[0084] Figure 6 FIGS. - Figure 6 illustrate embodiments of a charge pump according to example embodiments of the present disclosure. For example, Figure 6 the illustrated embodiments can be used with any of the PLLs, VCOs, etc. disclosed herein. The charge pump 614 can include a first current mirror 623 arranged to generate a positive charge pump current I BU at a value I UP determined by a first bias current source 621. The charge pump 614 can also include a second current mirror 624 arranged to generate a negative charge pump current I BD at a value I DN determined by a second bias current source 622. The values of I BU and I BD can match, and the current ratios of the current mirrors 623 and 624 can match, so that the magnitudes of I UP and I DN can match.

[0085] When the UP signal is asserted, the first switch 625 can provide the positive charge pump current I UP as the charge pump output current I CP at the output terminal 616. When the DN signal is asserted, the second switch 626 can provide the negative charge pump current I DN as the charge pump output current I CP at the output terminal 616. The UP signal and the DN signal can be provided by a PFD (such as the PFD 413 shown in Figure 4 FIG. Figure 4 ).

[0086] Figure 7An embodiment of a phase-locked loop expressed in complex frequency according to an example embodiment of the present disclosure is shown. For example, Figure 7 The illustrated embodiment may be based on Figure 4 the PLL shown, but with one or more components, signals, transfer functions, etc. transformed into the complex frequency domain (e.g., the s-domain).

[0087] Referring to Figure 7 , the PLL may include a VCO 704, a frequency divider 712, a summing node 720, a phase-frequency detector 713, a charge pump 714, and / or a loop filter 715. The VCO 704 may have a transfer function of 2πK VCO / s and may generate an output signal with a phase of Φ VCO (s). The frequency divider 712 may have a transfer function of 1 / N DIV and may generate a feedback signal with a phase of Φ VCO (s) by dividing Φ DIV (s) by N div (s). The summing node 720 may generate a phase error Φ div (s) by taking the difference between the phase Φ ref (s) of the feedback signal and the phase Φ e (s) of the reference signal, and the reference signal may be provided, for example, by a crystal oscillator or any other reference frequency source. The phase-frequency detector 713, the charge pump 714, and the loop filter 715 may have transfer functions of 1 / 2π, I cp , and Z(s), respectively.

[0088] Using Figure 7 the transfer functions shown, the loop gain T(s) of the PLL can be expressed as follows:

[0089]

[0090] Substituting for Z(s) in Equation 7c, the loop gain T(s) can be rewritten as follows:

[0091]

[0092] Figure 8 An example embodiment of the frequency response characteristics of a phase-locked loop and its components according to an example embodiment of the present disclosure is shown. For illustrative purposes, Figure 8 the illustrated embodiment may be described in the context of the PLL shown in Figure 7 , where the loop filter 715 may be implemented using a loop filter similar to the loop filter shown in Figure 5 , and the VCO 704 may be implemented using a VCO similar to the VCO shown in Figure 3The VCO 300 shown is implemented with a similar VCO, but other loop filters, VCOs, and / or other components may also be used.

[0093] Reference Figure 8 , the graph 800A will Figure 3 show the transconductance G of the input stage 305 and / or the current mirror 306 shown m as a function of frequency. Depending on the implementation details, G m may be characterized as the low-frequency or DC gain. Both the vertical (G m ) axis and the horizontal (frequency) axis are shown on a logarithmic scale (e.g., a log-log graph). Depending on the implementation details, the magnitude of G m may be substantially constant within the Figure 8 shown frequency range.

[0094] The graph 800B also shows on a log-log scale the magnitude of G combined with the frequency response of the gain coefficient K Figure 3 of the current-controlled oscillator 307 shown ICO as a function of frequency. Thus, the graph 800B can be characterized as m a graph of the magnitude of the gain coefficient K Figure 3 of the VCO 300 shown. The VCO 300 (and / or VCO the VCO 704 in Figure 7 ) can integrate the control voltage v cont , and thus can contribute a pole of the form 1 / s to the frequency response of the VCO 300 and the loop gain T(s) in Equation 8 and / or Equation 9. Depending on the implementation details, this pole can give a slope of -20 decibels per decade (dB / dec) to the magnitude of G m ·K ICO / s, as shown in the graph 800B.

[0095] The graph 800C shows the magnitude (on a log-log scale) of the loop gain T(s) of the PLL using Equation 9, where the zero frequency ω Figure 7 and the pole frequency ω z (expressed in radians per second (rad / s) in Equation 9) can be related to the zero frequency f p and the pole frequency f z (expressed in Hz in p ) according to the expression ω = 2πf. The magnitude of T(s) can be represented as |T(s)| in Figure 8 . Figure 8

[0096] Depending on implementation details, the poles can impart a slope of -20 dB / dec, while the zeros can impart a slope of +20 dB / dec. Thus, due to the two poles at the origin in Equation 9 (one pole (1 / s) from the loop filter 715 and one pole (1 / s) from the VCO 704), the initial slope of the magnitude of T(s) can be -40 dB / dec at f = 0. In some embodiments, the two poles at the origin may cause instability in the PLL. However, the zero at f z (corresponding to ω z in Equation 9) can increase the slope by +20 dB / dec, and thus, between the zero frequency f z and the pole frequency f p , the magnitude of T(s) can be -20 dB / dec, where the second pole contributed by the loop filter 715 can decrease the slope back by -20 dB / dec. Therefore, the magnitude of T(s) can be -40 dB / dec at frequencies above f p .

[0097] The crossover frequency f c (which can also be referred to as the loop bandwidth) can be the frequency at which the magnitude of T(s) can be 1 (0 on a logarithmic scale). In some embodiments, and depending on implementation details, when the loop bandwidth frequency falls between the zero frequency and the pole frequency (e.g., far enough from the zero to ensure sufficient phase margin, as shown below), the PLL may generally be stable.

[0098] Graph 800D shows the phase of T(s) of the PLL shown as a function of frequency on a double-logarithmic scale. The phase of T(s) can be represented as Arg or ∠T(s) in Figure 7 . Due to the two poles at the origin, the initial phase of T(s) can be -180 degrees at f = 0. However, the zero at f Figure 8 can start increasing the phase (e.g., at a rate of +45 deg / dec) at about 10 decades before f z . The phase of T(s) can continue to increase towards -90 degrees (but not necessarily reach -90 degrees) until the third pole at f z can start decreasing the phase back (e.g., at a rate of -45 deg / dec) at about 10 decades before f p . The difference between the phase of T(s) at the loop bandwidth f p and -180 degrees can be referred to as the phase margin. In some embodiments, and depending on implementation details, if the phase margin is greater than a certain value, the operation of the PLL may be stable. Thus, the phase ∠T(s) may be at the loop bandwidth f c c ​Nearby (e.g., a certain amount greater than -180 degrees) includes regions where the phase margin may be sufficient to ensure stable operation of the PLL.

[0099] Figure 9 An embodiment of a voltage controlled oscillator and a calibration scheme according to an example embodiment of the present disclosure is shown. Figure 9 The illustrated VCO 904 may include an input stage 905, a current mirror 906, and a current controlled oscillator 907 that may be implemented using components similar to those in Figure 3 the illustrated VCO 304, where similar elements may be indicated by reference numerals that end with the same numbers, letters, etc. and / or include the same numbers, letters, etc.

[0100] Figure 9 The illustrated VCO 904 may further include a calibration current mirror 908 that may generate a calibration current I 905 , the calibration current I 905 that may be added to the current I 903 from the current mirror 906 to generate a combined current I 907 to drive the current controlled oscillator 907. The calibration current mirror 908 may include a first transistor Q904 having a source connected to a supply voltage (e.g., V DD ), a drain connected to receive a bias current I B3 from a current source 909, and a gate connected back to the source in a diode-connected arrangement. The calibration current mirror 908 may further include a second transistor (or transistors) Q905 having a source connected to the supply voltage, a drain connected to generate the calibration current I 905 , and a gate connected to the gate of Q904.

[0101] The transistor Q905 may be arranged to generate the calibration current I 905 as a multiple of the bias current I B3 . The ratio of the calibration current I 905 to the bias current I B3 may be determined by a select code (indicated as sel <n:1>) is determined by the value of, and the select code can have n possible values. For example, in some embodiments, transistor Q905 can be implemented using n parallel transistors, and the outputs of these n parallel transistors are controlled by n switches. The decoder can control the switches based on the value of the select code such that the select code can determine how many of the outputs of the n transistors are connected in parallel and thus contribute to the calibration current I 905 .

[0102] Figure 9 The illustrated embodiment may also include a calibration input circuit 930, which includes transistor Q906, resistor R902, bias current source 910, an operational amplifier (which may also be referred to as an op-amp, opamp, or op amp) 929, and / or switches 927 and 928.

[0103] Figure 9 The illustrated embodiment may also include a loop filter 915, which may be implemented using an embodiment similar to that of Figure 5 the illustrated loop filter 515. A part of the charge pump 914 similar to the embodiment of Figure 6 the illustrated embodiment is also included in Figure 9 to assist in understanding the operation and / or calibration scheme of the VCO 904.

[0104] Figure 10 Illustrated are an example embodiment of the frequency-voltage characteristic of a voltage-controlled oscillator and an example embodiment of the output voltage-current characteristic of a charge pump according to an example embodiment of the present disclosure. For example,[[]] Figure 10 the illustrated graph may show Figure 9 the frequency-voltage characteristic of the voltage-controlled oscillator 904 and the output voltage-current characteristic of the charge pump 914 shown in

[0105] Referring to Figure 9 and / or Figure 10 , an example embodiment of the calibration operation of the VCO 904 may be as follows. During the calibration operation, the calibration enable signal (indicated as cal_en) can be asserted to open switch 927, which can cause the input stage (e.g., voltage-current converter) 905 to be isolated from the loop filter 915, thereby opening the loop of the PLL of the embodiment shown in Figure 9 . Asserting the calibration enable signal can also close switch 928, thereby connecting the output of the op-amp 929 to the gates of Q901 and Q906 at node 931. The op-amp 929 can use voltages V a and V b A balanced voltage drives the gates of Q901 and Q906. This can cause Q901 and Q906 to operate in a manner similar to a current mirror. Thus, current I 902 can be driven to a value equal to the bias current I B2 (assuming the geometries of Q901 and Q906 and / or the values of R901 and R902 are the same) or a multiple of I B2 if the geometries of Q901 and Q906 and / or the values of R901 and R902 are scaled).

[0106] The current I 902 established by op-amp 929 in Q901 can also flow through Q902 in current mirror 906, where the current I 902 can be mirrored in Q903 to generate I 903 with a scaling factor determined by the current mirror ratio 1:N. The select code sel <n:1>to adjust the calibration current I 905 until the combined current I 907 applied to the current controlled oscillator 907 is adjusted such that when the voltage of the input signal (e.g., v cont ) at node 931 is equal to or close to a calibration value (such as the midpoint of the supply voltage V DD (e.g., V mid ≈V DD / 2)), the output frequency f out is equal to or close to the target value f target , as shown by the graph 1000A in Figure 10 . For example, the value V mid can be selected because when the output of the charge pump 914 operates at or near the midpoint V DD of the supply voltage V mid , the positive charge pump current I UP and the negative charge pump current I DN can match, as explained in more detail below with respect to Figure 10 in the graph 1000B.

[0107] During calibration, in some embodiments, the voltage at node 931 may not be directly controlled. However, the value of I B2 and / or R902 can be selected to maintain the voltage at node 931 at or near a specific value. For example, the current I B2 flowing through Q906 and R902 can establish a voltage across R902 in combination with the threshold voltage between the gate and source of Q906, which can maintain node 931 at a voltage equal to or close to a specific value (such as V mid ), while changing the select code sel <n:1>To adjust the calibration current I 905 .

[0108] Reference Figure 10 In the curve graph 1000A in, the curves labeled 7, 8, and / or 9 (which can be straight lines in this example) show when the VCO 904 is operating at a specific combination of PVT values for sel <n:1>These three values of the input signal v cont Output frequency f of the VCO 904 as a function of out . The slope of the curve can be determined by the gain coefficient K of the VCO 904 VCo . For illustrative purposes Figure 9 and Figure 10 The embodiments shown can be described in the context of calibrating the current mirror 908. The range of the selection code for calibrating the current mirror 908 can be from 1 to 16, but any number and / or configuration of selection codes can also be used.

[0109] As shown in the graph 1000A, the curve corresponding to the selection code 8 can intersect the target frequency at or near a certain point, where the voltage of the input signal v cont is V at a specific combination of PVT values at which the VCO 904 can be calibrated mid . However, at one or more different PVT values, the curves corresponding to different selection codes can intersect the target frequency at or near V mid . For example, if the VCO 904 is calibrated at a lower temperature, the curve corresponding to the selection code 7 can intersect the target frequency at or near V mid . As another example, if the VCO 904 is calibrated at a higher temperature, the curve corresponding to the selection code 9 can intersect the target frequency at or near V mid .

[0110] Figure 10 The graph 1000B in shows the positive charge pump current I UP and the negative charge pump current I DN respectively as functions of the voltage at the output node 916 of the charge pump 914. The value I shown by the dashed line cpNOM can represent the nominal (e.g., ideal) current value of I UP and / or I DN . The values of I UP and I DN may be equal at or near the midpoint V mid , but may become mismatched by a certain increase as the voltage at the output node 916 of the charge pump 914 moves away from V mid . Therefore, depending on the implementation details, when the voltage at the output node 916 of the charge pump 914 remains close to V mid , the spurs, jitter, phase noise, etc. caused by the mismatch between the positive charge pump current I UP and the negative charge pump current I DN may be reduced or minimized.

[0111] In determining the selection code sel <n:1>After that, the assertion of the calibration enable signal cal_en can be cancelled. Cancelling the assertion of cal_en can turn off switch 928, thereby decoupling the current I 905 from the bias current I B2 and enabling the input stage 905 to perform a voltage-current conversion based on the voltage at node 931. Cancelling the assertion of cal_en can also close switch 927 that can connect node 931 to the input terminal 901, thereby applying the input signal v cont to node 931 and closing the feedback control loop of the PLL. The VCO 904 can then operate using the calibration current I 905 determined by the selection code selected during calibration. For example, in some embodiments, as the current I 905 varies based on the input signal v cont , the calibration current I 905 can remain constant.

[0112] In some embodiments, and depending on the implementation details, one or more operating characteristics of the VCO 904 may drift based on changes in one or more PVT values. For example, for a constant value of I 907 , the output frequency f out of the current controlled oscillator 907 can increase as the temperature decreases. Thus, if the VCO 904 initially operates at the calibrated frequency of the VCO 904, the output frequency f out can initially be locked at the target frequency f cont when the value of v mid stabilizes at or near V target . As the temperature of the PLL decreases, the feedback loop of the PLL can cause the value of v cont to decrease, thereby causing the frequency f out to remain locked at f target . Thus, when the VCO operates at a temperature lower than the calibrated VCO, the value of v cont can stabilize at a value lower than the value of V mid .

[0113] Figure 11 Illustrates an example embodiment of the frequency-voltage characteristics of a voltage controlled oscillator and the current-voltage characteristics of a charge pump at a reduced operating temperature according to an example embodiment of the present disclosure. For example, Figure 11 the graph shown can illustrate Figure 9 the frequency-voltage characteristics of the voltage controlled oscillator 904 and the output voltage-current characteristics of the charge pump 914 shown.

[0114] Referring Figure 11 , the lower curve in graph 1100A shows when at a similar to Figure 10 Calibrate the temperature T of the VCO 904 using a selection code (e.g., 8) in the manner of the curve 1000A in cal The frequency - voltage characteristic of the VCO 904 during the following operation. The upper curve in the graph 1100A shows that when using the same selection code (e.g., 8) as that used for calibrating the VCO 904 while operating at a lower temperature (T cal -ΔT) than when calibrating the VCO 904, the frequency - voltage characteristic of the VCO 904. The temperature change -ΔT can cause the frequency - voltage curve to drift upward, resulting in a frequency error. To eliminate the frequency error and maintain f out locked to the reference frequency, the PLL can reduce the input signal v cont by a certain amount -Δv cont . Thus, v cont can be stabilized to a new value V cold = V mid -ΔV cont .

[0115] Reference Figure 11 to the graph 1100B in cold = V mid -ΔV cont operating the input signal v cont at can cause the charge pump 914 to have a positive charge pump current I UP and a negative charge pump current I DN that may be mismatched (e.g., by a certain amount ΔI c ) at the output voltage V mid -ΔV cont . Depending on the implementation details, the mismatched charge pump currents may cause spurs, jitter, phase noise, etc. in the PLL 904.

[0116] Figure 12 illustrates an example embodiment of the frequency - voltage characteristic of a voltage - controlled oscillator and the current - voltage characteristic of a charge pump at an elevated operating temperature according to an example embodiment of the present disclosure. In some aspects, Figure 12 the illustrated embodiment may be similar to Figure 11 the illustrated embodiment, except that Figure 12 the curves in cal show the curves of the PLL 904 that can be operated at a higher temperature (T

[0117] +ΔT) than when calibrating the PLL 904 while using the same selection code (e.g., 8) as that used for calibrating the PLL 904. cal The lower curve in the graph 1200A shows that when at T cal Frequency-voltage characteristic of VCO 904 when operating at +ΔT. A temperature change of +ΔT can cause the frequency-voltage curve to shift downward, causing the PLL to increase the input signal v cont to stabilize to a new value V hot = V mid +ΔV cont . Referring to the reference graph 1200B, this can cause the charge pump 914 to have a positive charge pump current I UP and a negative charge pump current I DN that may be mismatched (e.g., by an amount ΔI h ) at the output voltage V mid +ΔV cont .

[0118] When the input signal v cont is stabilized at a value far from V mid , a possible way to reduce the mismatch between the positive charge pump current I UP and the negative charge pump current I DN is to improve the current matching between I DD and I UP over a larger portion of the voltage range between zero and V DN (e.g., flatten the curves of I UP and I DN so that they are closer to the nominal value of I cpNOM ). For example, the output dynamic range of the charge pump can be increased by using a low-voltage cascode arrangement to increase the impedance. As another example, a differential structure and / or unity-gain buffer can be used to implement charge sharing and / or distribution in the charge pump. However, depending on the implementation details, these methods may increase the cost, complexity, design effort, etc. of the charge pump and may still not provide sufficient current matching.

[0119] Figure 13 Shows an embodiment of an oscillator with a modified gain coefficient according to an example embodiment of the present disclosure. Figure 13 The oscillator 1342 shown may include an input stage 1305, a current-controlled oscillator 1307, and a calibration input circuit 1330 that can be implemented using components similar to those in the Figure 9 shown embodiment, where similar elements may be indicated by reference numerals ending with the same numbers, letters, etc. and / or containing the same numbers, letters, etc.

[0120] However, in the Figure 13 shown oscillator 1342, the gain coefficient K Vco It can be increased, for example, by arranging one or more transistors Q1308 (which can be used for calibration based on the selection code sel<n:1>) to have a current mirror with Q1302. For example, transistor Q1308 can have a source connected to a first power supply voltage (e.g., V DD ) and a gate connected to the gate of Q1302. Thus, the drain of Q1308 can provide a calibration current I 1302 that can be controlled by I 1308 , and I 1302 can in turn be controlled by an input signal v cont received at input terminal 1301. Therefore, the current path of I 1303 through Q1303 and the current path of I 1308 through Q1308 can both be controlled by the input signal v cont . Currents I 1303 and I 1308 can be combined (e.g., summed at node 1334) to generate a current I 1309 that can be used to drive current-controlled oscillator 1307. This may increase the gain coefficient K VCO of oscillator 1342 (which can cause the slope K Figure 12 shown in graph 1200A in VCO to increase). However, increasing K VCO may involve changing one or more parameters of the VCO and / or PLL, as explained in more detail below. Although Q1308 can be shown as being configured to provide current I 1308 as a calibration current based on the selection signal sel<n:1>, in other embodiments, transistor Q1308 can also be implemented without a calibration function.

[0121] Figure 14 shows an example embodiment of the frequency response characteristics of a phase-locked loop with a modified gain coefficient and its components according to an example embodiment of the present disclosure. For example, Figure 14 the embodiment shown can show one or more effects of the varying K Figure 13 in oscillator 1342 shown in Vco .

[0122] Referring to Figure 14 , the lower curve in graph 1400C (identified as K VCO1 ) shows the magnitude of the loop gain T(s) of the PLL without a modified K Figure 8 such as that shown in graph 800C in VCO . The upper curve in graph 1400C (identified as K VCO2 ) shows the case where K VCO has been, for example, used Figure 13 The technique shown increases ΔK VCO the magnitude of the loop gain T(s) of the PLL of VCO . As shown in graph 1400C, increasing K VCO can cause T(s) to shift upward by an amount ΔK VCO . Although increasing K VCO can enable the VCO and / or PLL to operate over a relatively wide frequency range, the upward shift in the magnitude of T(s) can also cause the loop bandwidth to shift to a higher frequency, thereby reducing or eliminating the phase margin as shown by curve 1400D in Figure 14 (e.g., compared to the phase margin shown by curve 800D in Figure 8 ). Depending on implementation details, reducing the phase margin can cause the PLL to become unstable.

[0123] To maintain the stability of the PLL in which the gain coefficient K VCO has been increased, one or more parameters of the PLL and / or VCO can be adjusted to maintain the loop gain at a relatively constant value. For example, referring to Equation 8 and / or Equation 9, the I cp value can be decreased to compensate for the increase in K VCO . For example, the charge pump current I cp can be decreased by decreasing the values of I UP and I DN (e.g., by reducing the geometry and / or number of mirror transistors in current mirrors 623 and / or 624 as shown in Figure 6 ). However, decreasing I cp may increase the noise of the charge pump. Alternatively or additionally, the loop gain can be adjusted by increasing the value of one or more capacitors in loop filter 915. However, this may increase the area occupied by one or more capacitors.

[0124] Figure 15 illustrates an embodiment of an oscillator having one or more frequency characteristics according to an example embodiment of the present disclosure. Figure 15 The oscillator 1542 shown can include a signal generator 1535 and / or a variable frequency oscillator (VFO) 1536. The variable frequency oscillator 1536 can generate a frequency f based on a first signal 1544 out Output signal 1502. The signal generator 1535 may generate a first signal 1544 based on a second signal 1546, and the second signal 1546 may be referred to as a control signal CTRL. The signal generator 1535 may include a first path (e.g., a first signal path) 1540 that may generate a first portion 1544a of the first signal 1544 based on the second signal 1546. The signal generator 1535 may further include a second path (e.g., a second signal path) 1541 that may generate a second portion 1544b of the first signal 1544 based on the second signal 1546.

[0125] In some embodiments, the first portion 1544a and the second portion 1544b may be at least partially combined into a signal 1544, and the signal 1544 may be applied to a variable frequency oscillator 1536. For example, the first portion 1544a and the second portion 1544b may be combined using a combining circuit. In embodiments where the signal 1544 may be implemented as a current, the combining circuit may be implemented, for example, using a summing node that may sum the first portion 1544a (e.g., the first portion of the current) and the second portion 1544b (e.g., the second portion of the current). Alternatively or additionally, the first portion 1544a and the second portion 1544b may be separately (at least partially) applied to the variable frequency oscillator 1536.

[0126] The first path 1540 may have a first frequency characteristic typically indicated by a first transfer function H 1 and the second path 1541 may have a second frequency characteristic typically indicated by a second transfer function H 2 The first portion 1544a of the first signal 1544 may have a first frequency characteristic (e.g., relative to the second signal 1546), and the second portion 1544b of the first signal 1544 may have a second frequency characteristic (e.g., relative to the second signal 1546). For illustrative purposes, some embodiments may be described in the context of continuous structures and / or signals, where one or more of the transfer functions H 1 and / or H 2 may be at least partially expressed as a function of a complex frequency s, e.g., H 1 (s) and / or H 2 (s). However, other embodiments may be implemented at least partially using discrete structures and / or signals, in which case one or more of the transfer functions H 1 and / or H 2 may be at least partially expressed as a function of discrete values, e.g., H 1 (z) and / or H 2 (z).

[0127] Although Figure 15 The first path 1540 and the second path 1541 shown are not limited to any specific form, but in some example embodiments, they can be implemented using, for example, current mirror transistors. For example, in some embodiments, the first path 1540 can be implemented using a first current mirror transistor that can generate a first portion 1544a of the first signal 1544 based on the second signal 1546, and the second path 1541 can be implemented using a second current mirror transistor that can generate a second portion 1544b of the first signal 1544 based on the second signal 1546.

[0128] Although the transfer function H 1 and / or H 2 is not limited to any specific form, but in some example embodiments, the transfer function H 1 can be implemented using a through function (e.g., H 1 (s)=1), and the transfer function H 2 can be implemented using a low-pass function (e.g., H 2 (s)=1 / (1 + RCs)), where R and C can represent the resistance and capacitance of the low-pass RC filter, respectively.

[0129] Depending on the implementation details, Figure 15 the oscillator 1542 shown can achieve frequency response shaping of the oscillator 1542 and / or another system (e.g., PLL) in which the oscillator 1542 can be used. For example, in some embodiments, the first path 1540 can generate a first portion 1544a of the signal 1544 having relatively high-frequency characteristics (which can also be referred to as AC characteristics), and the second path 1541 can generate a second portion 1544b of the signal 1544 having relatively low-frequency characteristics (which can also be referred to as DC characteristics). Depending on the implementation details, this can enable the oscillator 1542 and / or another system in which the oscillator 1542 can be used to provide improved performance, efficiency, flexibility, cost, calibration, stability, etc. For example, in some embodiments, using signal paths with different frequency characteristics can increase the gain coefficient of the oscillator 1542 with little or no change to other components, loop coefficients, etc.

[0130] Although Figure 15 the oscillator 1542 shown is not limited to any specific application, but in one example application, the oscillator 1542 can be used in a PLL in which the control signal CTRL can be driven directly or indirectly by an input signal (such as v cont ).

[0131] Figure 16 Shows an example embodiment of an oscillator having one or more frequency characteristics according to an example embodiment of the present disclosure. Figure 16 The illustrated oscillator 1642 can provide an example of how Figure 15 the illustrated oscillator 1542 can be implemented. For example, Figure 15 the illustrated signal generator 1535 and / or variable frequency oscillator 1536 can be implemented using, respectively, Figure 16 the illustrated current generator 1635 and / or current controlled oscillator 1636.

[0132] The current generator 1635 can include a first current path 1640 that can have a transfer function H 1 (s) and can generate a first portion I 1644 of current I 164 based on a first control signal CTRL1. The current generator 1635 can also include a second current path 1641 that can have a transfer function H 2 (s) and can generate a second portion I 1644 of current I 1644b based on the first control signal CTRL1. The first portion I 1644a and the second portion I 1644b can be combined by a combinational circuit (e.g., a summing node) 1649 to generate current I 1644 , and current I 1644 can be applied to the current controlled oscillator 1636 to control the frequency f out of the output signal 1602.

[0133] The current generator 1635 can include a signal converter 1647 that can generate a first control signal CTRL1 (which can be referred to as an intermediate signal) at node 1645 based on a second control signal CTRL2. For example, the signal converter 1647 can be implemented as a third current path that can convert the second control signal CTRL2 from current I 1646 to voltage at node 1645.

[0134] Although Figure 16 the illustrated current generator 1635 and / or current paths 1640 and / or 1641 are not limited to any particular form, in some embodiments they can be implemented using current mirrors that can achieve frequency response shaping of the oscillator 1642 and / or another system (e.g., a PLL) in which the oscillator 1642 can be used.

[0135] Figure 17 Shows an example embodiment of a voltage controlled oscillator having one or more frequency characteristics according to an example embodiment of the present disclosure. For example, Figure 17 The VCO 1742 shown can be used to implement Figure 16 the oscillator 1642 shown.

[0136] Referring Figure 17 , the VCO 1742 can include an input stage 1705, a current-controlled oscillator 1707, and a calibration input circuit 1730 that can be implemented using components similar to those in the Figure 9 and / or Figure 13 embodiments shown, where similar elements can be indicated by reference numerals that end with the same numbers, letters, etc. and / or contain the same numbers, letters, etc.

[0137] The VCO 1742 can also include a current mirror 1735, which in some aspects can be similar to Figure 13 the current mirror 1343 shown. However, Figure 17 the current mirror 1735 shown can also include a filter (e.g., a low pass filter (LPF)) 1748 having a first terminal 1758 (at node 1745) connected to the gates of Q1702 and Q1703 and a second terminal 1759 connected to the gate of Q1708. Depending on the implementation details, the LPF 1748 can cause the current I 1708 generated by Q1708 to have 1703 a different frequency characteristic from the current I 1703 generated by Q1703. Thus, the transistor Q1703 can form a first current path 1740 that can generate I 1709 as the AC or relatively high-frequency portion of the current I 1708 based on the voltage at node 1745. The low pass filter 1748 and the transistor Q1708 can form a second current path 1741 that can generate I 1709 as the DC or relatively low-frequency portion of the current I 1703 . The currents I 1708 and I out can be combined at a summing node 1734 to generate a current I 1709 that can control the output frequency f 1702 of the current-controlled oscillator 1707. The transistor Q1702 can act as a signal converter 1747 to convert the current I

[0138] Frequency response shaping of oscillator 1742 and / or another system (e.g., PLL) in which oscillator 1742 can be used can be achieved using current paths with different frequency characteristics. For example, the gain factor K of VCO 1742 VCO of the DC or low-frequency portion can be increased because current I 1708 (which can vary based on input signal v cont ) can be added to the total current I out used to control the output frequency f 1709 . However, using low-pass filter 1748 having poles and / or zeros at one or more frequencies below the loop bandwidth frequency f c may reduce or effectively eliminate the contribution of I 1708 at higher frequencies. Depending on implementation details, this can cause the frequency response of oscillator 1742 at higher frequencies to be the same as or similar to the frequency response of the VCO shown in Figure 9 . Thus, the frequency response at higher frequencies may vary little or not at all, and the values of one or more of the charge pump current I CP , resistors, and / or capacitors in the loop filter can remain unchanged while maintaining the same or similar loop bandwidth and / or PLL stability.

[0139] Although Figure 17 Q1708 in

[0140] is shown as being implemented using one or more transistors that can be adjusted based on a selection code sel<n:1> for calibration purposes, in other embodiments, any other arrangement of Q1708 (e.g., fixed geometry and / or device count) can also be used. cont In some embodiments, the control voltage v out can be kept relatively constant to, for example, provide a relatively fixed output frequency f cont and / or phase. In some embodiments, the control voltage v out (e.g., using a feedback scheme) can be varied to provide a variable output frequency f cont and / or phase. For example, in embodiments in which VCO 1742 can be used to implement a frequency modulation (FM) scheme, the control voltage v out can be controlled (e.g., modulated by a feedback circuit) to adjust the output frequency f cont and / or phase. Thus, some embodiments can control the frequency and / or phase of the control voltage v

[0141] Figure 18 illustrates an example embodiment of the frequency response characteristics of a voltage controlled oscillator having a low pass filter and a phase locked loop as shown in Figure 17 . In these example embodiments, both the poles and zeros of the low pass filter 1748 can be below (e.g., far below) the loop bandwidth f c .

[0142] Graph 1800A shows Figure 17 a curve shown as a solid line of the magnitude of the transconductance G of the input stage 1705 and / or the current mirror 1735 as shown in m . The low pass filter 1748 can be implemented to have a pole at the frequency f pLPF and a zero at the frequency f zLPF . For comparison, the corresponding curve from Figure 8 Graph 800A in

[0143] is shown as a dashed line. Between the frequencies f = 0 and f PLPF , the contribution from I in the DC or low frequency path 1741 1708 can cause the DC or low frequency G m to increase by a certain amount ΔDCK VCO . At f PLPF , the pole of the low pass filter 1748 can cause the contribution from I 1708 to gradually decrease. Thus, the magnitude of G m can decrease, for example, with a slope of -20 dB / dec. At f ZLPF , the zero of the low pass filter 1748 can change the slope by +20 dB / dec. Thus, G m may flatten at a value that may be the same or similar to the value that would remove the DC or low frequency current path 1741.

[0144] Graph 1800B shows a curve shown as a solid line of the magnitude of G combined with the magnitude of the frequency response of the gain coefficient K of the current controlled oscillator 1707 as shown in Figure 7 . For comparison, the corresponding curve from ICO Graph 800B in m is shown as a dashed line. Figure 8 The current controlled oscillator 1707 can integrate the control signal and thus can contribute a pole at the origin and a slope of -20 dB / dec. Thus, the initial slope of the curve between f = 0 and f

[0145] is -20 dB / dec, the slope between f PLPF and f PLPF is -40 dB / dec, and the slope is -40 dB / dec above f ZLPF and above f ZLPF The slope at the frequency of is -20 dB / dec. The curve shown by the dashed line can show how the curve of G will be when the DC or low-frequency current path 1741 is removed. m will be.

[0146] Graph 1800C shows a curve shown by the solid line of the magnitude of the loop gain T(s) of a PLL that can include the VCO 1742 shown. For comparison, the corresponding curve from Graph 800C in Figure 17 is shown by the dashed line. Figure 8 is shown using a dashed line.

[0147] At frequencies between f = 0 and f PLPF the contribution from I in the DC or low-frequency path 1741 can cause the DC or low-frequency G 1708 to increase by a certain amount ΔDCK m . Due to two poles at the origin (one from the current-controlled oscillator 1707 and the other from the capacitor C in the loop filter VCO ), the initial slope of the curve can be -40 dB / dec. At f 1 the pole of the low-pass filter 1748 can lower the slope to -60 dB / dec. At f PLPF the zero of the low-pass filter 1748 can raise the slope to -40 dB / dec. ZLPF At f

[0148] At f z (corresponding to ω in Equation 9 z ) the zero contributed by the R in the loop filter can raise the slope (+20 dB / dec) to -20 dB / dec, and at f 1 the second pole contributed by the capacitor C in the loop filter can lower the slope back to -40 dB / dec. The crossover frequency f p (loop bandwidth) can fall between f p and f 2 in a manner similar to the curve shown in Graph 800C in c . Figure 8 between f z and f p .

[0149] Graph 1800D shows a curve shown by the solid line of the phase of the PLL frequency response that can include the VCO 1742 shown. Figure 17

[0150] Due to two poles at the origin, the initial phase can be -180 degrees at f = 0. The pole of the low-pass filter 1748 may cause a phase that can cause the phase to be at the pole frequency f pLPF A phase shift reduced below -180 degrees in the vicinity. The zero of the low-pass filter 1748 may cause a phase shift that can cause the phase to return to -180 degrees in the vicinity of the zero frequency f zLPF The phase shift of the frequency response can be the same as or similar to that of the embodiment shown in the graph 800D in Figure 8 at higher frequencies. Thus, the poles and / or zeros of the low-pass filter 1748 in the DC or low-frequency current path 1741 have little or no effect on the phase margin and / or stability of the PLL, as shown in the graph 1800D.

[0151] Therefore, Figure 17 The addition of the DC or low-frequency current path 1741 shown in ZLPF can provide increased DC or low-frequency K VCO and / or loop gain at frequencies below approximately f

[0152] Figure 19 while causing little or no change to the loop dynamics at higher frequencies. Depending on the implementation details, this can enable the PLL including the VCO 1742 to operate over a relatively wide frequency range while maintaining the loop PLL loop dynamics (e.g., stability). Figure 17 The frequency-voltage characteristics of a voltage-controlled oscillator shown at a reduced operating temperature according to an example embodiment of the present disclosure and an example embodiment of the current-voltage characteristics of a charge pump that can be used with the Figure 17 shown voltage-controlled oscillator.

[0153] For comparison purposes, Figure 19 The graph 1900A in Figure 11 basically shows a reproduction of the graph 1100A in Figure 9 where the gain coefficient is indicated as K VCO1 that can be determined by the gain coefficient of the VCO 904 shown in

[0154] The lower curve shown in the graph 1900X shows the frequency-voltage characteristics of the VCO 1742 when operating at the temperature T Figure 17 shown while calibrating with a selection code (e.g., 8). The upper curve in the graph 1900X shows the frequency-voltage characteristics of the VCO 1742 when operating at a temperature lower than the calibration of the VCO 1742 (T cal -ΔT) while using the same selection code (e.g., 8) used to calibrate the VCO 1742. The slope of the curve in the graph 1900X is indicated as K cal and can be the DC K of the VCO 1742 VCO2 VCO ​To determine, this can include the contribution from I in the DC or low-frequency path 1741 1708 of.

[0155] Because K VCO2 may be greater than K VCO1 (e.g., due to the large DC K of VCO 1742 VCO ), so for K VCO2 when the PLL is locked, the stable value of v cont may be closer to V VCO than for K mid , therefore, the mismatch between the positive charge pump current I shown in the graph 1900B UP and the negative charge pump current I DN may be lower. For example, as shown in the graph 1800B, the current mismatch between I UP and I DN can be ΔI VCO1 for K 1 and ΔI VCO2 for K 2 . Therefore, depending on the implementation details, Figure 17 the addition of the DC or low-frequency current path 1741 shown can reduce the mismatch of the charge pump, which in turn can reduce spurs, jitter, phase noise, etc. in the PLL. The DC or low-frequency current path 1741 may cause a similar reduction in the charge pump current when the VCO 1742 operates at a temperature (T cal +ΔT) higher than the calibrated VCO 1742.

[0156] Figure 20 shows an embodiment of an oscillator with an input stage according to an example embodiment of the present disclosure. Figure 20 The oscillator 2062 shown can include an input stage 2064 and / or a variable frequency oscillator 2036. The variable frequency oscillator 2036 can generate an output signal 2002 having a frequency f out based on a control signal (CTRL) 2065. The input stage 2064 can be configured to generate the control signal 2065 based on a comparison of an input signal 2066 and a reference signal 2067. For example, the input stage 2064 can be implemented using a differential circuit that can generate the control signal 2065 based on the difference between the input signal 2066 and the reference signal 2067.

[0157] Depending on the implementation details, using the input stage 2064 that can operate based on the comparison of two signals can enable the input signal 2066 to be maintained at a voltage that may be beneficial to the previous stage. For example, if used in a PLL Figure 20 For the oscillator 2062 shown, the input stage 2064 can operate to maintain the voltage of the input signal 2066 at a voltage (e.g., the midpoint of the power supply) at which a charge pump that drives the input signal 2066 can generate relatively matched positive and negative output currents.

[0158] Figure 21 An example embodiment of a voltage controlled oscillator having an input stage in accordance with an example embodiment of the present disclosure is shown. Figure 21 The VCO 2142 shown can include an input stage 2164 having differential inputs arranged in a certain configuration, which depending on implementation details, can be characterized as pseudo-differential. The VCO 2142 can also include a current mirror 2168 having a first current path and a second current path, the first and second current paths having first and second frequency responses, respectively. Additionally, depending on implementation details, the input stage 2164 and the current mirror 2168 can be integrated in a manner that can produce a synergistic result.

[0159] The input stage 2164 can include a first input transistor Q2110 having a gate connected to receive an input signal v at node 2101, a source connected to a first power supply (e.g., ground or GND) through a first bias current generator 2175 that can generate a first bias current I cont , and a drain connected to node 2173. The input stage 2164 can also include a second input transistor Q2111 having a gate connected to receive an input signal v at node 2172, a source connected to a first power supply (e.g., ground or GND) through a second bias current generator 2176 that can generate a second bias current I 2110 , and a drain connected to node 2174. A degeneration resistor R2103 can be connected between the sources of Q2110 and Q2111. ref 2111 m cont

[0160] In some embodiments, and depending on implementation details, the transistors Q2110 and Q2111 can be characterized as a differential pair of input transistors (e.g., differential G m pair) that can receive differential input signals at node 2101 (e.g., positive input) and node 2172 (e.g., negative input) and provide differential outputs at nodes 2173 and 2174. Depending on implementation details, the input stage 2164 can be characterized as pseudo-differential because the positive input signal v cont can be used as a single-ended signal while the negative input can be connected to a stable reference signal v ref . Thus, during operation (e.g., in a PLL where the VCO 2142 can be used), the input signal v cont The value can vary as the PLL control loop acquires and / or maintains a locked condition, while the reference signal v ref can be maintained at a constant voltage.

[0161] However, although the input signal v cont may vary, the transconductance (e.g., gain) of Q2110 and Q2111 can also cause v cont to vary by a relatively small amount from v ref . For example, if the transconductance of Q2110 and Q2111 is set to a relatively high value, this can also cause the DC or relatively low-frequency gain factor of VCO 2142 to be relatively high. Thus, with v ref maintained at a stable voltage (such as the midpoint of the power supply voltage V DD (e.g., V mid = V DD / 2)), the input stage 2164 can cause (e.g., force) v cont to remain relatively close to v ref . This can cause the output terminal of the charge pump that can drive v cont to remain close to v ref , and v ref can be set to a voltage at which the positive and negative outputs of the charge pump can match relatively closely (e.g., V mid ).

[0162] In some embodiments, and depending on implementation details, e.g., due to the relatively high impedance of current sources 2175 and / or 2176, using currents I 2110 and / or I 2111 for biasing transistors Q2110 and / or Q2111 can provide a relatively high power supply rejection ratio (PSRR). Additionally or alternatively, the value of degeneration resistor R2103 can be varied to vary the transconductance of Q2110 and / or Q2111. Further, depending on implementation details, the value of R2103 can be varied with little or no effect on the bias currents I 2110 and / or I 2111 .

[0163] In the example embodiment shown in Figure 21 , for illustrative purposes, a differential pair of transistors Q2110 and Q2111, a degeneration resistor R2103, and bias current sources 2175 and / or 2176 are shown, but other types of differential amplifiers, degeneration, and / or biasing arrangements can also be used.

[0164] The output nodes 2173 and 2174 of the input stage 2164 can be respectively connected to the drains of transistors Q2112 and Q2113, which, depending on implementation details, can perform multiple functions cooperatively. First, transistors Q2112 and Q2113 can form a current mirror load that can convert the differential output of the input stage 2164 into a single-ended current I 2116 whose single-ended current I 2116 can provide a current I out that can control the output frequency f 2117 of the current-controlled oscillator 2107. Secondly, transistors Q2112 and Q2113 can generate a voltage at node 2170 that can drive the gate of another mirror transistor Q2114 through a filter (e.g., a low-pass filter) 2148. Depending on implementation details, this can cause Q2114 to generate a current I 2117 that is a relatively low-frequency component I 2114 of the current I 2114 and I 2116 can be combined, for example, by summing at node 2169.

[0165] In some embodiments, transistor Q2113 can be characterized as a first current path having a first frequency characteristic, and filter 2148 and transistor Q2114 can be characterized as a second current path having a second frequency characteristic. Depending on implementation details, this can, for example, be implemented in a manner similar to that described with respect to Figure 17 and Figure 18 to achieve frequency response shaping of VCO 2142 and / or another system (e.g., a PLL) in which VCO 2142 can be used.

[0166] Thus, the arrangement of current mirror 2168 can enable the input stage 2164 to maintain (e.g., control) the input signal v cont at a level that can improve the matching of the charge pump current, while also implementing a current path having a frequency response that can increase the K VCO of the oscillator at relatively low frequencies, maintain stable PLL operation at relatively high frequencies, and / or increase the operating frequency range of the PLL.

[0167] In some embodiments, transistor Q2114 may be used to calibrate VCO 2142 using, for example, one or more of the selection codes described above. However, in some embodiments and depending on implementation details, using an input stage based on signal comparison (e.g., a differential or pseudo-differential input stage) may enable VCO 2142 and / or a PLL or other system in which VCO 2142 may be used to operate without calibration for one or more PVT values. In such embodiments, even without PVT calibration, transistor Q2114 may be implemented to provide an adjustable current I that may be used for frequency calibration and / or frequency range adjustment, selection, etc. 2114 . During calibration operation, node 2101 may be disconnected from the loop filter, charge pump, and / or any other source of input signal v cont that may be connected to node 2101 (e.g., using a first switch controlled by a calibration enable signal cal_en), and the differential inputs at nodes 2101 and 2172 may be connected together (e.g., using a second switch controlled by the calibration enable signal cal_en).

[0168] In some embodiments and depending on implementation details, using an input stage that may operate based on the comparison of two input signals (e.g., a differential or pseudo-differential input stage that may operate based on the difference between an input signal and a reference signal, as Figure 21 shown) may enable the transconductance of the input stage to be adjusted by changing the values of one or more degeneration resistors, bias current sources, etc. Additionally, depending on implementation details, such adjustment of one or more degeneration resistors may be performed without affecting one or more bias currents. Additionally or alternatively, embodiments such as Figure 21 shown may provide relatively high PSRR and / or improved flexibility in the selection of one or more degeneration resistors.

[0169] Figure 22 shows an example embodiment of the frequency-voltage characteristics of a voltage-controlled oscillator at a reduced operating temperature Figure 21 shown and the current-voltage characteristics of a charge pump that may be used with the Figure 21 shown voltage-controlled oscillator.

[0170] For purposes of comparison, Figure 22 the graph 2200X in Figure 19 substantially shows a reproduction of the graph 1900X in VCO2 , where the gain coefficient indicated as K Figure 17 may be determined by the gain coefficient of the VCO 1742 shown in

[0171] The lower curve shown in the graph 1900Y shows that when calibrating using a selection code (e.g., 8), Figure 21 the temperature T of the VCO 2142 shown cal the frequency-voltage characteristic of the VCO 2142 when operating under. The upper curve in the graph 2200Y shows that when using the same selection code (e.g., 8) used to calibrate the VCO 2142 while operating at a temperature lower than the calibration of the VCO 2142 (T cal -ΔT), the frequency-voltage characteristic of the VCO 2142. The slope of the curve in the graph 2200Y is indicated as K VCO3 , and can be determined by the DC K of the VCO 2142 VCO , which can include the contribution from the I in the transistor Q2114 2114 . The transistor Q2114 can be part of a DC or low-frequency current path that can include the low-pass filter 2148.

[0172] Because K VCO3 may be greater than K VCO2 (e.g., due to the larger DC K of the VCO 2142 VCO ), so for K VCO3 when the PLL is locked, the stable value of v cont may be closer to V than for K VCO2 . Therefore, the mismatch between the positive charge pump current I mid and the negative charge pump current I UP shown in the graph 2200B may be lower. Therefore, in some embodiments, using DN the input stage 2164 shown (e.g., a pseudo-differential input stage) can reduce the mismatch of the charge pump, which in turn can reduce spurs, jitter, phase noise, etc. in the PLL. Additionally, depending on the implementation details, using a pseudo-differential input stage can reduce the charge pump mismatch to the extent that one or more calibration operations (e.g., calibration for PVT values) can be eliminated. Using the input stage 2164 may cause a similar reduction in the charge pump current when the VCO 2142 operates at a temperature higher than the calibration of the VCO 2142 (T Figure 21 +ΔT). cal +ΔT).

[0173] Figure 23 shows an embodiment of a voltage-controlled oscillator having one or more frequency characteristics and a cascode scheme according to an example embodiment of the present disclosure. In some aspects, Figure 23 the VCO 2342 shown can be similar to Figure 17 the embodiment shown, where similar elements can be indicated by reference numerals ending with the same numbers, letters, etc. and / or including the same numbers, letters, etc. However, Figure 23 The illustrated embodiments may include a pseudo-cascode arrangement that includes transistors Q2315, Q2316, Q2317, Q2318, and / or Q2319 and / or current source 2377. Depending on implementation details, filter 2348 may be implemented with the low-pass filter (LPF) shown in Figure 23 which may cause current I 2320 to provide a DC or relatively low-frequency component based on the input signal v at terminal 2301 cont to current I 2321 while current I 2316 (which may be combined with I at summing node 2378 2320 ) may provide an AC or relatively high-frequency component based on the input signal v at terminal 2301 cont to current I 2321 .

[0174] Additionally or alternatively, transistor Q2319 may be configured to provide a calibration component to current I 2320 for example based on select code sel<n:1>.

[0175] Figure 24 An embodiment of a voltage-controlled oscillator having one or more frequency characteristics and a cascode scheme in accordance with an example embodiment of the present disclosure is shown. In some aspects, Figure 24 the illustrated VCO 2442 may be similar to Figure 21 the illustrated embodiment, where like elements may be indicated by reference numerals that end with the same digits, letters, etc. and / or include the same digits, letters, etc. However, Figure 24 the illustrated embodiment may include a pseudo-cascode arrangement that includes transistors Q2415, Q2416, Q2418, and / or Q2419 and / or current source 2477. Depending on implementation details, current I 2420 may provide a DC or relatively low-frequency component based on the input signal v at terminal 2401 cont to current I 2421 while current I 2423 (which may be combined with I at summing node 2478 2420 ) may provide an AC or relatively high-frequency component based on the input signal v at terminal 2401 cont to current I 2421 .

[0176] Additionally or alternatively, transistor Q2419 may be configured to provide a calibration component to current I 242o for example based on select code sel<n:1>.

[0177] In some embodiments, filter 2448 may be implemented with, as shown in Figure 24 is implemented by an exemplary embodiment of the low-pass RC filter shown. For example, capacitor C 4 may have a first terminal connected to a power supply voltage (e.g., V DD ), and a second terminal connected to the gate of transistor Q2414 (e.g., at node 2459), and resistor R 4 may have a first terminal connected to the gates of transistors Q2412 and Q2413 (at node 2458) and a second terminal connected to the second terminal of capacitor C 4 .

[0178] An exemplary embodiment of the low-pass filter 2448 can be used in any embodiment disclosed herein. Other examples of filters that can be used herein may include any combination of passive components (e.g., resistors, capacitors, inductors, etc.) and / or active components (e.g., transistors, operational amplifiers, etc.) having any frequency characteristics (e.g., real and / or complex poles, zeros, etc.) that implement frequency response shaping of one or more signal paths, signals, etc.

[0179] Figure 25 An exemplary embodiment of a low-pass filter having a capacitor and a resistor is shown in accordance with an exemplary embodiment of the present disclosure. For illustrative purposes, the low-pass filter 2548 can be shown in the context of a VCO 2542 similar to the Figure 21 embodiment shown, where like elements can be indicated by reference numerals ending with the same numbers, letters, etc. and / or including the same numbers, letters, etc. However, in accordance with an exemplary embodiment of the present disclosure, the low-pass filter 2548 can be used in any other type of oscillator.

[0180] Referring Figure 25 to, the low-pass filter 2548 can include capacitor C 5 and resistor R 5 , capacitor C 5 may have a first terminal connected to a power supply voltage (e.g., V DD ), and a second terminal connected to the gate of transistor Q2514 (e.g., at node 2559), and resistor R 5 may have a first terminal connected to the gates of transistors Q2512 and Q2513 (at node 2558) and a second terminal connected to the second terminal of capacitor C 5 .

[0181] In some embodiments, the first terminal of C 5 may be connected to a power supply voltage (e.g., V Figure 25 as shown DD ) because this can cause the gate of Q2514 to follow the fluctuations of the power supply voltage, thereby reducing or eliminating the current flowing through C caused by the fluctuations of the power supply voltage (thus reducing or eliminating the voltage fluctuations at the gate of Q2514). Depending on the implementation details, this can improve the power supply rejection ratio (PSRR) associated with some or all of the VCO 2542. 5 In some embodiments, the low-pass filter 2548 can be implemented using, for example, relatively low-frequency poles at a frequency f (e.g., the loop bandwidth) that may be lower than (e.g., much lower than) the crossover frequency f as shown.

[0182] In some embodiments, implementing the low-pass filter 2548 with relatively low-frequency poles may involve using resistors R and / or capacitors C that have relatively large resistance values and / or capacitance values, respectively. Figure 18 shown. c (e.g., the loop bandwidth). pLPF For example, in some embodiments, the RC filter can have a pole at a frequency f (e.g., the -3dB frequency), and the frequency f can be given by the following formula. 5 and / or 5 capacitors C. pole (e.g., the -3dB frequency). pole Therefore, depending on the implementation details, implementing a low-pass filter with relatively low-frequency poles may involve using relatively large resistors and / or capacitors that may occupy a relatively large area on an integrated circuit (IC).

[0183]

[0184] Fig. shows an example embodiment of a low-pass filter having capacitors and resistors based on one or more electronically controllable devices according to an example embodiment of the present disclosure. For illustrative purposes, the low-pass filter 2648 can be shown in the context of a VCO 2642 similar to the embodiment shown, where similar elements can be indicated by reference numerals that end with the same numbers, letters, etc. and / or contain the same numbers, letters, etc. However, according to an example embodiment of the present disclosure, the low-pass filter 2648 can be used in any other type of oscillator.

[0185] Figure 26 In the embodiment shown, the low-pass filter 2648 can include a resistor 2650, and the value R of the resistor 2650 Figure 21 shown.

[0186] In Figure 26 the embodiment shown, the low-pass filter 2648 can include a resistor 2650, and the value R of the resistor 2650 6 It can be implemented using one or more electronically controllable devices, such as one or more transistors M2-1, M2-2, ……, M2-Nd (which can be collectively and / or individually referred to as transistor M2), where Nd can indicate the number of devices. For example, transistor M2 can be implemented using one or more metal oxide semiconductor field effect transistors (MOSFETs), and one or more MOSFETs can be connected in series (e.g., stacked) and configured to operate in the triode region (which can also be referred to as the linear region), in which the transistor can be used as a drain-source (e.g., channel) on-resistance R on Based on the gate-source voltage (V GS ) and varying variable resistor.

[0187] As Figure 26 shown, transistor M2-1 can have a source connected to the gate of Q2613 at node 2658, a gate connected to node 2671, and a drain connected to the source of the next serially connected transistor (e.g., M2-2) or the gate of Q2614 at node 2659. The gates of one or more next serially connected transistors M2-1, M2-2, ……, M2-Nd can be connected together at node 2671.

[0188] The gate drive circuit 2672 can include transistor M1 and / or current source 2673. Transistor M1 can have a drain connected to a first power supply voltage (e.g., V DD ), a gate connected to the gates of Q2612 and Q2613 at node 2670, and a source connected to current source 2672 at node 2674 to receive a bias current I B4 . The current source 2672 can be connected between node 2674 and a second power supply voltage (e.g., ground or GND).

[0189] The gate drive circuit 2672 can generate a gate drive voltage V drive between the gate of M1 at node 2670 and the source of M1 at node 2674. The gate drive voltage can be applied to the gates of transistors M2-1, M2-2, ……, M2-Nd between nodes 2658 and 2671, causing transistors M2-1, M2-2, ……, M2-Nd to act as resistors (e.g., in the triode region of one or more of transistors M2-1, M2-2, ……, M2-Nd).

[0190] Figure 27 2700A shows some example operating characteristics of an embodiment of a transistor operating in the triode region according to an example embodiment of the present disclosure. GS1 、V GS and V GS Three different V GS The value of the drain current I D For drain-source voltage V DS Each curve may have a relatively linear region that may start at a relatively low V DS value, and increases V at a relatively linear rate DS values ​​until the curve becomes nonlinear, for example when the transistor starts to operate in the saturation region.

[0191] Graph 2700B shows an enlarged view of the area of ​​graph 2700A, where the area indicated as V GS1 、V GS2 and V GS3 The curve can be the most linear. For a given V GS Value, V DS The value change can be related to I D The slope of the curve can determine the resistance, depending on the implementation details. For example, for lower V GS Value (for example, V GS1 ) can have a lower slope and correspondingly higher resistance.

[0192] In some embodiments, the resistance R of a transistor operating in the triode region is on can be determined as follows:

[0193]

[0194] where μ n can represent the charge carrier mobility (e.g., μ n can represent electron mobility and / or μ p can represent hole mobility, which may be relevant to different device types such as NMOS and / or PMOS transistors), C ox may represent the capacitance per unit area of ​​the gate oxide layer, W may represent the channel width, L may represent the channel length, and / or V may represent the gate oxide layer. TH Represents the threshold voltage of the transistor.

[0195] As shown in Equation 11, in some embodiments, the resistor R on This can be increased by one or more of the following: increasing the channel width W, reducing the channel length L and / or, for example, by reducing the threshold voltage V TH to reduce V GS -V TH value.

[0196] Reference Figure 26 , in some embodiments, the gate drive voltage V generated by M1 in the gate drive circuit 2672 and applied to the gates of M2-1, M2-2, ……, M2-Nd at node 2671 drive can depend on one or more parameters, such as the geometry and / or process value of M1, the bias current I B4 value, etc. In addition, one or more of these parameters can be adjusted to adjust the corresponding resistance R of the resistor 2650 6 . Depending on the implementation details, this can adjust the poles of the low-pass filter 2648.

[0197] For example, to reduce the frequency f of the pole given by Equation 10 pole , the resistance R given by Equation 11 on can be increased by reducing the threshold voltage V TH . Depending on the implementation details, this can be done, for example, by increasing the number of transistors Nd and / or increasing the width of the transistor M1 (which can reduce V GS ).

[0198] Some of the embodiments disclosed above have been described in the context of various implementation details, but the principles of the present disclosure are not limited to these or any other specific details. For example, a certain function has been described as being implemented by certain components, but in other embodiments, the function can be distributed among different systems and components located in different positions and having various user interfaces. Some embodiments have been described as having specific processes, operations, etc., but these terms also cover embodiments in which the specific processes, operations, etc. can be implemented using multiple processes, operations, etc. or in which multiple processes, operations, etc. can be integrated into a single process, step, etc. A reference to a component or element may refer only to a part of that component or element. For example, a reference to a block may refer to the entire block or one or more sub-blocks. The use of terms such as "first" and "second" in the present disclosure and the claims may be for the sole purpose of distinguishing the elements they modify and may not indicate any spatial or temporal order, unless it is obvious from the context. In some embodiments, a reference to an element may refer to at least a part of that element, for example, "based on" may mean "at least partially based on", etc. A reference to a first element does not imply the existence of a second element. The principles disclosed herein have independent utility and can be embodied separately, and not every embodiment can utilize every principle. However, these principles can also be embodied in various combinations, some of which can amplify the benefits of a single principle in a synergistic manner. In accordance with the inventive principles disclosed in this patent, the various details and embodiments described above can be combined to produce additional embodiments.

[0199] In some embodiments, a part of an element may refer to less than the entire element or the whole of that element. The first part of an element and the second part of an element may refer to the same part of the element. The first part of an element and the second part of an element may overlap (e.g., a part of the first part may be the same as a part of the second part).

[0200] Since the inventive principles disclosed in this patent can be modified in arrangement and detail without departing from the inventive concept, such changes and modifications are considered to fall within the scope of the following claims.

Claims

1. A method for controlling the frequency response of an oscillator, comprising: generating, using an oscillator, a first signal having a frequency based on the current; generating a first portion of the current based on a second signal, the first portion of the current having a first frequency characteristic; as well as A second portion of the current is generated based on the second signal, the second portion of the current having a second frequency characteristic.

2. The method according to claim 1, further comprising: controlling the frequency of the second signal; as well as The gain of the first frequency characteristic is controlled based on the frequency of the second signal.

3. The method according to claim 1, wherein: The first frequency characteristic includes: a first gain at a first frequency; and A second gain at a second frequency.

4. The method according to claim 3, wherein: The first gain is greater than the second gain; and The second frequency is greater than the first frequency.

5. The method according to claim 1, further comprising: controlling a phase of the second signal; as well as The gain of the first frequency characteristic is controlled based on the phase of the second signal.

6. The method according to claim 1, wherein: The first frequency characteristic includes: a first phase shift at a first frequency; and A second phase shift at a second frequency.

7. The method according to claim 6, wherein: The first phase shift is in a first direction; and The second phase shift is in a second direction.

8. A circuit for controlling the frequency response of an oscillator, comprising: an oscillator configured to generate a first signal having a frequency based on the current; as well as a current generator configured to generate a current; Wherein, the current generator comprises: The first path is configured to generate a first portion of the current based on a second signal, The first path has a first frequency characteristic; and A second path is configured to generate a second portion of the current based on the second signal, the second path having a second frequency characteristic.

9. The circuit of claim 8, wherein: the first path includes a first transistor configured to generate a first portion of the current based on the second signal; and The second path includes a second transistor configured to generate a second portion of the current based on the second signal.

10. The circuit according to claim 9, wherein: The second path includes a filter configured to control the second transistor based on the second signal.

11. The circuit according to claim 10, wherein: The current generator includes a third transistor configured to control the first transistor and the second transistor based on the second signal.

12. The circuit of claim 8, wherein: The first path is configured to generate a first portion of the current based on a third signal; The second path is configured to generate a second portion of the current based on the third signal; and The circuit also includes an input stage configured to generate the third signal based on the second signal.

13. The circuit of claim 12, wherein: The current is a first current, the third signal is a second current, and the current generator includes a current mirror configured to: generating a first portion of the first current based on the second current using the first path; as well as A second portion of the first current is generated based on the second current using the second path.

14. The circuit of claim 12, wherein: The input stage is configured to generate the third signal based on a comparison of the second signal and a fourth signal. 15 . The circuit of claim 8 , further comprising a detector circuit configured to generate the second signal based on a comparison of the first signal and a third signal.

16. The circuit of claim 14, wherein: The circuit has a loop bandwidth; The first path has a pole at a pole frequency; and The loop bandwidth is greater than the pole frequency.

17. A circuit for controlling the frequency response of an oscillator, comprising: an oscillator configured to generate a first signal having a frequency based on the current; a current generator configured to generate the current; as well as An input stage is configured to control the current generator based on a comparison of the second signal and the third signal.

18. The circuit of claim 17, wherein: The second signal comprises an input signal; and The third signal includes a reference signal.

19. The circuit of claim 17, wherein: The input stage comprises: a first transistor including a first terminal connected to a power source, a second terminal configured to receive the second signal, and a third terminal connected to the current generator; and The second transistor includes a first terminal connected to the power supply, a second terminal configured to receive the third signal, and a third terminal connected to the current generator.

20. The circuit of claim 19, wherein: The second terminal of the first transistor is connected to the power supply using a first current source; The second terminal of the second transistor is connected to the power supply using a second current source; and The input stage also includes a resistor connected between the first transistor and the second transistor.

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