Photoelectric conversion device and apparatus

Abstract

The invention discloses a photoelectric conversion device and apparatus. The photoelectric conversion device includes: a pixel including a conversion unit configured to accumulate an electric charge based on incident light, the pixel configured to output a photoelectric conversion signal based on the accumulated electric charge; a sample and hold unit configured to sample and hold a first photoelectric conversion signal and a second photoelectric conversion signal output from the pixel; and an oversampling conversion unit configured to perform analog-to-digital conversion, i.e., AD conversion, on the first photoelectric conversion signal and the second photoelectric conversion signal output from the sampling and holding unit, in a process from when the first photoelectric conversion signal and the second photoelectric conversion signal are output from the pixel to when AD conversion is performed on the first photoelectric conversion signal and the second photoelectric conversion signal, the first photoelectric conversion signal and the second photoelectric conversion signal are processed. The gain set for the first photoelectric conversion signal is different from the gain set for the second photoelectric conversion signal.

Description

Technical Field

[0001] Aspects of the present embodiment relate to optoelectronic conversion devices and apparatuses. Background Art

[0002] Some solid-state image sensors include a delta-sigma analog-to-digital (AD) conversion circuit as an oversampling AD conversion circuit. WO 2019 / 069614 discusses a solid-state image sensor that achieves a wide input voltage range through two capacitor elements, where the two capacitor elements are used to store signals from pixels and output a weighted average of the voltages stored in the two capacitor elements.

[0003] However, there is still room for improvement in optimizing the AD conversion operation of optoelectronic conversion devices equipped with an oversampling AD conversion circuit including a delta-sigma AD conversion circuit as described in WO 2019 / 069614. Summary of the Invention

[0004] According to an aspect of the present embodiment, an optoelectronic conversion device includes: a pixel including a photoelectric conversion unit configured to accumulate charge based on incident light, the pixel being configured to output a photoelectric conversion signal based on the accumulated charge; a sampling and holding unit configured to sample and hold a first photoelectric conversion signal and a second photoelectric conversion signal output from the pixel; and an oversampling conversion unit configured to perform analog-to-digital conversion, i.e., AD conversion, on the first photoelectric conversion signal and the second photoelectric conversion signal output from the sampling and holding unit, wherein, in the process from when the first photoelectric conversion signal and the second photoelectric conversion signal are output from the pixel to when the AD conversion is performed on the first photoelectric conversion signal and the second photoelectric conversion signal, the gain set for the first photoelectric conversion signal is different from the gain set for the second photoelectric conversion signal.

[0005] Other features of the present disclosure will become apparent from the following description of exemplary embodiments with reference to the accompanying drawings. Brief Description of the Drawings

[0006] Figure 1 is a block diagram for describing an optoelectronic conversion device according to a first exemplary embodiment.

[0007] Figure 2 is a circuit diagram for describing an optoelectronic conversion device according to a first exemplary embodiment.

[0008] Figure 3 is a circuit diagram for describing an optoelectronic conversion device according to a first exemplary embodiment.

[0009] Figure 4 is a driving timing diagram for describing an optoelectronic conversion device according to a first exemplary embodiment.

[0010] Figure 5 is a circuit diagram for describing a reference photoelectric conversion device.

[0011] Figure 6 is a circuit diagram for describing a photoelectric conversion device according to a modification of the first exemplary embodiment.

[0012] Figure 7 is a circuit diagram for describing a photoelectric conversion device according to the second exemplary embodiment.

[0013] Figure 8 is a driving timing diagram for describing a photoelectric conversion device according to the second exemplary embodiment.

[0014] Figures 9A to 9C is a schematic diagram for describing a device according to the third exemplary embodiment. Detailed implementation manners

[0015] Hereinafter, exemplary embodiments will be described with reference to the drawings. However, the exemplary embodiments described below do not limit the scope of the present disclosure according to the appended claims. Although multiple features are described in the exemplary embodiments, all of the multiple features are not necessarily essential for the present disclosure, and the multiple features can be combined arbitrarily. In the drawings, similar components are denoted by the same reference numerals, and repeated descriptions will be omitted. In each of the exemplary embodiments described below, a sensor for imaging will be mainly described as an example of a photoelectric conversion device. However, each exemplary embodiment is not limited to a sensor for imaging, and can be applied to other examples of photoelectric conversion devices. Such examples include imaging devices, distance measurement devices (devices that measure distance using focus detection or time-of-flight (TOF)), and light measurement devices (devices that measure the amount of incident light).

[0016] In this specification, terms indicating specific directions and positions (e.g., "up", "down", "right", "left", and other terms including these terms) are used when necessary. The use of these terms is for facilitating the understanding of the exemplary embodiments with reference to the drawings, and the technical scope of the present disclosure is not limited by the meanings of these terms.

[0017] In this specification, the description that "component A and component B are electrically connected" does not limit the case where component A and component B are directly connected. For example, even if another component C is connected between component A and component B, it is sufficient to describe that they are electrically connected.

[0018] will refer to Figures 1 to 4 describe a photoelectric conversion device according to the first exemplary embodiment of the present disclosure.

[0019] Figure 1This is an example showing a block diagram of a photoelectric conversion device according to the present exemplary embodiment.

[0020] The photoelectric conversion device includes a pixel substrate 1 and a circuit substrate 2 on which a circuit is mounted. Pixel units 5 are arranged on the pixel substrate 1. The pixel units 5 include a plurality of pixels 10 arranged in a matrix, and each pixel includes a photoelectric conversion unit for generating charges based on incident light. Outputs from the plurality of pixels 10 are output to the circuit substrate 2 via vertical signal lines 30. The circuit substrate 2 may be stacked on the pixel substrate 1, or the foregoing components on the pixel substrate 1 and the circuit substrate 2 may be arranged on the same substrate. As used herein, the column direction refers to Figure 1 the vertical direction in Figure 1 or equivalently, the vertical direction in which the vertical signal lines 30 extend from the pixel substrate 1 to the circuit substrate 2. The row direction refers to

[0021] the horizontal direction in

[0022] i.e., the direction perpendicular to the vertical signal lines 30. A current source 40, a sample-and-hold unit 50, a conversion unit 60, a data processing unit 90, and an output unit 100 are arranged on the circuit substrate 2. The current source 40 is positioned corresponding to the respective vertical signal lines 30. The current source 40 supplies a bias current to the pixels 10 from which pixel signals are to be read via the vertical signal lines 30. The vertical signal lines 30 transmit pixel signals based on charges generated by the photoelectric conversion units of the pixels 10 from the pixels 10 to the sample-and-hold unit 50.

[0023] The sample-and-hold unit 50 samples and holds the pixel signals generated by each pixel 10 from the pixel unit 5 via the vertical signal lines 30. In the present exemplary embodiment, each sample-and-hold unit 50 includes two sample-and-hold circuits. The first sample-and-hold circuit samples and holds the pixel signal corresponding to the reset level when the photoelectric conversion unit is reset (hereinafter referred to as the reset level signal). The second sample-and-hold circuit samples and holds the pixel signal corresponding to the imaging signal obtained when the photoelectric conversion unit performs a photoelectric conversion operation (hereinafter referred to as the photoelectric conversion signal). The first sample-and-hold circuit and the second sample-and-hold circuit are provided for each vertical signal line 30.

[0024] The data processing unit 90 processes the digital signal output from the conversion unit 60. The data processing unit 90 also performs digital processing such as correction processing and interpolation processing on the digital signal output from the conversion unit 60. The output unit 100 outputs the signal processed by the data processing unit 90 to the outside.

[0025] Figure 2 is an example of a circuit diagram of the pixel 10 included in the photoelectric conversion device according to the present exemplary embodiment. The present exemplary embodiment is applicable to both a front-illuminated sensor and a back-illuminated sensor.

[0026] The pixel 10 includes a photoelectric conversion unit 400, a transfer transistor 410, a reset transistor 455, an amplification transistor 430, and a selection transistor 440. An example of the photoelectric conversion unit 400 is a photodiode. One of the main electrodes of the photoelectric conversion unit 400 is connected to the reference voltage 450. The photoelectric conversion unit 400 photoelectrically converts the received light into charges (such as photoelectrons, etc.) having an amount corresponding to the amount of the received light, and accumulates the charges.

[0027] The other main electrode of the photoelectric conversion unit 400 is electrically connected to the gate electrode of the amplification transistor 430 via the transfer transistor 410. The node 420 to which the gate electrode of the amplification transistor 430 is connected serves as a floating diffusion (FD). The FD section serves as a charge-voltage conversion unit, and the charge generated by the photoelectric conversion unit 400 is input to the charge-voltage conversion unit, and the charge-voltage conversion unit converts the input charge into a signal voltage. Hereinafter, the node 420 may be referred to as the FD section 420.

[0028] A transfer signal TX is supplied to the gate electrode of the transfer transistor 410. The transfer transistor 410 becomes conductive in response to the transfer signal TX, whereby the charge accumulated in the photoelectric conversion unit 400 is transferred to the node 420 serving as the FD section.

[0029] The reset transistor 455 is connected between the power supply voltage 460 and the node 420. The expression that a transistor is connected between A and B means that one of the main electrodes (source and drain) of the transistor is connected to A and the other main electrode is connected to B. The gate electrode of the transistor is not connected to A or B.

[0030] A reset signal RES is supplied to the gate electrode of the reset transistor 455. The reset transistor 455 becomes conductive in response to the reset signal RES, whereby the charge held in the FD section 420 is cleared. The voltage of the node 420 is thereby reset to the power supply voltage 460. The pixel 10 is reset by this reset operation.

[0031] The gate electrode of the amplification transistor 430 is connected to the node 420, one of the main electrodes is connected to the power supply voltage 460, and the other main electrode is connected to the selection transistor 440.

[0032] The gate electrode of the amplification transistor 430 serves as the input of a source follower circuit for reading a signal obtained by photoelectric conversion by the photoelectric conversion unit 400. The other main electrode of the amplification transistor 430 is connected to the vertical signal line 30 via the selection transistor 440. The amplification transistor 430 and the current source 40 connected to the vertical signal line 30 constitute a source follower that converts the voltage of the node 420 into the voltage of the vertical signal line 30.

[0033] The selection transistor 440 is connected between the amplification transistor 430 and the vertical signal line 30. The selection signal SEL is supplied to the gate electrode of the selection transistor 440. The selection transistor 440 becomes conductive in response to the selection signal SEL, whereby the pixel 10 enters the selected state. In the selected state, a signal based on the voltage of the node 420 is output as a pixel signal to the vertical signal line 30 via the amplification transistor 430.

[0034] The circuit configuration of the pixel 10 is not limited to Figure 2 the configuration shown. For example, the selection transistor 440 may be connected between the power supply voltage 460 and the amplification transistor 430. In the case where more than one vertical signal line 30 is included in a single pixel column, each pixel 10 may include a plurality of selection transistors 440 connected to respective different vertical signal lines 30. In Figure 2 the configuration shown, the pixel 10 has a 4-transistor (4Tr.) configuration including a transfer transistor 410, a reset transistor 455, an amplification transistor 430, and a selection transistor 440. However, this is not restrictive. For example, the pixel 10 may have a 3Tr. configuration in which the selection transistor 440 is omitted and the voltage of the node 420 is controlled to operate the amplification transistor 430 also as a selection transistor. The number of transistors may be increased to form a 5Tr. or higher-order configuration.

[0035] When the pixel 10 is given a reset signal RES, the reset transistor 455 resets the voltage of the node 420. As the pixel 10 is reset, the pixel 10 outputs a reset level signal corresponding to the reset level when the photoelectric conversion unit 400 is reset. This results in the output of a photoelectric conversion signal corresponding to the imaging signal generated by photoelectric conversion based on the light incident on the photoelectric conversion unit 400.

[0036] Figure 3 is an example of a circuit diagram of a sampling and holding unit 50 and a conversion unit 60 included in the photoelectric conversion device according to the present exemplary embodiment. Figure 3A sampling and holding unit 50 and a conversion unit 60 are shown as being arranged corresponding to the vertical signal lines 30. In the present exemplary embodiment, one sampling and holding unit 50 and one conversion unit 60 are provided for each of the vertical signal lines 30.

[0037] The sampling and holding unit 50 includes a first sampling and holding circuit 210 and a second sampling and holding circuit 211. As will be described below, the first sampling and holding circuit 210 samples and holds the reset level signal output from the pixel 10 when the photoelectric conversion unit 400 is reset. The second sampling and holding circuit 211 samples and holds the photoelectric conversion signal generated based on the light incident on the photoelectric conversion unit 400.

[0038] The first sampling and holding circuit 210 includes a capacitive element 120 and an inverting amplifier 220.

[0039] The switch 110 controls the connection between the vertical signal line 30 and the capacitive element 120 based on the control signal Smp_n. Examples of the inverting amplifier 220 include a combination of a common-source circuit and a source follower circuit. The inverting amplifier 220 includes transistors 130, 140, 150, 160 and 230, switches 170, 180 and 190, and a current source 200. The switch 170 is connected between the input and output of the common-source circuit including transistors 130, 140, 150 and 160 and is controlled by the control signal Smpa_n. The reset level signal is output via the inverting amplifier 220 in response to the control signal Hld_n.

[0040] The second sampling and holding circuit 211 may have a configuration similar to that of the first sampling and holding circuit 210, but mainly differs from the first sampling and holding circuit 210 in that switches 112 and 192 and a capacitive element 122 are added. The second sampling and holding circuit 211 includes capacitive elements 121 and 122 for holding the pixel signal from the vertical signal line 30, and an inverting amplifier 221. The switches 111 and 112 control the connection between the vertical signal line 30 and the capacitive elements 121 and 122 based on the control signals Smp_s1 and Smp_s2, respectively.

[0041] Similar to the inverting amplifier 220, examples of the inverting amplifier 221 include a combination of a common-source circuit and a source follower circuit. The inverting amplifier 221 includes transistors 131, 141, 151, 161 and 231, switches 171, 181, 191 and 192, and a current source 201. The switch 171 is connected between the input and output of the common-source circuit including transistors 131, 141, 151 and 161 and is controlled by the control signal Smpa_s. The photoelectric conversion signal is output via the inverting amplifier 221 in response to the control signal Hld_s1 or Hld_s2.

[0042] The resistance element 240 is electrically connected between the output node of the first sample-and-hold circuit 210 and the output node of the second sample-and-hold circuit 211. A description is given of the case where the first sample-and-hold circuit 210 outputs a reset level signal and the second sample-and-hold circuit 211 outputs a photoelectric conversion signal. The current I flowing through the resistance element 240 is represented by the following formula (1):

[0043] I = (Vn - Vs) / R (Formula 1),

[0044] where the voltage at the output node of the first sample-and-hold circuit 210, i.e., the voltage of the reset level signal, is Vn, the voltage at the output node of the second sample-and-hold circuit 211, i.e., the voltage of the photoelectric conversion signal, is Vs, and the resistance of the resistance element 240 is R.

[0045] This current I is input to the conversion unit 60. As shown in (Formula 1), the current I flowing through the resistance element 240 here is proportional to the difference between the voltage Vn of the reset level signal and the voltage Vs of the photoelectric conversion signal. This means that correlated double sampling (CDS) is performed at the stage where the current I is input to the conversion unit 60.

[0046] The conversion unit 60 is an oversampling AD conversion circuit, such as a ΔΣ AD conversion circuit. The ΔΣ AD conversion circuit includes a first integrator, a second integrator, a quantizer 370, and a decimation filter 380. In the conversion unit 60, the first integrator includes an integration capacitor 320. The second integrator includes a voltage-current conversion circuit (Gm unit) 330 that converts a voltage into a current, and an integration capacitor 360. An AD converter 305 including a current source 300 and a switch 310 is connected to the input node of the first integrator.

[0047] The AD converter 305 controls the current to the first integrator based on the digital signal via the second integrator and the quantizer 370. An AD converter 345 including a current source 340 and a switch 350 is connected to the input node of the second integrator. The AD converter 345 controls the current to the second integrator based on the output of the second integrator quantized by the quantizer 370.

[0048] In the conversion unit 60, the quantizer 370 feeds back the previous quantization value to the second integrator and the first integrator through the AD converters 305 and 345. The previous quantization value is fed back to the AD converters 305 and 345 in such a way that the previous quantization value passes through the integrators twice, which enables obtaining a second-order noise shaping characteristic. In addition, the decimation filter 380 located at the subsequent stage of the quantizer 370 removes high-frequency noise, thereby obtaining an accurate AD conversion output.

[0049] Figure 4This is an example of a driving timing diagram showing the operation timings of the sampling and holding unit 50 and the conversion unit 60 included in the photoelectric conversion device according to the present exemplary embodiment. Figure 4 The horizontal axis represents time, and the vertical axis represents voltage. The control signal RES is a signal for resetting the pixel 10. The transfer signal TX controls the signal read from the photoelectric conversion unit 400. The control signals Smpa_n, Smp_n, Smpa_s, Smp_s1, Smp_s2, Hld_n, Hld_s, Hld_s1, and Hld_s2 control the switches in the first sampling and holding circuit 210 and the second sampling and holding circuit 211. In the following description, during Figure 4 the waveform of the corresponding signal in is at a high level (for example, see the state of the waveform of the control signal RES between times t1 and t2), the switch will be described as being on, while during the period when the corresponding control signal is at a low level, the switch will be described as being off. A switch being on means that the input node and the output node of the switch are in a conducting state. On the other hand, a switch being off means that the input node and the output node of the switch are not in a conducting state.

[0050] At times t1 to t2, Figure 2 the control signal RES goes high, and the reset transistor 455 turns on, thereby resetting the FD section 420. Figure 2 The control signal SEL shown is also controlled, whereby the voltage of the vertical signal line 30 is set to the reset level voltage Vn. At time t1, the control signals Smp_n and Smpa_n go high, and the switches 110 and 170 of the first sampling and holding circuit 210 turn on. Next, at time t3 when the control signal Smpa_n changes from high to low, the reset level voltage Vn is sampled and accumulated in the capacitor element 120. At time t4, the control signal Smp_n changes from high to low, and the switch 110 turns off, whereby the capacitor element 120 is disconnected from the vertical signal line 30.

[0051] At times t5 to t6, Figure 2 the control signal TX goes high, and the transfer transistor 410 turns on. At the same time, the charge generated by the light incident between times t2 and t6 in the photoelectric conversion unit 400 is transferred to the FD section 420. In other words, the period between time t2 and time t6 is the exposure period. The voltage of the FD section 420 drops based on the amount of charge. In response to the control signal SEL, the voltage of the FD section 420 is output to the vertical signal line 30 via the amplification transistor 430.

[0052] The voltage of the vertical signal line 30 is thus set to the voltage Vs1 of the first photoelectric conversion signal. At time t5, the control signals Smp_s and Smpa_s1 go high, and the switches 111 and 171 in the second sample-and-hold circuit 211 for the photoelectric conversion signal are turned on.

[0053] Next, at time t7 when the control signal Smpa_s changes from high to low, the switch 171 is turned off, and the voltage Vs1 of the first photoelectric conversion signal is sampled and accumulated in the capacitor element 121. At time t8, the control signal Smp_s1 changes from high to low, and the switch 111 is turned off, whereby the capacitor element 121 is disconnected from the vertical signal line 30.

[0054] When the switch 171 is turned off at time t7, the voltage across the switch 171 remains substantially the same regardless of the voltage of the vertical signal line 30. Therefore, the disconnection of the switch 171 does not cause any charge injection, and no error voltage appears for the voltage Vs1 of the first photoelectric conversion signal accumulated in the capacitor element 121. When the switch 111 is turned off at time t8, the capacitor element 121 is in a high-impedance state at both ends. Therefore, the disconnection of the switch 111 has no effect. In this way, the appearance of an error voltage for the voltage Vs1 of the first photoelectric conversion signal is prevented.

[0055] At times t9 to t10, Figure 2 the control signal TX for

[0056] goes high, and the transfer transistor 410 is turned on again. At the same time, the charges generated by the light incident between times t6 and t10 in the photoelectric conversion unit 400 are additionally transferred to the FD section 420. In other words, in addition to the period from time t2 to t6, the period from time t6 to t10 is also used as an exposure period. The voltage of the FD section 420 further drops based on the amount of charge. As a result, the voltage of the vertical signal line 30 drops to the voltage Vs2 of the second photoelectric conversion signal. At time t9, the control signals Smp_s and Smpa_s2 go high, and the switches 112 and 171 in the second sample-and-hold circuit 211 for the photoelectric conversion signal are turned on. Next, at time t11 when the control signal Smpa_s changes from high to low, the voltage Vs2 of the second photoelectric conversion signal is sampled and accumulated in the capacitor element 122. At time t12, the control signal Smp_s2 changes from high to low, and the switch 112 is turned off, whereby the capacitor element 122 is disconnected from the vertical signal line 30.

[0057] When the switch 171 is turned off at time t11, regardless of the voltage of the vertical signal line 30, the voltage across the switch 171 remains substantially the same. Therefore, the turn-off of the switch 171 does not cause any charge injection, and there is no error voltage in the voltage Vs2 of the second photoelectric conversion signal accumulated in the capacitor element 122. In addition, when the switch 112 is turned off at time t12, the capacitor element 122 is in a high impedance state at both ends. Therefore, the turn-off of the switch 112 has no effect. In this way, the occurrence of an error voltage in the voltage Vs2 of the second photoelectric conversion signal is prevented.

[0058] At time t13, the control signal Hld_n goes high, and the switches 180 and 190 are turned on, so that the capacitor element 120 in the first sample-and-hold circuit 210 outputs the voltage Vn of the reset level signal. At time t13, the control signals Hld_s1 and Hld_s go high, and the switches 181 and 191 are also turned on, whereby the capacitor element 121 in the second sample-and-hold circuit 211 outputs the voltage Vs1 of the first photoelectric conversion signal.

[0059] As described above, the input current of the conversion unit 60 is a current based on the difference between the voltage Vn of the reset level signal at the output node of the first sample-and-hold circuit 210 and the voltage Vs1 of the first photoelectric conversion signal at the output node of the second sample-and-hold circuit 211. The conversion unit 60 performs AD conversion on the current based on the difference between the voltages Vn and Vs1.

[0060] At time t14, the control signal Hld_s1 goes low, and the switch 191 is turned off. Then, at time t15, the control signal Hld_s2 goes high and the switch 192 is turned on, whereby the capacitor element 122 in the second sample-and-hold circuit 211 outputs the voltage Vs2 of the second photoelectric conversion signal.

[0061] As described above, the input current of the conversion unit 60 is a current based on the difference between the voltage Vn of the reset level signal at the output node of the first sample-and-hold circuit 210 and the voltage Vs2 of the second photoelectric conversion signal at the output node of the second sample-and-hold circuit 211. The conversion unit 60 performs AD conversion on the current based on the difference between the voltages Vn and Vs2.

[0062] At time t16, the control signal Hld_n goes low, and the switches 180 and 190 are turned off. At time t16, the control signal Hld_s also goes low, and the switch 181 is turned off. At time t16, the control signal Hld_s2 also goes low, and the switch 192 is turned off.

[0063] Since the first and second photoelectric conversion signals are pixel signals corresponding to different lengths of accumulation times, it is unlikely that the signals have the same output amplitude except in the unexposed dark state. The exposure period (from t2 to t10) for accumulating the charge corresponding to the second photoelectric conversion signal is longer than the exposure period (from t2 to t6) for accumulating the charge corresponding to the first photoelectric conversion signal. When the amount of light incident on the photoelectric conversion unit 400 does not change much, the voltage Vs2 thus provides a signal with a larger output amplitude compared to the voltage Vs1. In other words, the first and second photoelectric conversion signals have different output amplitude ranges. As described above, in the present exemplary embodiment, a plurality of photoelectric conversion signals (the first and second photoelectric conversion signals) having different lengths of charge accumulation times are read, thereby obtaining a high dynamic range signal. Therefore, using the high dynamic range signal enables the generation of high dynamic range (HDR) images and HDR moving images. As used herein, the output amplitude refers to the voltage difference with respect to the reference voltage when the voltage of the signal output from the pixel 10 when the FD unit 420 is reset is used as the reference voltage. This also applies to the output amplitude described below, that is, unless otherwise specified, the reference voltage can be used as the signal output from the pixel 10 when the FD unit 420 is reset. This signal level is generally close to the voltage of the power supply voltage 460.

[0064] As described above, in the present exemplary embodiment, the occurrence of error voltages for the first and second photoelectric conversion signals is prevented. This prevents the deterioration of the HDR signal quality.

[0065] Therefore, the deterioration of the image quality of the HDR images and HDR moving images generated using the HDR signal is prevented.

[0066] The resistance element 240 electrically connected between the output nodes of the first sample and hold circuit 210 and the second sample and hold circuit 211 may be a variable resistance circuit. In other words, the output amplitude level of the signal input to the conversion unit 60 can be adjusted according to the resistance value. In this case, the resistance element 240 serves as a gain setting unit. The resistance of the resistance element 240 changes between the times t13 to t14 when the capacitor element 121 reads the voltage Vs1 of the first photoelectric conversion signal, and the resistance of the resistance element 240 changes between the times t15 to t16 when the capacitor element 122 reads the voltage Vs2 of the second photoelectric conversion signal. Changing the resistance to change the set gain enables the reduction of noise or power consumption according to the output amplitude level. A description thereof will now be given.

[0067] When the resistance at times t13 to t14 is set to be relatively lower than the resistance at times t15 to t16, the reduction in thermal noise generated from the resistance element 240 reduces the noise in the voltage Vs1 of the first photoelectric conversion signal. On the other hand, when the resistance from time t13 to t14 is set to be relatively higher than the resistance from time t15 to t16, the reduction in the output current to the conversion unit 60 reduces the power consumption. By configuring the gain set for the first photoelectric conversion signal to be higher than the gain set for the second photoelectric conversion signal, the aforementioned effects can be obtained.

[0068] In the present exemplary embodiment, during the process from the generation of the first and second photoelectric conversion signals to the AD conversion, the gain set for the first photoelectric conversion signal and the gain set for the second photoelectric conversion signal are different from each other. In other words, multiple photoelectric conversion signals are read with respective different gains. Further, in operation, the noise or power consumption is reduced. A configuration for changing the gain in a manner other than making the resistance of the resistance element 240 variable can be adopted. For example, the gain can be changed by making the value of the current output from the current source 300 variable. Note that in the case of switching the value of the current output from the current source 300, after the current value is switched, the current value requires a certain amount of time to stabilize. Therefore, compared with switching the value of the current output from the current source 300, switching the resistance of the resistance element 240 enables faster signal processing.

[0069] In the present exemplary embodiment, the capacitor elements 121 and 122 share the second sample and hold circuit 211, which enables reading the first and second photoelectric conversion signals without increasing the operating power.

[0070] In the present exemplary embodiment, the first and second photoelectric conversion signals are read using a common resistance element 240. Therefore, the level fluctuations caused by temperature and process variations may be similarly manifested. This prevents the overlap of different variations on the first and second photoelectric conversion signals, thereby preventing the deterioration of the HDR signal quality. As a result, the image quality of the HDR image and the HDR moving image generated using the HDR signal is prevented from deteriorating.

[0071] In the present exemplary embodiment, the resistance element 240 for setting the gain when reading the first and second photoelectric conversion signals is located at the subsequent stage of the first sample and hold circuit 210 and the second sample and hold circuit 211. Even when the resistance of the resistance element 240 is set to be variable when reading each of the first and second photoelectric conversion signals, this configuration brings about precise CDS. A description thereof will now be given.

[0072] Figure 5A reference example is shown. Figure 5 The photoelectric conversion device shown includes a gain setting circuit 1000, a capacitive element 1030 for accumulating a reset level signal, a capacitive element 1040 for accumulating a first photoelectric conversion signal, and a capacitive element 1050 for accumulating a second photoelectric conversion signal. The gain setting circuit 1000 includes an operational amplifier 1001, a resistive element 1002, and a variable resistive element 1003. A switch 1060 is electrically connected between the gain setting circuit 1000 and the capacitive element 1030. As the switch 1060 is turned on, the signal output from the gain setting circuit 1000 is input to the capacitive element 1030 via the switch 1060. A switch 1070 is electrically connected between the gain setting circuit 1000 and the capacitive element 1040. As the switch 1070 is turned on, the signal output from the gain setting circuit 1000 is input to the capacitive element 1040 via the switch 1070. A switch 1080 is electrically connected between the gain setting circuit 1000 and the capacitive element 1050. As the switch 1080 is turned on, the signal output from the gain setting circuit 1000 is input to the capacitive element 1050 via the switch 1080. In other words, in Figure 5 this configuration, the gain setting circuit 1000 is located at the front stage of the capacitive elements 1030, 1040, and 1050, rather than the rear stage. The capacitive elements 1030, 1040, and 1050 respectively correspond to Figure 3 the capacitive elements 120, 121, and 122 shown. The switches 1060, 1070, and 1080 respectively correspond to Figure 3 the switches 110, 111, and 112 shown.

[0073] In Figure 5 this configuration, a description is given of the case where correlated double sampling (CDS) is performed on both the first photoelectric conversion signal and the second photoelectric conversion signal read at different gains using a common reset level signal. In this case, since the gain setting circuit 1000 is located at the front stage of the capacitive element 1030, the gain setting circuit 1000 cannot change the gain for the reset level signal accumulated in the capacitive element 1030. Therefore, the gain for at least one of the first photoelectric conversion signal and the second photoelectric conversion signal and the gain for the reset level signal are different. This reduces the accuracy of the CDS using at least one of the conversion signals corresponding to the gain different from the gain for the reset level signal in the first photoelectric conversion signal and the second photoelectric conversion signal. For example, in the case where the reset level signal and the first photoelectric conversion signal are read at a first gain and the second photoelectric conversion signal is read at a second gain, the accuracy of the CDS related to the second photoelectric conversion signal is reduced. The reason is as follows: When reading the reset level signal and when reading the second photoelectric conversion signal, different gains are applied to the offset component of the operational amplifier 1001 and the pixel signal.

[0074] InFigure 3 In the configuration shown, a description is given of a case where correlated double sampling (CDS) is performed on both a first photoelectric conversion signal and a second photoelectric conversion signal read at different gains using a common reset level signal. In this case, since the resistance element 240 is located at the subsequent stage of the first sample and hold circuit 210 and the second sample and hold circuit 211, the resistance element 240 can change the gain for the reset level signal accumulated in the capacitor element 120. Even when the gains for the first photoelectric conversion signal and the second photoelectric conversion signal are set differently, the gain for the reset level signal is thus set to substantially the same gain as the respective gains for the first photoelectric conversion signal and the second photoelectric conversion signal. This enables precise CDS of the first photoelectric conversion signal and the second photoelectric conversion signal to be achieved even in the case where CDS is performed on the first photoelectric conversion signal and the second photoelectric conversion signal read at different gains using a common reset level signal.

[0075] will be described with reference to Figure 6 a photoelectric conversion device according to a modified example of the first exemplary embodiment of the present disclosure. Components similar to those of the first exemplary embodiment are denoted by the same reference numerals. The description of such components may be omitted or simplified.

[0076] The modified example of the first exemplary embodiment differs from the first exemplary embodiment in the configuration of the pixel circuit. Figure 6 is an example of a circuit diagram of a pixel 10 included in the photoelectric conversion device according to the modified example.

[0077] As Figure 6 shown, the pixel 10 may include a transistor 456 (FD capacitance switching transistor 456) for switching the capacitance of the FD unit 420. For example, during a read period, the on / off state of the FD capacitance switching transistor 456 is switched at time t9 of Figure 4 by using a signal FDINC to change the capacitance of the FD unit 420. Here, the FD capacitance switching transistor 456 serves as a gain change unit (gain setting unit) for changing the capacitance of the FD unit 420. When outputting the first photoelectric conversion signal and the second photoelectric conversion signal, the FD capacitance switching transistor 456 switches the capacitance of the FD unit 420 accordingly.

[0078] Other capacitor elements may be connected to the FD unit 420 via transistors and the on / off states of the transistors may be switched to change the capacitance. The gain change unit enables pixel signals having different voltage conversion gains to be output to and held in the capacitor elements 121 and 122. By using signals with different voltage gains, an HDR image and an HDR moving image are obtained.

[0079] By further switching the resistance of the resistance element 240, an even higher gain can be set for the high-gain pixel signal output when the FD capacitance switching transistor 456 is turned off. In this case, a signal with an even higher dynamic range is obtained. By using such a signal with an even higher dynamic range, an HDR image and an HDR moving image are generated.

[0080] will refer to Figure 7 and Figure 8 describe a photoelectric conversion device according to a second exemplary embodiment of the present disclosure. Components similar to those in the first exemplary embodiment are denoted by the same reference numerals. The description of these components may be omitted or simplified.

[0081] This exemplary embodiment is different from the first exemplary embodiment in that a single pixel includes a plurality of photoelectric conversion units. Figure 7 is an example of a circuit diagram of a pixel 10 included in the photoelectric conversion device according to this exemplary embodiment. This exemplary embodiment is applicable to both a front-illuminated sensor and a back-illuminated sensor.

[0082] As Figure 7 shown, the pixel 10 further includes a photoelectric conversion unit 401 and a transfer transistor 411. An example of the photoelectric conversion unit 401 is a photodiode. One of the main electrodes of the photoelectric conversion unit 401 is connected to a reference voltage 450. The photoelectric conversion unit 401 photoelectrically converts the received light into charge (such as photoelectrons, etc.) having an amount corresponding to the amount of received light, and accumulates the charge.

[0083] The other main electrode of the photoelectric conversion unit 401 is electrically connected to the gate electrode of the amplification transistor 403 via the transfer transistor 411. The node 420 to which the gate electrode of the amplification transistor 430 is electrically connected serves as an FD. The FD section 420 serves as a charge-voltage conversion unit for converting the charge generated by the photoelectric conversion units 400 and 401 into a signal voltage. The pixel 10 is configured such that the photoelectric conversion units 400 and 401 share the FD section 420.

[0084] Considering that each pixel includes two photoelectric conversion units arranged in the column direction and one FD section, Figure 7 the pixel 10 of Figure 2 corresponds to two pixels 10 arranged in the column direction.

[0085] The transmission signal TXA is supplied to the gate electrode of the transfer transistor 410. In response to the transmission signal TXA, the transfer transistor 410 becomes conductive, whereby the charge accumulated in the photoelectric conversion unit 400 is transferred to the FD unit 420. The transmission signal TXB is supplied to the gate electrode of the transfer transistor 411. In response to the transmission signal TXB, the transfer transistor 411 becomes conductive, whereby the charge accumulated in the photoelectric conversion unit 401 is transferred to the FD unit 420.

[0086] In the present exemplary embodiment, the pixel signal output from the photoelectric conversion unit 400 is held in the capacitor element 121, and the pixel signal output from the photoelectric conversion unit 401 is held in the capacitor element 122. This configuration enables reading of two rows of pixel signals during a single read period to achieve faster reading.

[0087] The circuit configuration of the pixel 10 is not limited to Figure 7 the configuration shown. For example, the selection transistor 440 may be connected between the power supply voltage 460 and the amplification transistor 430. In the case where a single pixel column includes more than one vertical signal line 30, a single pixel 10 may include a plurality of selection transistors 440 connected to respective different vertical signal lines 30. In Figure 7 the configuration shown, the pixel 10 has a 4-transistor (4Tr.) configuration including transfer transistors 410 and 411, a reset transistor 455, an amplification transistor 430, and a selection transistor 440. However, this is not restrictive. For example, the pixel 10 may have a 3Tr. configuration in which the selection transistor 440 is omitted and the voltage of the node 420 is controlled to operate the amplification transistor 430 also as a selection transistor. The number of transistors may be increased to form a 5Tr. or higher-order configuration.

[0088] Figure 8 is an example of a driving timing chart showing the operation timings of the sampling and holding unit 50 and the conversion unit 60 included in the photoelectric conversion device according to the present exemplary embodiment. Figure 8 The horizontal axis of [the driving timing chart] represents time, and the vertical axis represents voltage. The control signal RES is a signal for resetting the pixel 10. The transmission signal TXA controls the signal reading from the photoelectric conversion unit 400, and the transmission signal TXB controls the signal reading from the photoelectric conversion unit 401. The control signals Smpa_n, Smp_n, Smpa_s, Smp_s1, Smp_s2, Hld_n, Hld_s, Hld_s1, and Hld_s2 control the switches in the first sampling and holding circuit 210 and the second sampling and holding circuit 211. In the following description, in Figure 8During the period when the waveform of the corresponding signal in [ ] is at a high level (for example, refer to the state of the waveform of the control signal RES between times t1 and t2), the switch will be described as being on, while during the period when the corresponding control signal is at a low level, the switch will be described as being off. The switch being on means that the input node and the output node of the switch are in a conducting state. On the other hand, the switch being off means that the input node and the output node of the switch are not in a conducting state.

[0089] From time t1 to t2, Figure 7 the control signal RES of [ ] goes high, and the reset transistor 455 turns on, thereby resetting the FD section 420. Figure 7 The control signal SEL shown is also controlled, whereby the voltage of the vertical signal line 30 is set to the reset level voltage Vn. At time t1, the control signals Smp_n and Smpa_n go high, and the switches 110 and 170 of the first sample and hold circuit 210 turn on. Next, at time t3 when the control signal Smpa_n changes from high to low, the reset level voltage Vn is sampled and accumulated in the capacitor element 120. At time t4, the control signal Smp_n changes from high to low, and the switch 110 turns off, whereby the capacitor element 120 is disconnected from the vertical signal line 30.

[0090] From time t5 to t6, Figure 7 the control signal TXA of [ ] goes high, and the transfer transistor 410 turns on. At the same time, the charge generated by the light incident between time t2 and time t6 in the photoelectric conversion unit 400 is transferred to the FD section 420. In other words, the period between time t2 and time t6 is the exposure period. The voltage of the FD section 420 decreases based on the amount of charge. In response to the control signal SEL, the voltage of the FD section 420 is output to the vertical signal line 30 via the amplification transistor 430.

[0091] The voltage of the vertical signal line 30 is thus set to the voltage Vs1 of the first photoelectric conversion signal. At time t5, the control signals Smp_s and Smpa_s1 go high, and the switches 111 and 171 in the second sample and hold circuit 211 for the photoelectric conversion signal turn on.

[0092] Next, at time t7 when the control signal Smpa_s changes from high to low, the switch 171 turns off, and the voltage Vs1 of the first photoelectric conversion signal is sampled and accumulated in the capacitor element 121. At time t8, the control signal Smp_s1 changes from high to low, and the switch 111 turns off, whereby the capacitor element 121 is disconnected from the vertical signal line 30.

[0093] When the switch 171 is turned off at time t7, the voltage across the switch 171 remains substantially the same regardless of the voltage of the vertical signal line 30. Therefore, the turn-off of the switch 171 does not cause any charge injection, and no error voltage appears for the voltage Vs1 of the first photoelectric conversion signal accumulated in the capacitor element 121. When the switch 111 is turned off at time t8, the capacitor element 121 is in a high-impedance state at both ends. Therefore, the turn-off of the switch 111 has no effect. In this way, the appearance of an error voltage for the voltage Vs1 of the first photoelectric conversion signal is prevented.

[0094] At times t9 to t10, Figure 7 the control signal TXB goes high and the transfer transistor 411 is turned on. At the same time, the charge generated by the light incident between times t2 and t10 in the photoelectric conversion unit 401 is transferred to the FD unit 420. The voltage of the FD unit 420 further drops based on the amount of charge. As a result, the voltage of the vertical signal line 30 drops to the voltage Vs2 of the second photoelectric conversion signal. At time t9, the control signals Smp_s and Smpa_s2 go high, and the switches 112 and 171 in the second sample-and-hold circuit 211 for the photoelectric conversion signal are turned on.

[0095] Next, at time t11 when the control signal Smpa_s changes from high to low, the voltage Vs2 of the second photoelectric conversion signal is sampled and accumulated in the capacitor element 122. At time t12, the control signal Smp_s2 changes from high to low, and the switch 112 is turned off, whereby the capacitor element 122 is disconnected from the vertical signal line 30. In short, the voltage Vs2 of the second photoelectric conversion signal based on the charge generated in the photoelectric conversion units 400 and 401 is accumulated in the capacitor element 122.

[0096] When the switch 171 is turned off at time t11, the voltage across the switch 171 remains substantially the same regardless of the voltage of the vertical signal line 30. Therefore, the turn-off of the switch 171 does not cause any charge injection, and no error voltage appears for the voltage Vs2 of the second photoelectric conversion signal accumulated in the capacitor element 122. In addition, when the switch 112 is turned off at time t12, the capacitor element 122 is in a high-impedance state at both ends. Therefore, the turn-off of the switch 112 has no effect. In this way, the appearance of an error voltage for the voltage Vs2 of the second photoelectric conversion signal is prevented.

[0097] At time t13, the control signal Hld_n goes high, and switches 180 and 190 are turned on, so that the capacitor element 120 in the first sample and hold circuit 210 outputs the voltage Vn of the reset level signal. At time t13, the control signals Hld_s1 and Hld_s go high, and switches 181 and 191 are also turned on, whereby the capacitor element 121 in the second sample and hold circuit 211 outputs the voltage Vs1 of the first photoelectric conversion signal.

[0098] As described above, the input current to the conversion unit 60 is a current based on the difference between the voltage Vn of the reset level signal at the output node of the first sample and hold circuit 210 and the voltage Vs1 of the photoelectric conversion signal at the output node of the second sample and hold circuit 211. The conversion unit 60 performs AD conversion on the current based on the difference between the voltages Vn and Vs1.

[0099] At time t14, the control signal Hld_s1 goes low, and switch 191 is turned off. Then, at time t15, the control signal Hld_s2 goes high and switch 192 is turned on, whereby the capacitor element 122 in the second sample and hold circuit 211 outputs the voltage Vs2 of the second photoelectric conversion signal.

[0100] As described above, the input current to the conversion unit 60 is a current based on the difference between the voltage Vn of the reset level signal at the output node of the first sample and hold circuit 210 and the voltage Vs2 of the photoelectric conversion signal at the output node of the second sample and hold circuit 211. The conversion unit 60 performs AD conversion on the current based on the difference between the voltages Vn and Vs2.

[0101] At time t16, the control signal Hld_n goes low, and switches 180 and 190 are turned off. At time t16, the control signal Hld_s also goes low, and switch 181 is turned off. At time 16, the control signal Hld_s2 also goes low, and switch 192 is turned off.

[0102] Here, the first photoelectric conversion signal corresponds to the charge generated by the photoelectric conversion unit 400, and the second photoelectric conversion signal corresponds to the charge generated by the photoelectric conversion units 400 and 401. In other words, the first photoelectric conversion signal is output from one of the plurality of photoelectric conversion units, and the second photoelectric conversion signal is output from the plurality of photoelectric conversion units. At time t16 or after time t16, a digital signal corresponding to the charge generated by the photoelectric conversion unit 401 is obtained by determining the difference between the digital signal corresponding to the current based on the difference between the voltages Vn and Vs1 and the digital signal corresponding to the current based on the difference between the voltages Vn and Vs2. The first photoelectric conversion signal may correspond to the charge generated by the photoelectric conversion unit 400, and the second photoelectric conversion signal may correspond to the charge generated by the photoelectric conversion unit 401. In other words, the first photoelectric conversion signal may be output from one of the plurality of photoelectric conversion units, and the second photoelectric conversion signal may be output from another one of the plurality of photoelectric conversion units.

[0103] As described above, according to the present exemplary embodiment, pixel signals corresponding to two rows of pixels are read during a unit read period to achieve a faster read operation. According to the pixel configuration, the image signal read during the unit read period may be an image signal corresponding to multiple rows of pixels or an image signal corresponding to multiple columns of pixels.

[0104] As described above, according to the present exemplary embodiment, the occurrence of error voltages for the first and second photoelectric conversion signals is prevented, thereby preventing image quality degradation.

[0105] The resistance element 240 electrically connected between the output node of the first sample-and-hold circuit 210 and the output node of the second sample-and-hold circuit 211 may be a variable resistance circuit. In other words, the output amplitude level of the signal input to the conversion unit 60 can be adjusted according to the resistance. In this case, the resistance element 240 serves as a gain setting unit. The resistance of the resistance element 240 changes between time t13 and t14 when the capacitor element 121 reads the voltage Vs1 of the first photoelectric conversion signal, and the resistance of the resistance element 240 changes between time t15 and t16 when the capacitor element 122 reads the voltage Vs2 of the second photoelectric conversion signal. Similar to the first exemplary embodiment, according to the present exemplary embodiment, a plurality of photoelectric conversion signals are read with different respective gains, and in operation, noise or power consumption is reduced.

[0106] Configurations for changing the gain in ways other than varying the resistance of the resistance element 240 can be employed. For example, the gain can be changed by varying the value of the current output from the current source 300. However, in the case of switching the value of the current output from the current source 300, after switching the current value, a certain amount of time is required for the current value to stabilize. Therefore, switching the resistance of the resistance element 240 enables faster signal processing compared to switching the value of the current output from the current source 300.

[0107] In the present exemplary embodiment, the capacitor elements 121 and 122 share the second sample-and-hold circuit 211, which enables reading of the first and second photoelectric conversion signals without increasing the operating power.

[0108] In the present exemplary embodiment, the first and second photoelectric conversion signals are read using the common resistance element 240. Thus, level fluctuations caused by temperature and process variations may similarly behave. This prevents the overlap of different variations on the first and second photoelectric conversion signals, thereby preventing deterioration of the signal quality.

[0109] In the present exemplary embodiment, the resistance element 240 for setting the gain when reading the first and second photoelectric conversion signals is located at the subsequent stage of the first sample-and-hold circuit 210 and the second sample-and-hold circuit 211. Even when the resistance of the resistance element 240 is set to be variable when reading each of the first and second photoelectric conversion signals, this configuration provides accurate CDS.

[0110] A microlens can be provided for one pixel 10 (i.e., a pair of photoelectric conversion units 400 and 401). In this case, the photoelectric conversion units 400 and 401 can be used as pixels for phase difference detection. By being used as pixels for phase difference detection, the photoelectric conversion units 400 and 401 enable focus detection of a subject. In this case, the foregoing first photoelectric conversion signal serves as an autofocus (AF) signal, and the second photoelectric conversion signal serves as an imaging signal. Even when the photoelectric conversion units 400 and 401 are used as pixels for phase difference detection, a plurality of photoelectric conversion signals are read with different respective gains. For example, the AF accuracy is improved by setting the gain for the first photoelectric conversion signal relatively high. However, if the resistance of the resistance element 240 is decreased to increase the gain, the current output to the conversion unit 60 may exceed the current value of the current source 300. If the current output to the conversion unit 60 exceeds the current value of the current source 300, the current output to the conversion unit 60 may exceed the range of the current value capable of performing AD conversion. The range of the output amplitude of the second photoelectric conversion signal obtained by two photoelectric conversion units is generally larger than the range of the output amplitude of the first photoelectric conversion signal obtained by one photoelectric conversion unit. Even if the current corresponding to the first photoelectric conversion signal with a certain gain does not exceed the range of the current value capable of performing AD conversion, the current corresponding to the second photoelectric conversion signal with substantially the same gain may exceed the range of the current value capable of performing AD conversion. Increasing the gain when reading the first photoelectric conversion signal and decreasing the gain when reading the second photoelectric conversion signal enables improvement of the AF accuracy while preventing the signal from exceeding the range of the current value capable of performing AD conversion. According to the present exemplary embodiment, a plurality of photoelectric conversion signals are read with different respective gains, and in operation, the AF accuracy is improved while preventing the signal from exceeding the range of the current value capable of performing AD conversion.

[0111] In Figure 7 , the photoelectric conversion units 400 and 401 can have different areas. The photoelectric conversion unit with a larger area and the photoelectric conversion unit with a smaller area store different amounts of charge. In other words, the photoelectric conversion unit with a larger area and the photoelectric conversion unit with a smaller area generate different amounts of charge for light incident in the same time period. Therefore, the photoelectric conversion units 400 and 401 output signals with different output amplitude ranges.

[0112] In Figure 7In [the device], pixel 10 may further include an FD capacitance switching transistor 456, and reads pixel signals having different voltage conversion gains by switching the on and off states of the FD capacitance switching transistor 456 during a pixel signal reading period. Even in this case, the photoelectric conversion units 400 and 401 output signals having respective different output amplitude ranges. This is achieved, for example, due to the difference in the thresholds of the reset transistor 455 and the FD capacitance switching transistor 456. When the reset transistor 455 has a relatively high threshold, the output amplitude range of the pixel signal having a lower voltage conversion gain increases as the FD capacitance switching transistor 456 is turned on. The reason is that the voltage of the FD section 420 drops from the reset level to an even lower level.

[0113] The third exemplary embodiment is applicable to both the first exemplary embodiment and the second exemplary embodiment. Figure 9A FIG. [number] is a schematic diagram of a device 9191 including a semiconductor device 930 according to the present exemplary embodiment. As the semiconductor device 930, an optoelectronic conversion device (imaging device) according to each of the above-described exemplary embodiments can be used. The device 9191 including the semiconductor device 930 will be described in detail. The semiconductor device 930 includes a semiconductor device 910. In addition to the semiconductor device 910, the semiconductor device 930 may include a package 920 that stores the semiconductor device 910. The package 920 includes a base member on which the semiconductor device 910 is fixed and a cover member such as glass facing the semiconductor device 910. The package 920 may further include a bonding member such as a bonding wire or a bump for connecting the terminals arranged in the base member and the terminals arranged in the semiconductor device 910.

[0114] The device 9191 includes at least any one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 supports the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror, and includes an optical system for guiding light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0115] The processing device 960 processes the signals output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or an ASIC for forming an analog front end (AFE) or a digital front end (DFE). The display device 970 is an electroluminescent (EL) display device or a liquid crystal display device that displays the information (image) obtained in the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores the information (image) obtained in the semiconductor device 930. The storage device 980 is a volatile memory such as a static RAM (SRAM) or a dynamic RAM (DRAM), or a non-volatile memory such as a flash memory or a hard disk drive.

[0116] The mechanical device 990 includes a moving unit or a propulsion unit such as a motor or an engine. In the device 9191, the signals output from the semiconductor device 930 are displayed on the display device 970 and transmitted to the outside through a communication device (not shown) included in the device 9191. In this configuration, in addition to the storage circuit and the calculation circuit included in the semiconductor device 930, the device 9191 further includes the storage device 980 and the processing device 960. The mechanical device 990 can be controlled based on the signals output from the semiconductor device 930.

[0117] The device 9191 is applicable to electronic devices such as information terminals having a camera function (e.g., a smart phone or a wearable terminal) or cameras (e.g., an interchangeable lens camera, a compact camera, a video camera, a surveillance camera). The mechanical device 990 in the camera drives the components of the optical device 940 for zooming, focusing, or shutter operation. Alternatively, the mechanical device 990 in the camera moves the semiconductor device 930 for image stabilization operation.

[0118] Examples of the device 9191 include transportation devices such as vehicles, ships, or aircraft (drones, airplanes, etc.). The mechanical device 990 in the transportation device can be used as a moving device. The device 9191 used as a transportation device is applicable to a device for transporting the semiconductor device 930, or a device that uses the camera function to assist in driving (maneuvering) and / or automate driving (maneuvering). The processing device 960 for assisting in driving (maneuvering) and / or automating driving (maneuvering) performs processing for operating the mechanical device 990 used as a moving device based on the information obtained in the semiconductor device 930. Alternatively, the device 9191 can be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analysis device such as an electron microscope, an office device such as a copier, or an industrial device such as a robot.

[0119] According to the above-described exemplary embodiments, pixel characteristics can be obtained. This enables an increase in the value of the semiconductor device. The increase in value corresponds to at least any one of an increase in functionality, an improvement in performance, an improvement in characteristics, an improvement in reliability, an improvement in manufacturing yield, a reduction in environmental burden, a reduction in cost, miniaturization, and weight reduction.

[0120] Therefore, the use of the semiconductor device 930 according to the present exemplary embodiment in the apparatus 9191 also enables an increase in the value of the apparatus 9191. For example, the transport apparatus equipped with the semiconductor device 930 achieves excellent performance in imaging the outside of the transport apparatus or measuring the external environment. Therefore, when manufacturing and selling the transport apparatus, it is determined that installing the semiconductor device according to the present exemplary embodiment on the transport apparatus is beneficial for improving the performance of the transport apparatus itself. The semiconductor device 930 is particularly suitable for a transport apparatus that uses the information obtained in the semiconductor device 930 for driving assistance and / or automatic operation of the transport apparatus.

[0121] Reference will be made to Figure 9B and Figure 9C to describe the photoelectric conversion system and the movable body according to the present exemplary embodiment.

[0122] Figure 9BAn example of an optoelectronic conversion system related to an in-vehicle camera is shown. The optoelectronic conversion system 8 includes an optoelectronic conversion device 80. The optoelectronic conversion device 80 is an optoelectronic conversion device (imaging device) according to any of the above exemplary embodiments. The optoelectronic conversion system 8 includes an image processing unit 801 and a parallax acquisition unit 802. The image processing unit 801 performs image processing on a plurality of image data acquired by the optoelectronic conversion device 80, and the parallax acquisition unit 802 calculates a parallax (phase difference between parallax images) based on the plurality of image data acquired by the optoelectronic conversion system 8. Here, the optoelectronic conversion system 8 may include an optical system (not shown) such as a lens, a shutter, or a mirror for guiding light to the optoelectronic conversion device 80. A plurality of optoelectronic conversion units approximately equivalent to the pupil of the optical system may be arranged in the pixels included in the optoelectronic conversion device 80. For example, a plurality of optoelectronic conversion units approximately equivalent to the pupil are arranged in a manner corresponding to one microlens. By receiving light beams at mutually different positions of the pupil of the optical system through the plurality of optoelectronic conversion units, the optoelectronic conversion device 80 outputs image data corresponding to the light beams that have passed through different positions. Then, the parallax acquisition unit 802 can use the output image data to calculate the parallax. The optoelectronic conversion system 8 further includes a distance acquisition unit 803 and a collision determination unit 804. The distance acquisition unit 803 calculates the distance to an object based on the calculated parallax, and the collision determination unit 804 determines whether a collision is likely to occur based on the calculated distance. In the present exemplary embodiment, the parallax acquisition unit 802 and the distance acquisition unit 803 serve as examples of a distance information acquisition unit for acquiring distance information related to the distance to an object. More specifically, the distance information is information related to the parallax, the defocus amount, and the distance to the object. The collision determination unit 804 can use any of this distance information to determine the collision possibility. The time-of-flight (ToF) technology can be used to acquire the distance information. The distance information acquisition unit can be implemented by specially designed hardware, or can be implemented by a software module. The distance information acquisition unit can be implemented by an FPGA or an ASIC, or can be implemented by a combination of these.

[0123] The photoelectric conversion system 8 is connected to the vehicle information acquisition device 810 and acquires vehicle information such as vehicle speed, yaw rate, or steering angle. The electronic control unit (ECU) 820 is connected to the photoelectric conversion system 8. The ECU 820 serves as a control device that outputs a control signal for generating braking force for the vehicle based on the judgment result obtained by the collision judgment unit 804. The photoelectric conversion system 8 is also connected to the alarm device 830, and the alarm device 830 issues an alarm to the driver based on the judgment result obtained by the collision judgment unit 804. For example, when the judgment result obtained by the collision judgment unit 804 indicates a high collision possibility, the control ECU 820 performs vehicle control for avoiding collision or reducing damage by braking, releasing the accelerator, or suppressing engine output. The alarm device 830 issues an alarm to the user by emitting an alarm such as a sound, displaying warning information on the screen of the car navigation system, or vibrating the seat belt or the steering wheel.

[0124] In the present exemplary embodiment, the photoelectric conversion system 8 captures images such as a front image or a rear image around the vehicle, for example.

[0125] Figure 9C A photoelectric conversion system for capturing a front image (imaging range 850) of the vehicle is shown. The vehicle information acquisition device 810 issues an instruction to the photoelectric conversion system 8 or the photoelectric conversion device 80. With this configuration, the accuracy of distance measurement is further improved.

[0126] The above has given a description of an example of performing control to avoid collision with other vehicles. The photoelectric conversion system is also applicable to control for automatically driving to follow other vehicles or control for automatically driving to avoid deviating from the lane. In addition, the photoelectric conversion system 8 is applicable not only to vehicles such as automobiles but also to moving bodies (mobile devices) such as ships, airplanes, or industrial robots. Furthermore, in addition to mobile bodies, the photoelectric conversion system can be adopted in devices that widely use object recognition such as intelligent transportation systems (ITS).

[0127] As used herein, expressions such as "A or B", "at least one of A and B", "at least one of A or / and B", "one or more than one of A or / and B", etc. cover all possible combinations of the listed items, unless otherwise clearly defined. That is, the above expressions are understood to disclose all of the following cases: the case including at least one A; the case including at least one B; and the case including both at least one A and at least one B. This also applies to combinations of three or more elements.

[0128] The above exemplary embodiments may be appropriately modified without departing from the technical idea. The disclosure of this specification includes not only the content described in this specification, but also all content that can be understood from this specification and the drawings of this specification. This disclosure also includes supplements to the concepts described herein. That is, for example, when the description "A is greater than B" is given in this specification, even if the description "A is not greater than B" is omitted, it can be considered that this specification discloses "A is not greater than B". This is because when describing "A is greater than B", the description is based on the premise of "A is not greater than B".

[0129] According to an exemplary embodiment of the present disclosure, noise or power consumption can be reduced when reading a signal from a pixel.

[0130] Although the present disclosure has been described with reference to exemplary embodiments, it should be understood that the present disclosure is not limited to the disclosed exemplary embodiments. The scope of the appended claims is to be accorded the broadest interpretation so as to encompass all such modifications as well as equivalent structures and functions.

Claims

1. A photoelectric conversion device, comprising: a pixel including a photoelectric conversion unit configured to accumulate charges based on incident light, the pixel being configured to output a photoelectric conversion signal based on the accumulated charges; a sampling and holding unit configured to sample and hold a first photoelectric conversion signal and a second photoelectric conversion signal output from the pixel; as well as an oversampling conversion unit configured to perform analog-to-digital conversion, i.e., AD conversion, on the first photoelectric conversion signal and the second photoelectric conversion signal output from the sampling and holding unit, In which, in the processing from when the first photoelectric conversion signal and the second photoelectric conversion signal are output from the pixel to when the first photoelectric conversion signal and the second photoelectric conversion signal are AD converted, the gain set for the first photoelectric conversion signal and the gain set for the second photoelectric conversion signal are different.

2. The photoelectric conversion device according to claim 1, wherein The first photoelectric conversion signal and the second photoelectric conversion signal have different output amplitude ranges.

3. The photoelectric conversion device according to claim 2, wherein: An output amplitude range of the first photoelectric conversion signal is narrower than an output amplitude range of the second photoelectric conversion signal, and a gain set for the first photoelectric conversion signal is higher than a gain set for the second photoelectric conversion signal.

4. The photoelectric conversion device according to claim 1, wherein The photoelectric conversion unit is configured to accumulate charges for different durations, and a duration for accumulating charges corresponding to the first photoelectric conversion signal and a duration for accumulating charges corresponding to the second photoelectric conversion signal are different from each other.

5. The photoelectric conversion device according to claim 4, in, a duration for accumulating charges corresponding to the first photoelectric conversion signal is shorter than a duration for accumulating charges corresponding to the second photoelectric conversion signal, and The gain set for the first photoelectric conversion signal is higher than the gain set for the second photoelectric conversion signal.

6. The photoelectric conversion device according to claim 1, wherein The oversampling conversion unit is configured to AD-convert respective differences of the first photoelectric conversion signal and the second photoelectric conversion signal with respect to a reset level signal of the photoelectric conversion unit.

7. The photoelectric conversion device according to claim 6, wherein The sample and hold unit includes a first sample and hold circuit configured to sample and hold the reset level signal, and a second sample and hold circuit configured to sample and hold each of the first photoelectric conversion signal and the second photoelectric conversion signal.

8. The photoelectric conversion device according to claim 7, wherein The first photoelectric conversion signal and the second photoelectric conversion signal are held in two corresponding capacitors included in the second sample and hold circuit.

9. The photoelectric conversion device according to claim 6, wherein: The reset level signal includes a first reset level signal corresponding to the first photoelectric conversion signal and a second reset level signal corresponding to the second photoelectric conversion signal, and a gain set for the first reset level signal and a gain set for the second reset level signal are different from each other.

10. The photoelectric conversion device according to claim 1, wherein The sample and hold unit includes an inverting amplifier, and the first photoelectric conversion signal and the second photoelectric conversion signal are output via the inverting amplifier.

11. The photoelectric conversion device according to claim 1, further comprising: a gain setting unit configured to set the gain, The gain setting unit is configured to set a gain for the first photoelectric conversion signal and a gain for the second photoelectric conversion signal respectively.

12. The photoelectric conversion device according to claim 11, wherein The gain setting unit is electrically connected between respective output nodes of a plurality of sample and hold circuits included in the sample and hold unit.

13. The photoelectric conversion device according to claim 11, in, The gain setting unit includes a variable resistance circuit, and The gain for the first photoelectric conversion signal and the gain for the second photoelectric conversion signal are respectively set by changing the resistance of the variable resistance circuit.

14. The photoelectric conversion device according to claim 1, in, The pixel includes a floating diffusion to which charges are input and a floating diffusion capacitance switching unit configured to switch the capacitance of the floating diffusion, and When the pixel outputs the first photoelectric conversion signal and the second photoelectric conversion signal, the corresponding capacitance of the floating diffusion portion is switched.

15. The photoelectric conversion device according to claim 1, in, The pixel includes a plurality of photoelectric conversion units, and The first photoelectric conversion signal is a photoelectric conversion signal output from one of the plurality of photoelectric conversion units, and the second photoelectric conversion signal is a photoelectric conversion signal output from another of the plurality of photoelectric conversion units.

16. The photoelectric conversion device according to claim 1, in, The pixel includes a plurality of photoelectric conversion units, and The first photoelectric conversion signal is a photoelectric conversion signal output from one photoelectric conversion unit among the plurality of photoelectric conversion units, and the second photoelectric conversion signal is a photoelectric conversion signal output from the plurality of photoelectric conversion units.

17. The photoelectric conversion device according to claim 15 or 16, wherein Micro lenses are arranged corresponding to the pixels, and the plurality of photoelectric conversion units are arranged corresponding to the micro lenses.

18. The photoelectric conversion device according to claim 15 or 16, wherein The plurality of photoelectric conversion units are configured to generate different amounts of charge for light incident in the same period.

19. The photoelectric conversion device according to claim 15 or 16, wherein The plurality of pixels are arranged in a row direction and a column direction, and the plurality of photoelectric conversion units are arranged in a column direction.

20. An apparatus comprising the photoelectric conversion device according to any one of claims 1 to 16, the apparatus further comprising at least one of the following devices: an optical device configured to direct light to the photoelectric conversion device; a control device configured to control the photoelectric conversion device; a processing device configured to process a signal output from the photoelectric conversion device; a display device configured to display the information obtained by the photoelectric conversion device; a storage device configured to store the information obtained by the photoelectric conversion device; as well as A mechanical device is configured to operate based on information obtained by the photoelectric conversion device.

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