Printed circuit board

Abstract

The present disclosure provides a printed circuit board including: an electronic component including a body, a plurality of metal pads disposed on the body to be spaced apart from each other, and a passivation layer covering a portion of each of the plurality of metal pads; and an insulating layer covering at least a portion of the electronic component. The passivation layer has a plurality of first openings exposing another portion of each of the plurality of metal pads and a plurality of second openings spaced apart from the plurality of metal pads, the plurality of second openings respectively passing through at least a portion of the passivation layer. The insulating layer is disposed in a portion of each of the plurality of first openings and in at least a portion of each of the plurality of second openings.

Description

[0001] This application claims the benefit of priority of Korean Patent Application No. 10-2023-0178390, filed with the Korean Intellectual Property Office on December 11, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] Recently, in order to improve electrical characteristics such as power integrity and achieve high integration, it has been required to embed integrated passive devices (IPDs) in printed circuit boards. However, when IPDs are simply embedded in printed circuit boards, various delamination phenomena may occur. Summary of the Invention

[0004] One aspect of the present disclosure provides a printed circuit board capable of improving delamination that may occur when embedding electronic components such as integrated passive devices (IPDs).

[0005] According to one aspect of the present disclosure, additional openings may be formed before and / or after embedding an electronic component (such as an IPD) in an insulating layer (such as an Ajinomoto build-up film (ABF)) of a board to expose the body of the electronic component from the passivation layer of the electronic component.

[0006] For example, a printed circuit board according to one aspect of the present disclosure may include: an electronic component including a body, a plurality of metal pads disposed on the body at intervals from each other, and a passivation layer covering a part of each of the plurality of metal pads; and an insulating layer covering at least a part of the electronic component. The passivation layer may have a plurality of first openings exposing another part of each of the plurality of metal pads and a plurality of second openings spaced apart from the plurality of metal pads, the plurality of second openings respectively passing through at least a part of the passivation layer. The insulating layer may be disposed in a part of each of the plurality of first openings and at least a part of each of the plurality of second openings.

[0007] According to another aspect of the present disclosure, roughness may be formed on the surfaces of a plurality of metal pads of an electronic component before and / or after embedding the electronic component in an insulating layer (such as ABF) of a board.

[0008] For example, a printed circuit board according to another aspect of the present disclosure may include: an IPD including a body, a plurality of copper pads disposed on the body at intervals from each other, and a polyimide film, at least a part of the polyimide film being disposed between two adjacent ones of the plurality of copper pads on the body, the polyimide film covering a part of the upper surface and at least a part of the side surface of each of the plurality of copper pads; and an ABF covering a part of the upper surface of each of the plurality of copper pads and at least a part of the polyimide film. The surface roughness of the part of the upper surface of each of the plurality of copper pads covered by the ABF may be greater than the surface roughness of at least a part of the lower surface of each of the plurality of copper pads in contact with the body.

[0009] For example, a printed circuit board according to another aspect of the present disclosure may include: an electronic component including a body, a metal pad disposed on the body, and a passivation layer covering a part of the metal pad; an insulating layer covering at least a part of the electronic component; a wiring layer disposed on the insulating layer; and a connection via disposed in the insulating layer to connect the wiring layer and the metal pad to each other. The passivation layer may have an opening exposing a part of the upper surface of the metal pad. The surface roughness of the part of the upper surface of the metal pad exposed through the opening of the passivation layer and in contact with the insulating layer and the connection via may be greater than the surface roughness of the part of the lower surface of the metal pad in contact with the body.

[0010] The printed circuit board according to an exemplary embodiment of the present disclosure may improve delamination that may occur when embedding an electronic component such as an IPD. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood by combining the accompanying drawings and the following detailed description, in which: Figure 1 is a schematic block diagram of an example of an electronic device system; Figure 2 is a schematic perspective view of an example of an electronic device; Figure 3 is a schematic cross-sectional view of a printed circuit board according to an example; Figures 4A to 4C is Figure 3 a schematic enlarged cross-sectional view of various examples of region A of the printed circuit board; Figures 5A to 5G is for manufacturing Figure 3 a schematic cross-sectional view of an example of the printed circuit board; Figure 6is a schematic cross-sectional view of a printed circuit board according to another example; Figures 7A to 7C is Figure 6 a schematic enlarged cross-sectional view of various examples of region B of the printed circuit board; Figure 8 is a schematic cross-sectional view of a printed circuit board according to another example; and Figures 9A to 9C is Figure 8 a schematic enlarged cross-sectional view of various examples of region C of the printed circuit board. DETAILED DESCRIPTION

[0012] Hereinafter, example embodiments of the present disclosure are described with reference to the accompanying drawings. For a clearer description, the shapes and sizes of components in the drawings may be exaggerated or reduced.

[0013] Electronic device

[0014] Figure 1 is a schematic block diagram of an example of an electronic device system.

[0015] Referring to Figure 1 , the electronic device 1000 may house a main board 1010. The chip-related components 1020, network-related components 1030, and other components 1040 may be physically and / or electrically connected to the main board 1010. Such components may be connected to other electronic components described below via various signal lines 1090.

[0016] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM) or flash memory); application processor chips, such as a central processor (e.g., central processing unit (CPU)), a graphics processor (e.g., graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller; and logic chips, such as an analog-to-digital converter or an application-specific integrated circuit (ASIC). However, the chip-related components 1020 are not limited thereto, and may include other types of chip-related components. Additionally, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and / or electronic components.

[0017] The network-related components 1030 may include components that are compatible with or operate according to protocols such as: Wi-Fi (IEEE 802.11 series, etc.), WiMAX (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High-Speed Packet Access Plus (HSPA+), High-Speed Downlink Packet Access Plus (HSDPA+), High-Speed Uplink Packet Access Plus (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (Wireless LAN), 3rd Generation Mobile Communication Technology (3G) protocol, 4th Generation Mobile Communication Technology (4G) protocol, and 5th Generation Mobile Communication Technology (5G) protocol, as well as any other wireless and wired protocols specified after the above protocols. However, the network-related components 1030 are not limited thereto, and may also include components that are compatible with or operate according to various other wireless or wired standards or protocols. Additionally, the network-related components 1030 may be combined with each other together with the above chip-related components 1020.

[0018] The other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, Low Temperature Co-fired Ceramic (LTCC) components, Electromagnetic Interference (EMI) filters, Multi-Layer Ceramic Capacitors (MLCCs), etc. However, the other components 1040 are not limited thereto, and may also include passive components for various other purposes. Additionally, the other components 1040 may be combined with each other together with the above chip-related components 1020 and / or network-related components 1030.

[0019] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the main board 1010 or not physically and / or not electrically connected to the main board 1010. The other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. However, the other electronic components are not limited thereto, and may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a Compact Disc (CD), a Digital Versatile Disc (DVD), etc. Additionally, depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0020] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television set, a video game console, a smart watch, an automotive component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device for processing data.

[0021] Figure 2 FIG. is a schematic perspective view of an example of an electronic device.

[0022] Referring to Figure 2 , the electronic device may be, for example, the smart phone 1100. The main board 1110 may be accommodated in the smart phone 1100, and various electronic components 1120 may be physically and / or electrically connected to the main board 1110. In addition, other components (such as the camera module 1130 and / or the speaker 1140) that are physically and / or electrically connected to the main board 1110 or not physically and / or not electrically connected to the main board 1110 may be accommodated in the smart phone 1100. A part of the electronic components 1120 may be the above-mentioned chip-related components (e.g., the component package 1121), but the present disclosure is not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components (including active components and / or passive components) are surface-mounted. The electronic device does not have to be limited to the smart phone 1100 and may be other electronic devices as described above.

[0023] Printed circuit board

[0024] Figure 3 FIG. is a schematic cross-sectional view of a printed circuit board according to an example.

[0025] Figures 4A to 4C is Figure 3 a schematic enlarged cross-sectional view of various examples of region A of the printed circuit board of

[0026] Referring to Figures 3 to 4C, the printed circuit board 100A according to the example may include: an insulating layer 110; a wiring layer 120 disposed on or in the insulating layer 110; a via layer 130 disposed in the insulating layer 110; and an electronic component 150 disposed in the insulating layer 110 (e.g., at least a part of the insulating layer 110 covering the electronic component 150). For example, the printed circuit board 100A may have a board structure with the electronic component 150 embedded therein. The electronic component 150 may include: a main body 151; a plurality of metal pads 152 disposed on the main body 151 at intervals from each other; and a passivation layer 153 covering a part of each of the plurality of metal pads 152. The passivation layer 153 may have: a plurality of first openings h1 exposing a part of each of the plurality of metal pads 152 from the passivation layer 153; and a plurality of second openings h2 spaced apart from the plurality of metal pads 152, the plurality of second openings h2 respectively passing through at least a part of the passivation layer 153. The plurality of second openings h2 may respectively pass through at least a part of the passivation layer 153 located between two adjacent ones of the plurality of metal pads 152. For example, the plurality of second openings h2 may respectively pass through the passivation layer 153 until a part of the main body 151 is exposed from the passivation layer 153. The plurality of second openings h2 may respectively have various forms on a plane, such as grooves, holes, etc. At least two of the plurality of second openings h2 may be connected to each other. The insulating layer 110 may fill a part of the first openings h1 and at least a part of the second openings h2.

[0027] Recently, the market for large-area, high-specification server packaging boards is expanding. In connection with this, it is conceivable to embed integrated passive devices (IPDs) in a board (e.g., a printed circuit board) to manufacture a differentiated high-performance board with improved power integrity properties through reduced impedance. However, the surface of the copper pads of the IPD is usually relatively smooth or has a small roughness (the roughness is close to zero). When a process using a liquid chemical is performed while manufacturing the board, the liquid chemical can penetrate through the vias formed in the IPD. In addition, more severe gaps may be formed at the bottom of the vias. As a result, a lifting phenomenon may occur at the interface between the copper pad of the IPD and the insulating layer of the board, at the interface between the copper pad of the IPD and the polyimide film protecting the copper pad, at the interface of the edge region of the polyimide film, etc. Conversely, in the exemplary printed circuit board 100A, a plurality of second openings h2 may be formed in the passivation layer 153 provided on the main body 151 of the electronic component 150 (e.g., the IPD), and the insulating layer 110 may fill at least a part of each of the plurality of second openings h2. In this case, by filling the plurality of second openings h2 with the insulating layer 110, the adhesion between the plurality of metal pads 152 and the insulating layer 110 and / or the adhesion between the plurality of metal pads 152 and the passivation layer 153 can be improved. Therefore, even when the electronic component 150 is embedded in the printed circuit board 100A (e.g., in an IPD-embedded board including a plurality of copper pads and a polyimide film protecting the copper pads), the above-mentioned delamination problem, etc. can be improved. As a result, the exemplary printed circuit board 100A and the product including it can have improved reliability.

[0028] The passivation layer 153 may cover a part of the upper surface and at least a part of the side surface of each metal pad 152. For example, as Figure 4A shown, the passivation layer 153 may be located between two adjacent metal pads 152 among the plurality of metal pads 152 and may cover the edge portion of each metal pad 152 located between its upper surface and side surface. In this case, if necessary, roughness may be formed on the surface of the plurality of metal pads 152. For example, as Figure 4B shown, the surface roughness of the portion of the upper surface of each of the plurality of metal pads 152 exposed from the passivation layer 153 may be greater than the surface roughness of the lower surface of each of the plurality of metal pads 152 in contact with the main body 151 (e.g., the surface roughness of at least a part of the lower surface). For example, as Figure 4CAs shown, the surface roughness of at least a part of the upper surface of each of the plurality of metal pads 152 (the upper surface includes a plurality of portions respectively covered by the passivation layer 153, the insulating layer 110, and the via layer 130) and / or at least a part of the side surface (the side surface is covered by the passivation layer 153) can be greater than the surface roughness of the lower surface of each of the plurality of metal pads 152 that contacts the main body 151 (for example, the surface roughness of at least a part of the lower surface). In this case, due to the increase in the surface area of the plurality of metal pads 152, the adhesion between the plurality of metal pads 152 and the insulating layer 110 and / or the adhesion between the plurality of metal pads 152 and the passivation layer 153 can be further improved. Therefore, even when the electronic component 150 is embedded in the printed circuit board 100A (for example, in an IPD embedded board including a polyimide film with a plurality of copper pads and protective copper pads), the above-mentioned delamination problem and the like can be more effectively improved. As a result, the printed circuit board 100A according to the example and the product including the printed circuit board 100A can have improved reliability. The surface roughness can be formed during the manufacture of the electronic component 150, for example, during the manufacture of a single IPD, but the present disclosure is not limited thereto. For example, Figure 4B the surface roughness shown in can be formed during the embedding process, as will be described below.

[0029] The printed circuit board 100A according to the example can be applied as at least a part of a multilayer circuit board. For example, the printed circuit board 100A can be applied to the central part of the multilayer circuit board. In this case, a stacking process can be further performed on one or both sides of the printed circuit board 100A. The multilayer circuit board can be used as a flip chip board (FCB), a ball grid array (BGA) board, an interposer, a package board, etc., but the present disclosure is not limited thereto and can be applied to various other types of boards.

[0030] Hereinafter, the components of the printed circuit board 100A according to the example will be described in more detail with reference to the drawings.

[0031] The insulating layer 110 may include a first insulating layer 111 and a second insulating layer 112. The first insulating layer 111 has a through-hole H in which at least a part of the electronic component 150 is disposed. The second insulating layer 112 covers at least a part of each of the first insulating layer 111 and the electronic component 150, and the second insulating layer 112 fills at least a part of the through-hole H. The first insulating layer 111 may be a core layer, and the second insulating layer 112 may be a stacked layer, but the present disclosure is not limited thereto. Each of the first insulating layer 111 and the second insulating layer 112 may be formed of a plurality of insulating layers. The through-hole H may pass through the space between the upper surface and the lower surface of the first insulating layer 111, or may only pass through a part of the first insulating layer 111 from the upper surface of the first insulating layer 111 as needed. For example, the through-hole H may be a through cavity or a blind cavity. A stacked insulating layer may be further provided on the second insulating layer 112. The first insulating layer 111 and the second insulating layer 112 may include an inorganic insulating material and / or an organic insulating material. As a non-limiting example, both the first insulating layer 111 and the second insulating layer 112 may include an organic insulating material. Alternatively, the first insulating layer 111 may include an inorganic insulating material, and the second insulating layer 112 may include an organic insulating material. However, the present disclosure is not limited thereto. The organic insulating material may include a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material prepared by impregnating an inorganic filler, an organic filler, and / or glass fiber in a resin. For example, the organic insulating material may be a copper-clad laminate (CCL), a prepreg (PPG), ABF, a photosensitive dielectric (PID), etc., but the present disclosure is not limited thereto. The inorganic insulating material may include a glass plate, a silicon plate, and / or a ceramic plate. For example, the glass plate may include glass. The glass may include, for example, pure silica (about 100% SiO 2 ), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. However, the present disclosure is not limited thereto, and alternative glass materials such as fluorine glass, phosphate glass, chalcogenide glass, etc. may also be used as the material of the glass plate. Additionally, other additives may be further included to form a glass plate having specific physical properties. The above additives may be magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, as well as carbonates and / or oxides of the above elements, and the above additives may further include other elements. For example, the above additives may be lime (including calcium carbonate) and / or soda (including sodium carbonate). The glass may be distinguished from the glass fiber (e.g., a glass fabric exemplified by a glass cloth) included in the organic insulating material. Additionally, the silicon plate may include a silicon (Si) layer, and an oxide layer may be formed on the silicon (Si) layer as needed. Additionally, the silicon plate may include a nitride layer formed on the oxide layer. The oxide layer may include a silicon oxide film, and the nitride layer may include a silicon nitride film, but the present disclosure is not limited thereto. Additionally, the ceramic plate may include ceramics, and the ceramics may include, for example, alumina (Al 2 O3 ), aluminum nitride (AlN), silicon carbide (SiC), silicon nitride (Si 3 N 4 ), etc., but the present disclosure is not limited thereto.

[0032] The wiring layer 120 may include: a first wiring layer 121 disposed on the upper surface of the second insulating layer 112; a second wiring layer 122 disposed on the lower surface of the second insulating layer 112; a third wiring layer 123 disposed on the upper surface of the first insulating layer 111, and the third wiring layer 123 is at least partially embedded in the second insulating layer 112; and a fourth wiring layer 124 disposed on the lower surface of the first insulating layer 111, and the fourth wiring layer 124 is at least partially embedded in the second insulating layer 112. When the insulating layer 110 further includes a stacked insulating layer, the wiring layer 120 may further include a stacked wiring layer. The first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may each include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or their alloys. Preferably, the metal may be copper (Cu), but the present disclosure is not limited thereto. The first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may each perform various functions according to their designs. For example, they may respectively include signal patterns, power patterns, ground patterns, etc. These patterns may each have various forms, such as lines, planes, pads, etc. The first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may each include a seed layer and a plating layer formed on the seed layer. The seed layer may be an electroless plating layer (e.g., electroless copper plating layer) and / or a sputtering layer, and the plating layer may be an electrolytic plating layer (e.g., electrolytic copper plating layer), but the present disclosure is not limited thereto.

[0033] The via layer 130 may include a first via layer 131, a second via layer 132, and a third via layer 133. The first via layer 131 includes a plurality of first connection vias 131a respectively passing through a part of the second insulating layer 112 and a plurality of second connection vias 131b respectively passing through a part of the second insulating layer 112. Each of the plurality of first connection vias 131a connects each of the plurality of metal pads 152 to at least a part of the first wiring layer 121, and each of the plurality of second connection vias 131b connects at least a part of the first wiring layer 121 and at least a part of the third wiring layer 123 to each other; the second via layer 132 includes a plurality of third connection vias 132a respectively passing through a part of the second insulating layer 112, and the plurality of third connection vias 132a connect at least a part of the second wiring layer 122 and at least a part of the fourth wiring layer 124 to each other; the third via layer 133 includes a plurality of through vias 133a respectively passing through the first insulating layer 111, and the plurality of through vias 133a connect at least a part of the third wiring layer 123 and at least a part of the fourth wiring layer 124 to each other. In the case where the insulating layer 110 further includes a stacked insulating layer, the via layer 130 may further include a stacked via layer. The first via layer 131, the second via layer 132, and the third via layer 133 may respectively include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or their alloys. Preferably, the metal may be copper (Cu), but the present disclosure is not limited thereto. The first via layer 131, the second via layer 132, and the third via layer 133 may respectively include filled vias filling via holes or through holes, or may respectively include conformal vias disposed along the wall surfaces of the via holes or through holes. The first via layer 131, the second via layer 132, and the third via layer 133 may each perform various functions according to their designs. For example, they may respectively include ground vias, power vias, signal vias, etc. The first via layer 131, the second via layer 132, and the third via layer 133 may respectively include an electroless plating layer (e.g., electroless copper plating layer) and an electrolytic plating layer (e.g., electrolytic copper plating layer). A sputtering layer may be formed instead of the electroless plating layer (e.g., electroless copper plating layer), or may include both a sputtering layer and an electroless plating layer (e.g., electroless copper plating layer). Each of the plurality of first connection vias 131a and each of the plurality of second connection vias 131b may have a tapered shape in cross section, and the width of the upper end of the tapered shape is greater than the width of the lower end. Each of the plurality of third connection vias 132a may have a tapered shape in cross section, and the width of the lower end of the tapered shape is greater than the width of the upper end. The plurality of through vias 133a may have an hourglass shape in cross section. Optionally, the plurality of through vias 133a may have substantially vertical side surfaces in cross section and may have a columnar shape such as a cylinder, an elliptical cylinder, and a rectangular column, but the present disclosure is not limited thereto.The filling material may be disposed in each of a plurality of via holes or a plurality of through holes for forming the plurality of through vias 133a, and the filling material may include an insulating material or a conductive material.

[0034] The electronic component 150 may include an active component and / or a passive component. The electronic component 150 may be a chip component and may include, for example, an integrated circuit (IC) in which hundreds to millions of devices are integrated in a single chip. For example, the electronic component 150 may be formed based on an active wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as the substrate material included in the body 151. Various circuits may be formed in the body 151. A plurality of metal pads 152 may be formed on the body 151, and the plurality of metal pads 152 may each include a conductive material such as aluminum (Al), copper (Cu), etc. For example, the plurality of metal pads 152 may each include a copper pad. A passivation layer 153 for protecting the plurality of metal pads 152 may be formed on the body 151, and the passivation layer 153 may include an organic insulating film and / or an inorganic insulating film. For example, the passivation layer 153 may include a polyimide film. The passivation layer 153 may have a plurality of first openings h1 that respectively expose the plurality of metal pads 152 and a plurality of second openings h2 that respectively expose the body 151. Preferably, the electronic component 150 may be, for example, an IPD, but the present disclosure is not limited thereto. The metal pad 152 may have an inclined side surface such that the width of the upper end of the metal pad 152 is greater than the width of the lower end of the metal pad 152.

[0035] Figures 5A to 5G is an example of a method of manufacturing Figure 3 a printed circuit board.

[0036] Referring to Figure 5A a first insulating layer 111 may be prepared. The first insulating layer 111 may be a CCL, but the present disclosure is not limited thereto. Subsequently, via holes may be formed in the first insulating layer 111 using a method such as mechanical drilling, laser drilling, chemical etching, etc. Subsequently, a third wiring layer 123 and a fourth wiring layer 124 may be formed on the first insulating layer 111 and a third via layer 133 may be formed in the first insulating layer 111 using a plating process.

[0037] Referring to Figure 5B, a through-hole H can be formed in the first insulating layer 111 by methods such as mechanical drilling, laser drilling, chemical etching, etc. Subsequently, the tape 210 can be attached to the lower side of the first insulating layer 111. For example, the third wiring layer 123 can be attached to the tape 210. The tape 210 can include an adhesive containing epoxy resin, but the present disclosure is not limited thereto. Subsequently, the electronic component 150 (e.g., IPD) can be disposed face-down in the through-hole H of the first insulating layer 111 using the tape 210. For example, the passivation layer 153 can be attached to the tape 210. Optionally, a plurality of metal pads 152 can be attached to the tape 210.

[0038] Referring to Figure 5C , a second-first insulating layer 112-1 covering the first insulating layer 111 and the electronic component 150 can be formed. The second-first insulating layer 112-1 can be formed by laminating an insulating material such as ABF. The second-first insulating layer 112-1 can fill at least a part of the through-hole H. The second-first insulating layer 112-1 can be in an intermediate curing state.

[0039] Referring to Figure 5D , the tape 210 can be removed. The tape 210 can be removed using a physical method. As needed, the tape 210 can be removed using a chemical method. When the tape 210 is removed, a plurality of metal pads 152 and the passivation layer 153 of the electronic component 150 can be exposed from the second-first insulating layer 112-1.

[0040] Referring to Figure 5E , a plurality of second openings h2 can be formed in the exposed passivation layer 153 using laser drilling, chemical etching, etc. As needed, surface treatment can be used to form roughness on the surfaces of the plurality of exposed metal pads 152. In this case, as described above, due to the increase in the surface area, the delamination problem can be improved.

[0041] Referring to Figure 5F , a second-second insulating layer 112-2 covering the second-first insulating layer 112-1 and the electronic component 150 can be formed. The second-second insulating layer 112-2 can be formed by laminating an insulating material such as ABF on the side of the electronic component 150 opposite to the side where the second-first insulating layer 112-1 is formed. The second-second insulating layer 112-2 can cover the exposed passivation layer 153 and the plurality of exposed metal pads 152. For example, the second-second insulating layer 112-2 can fill at least a part of each of the plurality of first openings h1 and at least a part of each of the plurality of second openings h2. After lamination, the second-first insulating layer 112-1 and the second-second insulating layer 112-2 can be in a cured state and can be integrated with each other such that the interface between them may not be easily distinguishable. Thus, the second insulating layer 112 can be formed.

[0042] Referring toFigure 5G A method such as mechanical drilling, laser drilling, chemical etching, etc. can be used to process vias in the second insulating layer 112, and a plating process can be performed to form the first wiring layer 121, the second wiring layer 122, the first via layer 131, and the second via layer 132.

[0043] A series of processes can be used to fabricate the printed circuit board 100A according to the example, and other content can be substantially the same as that described in connection with the printed circuit board 100A according to the example, so repeated descriptions will be omitted.

[0044] Figure 6 is a schematic cross-sectional view of a printed circuit board according to another example.

[0045] Figures 7A to 7C is Figure 6 a schematic enlarged cross-sectional view of various examples of region B of the printed circuit board.

[0046] Referring to Figures 6 to 7C , compared with the printed circuit board 100A, in the printed circuit board 100B according to another example, each of the side surfaces of two adjacent metal pads 152 among the plurality of metal pads 152 may have a recess r that is recessed toward the inside of each metal pad 152. For example, the separation distance between the recesses r on the side surfaces of two adjacent metal pads 152 among the plurality of metal pads 152 may be greater than the separation distance between the upper ends of two adjacent metal pads 152 and / or the separation distance between the lower ends of two adjacent metal pads 152. In this case, the adhesion between the plurality of metal pads 152 and the passivation layer 153 can be further improved by an anchoring effect or the like. Therefore, even when the electronic component 150 is embedded in the printed circuit board 100B (for example, an IPD embedded board including a polyimide film having a plurality of copper pads and protective copper pads), the above-mentioned delamination problem and the like can be more effectively improved. Therefore, the printed circuit board 100B according to another example and products including the same can have further improved reliability. The recess r can be formed when manufacturing the electronic component 150, for example, when manufacturing a single IPD.

[0047] In the printed circuit board 100B according to another example, the passivation layer 153 can cover a part of the upper surface and at least a part of the side surface of each of the plurality of metal pads 152. For example, as Figure 7A shown, the passivation layer 153 can cover the edge portion of each metal pad 152 located between the upper surface and the side surface, and can be located between two adjacent metal pads 152 among the plurality of metal pads 152. In this case, if necessary, roughness can be formed on the surface of the plurality of metal pads 152. For example, as Figure 7BAs shown, the surface roughness of the portion of the upper surface of each of the plurality of metal pads 152 that is exposed from the passivation layer 153 may be greater than the surface roughness of the lower surface of each of the plurality of metal pads 152 that contacts the body 151 (e.g., the surface roughness of at least a portion of the lower surface). For example, as Figure 7C shown, the surface roughness of at least a portion of the upper surface of each of the plurality of metal pads 152 (the upper surface includes a plurality of portions respectively covered by the passivation layer 153, the insulating layer 110, and the via layer 130) and / or at least a portion of the side surface of each of the plurality of metal pads 152 that includes the recess r (the side surface is covered by the passivation layer 153) may also be greater than the surface roughness of the lower surface of each of the plurality of metal pads 152 that contacts the body 151 (e.g., the surface roughness of at least a portion of the lower surface). In this case, due to the increase in the surface area of the plurality of metal pads 152, the adhesion between the plurality of metal pads 152 and the insulating layer 110 and / or the adhesion between the plurality of metal pads 152 and the passivation layer 153 can be further improved. Therefore, even when the electronic component 150 is embedded in the printed circuit board 100B (e.g., in an IPD embedded board including a plurality of copper pads and a polyimide film that protects the plurality of copper pads), the above-mentioned delamination problem and the like can be more effectively improved. As a result, the printed circuit board 100B according to another example and the product including the same can have further improved reliability. The surface roughness may be formed during the manufacture of the electronic component 150. For example, it may be formed during the manufacture of a single IPD, but the present disclosure is not limited thereto. For example, Figure 7B the surface roughness shown may be formed during the embedding process.

[0048] Other contents may be substantially the same as those described in connection with the printed circuit board 100A according to the example and the method of manufacturing the printed circuit board 100A, and thus the repeated description will be omitted.

[0049] Figure 8 is a schematic cross-sectional view of a printed circuit board according to another example.

[0050] Figures 9A to 9C is Figure 8 a schematic enlarged cross-sectional view of various examples of region C of the printed circuit board of

[0051] Referring to Figures 8 to 9C, compared with the printed circuit board 100A, in the printed circuit board 100C according to another example, each of the side surfaces of two adjacent metal pads 152 among the plurality of metal pads 152 may have a protrusion p protruding toward the passivation layer 153. For example, the separation distance between the protrusions p on the side surfaces of two adjacent metal pads 152 among the plurality of metal pads 152 may be less than the separation distance between the upper ends of two adjacent metal pads 152 and / or the separation distance between the lower ends of two adjacent metal pads 152. In this case, the adhesion between the plurality of metal pads 152 and the passivation layer 153 can be further improved by an anchoring effect or the like. Therefore, even when the electronic component 150 is embedded in the printed circuit board 100C (for example, an IPD including a plurality of copper pads and a polyimide film protecting the plurality of copper pads is embedded in the board), the above-mentioned delamination problem and the like can be more effectively improved. Therefore, the printed circuit board 100C according to another example and a product including the same can have further improved reliability. The protrusion p can be formed when manufacturing the electronic component 150, for example, can be formed when manufacturing a single IPD.

[0052] In the printed circuit board 100C according to another example, the passivation layer 153 may cover a part of the upper surface and at least a part of the side surface of each of the plurality of metal pads 152. For example, as Figure 9A shown, the passivation layer 153 may cover the edge portion of each metal pad 152 located between the upper surface and the side surface, and may be located between two adjacent metal pads 152 among the plurality of metal pads 152. In this case, if necessary, roughness can be formed on the surface of the plurality of metal pads 152. For example, as Figure 9B shown, the surface roughness of the portion of the upper surface of each of the plurality of metal pads 152 exposed from the passivation layer 153 may be greater than the surface roughness of the lower surface of each of the plurality of metal pads 152 in contact with the main body 151 (for example, the surface roughness of at least a part of the lower surface). For example, as Figure 9CAs shown, at least a part of the upper surface of each of the plurality of metal pads 152 (the upper surface includes a plurality of portions respectively covered by a passivation layer 153, an insulating layer 110, and a via layer 130) and / or at least a part of the surface of the side surface of each of the plurality of metal pads 152 including the protrusion p (the side surface is covered by the passivation layer 153) may also have a surface roughness greater than the surface roughness of the lower surface of each of the plurality of metal pads 152 that contacts the main body 151 (e.g., the surface roughness of at least a part of the lower surface). In this case, due to the increase in the surface area of the plurality of metal pads 152, the adhesion between the plurality of metal pads 152 and the insulating layer 110 and / or the adhesion between the plurality of metal pads 152 and the passivation layer 153 can be further improved. Therefore, even when the electronic component 150 is embedded in the printed circuit board 100C (e.g., in an IPD embedded board including a plurality of copper pads and a polyimide film protecting the copper pads), the above-mentioned delamination problem and the like can be more effectively improved. As a result, the printed circuit board 100C according to another example and a product including the same can have further improved reliability. The surface roughness can be formed during the manufacturing of the electronic component 150. For example, it can be formed during the manufacturing of a single IPD, but the present disclosure is not limited thereto. For example, Figure 9B the surface roughness shown in may be formed during the embedding process.

[0053] Other contents may be substantially the same as those described in connection with the printed circuit board 100A according to the example and the method of manufacturing the printed circuit board 100A, and thus repeated descriptions will be omitted.

[0054] As used herein, the term "cover" may include complete covering as well as partial covering, and may include direct covering as well as indirect covering. Additionally, the terms "fill", "to fill", and "filled" may include not only complete filling but also substantially filling, for example, may include cases where there are some voids, holes, etc. Additionally, the term "surround" may include not only complete surrounding but also substantially surrounding. Additionally, "exposed" may include not only completely exposing a structure but also exposing a part of a structure, and "exposed" may mean exposing a component from another component in which the component is buried. For example, another component may be provided on the exposed component. In this case, the meaning of exposed is the same.

[0055] As used herein, it may include process errors or positional deviations that occur during the manufacturing process, errors during measurement, etc. For example, "substantially perpendicular" may include not only "completely perpendicular" but also "substantially perpendicular". Additionally, "substantially coplanar" may include not only "completely coplanar" but also "substantially coplanar".

[0056] As used herein, a "cross-section" or "cross-sectional view" may refer to the cross-sectional shape of an object when the object is vertically cut, or the shape of the object when viewed from a side view angle. Additionally, a "plane" or "plan view" may be the shape of the object when the object is horizontally cut, or the planar shape of the object when viewed from a top view angle or a bottom view angle.

[0057] As used herein, for ease of description, the upper side, upper portion, upper surface, etc. are used to refer to the direction of the surface of the cross-section based on the drawing towards which an electronic component can be mounted, and the lower side, lower portion, lower surface, etc. are used to refer to the opposite direction. However, the above directions are defined for ease of description. Therefore, it should be understood that the scope of the claims is not particularly limited by the above directions, and the concepts of "upper" and "lower" can change at any time.

[0058] As used herein, the term "connected" can refer not only to "directly connected" but also include "indirectly connected" by means of an adhesive layer or the like. The term "electrically connected" can include both cases where components are "physically connected" and cases where components are "not physically connected". Additionally, terms such as "first", "second", etc. can be used to distinguish one component from another component, and may not limit the order and / or importance, etc. related to the components. In some cases, without departing from the scope of the exemplary embodiments, the first component can be referred to as the second component, and similarly, the second component can be referred to as the first component.

[0059] As used herein, "through" can mean not only passing completely through the space between the upper surface and the lower surface of an object in the thickness direction or the stacking direction, but also passing through a part from the upper surface of the object in a recessed form or a blind cavity form or passing through a part from the lower surface of the object.

[0060] As used herein, thickness, width, length, depth, line width, interval, pitch, separation distance, surface roughness, etc. can be measured using a scanning electron microscope or an optical microscope based on a cross-section obtained by polishing or cutting a printed circuit board. The cross-section can be a vertical cross-section or a horizontal cross-section, and each value can be measured based on the desired cross-section. For example, the width of the upper end and / or the width of the lower end of a via can be measured in a cross-section taken along the central axis of the via. When these values are not constant, these values can be determined as the average of the values measured at five arbitrary points.

[0061] As used herein, the term "exemplary embodiment" is provided to emphasize a specific feature, structure, or characteristic, and does not necessarily refer to the same exemplary embodiment. Additionally, a specific characteristic or feature can be combined in any suitable manner in one or more exemplary embodiments. For example, unless described as being contrary to or inconsistent with the content in other exemplary embodiments, the content described in a specific exemplary embodiment can be used in other exemplary embodiments even if not described in other exemplary embodiments.

[0062] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the disclosure. As used herein, unless the context clearly dictates otherwise, the singular forms are also intended to include the plural forms.

[0063] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the disclosure defined by the appended claims.

Claims

1. A printed circuit board, comprising: An electronic component including a body, a plurality of metal pads disposed on the body to be spaced apart from each other, and a passivation layer covering a portion of each of the plurality of metal pads; as well as an insulating layer covering at least a portion of the electronic component, wherein the passivation layer has a plurality of first openings exposing another portion of each of the plurality of metal pads and a plurality of second openings spaced apart from the plurality of metal pads, the plurality of second openings respectively passing through at least a portion of the passivation layer, and The insulating layer is disposed in a portion of each of the plurality of first openings and in at least a portion of each of the plurality of second openings.

2. The printed circuit board according to claim 1, wherein: The at least a portion through which the plurality of second openings of the passivation layer respectively pass is located between two adjacent metal pads among the plurality of metal pads.

3. The printed circuit board according to claim 2, wherein: The plurality of second openings respectively expose a portion of the body.

4. The printed circuit board according to claim 1, wherein: The passivation layer covers a portion of an upper surface and at least a portion of a side surface of each of the plurality of metal pads.

5. The printed circuit board according to claim 4, wherein: Another portion of an upper surface of each of the plurality of metal pads exposed from the passivation layer has a surface roughness greater than a surface roughness of a lower surface of each of the plurality of metal pads contacting the body.

6. The printed circuit board according to claim 5, wherein: The surface roughness of the portion of the upper surface of each of the plurality of metal pads covered by the passivation layer and the at least portion of the side surface covered by the passivation layer is greater than the surface roughness of the lower surface of each of the plurality of metal pads in contact with the body.

7. The printed circuit board according to claim 4, wherein: A side surface of each of two adjacent metal pads among the plurality of metal pads has a concave portion that is concave toward an interior of a corresponding metal pad among the two adjacent metal pads.

8. The printed circuit board according to claim 7, wherein: A separation distance between the recessed portions on the side surfaces of the two adjacent metal pads among the plurality of metal pads is greater than a separation distance between upper ends of the two adjacent metal pads and / or a separation distance between lower ends of the two adjacent metal pads.

9. The printed circuit board according to claim 4, wherein: A side surface of each of two adjacent metal pads among the plurality of metal pads has a protrusion protruding toward the passivation layer.

10. The printed circuit board according to claim 9, wherein: A separation distance between the protrusions on the side surfaces of the two adjacent metal pads among the plurality of metal pads is smaller than a separation distance between upper ends of the two adjacent metal pads and / or a separation distance between lower ends of the two adjacent metal pads.

11. The printed circuit board according to claim 1, further comprising: a wiring layer, disposed on or in the insulating layer; as well as A via layer is provided in the insulating layer, The via layer includes a plurality of first connection vias respectively passing through at least a portion of the insulating layer and located on the plurality of first openings, and the plurality of first connection vias respectively connect each of the plurality of metal pads to at least a portion of the wiring layer.

12. The printed circuit board according to claim 11, wherein The insulating layer includes a first insulating layer and a second insulating layer, the first insulating layer having a through portion, at least a portion of the electronic component being disposed in the through portion, the second insulating layer covering at least a portion of each of the first insulating layer and the electronic component, the second insulating layer being disposed in at least a portion of the through portion, The wiring layer includes: a first wiring layer, which is arranged on the upper surface of the second insulating layer; a second wiring layer, which is arranged on the lower surface of the second insulating layer; a third wiring layer, which is arranged on the upper surface of the first insulating layer, and the third wiring layer is at least partially buried in the second insulating layer; and a fourth wiring layer, which is arranged on the lower surface of the first insulating layer, and the fourth wiring layer is at least partially buried in the second insulating layer, and The via layer includes: a first via layer, including the plurality of first connection vias respectively passing through a portion of the second insulating layer and the plurality of second connection vias respectively passing through a portion of the second insulating layer, the plurality of first connection vias respectively connecting each of the plurality of metal pads to at least a portion of the first wiring layer, and the plurality of second connection vias respectively connecting at least a portion of the first wiring layer and at least a portion of the third wiring layer to each other; a second via layer, including the plurality of third connection vias respectively passing through a portion of the second insulating layer, the plurality of third connection vias connecting at least a portion of the second wiring layer and at least a portion of the fourth wiring layer to each other; and a third via layer, including the plurality of through vias respectively passing through the first insulating layer, the plurality of through vias respectively connecting at least a portion of the third wiring layer and at least a portion of the fourth wiring layer to each other.

13. The printed circuit board according to claim 1, wherein: The electronic components include integrated passive devices, The plurality of metal pads each include copper, and The passivation layer includes polyimide.

14. A printed circuit board, comprising: An integrated passive device, comprising a body, a plurality of copper pads disposed on the body to be spaced apart from each other, and a polyimide film, at least a portion of the polyimide film being disposed between two adjacent copper pads of the plurality of copper pads on the body, the polyimide film covering a portion of an upper surface and at least a portion of a side surface of each of the plurality of copper pads; as well as an Ajinomoto deposited film covering a portion of the upper surface of each of the plurality of copper pads and at least a portion of the polyimide film, Wherein, the surface roughness of the portion of the upper surface of each of the multiple copper pads covered by the Ajinomoto deposited film is greater than the surface roughness of at least a portion of the lower surface of each of the multiple copper pads in contact with the main body.

15. The printed circuit board according to claim 14, wherein: The surface roughness of the portion of the upper surface of each of the multiple copper pads covered by the polyimide film and the at least portion of the side surface covered by the polyimide film is greater than the surface roughness of the at least portion of the lower surface of each of the multiple copper pads in contact with the body.

16. The printed circuit board according to claim 14, wherein: The at least a portion of the side surface of each of the plurality of copper pads covered by the polyimide film has a concave portion concave toward the inside of the corresponding copper pad of the plurality of copper pads or has a protruding portion protruding toward the polyimide film.

17. A printed circuit board, comprising: An electronic component includes a body, a metal pad disposed on the body, and a passivation layer covering a portion of the metal pad; an insulating layer covering at least a portion of the electronic component; A wiring layer, disposed on the insulating layer; as well as a connecting via provided in the insulating layer to connect the wiring layer and the metal pad to each other, wherein the passivation layer has an opening exposing a portion of the upper surface of the metal pad, The portion of the upper surface of the metal pad exposed through the opening of the passivation layer and in contact with the insulating layer and the connection via has a surface roughness greater than a surface roughness of a portion of the lower surface of the metal pad in contact with the body.

18. The printed circuit board according to claim 17, wherein: The passivation layer covers another portion of the upper surface of the metal pad and at least a portion of the side surface of the metal pad.

19. The printed circuit board according to claim 18, wherein The other portion of the upper surface of the metal pad covered by the passivation layer has a surface roughness greater than a surface roughness of the portion of the lower surface of the metal pad in contact with the body.

20. The printed circuit board according to claim 18, wherein The other portion of the upper surface of the metal pad covered by the passivation layer and the at least a portion of the side surface of the metal pad covered by the passivation layer have surface roughness greater than the surface roughness of the portion of the lower surface of the metal pad in contact with the body.

21. The printed circuit board according to claim 17, wherein The metal pad has an inclined side surface such that a width of an upper end of the metal pad is greater than a width of a lower end of the metal pad.

22. The printed circuit board according to claim 17, wherein: There are protrusions on the side surfaces of two adjacent metal pads, respectively, so that the distance between the protrusions of the two adjacent metal pads is smaller than the distance between the lower ends of the two adjacent metal pads and / or the distance between the upper ends of the two adjacent metal pads.

23. The printed circuit board according to claim 17, wherein: There are respectively recessed portions on the side surfaces of two adjacent metal pads, so that the distance between the recessed portions of the two adjacent metal pads is greater than the distance between the lower ends of the two adjacent metal pads and / or the distance between the upper ends of the two adjacent metal pads.

24. The printed circuit board according to claim 17, wherein: The insulating layer includes a first insulating layer and a second insulating layer, the first insulating layer having a through portion in which at least a portion of the electronic component is disposed, and the second insulating layer covers at least a portion of each of the first insulating layer and the electronic component, and The second insulating layer is disposed in at least a portion of the through-portion and in the opening of the passivation layer to contact the metal pad.

25. The printed circuit board according to claim 24, wherein The electronic components include integrated passive devices, The metal pad comprises copper, The passivation layer includes polyimide, and The second insulating layer includes an Ajinomoto deposited film.

Images