A three-dimensional ferroelectric memory array and methods of making and operating the same

Abstract

The application discloses a three-dimensional ferroelectric memory array and a preparation method and an operating method thereof, and belongs to the technical field of microelectronics and integrated circuits. The three-dimensional ferroelectric memory array comprises memory cells which are arranged in a vertical direction and a horizontal direction on a substrate, and each memory cell comprises, from left to right or from right to left in the horizontal direction, a gate metal layer, a first isolation layer, a ferroelectric material layer, a floating gate metal layer, a second isolation layer and a channel layer. The application adds the floating gate metal layer in the ferroelectric NAND Flash memory, can homogenize the electric field distribution between the ferroelectric material layer and the channel layer, reduces the local electric field change caused by the non-ferroelectric phase, effectively shields the influence of the non-ferroelectric phase in the ferroelectric material layer on the threshold voltage, reduces the fluctuation of the threshold voltage, and increases the stored logic states.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of microelectronics and integrated circuits, and particularly relates to a three-dimensional ferroelectric memory array and a preparation method and an array operation method thereof. BACKGROUND

[0002] With the continuous progress of process technology, the number of stacked layers of 3D NAND Flash is gradually increased, and the density of the memory is continuously improved. However, with the increase of the number of stacked layers, the existing etching process becomes more and more difficult to meet the production needs, especially in the preparation process of the memory above the thousand layer level, how to effectively control the etching precision and the height of each layer has become a major challenge. In order to continue to increase the number of stacked layers to improve the storage density, it is necessary to reduce the height of each layer.

[0003] However, the operating voltage of the existing 3D NAND Flash is high, when the height of each layer is thinned, the interference between adjacent cells increases, which makes the storage performance and reliability of the device decline. As a new storage technology, ferroelectric NAND (FeNAND) has a lower operating voltage and can be stacked at a lower height, which has become one of the potential alternatives for thousand-layer NAND Flash. The characteristics of ferroelectric material enable FeNAND to work stably at low voltage, but the phase distribution inside the ferroelectric layer will cause the threshold voltage of the device to fluctuate, thereby reducing the storage window and affecting the stability of data reading and writing. SUMMARY

[0004] The purpose of the present application is to propose a three-dimensional ferroelectric memory array and a preparation method and an operation method thereof, which shield the influence of the non-ferroelectric region inside the ferroelectric material layer on the threshold voltage of the device, improve the distribution, and increase the storage logic state of the three-dimensional NAND Flash.

[0005] The technical solutions of the present application are as follows:

[0006] A three-dimensional ferroelectric NAND Flash memory array, characterized in that it comprises memory cells arranged in a vertical direction and a horizontal direction on a substrate, the memory cells are sequentially arranged from left to right or from right to left along the horizontal direction as a gate metal layer, a first isolation layer, a ferroelectric material layer, a floating gate metal layer, a second isolation layer and a channel layer, wherein the floating gate metal layer serves as a conductive layer for uniform electric field distribution between the ferroelectric material layer and the channel layer, and an isolation medium layer is arranged between the gate metal layers or the channel layers of adjacent memory cells.

[0007] Preferably, the gate metal layer and floating gate metal layer material is generally one or more of aluminum Al, tungsten W, titanium Ti, cobalt Co, gold Au, tantalum Ta, platinum Pt, ruthenium Ru, nickel Ni, or an alloy of the above materials, or titanium nitride TiN, indium oxide In2O3, indium tin oxide ITO, indium zinc oxide InZnO x and other metal oxides, or tungsten silicide WSi x , cobalt silicide CoSi x , graphite and other low resistivity materials. The gate metal layer height is 10-40 nm, and the floating gate metal layer thickness is 5-10 nm.

[0008] Preferably, the ferroelectric material layer material is generally a doped hafnium oxide system, such as hafnium zirconium oxide HfZrO x , hafnium silicon oxide HfSiO x , hafnium aluminum oxide HfAlO x , hafnium lanthanum oxide HfLaO x , and aluminum nitride AlN, aluminum scandium nitride AlScN x and other ferroelectric materials. The ferroelectric material layer thickness is 5-20 nm.

[0009] Preferably, the first and second isolation layers, the isolation medium layer material is generally silicon oxide SiO2, silicon nitride Si3N4, aluminum oxide Al2O3, niobium pentoxide Nb2O5, hafnium oxide HfO2, silicon oxynitride SiO x N y , or phosphorus-silicon glass PSG, boron-phosphorus-silicon glass BPSG and other electrically insulating materials. The first and second isolation layer thickness is 5-20 nm, and the isolation medium layer thickness is 10-30 nm.

[0010] Preferably, the channel layer material is generally single crystal silicon, polycrystalline silicon, silicon germanium alloy SiGe, silicon carbide SiC, gallium arsenide GaAs, gallium nitride GaN, or indium gallium zinc oxide IGZO, indium oxide In2O3, tungsten-doped indium oxide IWO, indium zinc oxide InZnO x , indium gallium oxide InGaO x and other oxide semiconductor materials, or transition metal sulfides such as molybdenum disulfide MoS2, molybdenum diselenide MoSe2, tungsten diselenide WSe2, tungsten disulfide WS2 and other two-dimensional materials. The channel layer thickness is 5-30 nm.

[0011] The present application further provides a preparation method of a three-dimensional ferroelectric memory array, the steps of which include the following:

[0012] 1) sequentially depositing a multilayer isolation layer / sacrificial layer stack on a substrate;

[0013] 2) forming a trench region by lithography and etching;

[0014] 3) etching to remove the sacrificial layer;

[0015] 4) growing a gate metal layer to fill the original sacrificial layer position;

[0016] 5) growing a first isolation layer, a ferroelectric material layer, a floating gate metal layer, a second isolation layer and a growth protection layer along the sidewall in sequence;

[0017] 6) etching to remove the second isolation layer, the floating gate metal layer, the ferroelectric material layer and the first isolation layer at the bottom of the trench, and etching to remove the sidewall protection layer;

[0018] 7) growing a channel layer;

[0019] 8) growing an isolation medium layer to fill the trench, and planarizing.

[0020] Further, a method for preparing a three-dimensional ferroelectric memory array is provided, and the steps include the following:

[0021] 1) sequentially depositing a plurality of isolation medium layer / gate metal layer stacks on a substrate;

[0022] 2) forming a trench region by photolithography and etching;

[0023] 3) growing a first isolation layer, a ferroelectric material layer, a floating gate metal layer, a second isolation layer along the sidewall in sequence, and growing a protection layer;

[0024] 4) etching to remove the second isolation layer, the floating gate metal layer, the ferroelectric material layer and the first isolation layer at the bottom of the trench, and etching to remove the sidewall protection layer;

[0025] 5) growing a channel layer;

[0026] 6) growing an isolation medium layer to fill the trench, and planarizing.

[0027] Further, a method for preparing a three-dimensional ferroelectric memory array is provided, and the steps include the following:

[0028] 1) sequentially depositing a plurality of isolation medium layer / sacrificial layer stacks on a substrate;

[0029] 2) forming a trench region by photolithography and etching;

[0030] 3) growing a first isolation layer, a ferroelectric material layer, a floating gate metal layer, a second isolation layer along the sidewall in sequence, and growing a protection layer;

[0031] 4) etching to remove the second isolation layer, the floating gate metal layer, the ferroelectric material layer and the first isolation layer at the bottom of the trench, and etching to remove the sidewall protection layer;

[0032] 5) growing a channel layer;

[0033] 6) Growth of isolation dielectric layer to fill the trench and planarization;

[0034] 7) Etching of the sacrificial layer;

[0035] 8) Growth of gate metal layer to fill the original position of the sacrificial layer.

[0036] The present application further provides a method for operating the ferroelectric NAND Flash memory array as follows:

[0037] 1) Programming: the bit line where the selected memory cell is located is applied with 0V voltage, the bit line where the unselected memory cell is applied with inhibition voltage, all source lines are grounded, the word line where the selected memory cell is located is applied with programming voltage, and the word line where the unselected memory cell is applied with conducting voltage;

[0038] 2) Erasing: all bit lines and all word lines are applied with 0V voltage, the source line where the selected memory cell is applied with erasing voltage, and the whole string is erased;

[0039] 3) Reading: the bit line where the selected memory cell is located is applied with reading voltage, the bit line where the unselected memory cell is applied with 0V voltage, all source lines are grounded, the word line where the selected memory cell is applied with 1V voltage, and the word line where the unselected memory cell is voltage floating, the bit line current of the selected memory cell is read and compared with the reference current.

[0040] The present application has the following advantages:

[0041] The memory device structure in the FeNAND Flash memory array of the present application is sequentially arranged from left to right (from right to left) as the gate metal layer, the first isolation layer, the ferroelectric material layer, the floating gate metal layer, the second isolation layer, the channel layer and the isolation dielectric layer, wherein the ferroelectric material layer has unevenly distributed ferroelectric phase, anti-ferroelectric phase and paraelectric phase, only the ferroelectric phase has the non-volatile storage function. The non-ferroelectric phase region does not have spontaneous polarization characteristics and usually has low dielectric constant, and the uneven distribution of the ferroelectric material layer and the non-ferroelectric region will affect the distribution of the gate electric field, thereby affecting the threshold voltage. The floating gate metal layer as the conductive layer can homogenize the electric field distribution between the ferroelectric material layer and the channel, reduce the local electric field change caused by the non-ferroelectric phase, effectively shield the influence of the non-ferroelectric phase in the ferroelectric material layer on the threshold voltage, reduce the fluctuation of the threshold voltage, and increase the number of stored logic states. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 The present application is a schematic diagram of a ferroelectric NAND Flash memory structure;

[0043] Figure 2 The present application is a flow chart for preparing a ferroelectric NAND Flash string;

[0044] Figures 3-10 This is a cross-sectional view of the ferroelectric NAND Flash string fabrication process according to Embodiment 1 of the present invention;

[0045] Figure 11 for Figures 1-10 Legend;

[0046] Figure 12 This is a schematic diagram of the ferroelectric NAND Flash string array topology of the present invention. Detailed Implementation

[0047] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0048] It should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.

[0049] like Figure 1 As shown in the figure, a specific embodiment of the present invention is a three-dimensional ferroelectric NAND Flash memory. It is a device structure stacked vertically, with each memory layer consisting of a gate metal layer TiN, a first isolation layer SiO2, and a ferroelectric layer HfZrO from left to right. x The memory cell has a floating gate metal layer TiN, a second isolation layer SiO2, and a channel layer Si. The ferroelectric material layer between the first isolation layer and the floating gate metal layer has a non-ferroelectric phase region with uneven distribution. The floating gate metal layer serves as a conductive layer to uniformly distribute the electric field between the ferroelectric material layer and the channel layer. An isolation dielectric layer is provided between the gate metal layers or between the channel layers of adjacent memory cells.

[0050] The preparation process of the String in this invention is as follows: Figure 2 As shown, the specific steps include the following:

[0051] 1) A multilayer SiO2 isolation layer / Si3N4 sacrificial layer stack is sequentially deposited on the substrate, wherein the isolation layer is grown by chemical vapor deposition of 20 nm SiO2, and the sacrificial layer is grown by chemical vapor deposition of 20 nm Si3N4, such as... Figure 3 As shown;

[0052] 2) Trench regions are formed through photolithography and etching, such as... Figure 4 As shown;

[0053] 3) Etching removes the sacrificial layer Si3N4, such as... Figure 5 As shown;

[0054] 4) Physical vapor deposition to grow gate metal layer TiN, filling the original sacrificial layer position, as shown in Figure 6

[0055] 5) Along the sidewall, sequentially grow 5nm first isolation layer SiO2, 10nm ferroelectric material layer HfZrO x , 5nm floating gate metal layer TiN, 5nm second isolation layer SiO2, and grow protective layer Si3N4, wherein the first and second isolation layers and the protective layer are grown by chemical vapor deposition, and the ferroelectric material layer and the floating gate metal layer are grown by atomic layer deposition, as shown in Figure 7

[0056] 6) Vertical dry etching to remove the second isolation layer, floating gate metal layer, ferroelectric material layer, and first isolation layer at the bottom of the trench, and etching to remove the sidewall protective layer, as shown in Figure 8

[0057] 7) Chemical vapor deposition to grow 10nm polycrystalline silicon channel, as shown in Figure 9

[0058] 8) Chemical vapor deposition to grow isolation medium layer SiO2 to fill the trench, and chemical mechanical polishing for planarization, as shown in Figure 10

[0059] The present application further provides another preparation process, comprising the following steps:

[0060] 1) Sequentially deposit multiple interlayer isolation layer / gate metal layer stacks on the substrate, wherein the interlayer isolation layer is grown by plasma chemical vapor deposition to 20nm of Si3N4, and the gate metal layer is grown by physical vapor deposition to 20nm of TiN;

[0061] 2) Form the trench area filled with ferroelectric material layer and channel layer, etc. by lithography and etching;

[0062] 3) Along the sidewall, sequentially grow 5nm first isolation layer SiO2, 10nm ferroelectric material layer HfZrO x , 5nm floating gate metal layer TiN, 5nm second isolation layer SiO2, and grow protective layer Si3N4, wherein the first and second isolation layers and the protective layer are grown by chemical vapor deposition, and the ferroelectric material layer and the floating gate metal layer are grown by atomic layer deposition;

[0063] 4) Vertical dry etching to remove the second isolation layer, floating gate metal layer, ferroelectric material layer, and first isolation layer at the bottom of the trench, and etching to remove the sidewall protective layer;

[0064] 5) Chemical vapor deposition to grow 10nm polycrystalline silicon channel;

[0065] ​​​​​6) SiO2 was grown by chemical vapor deposition to fill the trenches, and planarization was performed by chemical mechanical polishing.

[0066] The present invention further provides another preparation method, the specific steps of which are as follows:

[0067] 1) A multilayer SiO2 isolation layer / Si3N4 sacrificial layer stack is sequentially deposited on the substrate, wherein the isolation layer is grown by chemical vapor deposition of 20nm SiO2 and the sacrificial layer is grown by chemical vapor deposition of 20nm Si3N4.

[0068] 2) Trench regions filled with ferroelectric material layers and channel layers are formed by photolithography and etching;

[0069] 3) A 5nm first isolation layer of SiO2 and a 10nm ferroelectric material layer of HfZrO are sequentially grown along the sidewall. x A 5nm floating gate metal layer TiN, a 5nm second isolation layer SiO2, and a protective layer Si3N4 are grown. The first and second isolation layers and the protective layer are grown by chemical vapor deposition, while the ferroelectric material layer and the floating gate metal layer are grown by atomic layer deposition.

[0070] 4) Vertical dry etching is used to remove the second isolation layer, floating gate metal layer, ferroelectric material layer and first isolation layer at the bottom of the trench, and etching is used to remove the sidewall protective layer;

[0071] 5) A 10nm polysilicon channel is grown using chemical vapor deposition;

[0072] 6) The trenches were filled with a SiO2 isolation medium layer grown by chemical vapor deposition and planarized by chemical mechanical polishing;

[0073] 7) Etching removes the sacrificial layer Si3N4;

[0074] 8) A gate metal layer TiN is grown by physical vapor deposition to fill the original sacrificial layer position.

[0075] The topology of the String array in this invention is as follows: Figure 12 As shown, the array operation method is as follows:

[0076] Programming: Taking programming the first cell of the first string as an example, apply 0V to bit line BL1, apply 2.5V suppression voltage to bit lines BL2 and BL3, ground all source lines, and apply programming voltage V to word line WL1. program (4V), a conduction voltage V is applied to word lines WL2 and WL3. pass (2V);

[0077] Erase: Taking the erasure of the first string as an example, apply 0V voltage to all bit lines and all word lines, and apply erase voltage V to source line SL1. erase(4V), source lines SL2 and SL3 apply 0V voltage;

[0078] Read: taking the first cell of the first string as an example, bit line BL1 applies read voltage V read (0.2-2V), bit line BL2 and BL3 apply 0V voltage, word line WL1 applies 1V voltage, word line WL2 and WL3 are floating, and all source lines are grounded. If the current of bit line BL1 is higher than reference current I ref , the data information stored in the first cell is "1"; if the current of bit line BL1 is lower than reference current I ref , the data information stored in the first cell is "0".

[0079] Although the present application has been disclosed with reference to the preferred embodiments, it is not intended to limit the present application. Any person skilled in the art, without departing from the scope of the present application, can make many possible changes and modifications to the present application, or modify equivalent embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments, without departing from the scope of the present application, are still within the scope of the present application.

Claims

1. A method of fabricating a three-dimensional ferroelectric memory array, comprising: The three-dimensional ferroelectric memory array includes memory cells arrayed in vertical and horizontal directions on a substrate, the memory cells in horizontal direction from left to right or from right to left are gate metal layer, first isolation layer, ferroelectric material layer, floating gate metal layer, second isolation layer and channel layer in turn, wherein the floating gate metal layer is used as a conductive layer to uniform the electric field distribution between the ferroelectric material layer and the channel layer, and isolation medium layers are arranged between the gate metal layers or the channel layers of adjacent memory cells, and the steps include the following: 1) depositing a plurality of isolation medium layer / sacrificial layer stacks on the substrate in turn; 2) forming a trench area by lithography and etching; 3) etching to remove the sacrificial layer; 4) growing the gate metal layer to fill the position of the original sacrificial layer; 5) growing the first isolation layer, the ferroelectric material layer, the floating gate metal layer, the second isolation layer and the growth protection layer in turn along the side wall; 6) etching to remove the second isolation layer, the floating gate metal layer, the ferroelectric material layer and the first isolation layer at the bottom of the trench, and etching to remove the side wall protection layer; 7) growing the channel layer; 8) growing the isolation medium layer to fill the trench, and performing planarization.

2. A method of fabricating a three-dimensional ferroelectric memory array, comprising: The three-dimensional ferroelectric memory array includes memory cells arrayed in vertical and horizontal directions on a substrate, the memory cells in horizontal direction from left to right or from right to left are gate metal layer, first isolation layer, ferroelectric material layer, floating gate metal layer, second isolation layer and channel layer in turn, wherein the floating gate metal layer is used as a conductive layer to uniform the electric field distribution between the ferroelectric material layer and the channel layer, and isolation medium layers are arranged between the gate metal layers or the channel layers of adjacent memory cells, and the steps include the following: 1) depositing a plurality of isolation medium layer / gate metal layer stacks on the substrate in turn; 2) forming a trench area by lithography and etching; 3) growing the first isolation layer, the ferroelectric material layer, the floating gate metal layer, the second isolation layer and the growth protection layer in turn along the side wall; 4) etching to remove the second isolation layer, the floating gate metal layer, the ferroelectric material layer and the first isolation layer at the bottom of the trench, and etching to remove the side wall protection layer; 5) growing the channel layer; 6) growing the isolation medium layer to fill the trench, and performing planarization.

3. A method of fabricating a three-dimensional ferroelectric memory array, comprising: The three-dimensional ferroelectric memory array includes memory cells arrayed in vertical and horizontal directions on a substrate, the memory cells in horizontal direction from left to right or from right to left are gate metal layer, first isolation layer, ferroelectric material layer, floating gate metal layer, second isolation layer and channel layer in turn, wherein the floating gate metal layer is used as a conductive layer to uniform the electric field distribution between the ferroelectric material layer and the channel layer, and isolation medium layers are arranged between the gate metal layers or the channel layers of adjacent memory cells, and the steps include the following: 1) depositing a plurality of isolation medium layer / sacrificial layer stacks on the substrate in turn; 2) forming a trench area by lithography and etching; 3) growing the first isolation layer, the ferroelectric material layer, the floating gate metal layer, the second isolation layer and the growth protection layer in turn along the side wall; 4) etching to remove the second isolation layer, the floating gate metal layer, the ferroelectric material layer and the first isolation layer at the bottom of the trench, and etching to remove the side wall protection layer; 5) growing the channel layer; 6) growing the isolation medium layer to fill the trench, and performing planarization. 7) etching to remove the sacrificial layer; 8) growing a gate metal layer to fill the location of the original sacrificial layer.

4. The method of claim 1, 2 or 3, wherein The material of the gate metal layer and the floating gate metal layer is one or more of aluminum Al, tungsten W, titanium Ti, cobalt Co, gold Au, tantalum Ta, platinum Pt, ruthenium Ru, nickel Ni, or an alloy of the above materials, or titanium nitride TiN, indium oxide In2O3, indium tin oxide ITO, indium zinc oxide InZnO x Metal oxide, or tungsten silicide WSi x Cobalt silicide CoSi x Graphite material, the thickness of the floating gate metal layer is 5-10 nm, and the thickness of the gate metal layer is 10-40 nm.

5. The method of claim 1, 2, or 3, wherein, The ferroelectric material layer is hafnium-zirconium oxide HfZrO x hafnium-silicon oxide HfSiO x hafnium-aluminum oxide HfAlO x hafnium-lanthanum oxide HfLaO x and aluminum nitride AlN, aluminum scandium nitride AlScN x The ferroelectric material layer has a thickness of 5-20 nm.

6. The method of claim 1, 2, or 3, wherein, The material of the first, second isolation layer and isolation medium layer is silicon oxide SiO2, silicon nitride Si3N4, aluminum oxide Al2O3, niobium pentoxide Nb2O5, hafnium oxide HfO2, silicon oxynitride SiO x N y , or phosphorus silicon glass PSG, boron phosphorus silicon glass BPSG electric insulating material, the thickness of the first, second isolation layer is 5-20nm, and the thickness of the isolation layer is 10-30nm.

7. The method of claim 1, 2, or 3, wherein, The channel layer material is monocrystalline silicon, polycrystalline silicon, silicon germanium alloy SiGe, silicon carbide SiC, gallium arsenide GaAs, gallium nitride GaN, or indium gallium zinc oxide IGZO, indium oxide In2O3, tungsten-doped indium oxide IWO, indium zinc oxide InZnO x , indium gallium oxide InGaO x , or molybdenum disulfide MoS2, molybdenum diselenide MoSe2, tungsten diselenide WSe2, tungsten disulfide WS2 two-dimensional material, and the channel layer thickness is 5-30 nm.

8. A method of operating a three-dimensional ferroelectric memory array, comprising: The three-dimensional ferroelectric memory array includes memory cells arranged in an array in a vertical direction and a horizontal direction on a substrate, the memory cells in the horizontal direction are in turn a gate metal layer, a first isolation layer, a ferroelectric material layer, a floating gate metal layer, a second isolation layer and a channel layer from left to right or from right to left, wherein the floating gate metal layer serves as a conductive layer for uniform electric field distribution between the ferroelectric material layer and the channel layer, and an isolation medium layer is arranged between the gate metal layers or between the channel layers of adjacent memory cells, and the steps include the following: 1) programming: the bit line where the selected memory cell is located applies a 0 V voltage, the bit line of the unselected memory cell applies an inhibition voltage, all source lines are grounded, and the word line where the selected memory cell is located applies a programming voltage, and the word line of the unselected memory cell applies a turn-on voltage; 2) erase: all bit lines and all word lines apply a 0 V voltage, the source line of the selected memory cell applies an erase voltage, and the entire string is erased; 3) read: the bit line where the selected memory cell is located applies a read voltage, the bit line of the unselected memory cell applies a 0 V voltage, all source lines are grounded, the word line of the selected memory cell applies a 1 V voltage, and the word line voltage of the unselected memory cell is floating, the bit line current of the selected memory cell is read and compared with the reference current.

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