Groove type silicon carbide JBS device and preparation method thereof
By forming a trench structure on a silicon carbide substrate and forming a Schottky junction, the problem that traditional JBS devices are prone to surface heating and burning when they withstand large currents is solved, and the device's short-circuit current tolerance is improved.
Patent Information
- Application Number
- CN202510358825.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-25
- Publication Date
- 2025-06-13
AI Technical Summary
Traditional junction barrier Schottky diode (JBS) devices are prone to surface heating and burning when they withstand high currents, reducing their short-circuit current tolerance.
By using the preparation method of the trench type silicon carbide JBS device, a trench type silicon carbide JBS device is formed by forming a first epitaxial layer and a second epitaxial layer on the silicon carbide substrate, and trench etching is performed on the first epitaxial layer, trench backfill is used to form a Schottky junction, and the electrode metal layer and a passivation layer are deposited in sequence, thereby forming a trench type silicon carbide JBS device.
Through the trench structure, the traditional PiN tube that withstands high current is buried into semiconductor materials, reducing the probability of heat generation and burning on the surface of the device and improving the device's short-circuit current tolerance.
Smart Images
Figure CN120152308A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a trench-type silicon carbide JBS device and a preparation method thereof. Background Art
[0002] With the rapid development of the semiconductor industry, the trench-type silicon carbide junction barrier schottky diode (JBS) device, as one of the common power devices in the semiconductor industry, has the characteristics of high frequency and high power density, which can greatly reduce the volume of the power supply and improve the conversion efficiency of the power supply.
[0003] In the traditional junction barrier schottky diode (JBS), since the junction depth of the SiC device is relatively shallow, the heat generated during short circuit is on the surface of the device, and it is easy to be burned out, thus reducing the short-circuit current tolerance of the device. Moreover, the traditional junction barrier schottky diode (JBS) requires a PiN tube that can withstand large currents, so there will be a situation where the surface of the device is heated and burned out. Summary of the Invention
[0004] Based on this, the purpose of the present invention is to provide a trench-type silicon carbide JBS device and a preparation method thereof to solve the deficiencies in the above technologies.
[0005] The present invention provides a trench-type silicon carbide JBS device, including: Form a first epitaxial layer on a silicon carbide substrate, and perform a masking process on the first epitaxial layer to implant a second conductivity type layer, and the implantation depth of the second conductivity type layer is 1 - 1.5 μm; Perform secondary epitaxy on the first epitaxial layer to form a second epitaxial layer, and perform trench etching on the first epitaxial layer to form a trench structure, wherein the depth of the trench etching penetrates the second epitaxial layer; Use a metal material for trench backfilling, remove the excess backfilled metal, and deposit and open an insulating dielectric layer to form a schottky junction; Deposit an electrode metal layer and a passivation layer in sequence, and package the deposited semiconductor structure to form a trench-type silicon carbide JBS device.
[0006] Further, the total implantation dose of the second conductivity type layer is 1e14 cm -2 ~1e17 cm -2 , the first epitaxial layer and the second epitaxial layer are both first conductivity type layers, and the concentration of the first conductivity type layer is 1e14 cm -3 ~9e17 cm -3 .
[0007] Further, the etching depth of the trench etching is greater than 0.3 μm.
[0008] Further, the metal material for trench backfilling is heavily doped polysilicon or tungsten metal.
[0009] Further, wet etching and reverse etching are used to remove the excess backfilled metal. The annealing temperature of the metal material is 750 °C to 1200 °C, and the annealing time is 1 min to 60 min.
[0010] Further, in the step of packaging the deposited semiconductor structure, the wire bonding positions of the power device metal of the deposited semiconductor structure are partitioned. Among them, the first partition is the electrode metal pad of the PiN transistor, and the second partition is the electrode metal pad of the Schottky junction.
[0011] The present invention also provides a trench-type silicon carbide JBS device, which is fabricated by the above-mentioned manufacturing method.
[0012] In the trench-type silicon carbide JBS device and its manufacturing method of the present invention, a first epitaxial layer is formed on a silicon carbide substrate, and a second epitaxial layer is formed by secondary epitaxy on the first epitaxial layer. Trench etching is performed on the first epitaxial layer to form a trench structure. A Schottky junction is formed by using a metal material for trench backfilling. An electrode metal layer and a passivation layer are sequentially deposited, thereby forming a trench-type silicon carbide JBS device. The trench structure buries the PiN transistor that bears a large current in the traditional junction barrier Schottky diode into the semiconductor material, thereby reducing the probability of device surface heating and burning out the device. Description of the Drawings
[0013] Figure 1 is a flowchart of the trench-type silicon carbide JBS device in the first embodiment of the present invention; Figure 2 is Figure 1 a detailed flowchart of step S101 in Figure 3 is Figure 1 a detailed flowchart of step S102 in Figure 4 is Figure 1 a detailed flowchart of step S103 in Figure 5 is a structural block diagram of the manufacturing method of the trench-type silicon carbide JBS device in the second embodiment of the present invention; Figure 6 is a structural block diagram of the computer in the third embodiment of the present invention.
[0014] In the figure: 101a, the first epitaxial layer; 102b, the second conductivity type layer; 103b, the second epitaxial layer; 202a, the trench structure; 205a, the terminal structure; 301a, the interlayer dielectric structure in the cell; The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. Specific embodiments
[0015] For ease of understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Several embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.
[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.
[0017] Embodiment 1 Please refer to Figure 1 , which shows the preparation method of the trench-type silicon carbide JBS device in the first embodiment of the present invention, specifically including steps S101 to S104: S101, form a first epitaxial layer on the silicon carbide substrate, and perform a masking process on the first epitaxial layer to implant a second conductivity type layer, and the implantation depth of the second conductivity type layer is 1 - 1.5 μm; S102, perform secondary epitaxy on the first epitaxial layer to form a second epitaxial layer, and perform trench etching on the first epitaxial layer to form a trench structure, wherein the depth of the trench etching penetrates the second epitaxial layer; S103, use a metal material for trench backfilling, remove the excess backfilled metal, and deposit and open an insulating dielectric layer to form a Schottky junction; S104, deposit an electrode metal layer and a passivation layer in sequence, and package the deposited semiconductor structure to form a trench-type silicon carbide JBS device.
[0018] In specific implementation, please refer to Figures 2 to 4, an oxide layer (i.e., the first epitaxial layer) is grown on a silicon carbide substrate. The thickness of the oxide layer is greater than 1 μm, and a photoresist (with a thickness of about 1 μm) is coated on the oxide layer for masking treatment. After lithography, the developed part of the photoresist is opened, and the oxide layer is dry-etched, terminating on the silicon carbide substrate. The photoresist is removed, leaving only the silicon carbide substrate and a layer of silicon dioxide layer with openings. The obtained structure is ion-implanted to implant a second conductivity type layer. The silicon dioxide layer is cleaned to obtain a semiconductor material after ion implantation. It can be understood that this process is to dope impurities into the semiconductor material to form a P-type region in the original N-type semiconductor material. In this embodiment, the implantation depth of the second conductivity type layer (102b) is 1 - 1.5 μm, and the total implantation dose of the second conductivity type layer is 1e14 cm -2 ~1e17 cm -2 .
[0019] Further, secondary epitaxy is performed on the first epitaxial layer to form a second epitaxial layer. Among them, the first epitaxial layer (101a) and the second epitaxial layer (103b) are both first conductivity type layers, and the concentration of the first conductivity type layer is 1e14 cm -3 ~9e17 cm -3 ; Similar to the previous lithography process, exposure and development are performed by growing an oxide layer and a photoresist layer. After etching the oxide layer, the photoresist is removed, and trench etching is performed on the first epitaxial layer to form a trench structure (202a), where the depth of the trench etching penetrates the second epitaxial layer and the etching depth of the trench etching is greater than 0.3 μm; Specifically, a metal material is used for trench backfilling. For the excess backfilled metal, the surface metal is first polished flat using CMP, and then removed by wet etching and anti-etching. Insulating dielectric layer deposition and opening are performed to form a Schottky junction. In this embodiment, the metal material for trench backfilling is heavily doped polysilicon or tungsten metal, preferably tungsten metal. It should be noted that the metal material for trench backfilling needs to have good conductivity, filling ability, and a high selectivity ratio with SiC; In this embodiment, the annealing temperature of the metal material is 750 °C to 1200 °C, and the annealing time is 1 min to 60 min. Trench backfilling and deposition of interlayer dielectric materials are performed using methods such as LPCVD, and then openings are made at the position where the SBD is formed and other positions. These other positions include, but are not limited to, contact holes at the positions where electrode metals converge in the 205a structure, possible contact holes in the terminal structure, etc., to form a structure as Figure 5 shown. For the convenience of understanding, Figure 5 is a cross-sectional view of the device, and 301a represents the interlayer insulating dielectric structure in the cell.
[0020] Further, an electrode metal layer and a passivation layer are sequentially deposited, and the deposited semiconductor structure is encapsulated to form a trench-type silicon carbide JBS device. In the step of encapsulating the deposited semiconductor structure, the wire bonding positions of the power device metal of the deposited semiconductor structure are partitioned. Among them, the first partition is the electrode metal pad of the PiN transistor, and the second partition is the electrode metal pad of the Schottky junction.
[0021] The wire bonding positions of the power device metal in this embodiment are partitioned. As Figure 6 shown, the metal is divided into two regions. Region a is actually the electrode metal pad of the PiN transistor, and region b is the electrode metal pad of the SBD transistor. It is possible to achieve partitioned wire bonding during encapsulation. For region a, which bears a relatively large current, a larger wire diameter can be selected. Region b undertakes the general current function, and a general wire diameter can be selected for adaptation. On the basis of cost savings, a relatively large current of the device can be achieved.
[0022] In summary, for the trench-type silicon carbide JBS device in the above embodiments of the present invention, a first epitaxial layer is formed on a silicon carbide substrate, and a second epitaxial layer is formed by secondary epitaxy on the first epitaxial layer. A trench etching is performed on the first epitaxial layer to form a trench structure. A Schottky junction is formed by backfilling the trench with a metal material. An electrode metal layer and a passivation layer are sequentially deposited to form a trench-type silicon carbide JBS device. The PiN transistor that bears a large current in the traditional junction barrier Schottky diode is buried in the semiconductor material through the trench structure, thereby reducing the probability of the device being burned out due to surface heating.
[0023] Embodiment 2 On the other hand, the present invention also proposes a trench-type silicon carbide JBS device manufactured by the above preparation method.
[0024] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.
[0025] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.
Claims
1. A method for preparing a trench-type silicon carbide JBS device, characterized in that: include: Forming a first epitaxial layer on a silicon carbide substrate, and performing mask processing on the first epitaxial layer to implant a second conductive type layer, wherein the implantation depth of the second conductive type layer is 1-1.5 μm; Performing secondary epitaxy on the first epitaxial layer to form a second epitaxial layer, and performing trench etching on the first epitaxial layer to form a trench structure, wherein the depth of the trench etching passes through the second epitaxial layer; The trench is backfilled with metal material, and the excess backfill metal is removed, and an insulating dielectric layer is deposited and a hole is opened to form a Schottky junction; The electrode metal layer and the passivation layer are deposited in sequence, and the deposited semiconductor structure is packaged to form a trench-type silicon carbide JBS device.
2. The trench-type silicon carbide JBS device according to claim 1, characterized in that: The total implantation dose of the second conductive type layer is 1e14 cm -2 ~1e17cm -2 The first epitaxial layer and the second epitaxial layer are both first conductivity type layers, and the concentration of the first conductivity type layer is 1e14 cm -3 ~9e17cm -3 .
3. The trench silicon carbide JBS device according to claim 1, characterized in that: The etching depth of the trench etching is greater than 0.3 μm.
4. The trench silicon carbide JBS device according to claim 1, characterized in that: The metal material used for backfilling the trench is heavily doped polysilicon or metal tungsten.
5. The trench silicon carbide JBS device according to claim 1, characterized in that: The excess backfill metal is removed by wet etching and reverse etching. The annealing temperature of the metal material is 750° C. to 1200° C., and the annealing time is 1 min to 60 min.
6. The trench silicon carbide JBS device according to claim 1, characterized in that: In the step of packaging the deposited semiconductor structure, the bonding positions of the power device metal of the deposited semiconductor structure are divided into zones, wherein the first zone is the electrode metal pad of the PiN tube, and the second zone is the electrode metal pad of the Schottky junction.
7. A trench-type silicon carbide JBS device, characterized in that: The invention is prepared by the preparation method according to any one of claims 1 to 6.