Ring gate transistor and preparation method thereof

Abstract

The invention provides a gate-all-around transistor and a preparation method thereof. The gate-all-around transistor comprises a substrate, a supporting part, a suspended channel, a metal gate, a source / drain electrode and a dielectric isolation layer, the supporting part is arranged on one side of the substrate; the suspended channel is located on the supporting part; the metal gate is formed around the suspended channel; the source / drain electrode is respectively connected with the suspended channel; the dielectric isolation layer is located below the source / drain electrode; the suspended channel is formed by removing the sacrificial layer through etching; the dielectric isolation layer is formed by performing anisotropic etching and isotropic etching on the inner side wall medium after the inner groove is filled with the inner side wall medium; the inner groove is formed by carrying out selective inner concave etching on the edge of the sacrificial layer. According to the invention, the dielectric isolation layer is formed at the bottom of the source / drain region, so that the sub-fin electric leakage phenomenon of the gate-all-around transistor is effectively weakened.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a gate-all-around transistor and a method for manufacturing the same. Background Art

[0002] With the continuous miniaturization of the transistor feature size, traditional planar transistors (MOSFETs) face severe challenges in aspects such as current control, leakage current management, and short-channel effects. To address these issues, the gate-all-around transistor (GAAFET) has emerged as an important three-dimensional transistor architecture. Compared with the mainstream FinFET, the gate-all-around transistor has superior gate control ability and current driving ability, and is a key device architecture that can effectively replace FinFET after the 3nm node. The core feature of the gate-all-around transistor is that the gate completely wraps the channel, and this geometric structure makes the internal electric field distribution of the channel more uniform, significantly improving the gate's control ability over the channel current, enhancing the switching characteristics of the device, and providing the possibility for further size miniaturization of the transistor.

[0003] Currently, the academic and industrial communities have paid great attention to the research on gate-all-around transistors. The continuously optimized manufacturing process and key processes have become the research hotspots in the field of new CMOS devices. The existing manufacturing process of gate-all-around transistors cannot control the formation of effective bottom isolation, resulting in sub-fin leakage, which seriously affects the working performance of gate-all-around transistors. Summary of the Invention

[0004] The present invention provides a gate-all-around transistor and a method for manufacturing the same, which can effectively reduce the sub-fin leakage phenomenon of the gate-all-around transistor by forming a dielectric isolation layer at the bottom of the source / drain region.

[0005] The present invention provides a gate-all-around transistor, including a substrate, a support portion, a suspended channel, a metal gate, source / drain electrodes, and a dielectric isolation layer; the support portion is disposed on one side of the substrate; the suspended channel is located on the support portion; the metal gate is formed around the suspended channel; the source / drain electrodes are respectively connected to the suspended channel; the dielectric isolation layer is located below the source / drain electrodes; the suspended channel is formed by etching away a sacrificial layer; the dielectric isolation layer is formed by anisotropic etching and isotropic etching of the inner sidewall dielectric after the inner groove is filled with the inner sidewall dielectric; the inner groove is formed by selectively recessing the edge of the sacrificial layer.

[0006] A gate-all-around transistor provided according to the present invention, wherein the dielectric isolation layer includes a first oxide film and a second oxide film; the second oxide film is formed above the first oxide film; the first oxide film is formed by thermally oxidizing the source / drain region; the second oxide film is formed by chemical vapor deposition; the growth quality of the first oxide film is greater than that of the second oxide film, and the growth rate of the first oxide film is less than that of the second oxide film.

[0007] A gate-all-around transistor provided according to the present invention, wherein both the first oxide film and the second oxide film are silicon oxide.

[0008] A gate-all-around transistor provided according to the present invention further includes an interlayer dielectric layer and a conductive channel; the interlayer dielectric layer is located above the source / drain electrode, and the conductive channel is formed in the interlayer dielectric layer and is respectively connected to the source / drain electrode and the metal gate.

[0009] The present invention also provides a method for manufacturing a gate-all-around transistor, including: performing selective inward concave etching on the edge of the sacrificial layer during the manufacturing process of the gate-all-around transistor to form an inner groove; depositing an inner sidewall dielectric on the source / drain region, and a part of the inner sidewall dielectric filling the inner groove forms a second sidewall; performing anisotropic etching and isotropic etching on the inner sidewall dielectric based on the outer side of the second sidewall to form a dielectric isolation layer at the bottom of the source / drain region; performing epitaxial growth on the exposed channel layer to form source / drain electrodes above the dielectric isolation layer.

[0010] A method for manufacturing a gate-all-around transistor provided according to the present invention, before performing the selective inward concave etching on the edge of the sacrificial layer, further includes: providing a substrate, one side of the substrate has a support portion, the sacrificial layer and the channel layer are alternately stacked along the extending direction of the support portion, and the support portion, the sacrificial layer and the channel layer together form a fin structure; forming a dummy gate on the fin structure; forming first sidewalls on both sides of the dummy gate; forming source / drain regions for manufacturing the source / drain electrodes on both sides of the first sidewalls.

[0011] A method for manufacturing a gate-all-around transistor provided according to the present invention, the depositing the inner sidewall dielectric on the source / drain region includes: thermally oxidizing the source / drain region to generate a layer of first oxide film on the surface of the support portion; depositing a second oxide film on the first oxide film by chemical vapor deposition to form the inner sidewall dielectric; the growth quality of the first oxide film is greater than that of the second oxide film, and the growth rate of the first oxide film is less than that of the second oxide film.

[0012] A method for manufacturing a gate-all-around transistor according to the present invention, forming a dielectric isolation layer at the bottom of the source / drain region includes: forming, by photolithography, a rectangular region not protected by a photomask on each side of the dummy gate; using the first sidewall as a hard mask, vertically and selectively etching the inner sidewall dielectric, and retaining a preset thickness of the inner sidewall dielectric at the bottom of the formed trench as the dielectric isolation layer.

[0013] A method for manufacturing a gate-all-around transistor according to the present invention, forming a dielectric isolation layer at the bottom of the source / drain region includes: forming, by photolithography, a matrix region not protected by a photomask on the source region side of the dummy gate; using the first sidewall as a hard mask, vertically and selectively etching the inner sidewall dielectric, and retaining a preset thickness of the inner sidewall dielectric as the dielectric isolation layer to form a source region trench; forming, by photolithography, a matrix region not protected by a photomask on the drain region side of the dummy gate; using the first sidewall as a hard mask, vertically and selectively etching the inner sidewall dielectric until the substrate is exposed to form a drain region trench.

[0014] A method for manufacturing a gate-all-around transistor according to the present invention, after forming the source / drain electrodes above the dielectric isolation layer, further includes: depositing an interlayer dielectric layer, performing chemical mechanical polishing on the interlayer dielectric layer until the dummy gate is exposed; removing the dummy gate; removing the sacrificial layer to release the channel layer to form a suspended channel; forming a metal gate around the suspended channel; forming contact holes respectively in contact with the source / drain electrodes and the metal gate, and forming a conductive channel in the contact holes.

[0015] A gate-all-around transistor and a manufacturing method thereof according to the present invention include a substrate, a support portion, a suspended channel, a metal gate, source / drain electrodes, and a dielectric isolation layer; the support portion is provided on one side of the substrate; the suspended channel is located on the support portion; the metal gate is formed around the suspended channel; the source / drain electrodes are respectively connected to the suspended channel; the dielectric isolation layer is located below the source / drain electrodes; the suspended channel is formed by etching away the sacrificial layer; the dielectric isolation layer is formed by anisotropic etching and isotropic etching of the inner sidewall dielectric after the inner groove is filled with the inner sidewall dielectric; the inner groove is formed by selectively recessing the edge of the sacrificial layer. By forming a dielectric isolation layer at the bottom of the source / drain region, the present invention effectively weakens the sub-fin leakage phenomenon of the gate-all-around transistor. Description of the Drawings

[0016] To more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 It is a schematic structural diagram of a gate-all-around transistor provided by the present invention.

[0018] Figure 2 It is a schematic process diagram of forming a fin structure provided by the present invention (wherein, sub-diagram a provides a substrate, sub-diagram b alternately stacks a sacrificial layer and a channel layer, sub-diagram c forms a fin structure, and sub-diagram d deposits a shallow trench isolation).

[0019] Figure 3 It is a schematic structural diagram after forming a dummy gate provided by the present invention.

[0020] Figure 4 It is a schematic structural diagram after forming a first sidewall provided by the present invention.

[0021] Figure 5 It is a schematic structural diagram after selectively recessing and etching the sacrificial layer provided by the present invention.

[0022] Figure 6 It is a schematic structural diagram after depositing a medial sidewall dielectric provided by the present invention.

[0023] Figure 7 It is a schematic structural diagram after chemical mechanical polishing to expose the first sidewall provided by the present invention.

[0024] Figure 8 It is a schematic structural diagram after forming source / drain trenches and exposing the Si channel provided by the present invention.

[0025] Figure 9 It is a schematic structural diagram after epitaxy and doping single-crystalline silicon provided by the present invention.

[0026] Figure 10 It is a schematic structural diagram after depositing an interlayer dielectric layer provided by the present invention.

[0027] Figure 11 It is a schematic structural diagram after removing the dummy gate and the sacrificial layer and releasing the channel layer provided by the present invention.

[0028] Figure 12 It is a schematic structural diagram after forming a high-k / metal gate provided by the present invention.

[0029] Figure 13 It is a schematic flow diagram of a method for manufacturing a gate-all-around transistor provided by the present invention.

[0030] Figure 14 It is a schematic structural diagram of another gate-all-around transistor provided by the present invention.

[0031] Figure 15 It is a comparison diagram of the quality of the inner sidewall formed by the inner sidewall process (wherein, sub-diagram a is the inner sidewall formed by the method of the present invention, sub-diagram b is the inner sidewall formed by under-etching, and sub-diagram c is the inner sidewall formed by over-etching).

[0032] Figure 16 It is a relationship diagram between the input capacitance Cgg of the device and the gate voltage Vg under different second sidewall conditions provided by the present invention.

[0033] Figure 17 It is an Id-Vg curve diagram of the gate-all-around transistor with and without a bottom dielectric isolation layer provided by the present invention.

[0034] Figure 18 It is a carrier density distribution diagram along the channel cross-section provided by the present invention.

[0035] Reference numerals: 1: Substrate; 2: Support part; 3: Sacrificial layer; 4: Channel layer; 5: Shallow trench isolation; 6: dummy gate; 7: Oxide hard mask; 8: First sidewall; 9: Inner sidewall dielectric; 10: Second sidewall; 11: Heavily doped source / drain region; 12: Interlayer dielectric layer; 13: High-k dielectric layer; 14: Metal gate; 15: Silicide; 16: Interconnect metal. Detailed implementation manners

[0036] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without making creative efforts based on the embodiments in the present invention belong to the scope of protection of the present invention.

[0037] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a gate-all-around transistor provided by the present invention.

[0038] The present invention provides a gate-all-around transistor, comprising a substrate 1, a support portion 2, a suspended channel, a metal gate 14, source / drain electrodes, and a dielectric isolation layer; the support portion 2 is disposed on one side of the substrate 1; the suspended channel is located on the support portion 2; the metal gate 14 is formed around the suspended channel; the source / drain electrodes are connected to the suspended channel; the dielectric isolation layer is located under the source / drain electrodes; the suspended channel is formed by etching away a sacrificial layer 3; the dielectric isolation layer is formed by anisotropic etching and isotropic etching of an inner sidewall dielectric 9 after the inner groove is filled with the inner sidewall dielectric 9; the inner groove is formed by selectively recessing the edge of the sacrificial layer 3.

[0039] As a preferred embodiment, the dielectric isolation layer comprises a first oxide thin film and a second oxide thin film; the second oxide thin film is formed above the first oxide thin film; the first oxide thin film is formed by thermal oxidation of the source / drain region; the second oxide thin film is formed by chemical vapor deposition; the growth quality of the first oxide thin film is greater than that of the second oxide thin film, and the growth rate of the first oxide thin film is less than that of the second oxide thin film.

[0040] As a preferred embodiment, both the first oxide thin film and the second oxide thin film are silicon oxide.

[0041] As a preferred embodiment, it further comprises an interlayer dielectric layer 12 and a conductive channel; the interlayer dielectric layer 12 is located above the source / drain electrodes, and the conductive channel is formed in the interlayer dielectric layer 12 and is respectively connected to the source / drain electrodes and the metal gate 14.

[0042] In order to solve the technical problems existing in the prior art, the present invention provides a gate-all-around transistor and a manufacturing method thereof. After the edge of the sacrificial layer 3 (such as SiGe) is selectively recessed, a dense and high-quality inner sidewall dielectric 9 (such as SiO 2 isolation dielectric) is filled in the trench, and then, taking the first sidewall 8 (such as SiN x ) formed in the previous step as a hard mask, the SiO 2 inner sidewall dielectric 9 is selectively etched with high alignment accuracy. The source / drain region trench is formed by self-aligned etching, and this process more conveniently exposes the end of the Si channel, and then the epitaxial growth of the channel layer 4Si is carried out. The present invention can reduce the manufacturing difficulty of the inner sidewall, especially in terms of high-precision anisotropic selective etching and filling effect. In addition, since the interface formation quality between SiO 2 and silicon is better, the filling quality of the second sidewall 10 can be improved. At the same time, the present invention can realize a controllable bottom dielectric isolation layer, and the thickness of the bottom dielectric isolation layer of the source / drain region can be precisely controlled by adjusting the etching depth parameters, so as to effectively optimize the sub-fin leakage, and further improve the working performance of the gate-all-around transistor.

[0043] In this embodiment, the detailed preparation process of the gate-all-around transistor is as follows: Please refer to Figure 2 , Figure 2 which is a schematic diagram of the process for forming the fin structure provided by the present invention (wherein, sub-diagram a shows providing a substrate, sub-diagram b shows alternately stacking a sacrificial layer and a channel layer, sub-diagram c shows forming a fin structure, and sub-diagram d shows depositing shallow trench isolation).

[0044] Prepare a bulk silicon substrate 1. After impurity implantation, diffusion, and annealing processes in the substrate 1, P-type and N-type regions are formed, and the impurity concentration is about 10 14 -10 16 cm -3 . For a P-type FET, the doped region of the substrate 1 is N-type, and the implanted impurity is an N-type impurity such as phosphorus (P); for an N-type FET, the doped region of the substrate 1 is P-type, and the implanted impurity is a P-type impurity such as boron (B).

[0045] Epitaxially grow a silicon / silicon germanium stacked structure, respectively control the thickness of the silicon germanium layer (sacrificial layer 3) (10 - 20 nm) and the thickness of the silicon layer (channel layer 4) (5 - 10 nm), and precisely control the germanium content in the SiGe layer to ensure a high selectivity with the silicon layer during the subsequent wet etching process. Here, it is necessary to make the top layer be a silicon germanium material, that is, the silicon layers are all sandwiched between the silicon germanium layers.

[0046] Form multiple periodically distributed fins (fin structures) through processes such as photolithography and etching. The upper part of the fin is a silicon / silicon germanium stacked structure, and the lower part is the substrate 1. The photolithography in this step can form fine stripes of different process nodes through advanced processes such as multiple exposures and ultraviolet lithography. The etching in this step can select dry etching or reactive ion etching. The finally formed fin height is about 50 nm - 400 nm, and the width is about 5 - 100 nm.

[0047] Form a shallow trench isolation 5 (STI) between adjacent fins. First, deposit a SiO 2 dielectric material, then perform a planarization process, and then selectively etch back the SiO 2 dielectric material until the stacked structure containing Si and SiGe is exposed, specifically: the upper surface of the dielectric material is lower than the bottom Si layer of the stacked structure in the fin, but not lower than the interface between the silicon of the substrate 1 and the SiGe layer in the fin. For convenience of description, the subsequent process flow schematic diagrams are shown from a cross-sectional perspective.

[0048] Please refer to Figure 3 , Figure 3 which is a schematic diagram of the structure after forming a dummy gate provided by the present invention.

[0049] Through processes such as chemical vapor deposition and planarization, a layer of polysilicon or amorphous silicon is first deposited above the fin structure as the dummy gate 6 material, with a thickness about 20 - 400 nm higher than the top of the fin, and then a layer of oxide hard mask 7 is deposited, with a thickness of about 10 - 50 nm. Then, through processes such as lithography and dry etching, multiple periodic dummy gates 6 are formed in a direction perpendicular to the fin lines, with a width of about 10 - 100 nm, and etched until the shallow trench isolation 5 region is exposed. The dummy gate 6 straddles the stacked structure on the upper part of the fin, and multiple dummy gates 6 are periodically distributed along the fin line direction.

[0050] Please refer to Figure 4 , Figure 4 which is the schematic diagram of the structure after forming the first sidewall provided by the present invention.

[0051] A layer of silicon nitride (SiN x ) is isotropically deposited on the surface of the above structure by chemical vapor deposition, with a thickness of about 2 - 10 nm. Then, anisotropic dry etching is carried out until the silicon / silicon germanium stacked structure not protected by the oxide hard mask 7 is completely removed. At this time, a first sidewall 8 is formed around the dummy gate 6, with a thickness of about 2 - 10 nm. Source / drain regions for preparing source / drain electrodes are formed on both sides of the first sidewall 8.

[0052] Please refer to Figure 5 , Figure 5 which is the schematic diagram of the structure after selective recess etching of the sacrificial layer provided by the present invention.

[0053] The silicon / silicon germanium stacked layer is exposed on both sides of the dummy gate 6. Then, selective wet etching is carried out on the silicon germanium layer to form a recessed groove, providing space for the subsequent deposition of the inner sidewall (the second sidewall 10). The recessed depth of the recessed groove is about 2 - 10 nm, for example, 4 - 5 nm.

[0054] Please refer to Figure 6 , Figure 6 which is the schematic diagram of the structure after depositing the inner sidewall dielectric provided by the present invention.

[0055] Thermal oxidation is carried out in a high - temperature environment (1000 - 1200 °C) to grow a first oxide film (dense SiO 2 film (100 - 200 Å)) on the exposed silicon and silicon germanium surfaces to improve the interface quality and ensure subsequent high - quality oxide filling.

[0056] A second oxide film SiO 2, by adjusting the deposition rate to ensure dense and flat filling until the deposition layer covers the first sidewall 8, forming the inner sidewall dielectric 9. The growth quality of the first oxide film is greater than that of the second oxide film, and the growth rate of the first oxide film is less than that of the second oxide film.

[0057] Please refer to Figure 7 , Figure 7 is a schematic structural diagram of the chemical mechanical polishing provided by the present invention after exposing the first sidewall.

[0058] Through chemical mechanical polishing, the dummy gate 6, oxide, and silicon nitride are polished to a position 30 - 200 nm above the silicon / silicon germanium stack, and the first sidewall 8 is exposed to ensure a flat surface for the subsequent self-aligned etching process.

[0059] Through anisotropic re-etching, a rectangular area not protected by the photomask is formed on each side of the dummy gate 6. At the same time, the first sidewall 8 also serves as a hard mask to achieve higher-precision alignment. Vertically downward selectively etch SiO 2 to 10 - 50 nm below the bottom silicon layer, and a preset thickness (5 - 50 nm) of SiO 2 is reserved at the bottom of the formed trench as the bottom dielectric isolation layer (BDI). Since the first sidewall 8 realizes self-alignment, the Si channel is basically exposed in the trenches on both sides of the dummy gate 6.

[0060] Please refer to Figure 8 , Figure 8 is a schematic structural diagram of the present invention after forming the source / drain region trenches and exposing the Si channel.

[0061] Through isotropic light etching, the SiO inside the trench is 2 slightly selectively etched, smoothing the rough profile caused by the previous vertical etching and completely exposing the end of the Si channel, and sufficient SiO is reserved at the concave part 2 to form the second sidewall 10.

[0062] Please refer to Figure 9 , Figure 9 is a schematic structural diagram of the present invention after epitaxial growth and doping of single-crystalline silicon.

[0063] Single-crystalline Si is grown in the trench obtained by the previous etching through epitaxial technology. It should be noted that the epitaxial Si grows almost only from the surface of the end of the Si channel and does not grow on the SiO 2 surface, thereby forming high-quality source / drain regions.

[0064] Dope the above source / drain regions. For PMOS, the doping element is B or BF 2, for NMOS, the doping elements are P or As to form highly doped source / drain regions 11 to ensure that the transistor has sufficient carriers, and the impurity concentration is about 10 18 -10 22 cm -3 . The source / drain regions are subjected to low-temperature rapid thermal annealing to activate the impurities.

[0065] Please refer to Figure 10 , Figure 10 , which is a schematic structural diagram of the structure after depositing the interlayer dielectric layer provided by the present invention.

[0066] An ILD0 oxide layer (interlayer dielectric layer 12) is deposited on the top of the device for isolation, and then chemical mechanical polishing is carried out from top to bottom until the polysilicon dummy gate 6 is exposed.

[0067] Please refer to Figure 11 , Figure 11 , which is a schematic structural diagram of the structure after removing the dummy gate and the sacrificial layer and releasing the channel layer provided by the present invention.

[0068] The dummy gate 6 is completely removed by selective wet etching to form a gate cavity, so that the Si-SiGe stacked layer is exposed.

[0069] The sacrificial layer 3SiGe exposed in the gate cavity is completely removed by selective wet etching to form a suspended Si channel.

[0070] Please refer to Figure 12 , Figure 12 , which is a schematic structural diagram of the structure after forming the high-k / metal gate provided by the present invention.

[0071] A high-k dielectric layer 13 and a metal gate 14 are deposited in the gate cavity by processes such as chemical vapor deposition and physical vapor deposition. The metal gate 14 includes a multi-layer structure of a capping layer, a barrier layer, a work function layer, and a filling layer. For the purpose of improving device performance and adjusting their respective work functions, the material of the metal gate 14 can be selected from one or a combination of several materials such as TiN, TaN, TiAl, Al, W, Co, Cr, or Cu. Then, the interlayer dielectric layer 12 ILD0, the high-k dielectric layer 13, and the metal gate 14 are chemically mechanically polished to make them flat, and the excess high-k dielectric layer 13 and metal gate 14 materials on the surface of the dielectric layer exposed outside the gate cavity are removed.

[0072] The interlayer dielectric layer 12 is deposited to protect the device structure. Contact holes respectively contacting the source / drain electrodes and the metal gate 14 are formed by processes such as photolithography and etching, and silicide 15 is deposited in the holes and contact electrodes (conductive channels) are led out. Subsequently, multi-layer back-end interconnect and protection processes are completed.

[0073] The above is the complete preparation process flow of the technology, and finally a gate-all-around transistor device is obtained.

[0074] The preparation method of the gate-all-around transistor provided by the present invention will be described below. The preparation method of the gate-all-around transistor described below can be correspondingly referred to the gate-all-around transistor described above.

[0075] Please refer to Figure 13 , Figure 13 which is a schematic flow chart of a preparation method of a gate-all-around transistor provided by the present invention.

[0076] The present invention also provides a preparation method of a gate-all-around transistor, including: 1301: Selectively recess-etch the edge of the sacrificial layer 3 during the preparation of the gate-all-around transistor to form an inner groove; 1302: Deposit an inner spacer dielectric 9 on the source / drain region. The part of the inner spacer dielectric 9 filling the inner groove forms a second spacer 10; 1303: Perform anisotropic etching and isotropic etching on the inner spacer dielectric based on the outer side of the second spacer 10 to form a dielectric isolation layer at the bottom of the source / drain region; 1304: Epitaxially grow the exposed channel layer 4 to form source / drain electrodes above the dielectric isolation layer.

[0077] As a preferred embodiment, before selectively recess-etching the edge of the sacrificial layer, it further includes: providing a substrate 1, one side of the substrate 1 has a support portion 2, the sacrificial layer 3 and the channel layer 4 are alternately stacked along the extending direction of the support portion 2, and the support portion 2, the sacrificial layer 3 and the channel layer 4 together form a fin structure; forming a dummy gate 6 on the fin structure; forming first spacers 8 on both sides of the dummy gate 6; forming source / drain regions for preparing source / drain electrodes on both sides of the first spacers 8.

[0078] As a preferred embodiment, depositing the inner spacer dielectric 9 on the source / drain region includes: thermally oxidizing the source / drain region to generate a first oxide film on the surface of the support portion 2; depositing a second oxide film on the first oxide film by chemical vapor deposition to form the inner spacer dielectric 9; the growth quality of the first oxide film is greater than that of the second oxide film, and the growth rate of the first oxide film is less than that of the second oxide film.

[0079] As a preferred embodiment, forming the dielectric isolation layer at the bottom of the source / drain region includes: through photolithography technology, forming an unprotected rectangular region by a photomask on both sides of the dummy gate 6; using the first spacer 8 as a hard mask, selectively etching the inner spacer dielectric 9 vertically downward, and retaining a preset thickness of the inner spacer dielectric 9 at the bottom of the formed trench as the dielectric isolation layer.

[0080] As a preferred embodiment, a dielectric isolation layer is formed at the bottom of the source / drain region, including: forming a matrix region that is not protected by a photomask on the source region side of the dummy gate 6 through lithography technology; using the first sidewall 8 as a hard mask to vertically and selectively etch the inner sidewall dielectric 9 downward, and retaining the inner sidewall dielectric 9 with a preset thickness as the dielectric isolation layer to form a source region trench; forming a matrix region that is not protected by a photomask on the drain region side of the dummy gate 6 through lithography technology; using the first sidewall 8 as a hard mask to vertically and selectively etch the inner sidewall dielectric 9 downward until the substrate 1 is exposed to form a drain region trench.

[0081] As a preferred embodiment, after forming the source / drain electrodes above the dielectric isolation layer, it further includes: depositing an interlayer dielectric layer 12, performing chemical mechanical polishing on the interlayer dielectric layer 12 until the dummy gate 6 is exposed; removing the dummy gate 6; removing the sacrificial layer 3 to release the channel layer 4 to form a suspended channel; forming a metal gate 14 around the suspended channel; forming contact holes that are respectively in contact with the source / drain electrodes and the metal gate 14, and forming a conductive channel in the contact holes.

[0082] In this embodiment, considering the aggravation of the device self-heating effect by the bottom dielectric isolation layer, only the source region of the surrounding gate transistor can be subjected to bottom dielectric isolation, while the other drain region is directly connected to the silicon of the substrate 1. This method can effectively dissipate the heat generated by the drain from the substrate 1, effectively reduce the self-heating effect, and since the source is isolated, the sub-fin leakage phenomenon can be effectively avoided.

[0083] Please refer to Figure 14 , Figure 14 which is a schematic structural diagram of another surrounding gate transistor provided by the present invention.

[0084] The detailed preparation process of the surrounding gate transistor is as follows: Prepare a bulk silicon substrate 1. After impurity implantation, diffusion and annealing processes in the substrate 1, P-type and N-type regions are formed, and the impurity concentration is 10 16 cm -3 . For the P-type FET, the doped region of the substrate 1 is N-type, and the implanted impurity is phosphorus (P); for the N-type FET, the doped region of the substrate 1 is P-type, and the implanted impurity is boron (B).

[0085] Epitaxially grow a silicon / silicon germanium stacked structure, respectively control the thickness of the silicon germanium layer (sacrificial layer 3) (12 nm) and the silicon layer (channel layer 4) (5 nm), and precisely control the germanium content (25%) in the SiGe layer to ensure a high selectivity with the silicon layer during the subsequent wet etching process. The top layer of the stack is silicon germanium material, and the silicon layers are all sandwiched between the silicon germanium layers.

[0086] Multiple periodically distributed fins (fin-type structures) are formed through processes such as lithography and etching. The upper part of the fin is a silicon / silicon germanium stacked structure, and the lower part is substrate 1. The lithography in this step is carried out through SiN x Multiple exposures of the hard mask form fine stripes with a width of 11 nm. The etching in this step selects dry etching, and the finally formed fin height is 100 nm.

[0087] A shallow trench isolation 5 (STI) is formed between adjacent fins. First, SiO 2 dielectric material is deposited, then planarization is carried out, and then the SiO 2 dielectric material is selectively etched back until the stacked structure containing Si and SiGe is exposed. Specifically, the upper surface of the dielectric material is lower than the bottom Si layer of the stacked structure in the fin, but not lower than the interface between the single-crystalline silicon of substrate 1 and the SiGe layer in the fin.

[0088] Through processes such as chemical vapor deposition and planarization, a layer of polysilicon is first deposited as the dummy gate 6 material above the above structure, with a thickness 250 nm higher than the top of the fin, and then a layer of oxide hard mask 7 is deposited, with a thickness of about 20 nm. Then, through processes such as lithography and dry etching, multiple periodic dummy gates 6 are formed in a direction perpendicular to the fin line, with a width of 12 nm, and etched until the shallow trench isolation 5 region is exposed. The dummy gate 6 straddles the stacked structure on the upper part of the fin, and multiple dummy gates 6 are periodically distributed along the fin line direction.

[0089] A layer of silicon nitride (SiN x ) is isotropically deposited on the surface of the above structure through chemical vapor deposition, with a thickness of 4 nm. Then, anisotropic dry etching is carried out until the silicon / silicon germanium stacked structure not protected by the oxide hard mask 7 is completely removed. At this time, a first sidewall 8 is formed around the dummy gate 6, with a thickness of about 4 nm. Source / drain regions for preparing source / drain electrodes are formed on both sides of the first sidewall 8.

[0090] The silicon / silicon germanium stacked layer is exposed on both sides of the dummy gate 6. Then, selective wet etching is carried out on the silicon germanium layer to form an inner groove, providing space for the subsequent deposition of the second sidewall 10. The inner concave depth of the inner groove is 5 nm.

[0091] Thermal oxidation is carried out in a high-temperature environment (1000 °C) to grow a first oxide film (dense SiO 2 film (150 Å)) on the exposed silicon and silicon germanium surfaces to improve the interface quality and ensure high-quality oxide filling in the subsequent process.

[0092] A second oxide film SiO 2, by adjusting the deposition rate to ensure dense and flat filling until the deposition layer covers the first sidewall 8, forming the inner sidewall dielectric 9. The growth quality of the first oxide film is greater than that of the second oxide film, and the growth rate of the first oxide film is less than that of the second oxide film.

[0093] Through chemical mechanical polishing, the dummy gate 6, the oxide, and the silicon nitride are polished to 30 nm above the silicon / silicon germanium stack, and the first sidewall 8 is exposed to ensure a flat surface for the subsequent self-aligned etching process.

[0094] Through anisotropic re-etching, a rectangular area (20×30 nm) not protected by a photomask is first formed on the source region side of the dummy gate 6. At the same time, the first sidewall 8 also serves as a hard mask to achieve higher-precision alignment. Vertically downward selective etching of SiO 2 is carried out to below the bottom silicon layer, and 5 nm thick SiO is reserved at the bottom of the trench. 2 As the bottom dielectric isolation to form the source region trench.

[0095] Through low-concentration isotropic wet etching, slight selective etching is carried out on the SiO inside the source region trench. 2 to smooth the rough profile caused by the previous vertical etching and completely expose the end of the Si channel, and sufficient SiO is reserved at the concave part. 2 , forming the second sidewall 10 of the source region.

[0096] Through epitaxial technology, single-crystalline Si is grown in the source region trench obtained by the previous etching. It should be noted that epitaxial Si grows almost only from the surface of the end of the Si channel and does not grow on the SiO 2 surface, thereby forming a high-quality source region, with a height slightly lower than the top of the trench.

[0097] Dope the single-crystalline silicon obtained by the above epitaxy. For PFET, the doping element is B, and for NFET, the doping element is P, to form a highly doped source region to ensure that the transistor has sufficient carriers, and the impurity concentration is 10 21 cm -3 .

[0098] Deposit a 100 nm thick oxide layer on the top of the source region for isolation, and then perform chemical mechanical polishing from top to bottom until the polysilicon dummy gate 6 is exposed.

[0099] Through anisotropic re-etching, another rectangular area (20×30 nm) not protected by a photomask is formed on the drain region side of the dummy gate 6, and vertically downward selective etching of SiO 2 is carried out until the substrate 1 silicon is exposed to form the drain region trench. Since the first sidewall 8 achieves self-alignment, the Si channel is basically exposed in the trench on the drain region side.

[0100] Slightly selective etching is performed on the SiO inside the trench of the drain region through isotropic wet etching at a low concentration, smoothing the rough profile caused by the previous vertical etching and completely exposing the end of the Si channel, and retaining sufficient SiO at the concave part 2 , forming the second sidewall 10 of the drain region. 2

[0101] Single-crystalline Si is grown in the drain region trench obtained by the previous etching through epitaxial technology. Since there is still bare substrate 1 silicon in the drain region trench of the dummy gate 6, the epitaxial growth rate will be higher. At this time, the epitaxial growth parameters need to be adjusted to form a high-quality drain region with a height slightly lower than the top of the trench.

[0102] The single-crystalline silicon obtained by the above epitaxy is doped. For PFET, the doping element is B, and for NFET, the doping element is P, forming a highly doped drain region to ensure that the transistor has sufficient carriers, and the impurity concentration is 10 21 cm -3 . Low-temperature rapid thermal annealing is used to activate the impurities in the source and drain regions.

[0103] A 100 nm thick ILD0 oxide layer (interlayer dielectric layer 12) is deposited on the top of the device for isolation, and then chemical mechanical polishing is carried out from top to bottom until the polysilicon dummy gate 6 is exposed.

[0104] The polysilicon dummy gate 6 is completely removed by selective wet etching to form a gate cavity, exposing the Si-SiGe stacked layer.

[0105] The exposed SiGe layer in the gate cavity is completely removed by selective wet etching to form a suspended Si channel.

[0106] A 2 nm thick high-k dielectric layer 13 and a metal gate 14 are deposited in the gate cavity by processes such as chemical vapor deposition and physical vapor deposition. The high-k dielectric layer 13 selects HfO 2 , and the multi-layer structure of the metal gate 14 selects the TiN / TaN / TiN combination for P-type FET and the TiN / TiAl / TiN combination for N-type FET. Then, chemical mechanical polishing is performed on the ILD0 dielectric layer, the HfO 2 dielectric layer, and the metal gate 14 to make them flat, and the excess HfO 2 dielectric layer and metal gate 14 materials exposed on the surface of the dielectric layer outside the gate cavity are removed.

[0107] Contact holes are formed through processes such as lithography and etching, and silicide 15 is deposited in the holes and contact electrodes (interconnect metal 16) (conductive channel) are led out. Subsequently, multi-layer back-end interconnection and protection processes are completed.

[0108] The above is the complete preparation process flow of this technology, and finally a gate-all-around transistor device is obtained.

[0109] In the epitaxial steps involved in the above embodiments, strain silicon technology can be introduced during the epitaxial growth of single-crystalline Si. For example, SiGe material can be epitaxially grown in the source / drain regions of PFETs, or SiC material can be epitaxially grown in the source / drain regions of NFETs to match / increase the carrier mobility of both. High-doped source / drain regions can also be directly epitaxially grown to simplify subsequent doping steps. In terms of material selection in the above embodiments, the sidewall material can be selected from a variety of low dielectric constant materials, such as SiON and SiCO, and only the deposition process needs to be adjusted and optimized accordingly.

[0110] The present invention can improve the formation quality of the second sidewall 10 and reduce its manufacturing difficulty. At the same time, a controllable bottom dielectric isolation technology is achieved. By adjusting the etching parameters, the bottom dielectric isolation layer of the source / drain region can be directly formed, effectively reducing the sub-fin leakage current of the gate-all-around transistor. In addition, this technical solution is compatible with the manufacturing method of gate-all-around transistors under the mainstream FinFET process, which is beneficial to further enhancing the application advantages of transistors.

[0111] Please refer to Figure 15 , Figure 15 for the quality comparison diagram of the inner sidewall formed by the inner sidewall process (where the a sub-diagram is the inner sidewall formed by the method of the present invention, the b sub-diagram is the inner sidewall formed by under-etching, and the c sub-diagram is the inner sidewall formed by over-etching).

[0112] For the inner sidewall formed by the present invention, due to the protective effect of the first sidewall 8 as a hard mask, over-etching and under-etching can be improved, effectively improving the quality of the Si channel ends and reducing damage. In addition, in the subsequent isotropic light etching, the high selectivity between SiN x and SiO 2 can reduce the damage to the first sidewall 8 and can control the retention of the bottom dielectric isolation layer.

[0113] Please refer to Figure 16 , Figure 16 for the relationship diagram of the input capacitance Cgg of the device and the gate voltage Vg under different second sidewall conditions provided by the present invention.

[0114] From the relationship curves of the input capacitance Cgg of the device and the gate voltage Vg under different second sidewall 10 conditions (with thicknesses of 3 nm and 6 nm respectively), it can be seen that as the thickness of the second sidewall 10 increases, the parasitic capacitance of the device decreases significantly. In addition, compared with the second sidewall 10 made of SiN x material, using SiO 2The material serves as the second sidewall 10 and has a smaller dielectric constant. Therefore, it has obvious advantages in parasitic effects. This is because the parasitic capacitance is mainly related to the dielectric thickness and dielectric constant. Increasing the dielectric thickness and decreasing the dielectric constant both contribute to reducing the parasitic capacitance, thereby increasing the switching speed. It should be noted that this technical solution can also replace the second sidewall 10 with other materials having a lower dielectric constant, such as SiON, SiCO, etc., but it is necessary to adjust and optimize the deposition technology to ensure the trench filling effect.

[0115] Please refer to Figure 17 , Figure 17 which is the Id-Vg curve graph of the surrounding gate transistor with and without the bottom dielectric isolation layer provided by the present invention.

[0116] Regarding the transfer characteristic curves of the surrounding gate transistor with and without the bottom dielectric isolation layer (BDI), where Vd is 0.1 V and the BDI thicknesses are 0 nm and 5 nm respectively. It can be seen that the presence of the bottom dielectric isolation layer effectively reduces the off-state current I off , greatly improving the device switching ratio. The main reason is that the bottom dielectric isolation layer effectively weakens the unique sub-fin leakage phenomenon of the surrounding gate transistor.

[0117] Please refer to Figure 18 , Figure 18 which is the carrier density distribution diagram along the channel cross-section provided by the present invention.

[0118] Regarding the carrier density distribution diagram along the channel cross-section of the surrounding gate transistor with and without the bottom dielectric isolation layer (BDI). It can be seen that the bottom dielectric isolation layer effectively isolates the diffusion of carriers in the active region to the substrate 1, and there is no obvious current path in the substrate 1 channel. While for the surrounding gate transistor without the bottom dielectric isolation layer structure, there is a current path that is difficult to turn off at the substrate 1 channel, resulting in leakage. Therefore, the surrounding gate transistor prepared by this technical solution can further optimize the sub-fin leakage and improve the device performance.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A gate-all-around transistor, characterized in that: It includes a substrate, a support portion, a suspended channel, a metal gate, a source / drain and a dielectric isolation layer; The support portion is arranged on one side of the substrate; the suspended channel is located on the support portion; the metal gate is formed around the suspended channel; the source / drain are respectively connected to the suspended channel; the dielectric isolation layer is located below the source / drain; the suspended channel is formed by removing the sacrificial layer by etching; the dielectric isolation layer is formed by anisotropically etching and isotropically etching the inner sidewall dielectric after the inner groove is filled with the inner sidewall dielectric; the inner groove is formed by selectively concave etching the edge of the sacrificial layer.

2. The gate-all-around transistor according to claim 1, characterized in that: The dielectric isolation layer includes a first oxide film and a second oxide film; the second oxide film is formed above the first oxide film; the first oxide film is formed by thermally oxidizing the source / drain region; the second oxide film is formed by chemical vapor deposition; the growth mass of the first oxide film is greater than the growth mass of the second oxide film, and the growth rate of the first oxide film is less than the growth rate of the second oxide film.

3. The gate-all-around transistor according to claim 2, characterized in that: The first oxide film and the second oxide film are both silicon oxide.

4. The gate-all-around transistor according to any one of claims 1 to 3, characterized in that: Also includes an interlayer dielectric layer and a conductive channel; The interlayer dielectric layer is located above the source / drain, and the conductive channel is formed in the interlayer dielectric layer and is respectively connected to the source / drain and the metal gate.

5. A method for preparing a gate-all-around transistor, characterized in that: include: In the process of preparing the ring-gate transistor, selectively performing concave etching on the edge of the sacrificial layer to form an inner groove; Depositing an inner sidewall dielectric on the source / drain region, wherein the inner sidewall dielectric fills a portion of the inner groove to form a second sidewall; Anisotropically etching and isotropically etching the inner sidewall dielectric based on the outer side of the second sidewall to form a dielectric isolation layer at the bottom of the source / drain region; Epitaxial growth is performed on the exposed channel layer to form source / drain electrodes on the dielectric isolation layer.

6. The method for preparing a gate-all-around transistor according to claim 5, characterized in that: Before the selective concave etching of the edge of the sacrificial layer, the method further comprises: Providing a substrate, wherein one side of the substrate has a support portion, the sacrificial layer and the channel layer are alternately stacked along an extension direction of the support portion, and the support portion, the sacrificial layer and the channel layer together form a fin-type structure; forming a dummy gate on the fin structure; A first spacer is formed on both sides of the dummy gate; and a source / drain region for preparing the source / drain is formed on both sides of the first spacer.

7. The method for preparing a gate-all-around transistor according to claim 6, characterized in that: The step of depositing an inner sidewall dielectric on the source / drain region comprises: Thermally oxidizing the source / drain region to form a first oxide film on the surface of the support portion; The inner sidewall dielectric is formed by depositing a second oxide film on the first oxide film by chemical vapor deposition; the growth mass of the first oxide film is greater than the growth mass of the second oxide film, and the growth speed of the first oxide film is less than the growth speed of the second oxide film.

8. The method for preparing a gate-all-around transistor according to claim 6, characterized in that: The step of forming a dielectric isolation layer at the bottom of the source / drain region comprises: By using photolithography technology, a rectangular area not protected by a photomask is formed on both sides of the dummy gate; The first sidewall spacer is used as a hard mask to selectively etch the inner sidewall dielectric vertically downward, and the inner sidewall dielectric of a preset thickness is retained at the bottom of the formed trench as the dielectric isolation layer.

9. The method for preparing a gate-all-around transistor according to claim 6, characterized in that: The step of forming a dielectric isolation layer at the bottom of the source / drain region comprises: By using photolithography technology, a matrix region not protected by a photomask is formed on one side of the source region of the dummy gate; Using the first sidewall as a hard mask, selectively etching the inner sidewall dielectric vertically downward, and retaining the inner sidewall dielectric of a preset thickness as the dielectric isolation layer to form a source region trench; By using photolithography technology, a matrix region not protected by a photomask is formed on one side of the drain region of the dummy gate; The first sidewall spacer is used as a hard mask, and the inner sidewall dielectric is selectively etched vertically downward until the substrate is exposed, thereby forming a drain region trench.

10. The method for preparing a gate-all-around transistor according to any one of claims 6 to 9, characterized in that: After forming a source / drain on the dielectric isolation layer, the method further includes: Depositing an interlayer dielectric layer, and performing chemical mechanical polishing on the interlayer dielectric layer until the dummy gate is exposed; removing the false grille; removing the sacrificial layer and releasing the channel layer to form a suspended channel; forming a metal gate around the suspended channel; Contact holes are formed to contact the source / drain and the metal gate respectively, and a conductive channel is formed in the contact holes.

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