Lif neuron device based on molybdenum disulfide floating gate transistor and preparation method thereof

Abstract

The application relates to a LIF neuron device based on a molybdenum disulfide floating gate transistor and a preparation method thereof, which comprises a SiO2 / Si substrate, a first electrode layer arranged on the SiO2 layer, a graphene floating gate layer and a functional layer arranged side by side on the first electrode layer, an h-BN floating gate medium layer and a MoS2 channel layer which are stacked on the floating gate layer, the floating gate medium layer extends to the surface of part of the functional layer, a second electrode layer arranged on the functional layer, a third electrode arranged on both sides of the channel layer and a fourth electrode connected to the second electrode layer; the first electrode layer is a live metal electrode connected to the floating gate layer; the threshold switch memristor is used for regulating and controlling the floating gate storage state of the floating gate transistor, the device has the advantages of non-volatile storage characteristics, continuous adjustable pulse response, high-density integration, low-power operation, fast response time, strong durability and the like, can realize batch preparation, and is suitable for industrial-scale production.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of artificial neural network devices, in particular to a LIF neuron device based on a molybdenum disulfide floating gate transistor and a preparation method thereof. BACKGROUND

[0002] Compared with the traditional von Neumann computing architecture, artificial neural network devices based on neuromorphic computing can realize the function of storing and computing. It is expected to greatly reduce the energy and time consumption of data-intensive computing. Among various artificial neural network devices, floating gate field effect transistors are widely used, in which the floating gate can provide charge storage, reversible and non-volatile channel carrier modulation and fast storage operation, can well simulate the function of artificial synapse, and realize neuromorphic computing. In addition to the basic data storage function, the floating gate effect can also be used to realize logic operation and other functions, further enriching the application scenarios of artificial neural network. In practical applications, a floating gate structure is usually built on a high-performance channel material (such as two-dimensional material molybdenum disulfide MoS2) transistor to construct a new type of low-power and high-efficiency electronic device.

[0003] At present, the threshold switch-based memristor has been reported as a new method for regulating transistor devices. The research on threshold switch mostly focuses on the basic characteristic analysis of the functional layer. As a new two-dimensional material device process, it is difficult to see substantial progress in using threshold switch and floating gate transistor to build a three-terminal artificial neural network device. And the existing neuron device still has problems such as small storage window, slow response speed, and insufficient stability. SUMMARY

[0004] The present application provides a LIF (Leaky Integrate-and-Fire Neuron) neuron device based on a molybdenum disulfide floating gate transistor and a preparation method thereof. The device uses MoS2 as the semiconductor channel, boron nitride (h-BN) as the floating gate dielectric, and graphene as the floating gate layer, and builds a threshold switch on the floating gate to form a LIF neuron device.

[0005] The semiconductor channel, floating gate dielectric and floating gate layer of the device are prepared based on the mechanical exfoliation method. The vdW contact between the materials is achieved through dry transfer, achieving a good van der Waals interface. The tunneling mechanism of the floating gate dielectric layer and the storage and release of charges of the floating gate are used to construct an artificial synapse device that simulates the behavior of biological synapses, supporting neuromorphic computing. The threshold switch characteristic memristor is prepared by using the characteristic of the active electrode to generate conductive filaments in the functional layer, and the floating gate layer is connected. The overall device can realize self-resetting response to pulses, thereby simulating the working mechanism of LIF neurons.

[0006] The application provides a LIF neuron device based on a molybdenum disulfide floating gate transistor, which comprises a SiO2 / Si substrate, a first electrode layer arranged on the SiO2 layer, a functional layer arranged on the first electrode layer, and a second electrode layer arranged on the functional layer, wherein the first electrode layer, the functional layer, and the second electrode layer form a threshold switch memristor.

[0007] The SiO2 layer is further provided with a graphene floating gate layer, an h-BN floating gate dielectric layer is arranged on the graphene floating gate layer and the functional layer, a MoS2 channel layer is arranged on the h-BN floating gate dielectric layer, and a third electrode and a fourth electrode are arranged on two sides of the MoS2 channel layer, respectively.

[0008] The first electrode layer is a noble metal electrode, which is connected to the graphene floating gate layer, and the second electrode layer is connected to the fourth electrode.

[0009] Further, the graphene floating gate layer and the functional layer are arranged side by side on the first electrode layer, so that the step of etching the first electrode layer in the preparation process is reduced,

[0010] Further, the functional layer is an Al2O3 film with a thickness of 7-10 nm.

[0011] Further, the second electrode is a noble metal electrode.

[0012] Further, the SiO2 layer is a gate dielectric layer, and the Si substrate is a bottom gate.

[0013] The fourth electrode is a grounding electrode of the threshold switch memristor.

[0014] Further, the MoS2 channel layer has a thickness of 10-15 nm, the h-BN floating gate dielectric layer has a thickness of 10-15 nm, and the graphene floating gate layer has a thickness of 15-20 nm.

[0015] Further, the noble metal electrode is an Ag electrode layer with a thickness of 20-25 nm.

[0016] The noble metal electrode is a Cr / Au electrode, the third electrode is a Cr / Au electrode, the fourth electrode is a Cr / Au electrode, the Cr layer has a thickness of 10-15 nm, and the Au layer has a thickness of 30-35 nm.

[0017] Further, the Al2O3 film is obtained by using an atomic layer deposition process, taking trimethylaluminum and H2O as precursors, and depositing 7-10 nm at 150°C.

[0018] Further, the graphene floating gate layer, the h-BN floating gate dielectric layer, and the MoS2 channel layer are obtained by using a mechanical exfoliation process.

[0019] The application also provides a preparation method of the LIF neuron device, which comprises the following steps: preparing a threshold switching memristor on a SiO2 layer, etching and removing part of the Al2O3 layer to expose the first electrode layer, transferring the graphene floating gate layer obtained by exfoliation to the exposed first electrode layer and the functional layer in parallel by using a dry transfer process, transferring the h-BN floating gate dielectric layer obtained by exfoliation to the graphene floating gate layer and the functional layer by using a dry transfer process, transferring the MoS2 channel layer obtained by exfoliation to the h-BN floating gate dielectric layer by using a dry transfer process, and finally depositing the third electrode and the fourth electrode on the MoS2 channel layer, and connecting the fourth electrode to the second electrode of the threshold switching memristor.

[0020] Or the application also provides a preparation method of the LIF neuron device, which comprises the following steps: preparing a threshold switching memristor on a SiO2 layer, etching and removing part of the Al2O3 layer and the first electrode layer to expose the SiO2 layer, transferring the graphene floating gate layer obtained by exfoliation to the SiO2 layer and the first electrode and the functional layer in parallel by using a dry transfer process, transferring the h-BN floating gate dielectric layer obtained by exfoliation to the graphene floating gate layer and the functional layer by using a dry transfer process, transferring the MoS2 channel layer obtained by exfoliation to the h-BN floating gate dielectric layer by using a dry transfer process, and finally depositing the third electrode and the fourth electrode on the MoS2 channel layer, and connecting the fourth electrode to the second electrode of the threshold switching memristor, and connecting the graphene floating gate layer to the first electrode layer by using an Ag wire.

[0021] The application builds the memristor with threshold switching characteristics on the floating gate layer of the floating gate transistor, regulates the storage state of the floating gate of the MoS2 floating gate transistor by using the threshold switching memristor, and the device has the synaptic characteristics of the floating gate transistor and the pulse response characteristics of the LIF neuron, realizes the integration of the non-volatile writing and erasing functions of the floating gate transistor and the charge accumulation and release functions of the LIF neuron on a single device, has the advantages of non-volatile storage characteristics, continuously adjustable pulse response, high-density integration, low-power operation, fast response time, strong durability, good stability, small leakage current, compatibility with semiconductor technology and the like. Under the condition of low gate voltage or low pulse amplitude, the device shows the non-volatile storage of the floating gate transistor, realizes the long-time writing and erasing effect. Under the condition of high pulse amplitude, the device can realize the charge accumulation and release functions of the LIF neuron due to the threshold switching characteristics of the memristor.

[0022] The threshold switch device of the application is prepared by metal thermal evaporation and ALD deposition processing, combined with mechanical peeling and dry transfer of the floating gate layer, the floating gate dielectric layer and the semiconductor channel layer to prepare the floating gate transistor, and the floating gate transistor and the threshold switch memristor are carried together, realizing large-area, batch and array preparation, which is suitable for industrial scale production, and the preparation process is simple, low in cost and low in requirement for experimental equipment, and has great prospects for constructing large-scale and high-performance thin film electronic devices, solving the complexity and array process compatibility problem of two-dimensional material device array preparation.

[0023] The LIF neuron device of the application realizes functions by utilizing the storage and release of charges in the floating gate layer of the floating gate transistor and the threshold switching characteristics of the memristor, and can be used to construct a hardware platform simulating the structure of a biological neural system, realizing efficient and energy-saving information processing mode. Based on the response of the device to different frequency or amplitude pulse signals, a series of synaptic plasticity and biological neuron reaction processes can be simulated, thereby supporting complex neural network operation, and the application field and application prospect of the artificial neural network device are very wide. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a structure schematic diagram of the LIF neuron device of an embodiment of the application.

[0025] Figure 2 is a Raman spectrum diagram of the two-dimensional material obtained by an embodiment of the application.

[0026] Figure 3 is an optical microscope diagram of the LIF neuron device of an embodiment of the application.

[0027] Figure 4 is the electrical transport performance of the LIF neuron device of an embodiment of the application under a smaller gate voltage.

[0028] Figure 5 is the electrical transport performance diagram of the LIF neuron device of an embodiment of the application under a larger gate voltage.

[0029] Figure 6 is a pulse response diagram of the LIF neuron device of an embodiment of the application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. The described embodiments are merely some, not all, of the embodiments of the present invention. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the scope of protection of the present invention. Unless otherwise specified, the experimental methods described in the following embodiments are conventional methods; the reagents and materials, unless otherwise specified, can be obtained from publicly available commercial channels.

[0031] This specification uses spatially relative terms such as “below,” “under,” “down,” “above,” “above,” and “upper” to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device, except for those different from those shown in the figures.

[0032] Furthermore, the use of terms such as "first" and "second" to describe various elements, layers, regions, and sections is not intended to be restrictive. The use of terms such as "having," "containing," "including," and "comprises" are open-ended terms, indicating the presence of the stated elements or features, but not excluding additional elements or features, unless the context explicitly states otherwise.

[0033] The LIF neuron (Leaky Integrate-and-Fire Neuron) is a classic neuron model used to simulate the fundamental dynamics of nerve cells. It is a simplified computational model that helps us understand the neuron's firing behavior and information processing. The firing mechanism involves the neuron "firing" an action potential (spike) when the membrane potential V(t) reaches a specific threshold Vth. After firing, the membrane potential is reset to a lower value Vreset, and no new action potentials are fired for a short period (called the refractory period). We simulate this behavior using floating-gate storage and memristors.

[0034] like Figure 1 As shown, one embodiment of the present invention provides a LIF neuron device based on a molybdenum disulfide floating-gate transistor, which consists of a floating-gate transistor and a memristor with a threshold switching function. The floating-gate transistor includes a substrate, a channel, a source, a drain, a floating gate dielectric, and a floating gate. Specifically, the substrate is a SiO2 / Si substrate, and a first electrode layer is disposed on a SiO2 layer on the Si substrate. The thickness of the SiO2 layer is 285 nm. The first electrode layer is an active metal electrode, preferably an Ag electrode, with a thickness of 20-25 nm; in a preferred embodiment, the thickness of the Ag electrode is 30 nm.

[0035] The floating gate layer is arranged on the first electrode layer, and is a graphene film obtained by a mechanical exfoliation process, with a thickness of 15-20 nm; in a preferred embodiment, the graphene floating gate layer has a thickness of 10 nm; the floating gate dielectric layer is arranged on the graphene floating gate layer, and is an h-BN film obtained by a mechanical exfoliation process, with a thickness of 10-15 nm; in a preferred embodiment, the h-BN film has a thickness of 10 nm; and the channel layer is arranged on the floating gate dielectric layer, and is an MoS2 film obtained by a mechanical exfoliation process, with a thickness of 10-15 nm.

[0036] The memristor comprises a first electrode layer, a functional layer and a second electrode layer, the functional layer is arranged on the first electrode layer in parallel and adjacent to the graphene floating gate layer, and the functional layer is an Al2O3 film with a thickness of 7-10 nm; the Al2O3 film is deposited on the first electrode layer by an ALD process; in a preferred embodiment, the Al2O3 film has a thickness of 10 nm.

[0037] The second electrode layer is arranged on the functional layer, and the second electrode layer is an inert metal electrode, and a Cr / Au electrode is selected; the Cr layer has a thickness of 10-15 nm, and the Au layer has a thickness of 30-35 nm; in a preferred embodiment, the Cr layer has a thickness of 10 nm, and the Au layer has a thickness of 30 nm.

[0038] The MoS2 channel layer is provided with a third electrode and a fourth electrode, which are respectively arranged on the two sides of the MoS2 channel layer; the second electrode layer is connected to the fourth electrode; the third electrode and the fourth electrode are Cr / Au electrodes; the Cr layer has a thickness of 10-15 nm, and the Au layer has a thickness of 30-35 nm; in a preferred embodiment, the Cr layer has a thickness of 10 nm, and the Au layer has a thickness of 30 nm; the third electrode and the fourth electrode are respectively a source electrode and a drain electrode; in an embodiment, the third electrode is the source electrode, and the fourth electrode is the drain electrode; in another embodiment, the third electrode is the source electrode, and the fourth electrode is the drain electrode.

[0039] The floating gate transistor is a bottom gate structure, that is, the silicon substrate serves as a bottom gate of the whole device, the silicon dioxide layer serves as a gate dielectric, the third electrode and the fourth electrode are respectively arranged on the two sides of the MoS2 film channel layer and in contact with the MoS2 film channel layer, and the fourth electrode is connected to the second electrode layer of the threshold switch memristor and simultaneously serves as a ground electrode of the threshold switch memristor; the device is a three-terminal electrode in actual testing, thereby reducing the use of test ports.

[0040] An embodiment of the present application also provides a preparation process of the LIF neuron device.

[0041] The graphene, h-BN and MoS2 two-dimensional material films are prepared by a mechanical exfoliation process. Figure 2As shown in a, b, c, the Raman spectra of the graphene film, h-BN film and MoS2 film obtained by mechanical exfoliation process are shown, and it can be known that relatively pure and narrow thickness distribution films are obtained.

[0042] Pre-treatment of the substrate: SiO2 / Si substrate is selected, the thickness of SiO2 is 285 nm, the substrate is ultrasonically cleaned with acetone, isopropyl alcohol and water respectively for 10 min, and the substrate is dried with nitrogen. Then, oxygen plasma treatment is used to improve the hydrophilicity of the substrate to obtain better transfer material and spin-on photoresist effect. Specifically, the oxygen plasma treatment is performed at a power of 200 w for 10 min.

[0043] Then, an Ag electrode is prepared on the above SiO2 / Si substrate by ultraviolet lithography, development, vacuum metal evaporation and stripping process, the Ag electrode covers the SiO2 layer, and the thickness of the Ag electrode is 10 nm; then, an aluminum oxide film is deposited on the Ag electrode by ALD process, specifically, an Al2O3 film with a thickness of 10 nm is deposited at 150°C using trimethylaluminum and water as precursors. Then, a Cr / Au (10 nm / 30 nm) electrode is prepared on the aluminum oxide surface by ultraviolet lithography, development, vacuum metal evaporation and stripping process. A threshold switching memristor is obtained on the substrate.

[0044] Then, the preparation of the floating gate transistor is carried out, a part of the aluminum oxide on the Ag electrode is etched to serve as the space of the floating gate transistor. By dry transfer, the graphene on the PDMS colloid is aligned with the silver electrode and transferred thereon, then the h-BN on the PDMS colloid is aligned with the graphene and transferred thereon, and finally the MoS2 on the PDMS colloid is aligned with the h-BN and transferred thereon. The channel region is drawn on the MoS2 surface by ultraviolet lithography, and then the Cr / Au (10 nm / 30 nm) electrodes are prepared on both ends of the MoS2 surface by development, vacuum metal evaporation and stripping process, and one of the electrodes is connected to the Cr / Au electrode of the memristor.

[0045] The optical microscope image of the obtained LIF neuron device is shown in Figure 3 The device is a typical floating gate transistor structure, which relies on the charge storage state of the floating gate layer to modulate the conductivity of the channel. Under the action of an external electric field, the floating gate generates charge storage, and this storage can be switched between two charges. As shown in Figure 4 The LIF neuron device shows typical n-type behavior and a very clear memory hysteresis window within the bottom gate voltage scanning range (±5V) that makes the floating gate storage voltage not higher than the threshold voltage (±3V) at V ds = 0.1V. The storage state can still be maintained even after the external electric field is removed.

[0046] But due to threshold switching, when the floating gate storage charge voltage reaches the threshold voltage V th , the carriers in the floating gate layer will be released, thus changing the memory window. Figure 5 As shown in V ds = 0.1V, when the bottom gate scanning voltage (±20V) can make the floating gate storage voltage reach the threshold voltage, there is a clear threshold switch to control the floating gate to release the charge, which produces a jump in the memory window curve.

[0047] The overall device switching ratio is >10 4 , allowing operation at low leakage current (10 -10 A), thus achieving low power consumption.

[0048] In our device, the floating gate is charged by applying a pulsed voltage on the bottom gate. When the floating gate voltage accumulates to the threshold voltage of the memristor, the memristor will quickly turn on, releasing the stored charge in the floating gate, thus changing the current transport of the floating gate transistor. As the floating gate voltage decreases, the memristor turns off again, and the floating gate is charged again. This cycle repeats, showing the periodic response of the device to the pulse. As shown in Figure 6 , the floating gate is charged and the current is increased when a 100ms / 1s pulse with a pulse width of 10V is applied. As the number of pulses increases, the floating gate storage voltage reaches the threshold voltage, making the memristor conduct, and the floating gate storage charge is released, and the current decreases rapidly. Increasing the pulse amplitude or increasing the pulse width can reduce the number of pulses. This periodic response to the pulse signal can simulate the working mechanism of LIF neurons.

[0049] The present application uses molybdenum disulfide (MoS2) as a semiconductor channel, boron nitride (h-BN) as a floating gate dielectric, and graphene as a floating gate layer to build a LIF neuron device with a threshold switch characteristic memristor on the floating gate layer, which is a unit in an artificial neural network device. The LIF neuron device has the advantages of non-volatile storage, continuous adjustable weight update, high-density integration, low-power operation, fast response time, and strong durability, and can simulate the behavior of biological neurons. In addition, the memristor part of the device is completed by ALD deposition of Al2O3 and thermal evaporation of metal electrodes, which can realize the array of the device, and the floating gate transistor preparation process is mainly dry transfer mechanical peeling of two-dimensional materials, which is simple and requires low experimental equipment. It has great prospects for building large-scale and high-performance thin film electronic devices.

[0050] The above embodiments are the preferred embodiments of the present application, but the embodiments of the present application are not limited to the above embodiments, and any changes, modifications, substitutions, combinations, simplifications, etc. made without departing from the spirit and principles of the present application should be equivalent replacement manners and should be included in the protection scope of the present application.

Claims

1. A LIF neuron device based on a molybdenum disulfide floating gate transistor, characterized in that, The threshold switching memristor comprises a SiO2 / Si substrate, a first electrode layer arranged on the SiO2 layer, a functional layer arranged on the first electrode layer, and a second electrode layer arranged on the functional layer, wherein the first electrode layer, the functional layer and the second electrode layer form the threshold switching memristor. The SiO2 layer further comprises a graphene floating gate layer, an h-BN floating gate dielectric layer arranged on the graphene floating gate layer and the functional layer, and a MoS2 channel layer arranged on the h-BN floating gate dielectric layer, and a third electrode and a fourth electrode are arranged on two sides of the MoS2 channel layer, respectively. The first electrode layer is a noble metal electrode connected to the graphene floating gate layer, and the second electrode layer is connected to the fourth electrode. The graphene floating gate layer and the functional layer are arranged side by side on the first electrode layer, the SiO2 layer is a gate dielectric layer, and the Si substrate is a bottom gate.

2. The LIF neuron device of claim 1, wherein, The functional layer is an Al2O3 film with a thickness of 7-10 nm.

3. The LIF neuron device of claim 2, wherein, The second electrode is a noble metal electrode.

4. The LIF neuron device of claim 3, wherein, The fourth electrode is a ground electrode of the threshold switching memristor.

5. The LIF neuron device according to claim 3 or 4, wherein, The MoS2 channel layer has a thickness of 10-15 nm, the h-BN floating gate dielectric layer has a thickness of 10-15 nm, and the graphene floating gate layer has a thickness of 15-20 nm.

6. The LIF neuron device according to claim 3 or 4, wherein The noble metal electrode is an Ag electrode layer with a thickness of 20-25 nm. The noble metal electrode is a Cr / Au electrode, the third electrode is a Cr / Au electrode, the fourth electrode is a Cr / Au electrode, the Cr layer has a thickness of 10-15 nm, and the Au layer has a thickness of 30-35 nm.

7. The LIF neuron device of claim 2, wherein, The Al2O3 film is deposited by an atomic layer deposition process using trimethylaluminum and H2O as precursors at 150°C for 7-10 nm.

8. The LIF neuronal device according to any one of claims 1, 2, 3, 4, 7, wherein, The graphene floating gate layer, the h-BN floating gate dielectric layer and the MoS2 channel layer are obtained by a mechanical exfoliation process.

9. The LIF neuron device of claim 8, wherein, The threshold switching memristor is prepared by the following steps: first, a threshold switching memristor is prepared on the SiO2 layer, then a part of the Al2O3 layer is etched to expose the first electrode layer, then the graphene floating gate layer obtained by exfoliation is transferred to the exposed first electrode layer and arranged side by side with the functional layer by a dry transfer process, then the h-BN floating gate dielectric layer obtained by exfoliation is transferred to the graphene floating gate layer and the functional layer by a dry transfer process, then the MoS2 channel layer obtained by exfoliation is transferred to the h-BN floating gate dielectric layer by a dry transfer process, and finally, the third electrode and the fourth electrode are deposited on the MoS2 channel layer, and the fourth electrode is connected to the second electrode of the threshold switching memristor. Or first prepare the threshold switch memristor on the SiO2 layer, then etch to remove part of the aluminum oxide layer and the first electrode layer to expose the SiO2 layer, then use the dry transfer process to transfer the graphene floating gate layer obtained by exfoliation to the SiO2 layer to be arranged side by side with the stack of the first electrode and the functional layer, then use the dry transfer process to transfer the h-BN floating gate dielectric layer obtained by exfoliation to the graphene floating gate layer and the functional layer, then use the dry transfer process to transfer the MoS2 channel layer obtained by exfoliation to the h-BN floating gate dielectric layer, and finally deposit the third electrode and the fourth electrode on the MoS2 channel layer, and connect the fourth electrode to the second electrode of the threshold switch memristor, and use the Ag wire to connect the graphene floating gate layer to the first electrode layer.

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