Array substrate and pixel circuit

Abstract

An array substrate and pixel circuit provided in an embodiment of the present application relate to the field of display technology. The array substrate includes a substrate and a drive wiring layer, wherein the drive wiring layer is located on one side of the substrate. The drive wiring layer includes a pixel circuit, a first voltage wiring, and a second voltage wiring. The pixel circuit includes a drive transistor and a first switch transistor. The drive transistor and the first switch transistor are both dual-gate transistors. The first gate of the drive transistor is electrically connected to the first voltage wiring, and the first gate of the first switch transistor is electrically connected to the second voltage wiring. The voltage value connected to the second voltage wiring is lower than the voltage value connected to the first voltage wiring. The present application can reduce the positive bias heating stress of the first switch transistor, thereby improving the display uniformity of the corresponding display panel, and ultimately improving the display effect of the corresponding display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a pixel circuit. Background Art

[0002] Organic light-emitting diodes (OLEDs) and flat-panel displays based on technologies such as light-emitting diodes (LEDs) have become a mainstream display panel technology, widely used in a variety of consumer electronics products, including mobile phones, televisions, laptops, and desktop computers, due to their advantages of high image quality, power efficiency, thin design, and wide application range. Traditionally, the production of display panels involves patterning the luminous pixels using a fine metal mask (FMM). While FMM technology is mature and boasts extensive mass production experience, it also suffers from limited precision, high development costs, and long development cycles. FMM-free technology eliminates the limitations of traditional OLED processes on display size, resolution, and other performance characteristics, offering the advantages of high performance, full-scale scalability, and agile delivery. Patents CN118251982A, CN115666161A, CN116648095A, CN117062489A, CN118678742A, CN118785761A, CN115224220A, CN118678729A, CN118660529A, and CN118660589A describe the non-fine metal mask technology for reference.

[0003] However, there are still some problems with display panels that need to be solved urgently. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the above technical background, an embodiment of the present application provides an array substrate, wherein the array substrate includes:

[0005] substrate;

[0006] A drive wiring layer is located on one side of the substrate, the drive wiring layer includes a pixel circuit, a first voltage wiring and a second voltage wiring, the pixel circuit includes a drive transistor and a first switching transistor, the drive transistor and the first switching transistor are both dual-gate transistors, the first gate of the drive transistor is electrically connected to the first voltage wiring, the first gate of the first switching transistor is electrically connected to the second voltage wiring, and the voltage value connected to the second voltage wiring is less than the voltage value connected to the first voltage wiring.

[0007] In some possible implementations, the voltage value connected to the second voltage line is greater than or equal to -1V and less than or equal to 0V;

[0008] Preferably, the voltage value connected to the first voltage line is greater than or equal to 2.8V and less than or equal to 4.6V.

[0009] In some possible implementations, the first switch transistor includes a first semiconductor layer, and the first gate of the first switch transistor is located on a side of the first semiconductor layer close to the substrate;

[0010] Preferably, the driving wiring layer further includes a second connecting wiring located between the substrate and the first gate of the first switching transistor, and a first connecting wiring located on a side of the second connecting wiring away from the substrate, and the first gate of the first switching transistor is electrically connected to the second voltage wiring via the first connecting wiring.

[0011] Preferably, the array substrate includes a display area and a non-display area surrounding at least a portion of the display area, at least a portion of the second voltage trace is located in the non-display area, and the first connecting trace extends to the non-display area and is electrically connected to the second voltage trace;

[0012] Preferably, the material of the first semiconductor layer includes metal oxide.

[0013] In some possible implementations, the driving transistor includes a second semiconductor layer, and the first gate of the driving transistor is located on a side of the second semiconductor layer close to the substrate;

[0014] Preferably, the driving wiring layer further includes a first connecting wiring located between the substrate and the second semiconductor layer and a second connecting wiring located between the first connecting wiring and the substrate, and the first gate of the driving transistor is electrically connected to the first voltage wiring through the second connecting wiring;

[0015] Preferably, the array substrate includes a display area and a non-display area surrounding at least part of the display area, at least part of the first voltage line is located in the non-display area, and the second connection line extends to the non-display area and is electrically connected to the first voltage line.

[0016] In some possible implementations, the pixel circuit further includes a second switch transistor, the second switch transistor is a dual-gate transistor, the drive wiring layer further includes a third voltage wiring, a first gate of the second switch transistor is electrically connected to the third voltage wiring, and a voltage value connected to the third voltage wiring is lower than a voltage value connected to the first voltage wiring;

[0017] Preferably, the second switch transistor includes a third semiconductor layer, and the first gate of the second switch transistor is located on a side of the third semiconductor layer close to the substrate;

[0018] Preferably, the driving wiring layer further includes a second connecting wiring located between the substrate and the first gate of the second switching transistor, and a third connecting wiring located on a side of the second connecting wiring away from the substrate, and the first gate of the second switching transistor is electrically connected to the third voltage wiring through the third connecting wiring;

[0019] Preferably, the array substrate includes a display area and a non-display area surrounding at least a portion of the display area, at least a portion of the third voltage trace is located in the non-display area, and the third connection trace extends to the non-display area and is electrically connected to the third voltage trace;

[0020] Preferably, the material of the third semiconductor layer includes metal oxide.

[0021] In some possible implementations, the voltage value connected to the third voltage line is greater than or equal to -1V and less than or equal to 0V;

[0022] Preferably, the voltage value connected to the third voltage line is equal to the voltage value connected to the second voltage line;

[0023] Preferably, the third voltage line reuses the second voltage line.

[0024] In some possible implementations, the present application further provides another array substrate, comprising:

[0025] substrate;

[0026] A drive wiring layer is located on one side of the substrate, the drive wiring layer includes a pixel circuit, a first voltage wiring and a third voltage wiring, the pixel circuit includes a drive transistor and a second switching transistor, the drive transistor and the second switching transistor are both dual-gate transistors, the first gate of the drive transistor is electrically connected to the first voltage wiring, the first gate of the second switching transistor is electrically connected to the third voltage wiring, and the voltage value connected to the third voltage wiring is less than the voltage value connected to the first voltage wiring.

[0027] In some possible implementations, the voltage value connected to the first voltage line is greater than or equal to 2.8V and less than or equal to 4.6V;

[0028] Preferably, the voltage value connected to the third voltage wiring is greater than or equal to -1V and less than or equal to 0V.

[0029] In some possible implementations, the pixel circuit further includes a first switching transistor, the first switching transistor being a dual-gate transistor, the drive wiring layer further includes a second voltage wiring, a first gate of the first switching transistor is electrically connected to the second voltage wiring, and a voltage value connected to the second voltage wiring is lower than a voltage value connected to the first voltage wiring;

[0030] Preferably, the voltage value connected to the second voltage line is greater than or equal to -1V and less than or equal to 0V;

[0031] Preferably, the voltage value connected to the second voltage line is equal to the voltage value connected to the third voltage line;

[0032] Preferably, the second voltage line reuses the third voltage line.

[0033] In some possible implementations, the present application further provides a pixel circuit, comprising:

[0034] a driving transistor, wherein the driving transistor is a dual-gate transistor;

[0035] a first switch transistor, wherein the first switch transistor is a double-gate transistor;

[0036] a first storage capacitor, the first storage capacitor comprising a first electrode plate and a second electrode plate;

[0037] The second gate of the driving transistor is electrically connected to the first electrode plate, the second electrode of the driving transistor is electrically connected to the first electrode of the first switching transistor, the second electrode of the first switching transistor is electrically connected to the first electrode plate, and the voltage value connected to the first gate of the first switching transistor is less than the voltage value connected to the first gate of the driving transistor.

[0038] In some possible implementations, the pixel circuit further includes a second switch transistor, the second switch transistor being a dual-gate transistor, the first electrode of the second switch transistor being electrically connected to the second electrode plate, and the voltage value connected to the first gate of the second switch transistor being smaller than the voltage value connected to the first gate of the driving transistor;

[0039] Preferably, the pixel circuit further includes a second storage capacitor, the second storage capacitor includes a third plate and a fourth plate, the third plate is electrically connected to the first electrode of the second switching transistor, and the fourth plate is electrically connected to the power supply voltage line;

[0040] Preferably, the second electrode of the second switch transistor is electrically connected to the data voltage signal line;

[0041] Preferably, the first electrode of the driving transistor is electrically connected to a power supply voltage line;

[0042] Preferably, the second gate of the first switch transistor is electrically connected to the first scan signal wiring;

[0043] Preferably, the second gate of the second switch transistor is electrically connected to the second scan signal wiring.

[0044] In some possible implementations, the pixel circuit further includes a third switch transistor, wherein a second electrode of the third switch transistor is electrically connected to the second electrode of the driving transistor and the first electrode of the first switch transistor;

[0045] Preferably, a gate of the third switching transistor is electrically connected to a light emitting control signal line, and a first electrode of the third switching transistor is electrically connected to a first electrode of the light emitting device.

[0046] In some possible implementations, the pixel circuit further includes a fourth switch transistor, wherein a first electrode of the fourth switch transistor is electrically connected to the first electrode of the third switch transistor and the first electrode of the light-emitting device;

[0047] Preferably, a gate electrode of the fourth switch transistor is electrically connected to the third scan signal line, and a second electrode of the fourth switch transistor is electrically connected to the initialization voltage signal line.

[0048] In some possible implementations, the present application further provides another pixel circuit, comprising:

[0049] a driving transistor, wherein the driving transistor is a dual-gate transistor;

[0050] a second switch transistor, wherein the second switch transistor is a double-gate transistor;

[0051] a first storage capacitor, the first storage capacitor comprising a first electrode plate and a second electrode plate;

[0052] The second gate of the driving transistor is electrically connected to the first plate, the first electrode of the second switching transistor is electrically connected to the second plate, and the voltage value connected to the first gate of the second switching transistor is smaller than the voltage value connected to the first gate of the driving transistor.

[0053] In some possible implementations, the pixel circuit further includes a first switching transistor, the first switching transistor being a dual-gate transistor, the second electrode of the driving transistor being electrically connected to the first electrode of the first switching transistor, the second electrode of the first switching transistor being electrically connected to the first electrode plate, and a voltage value connected to the first gate of the first switching transistor being smaller than a voltage value connected to the first gate of the driving transistor;

[0054] Preferably, the pixel circuit further includes a second storage capacitor, the second storage capacitor includes a third plate and a fourth plate, the third plate is electrically connected to the first electrode of the second switching transistor, and the fourth plate is electrically connected to the power supply voltage line;

[0055] Preferably, the second electrode of the second switch transistor is electrically connected to the data voltage signal line;

[0056] Preferably, the first electrode of the driving transistor is electrically connected to a power supply voltage line;

[0057] Preferably, the second gate of the first switch transistor is electrically connected to the first scan signal wiring;

[0058] Preferably, the second gate of the second switch transistor is electrically connected to the second scan signal wiring.

[0059] Compared with the prior art, this application has the following beneficial effects:

[0060] The present application provides an array substrate and pixel circuit. By electrically connecting the first gate of a driving transistor to a first voltage trace, and the first gate of a first switching transistor to a second voltage trace, and the voltage value connected to the second voltage trace is less than the voltage value connected to the first voltage trace, the positive bias heating stress of the first switching transistor can be reduced, thereby improving the display uniformity of the corresponding display panel, and ultimately improving the display effect of the corresponding display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0062] Figure 1 A schematic structural diagram of a pixel circuit of an array substrate provided in an embodiment of the present application;

[0063] Figure 2 A schematic diagram of a structure in which a first switch transistor is electrically connected to a first connecting line according to an embodiment of the present application;

[0064] Figure 3 A schematic diagram of the structure of the electrical connection between the driving transistor and the second connecting line provided in an embodiment of the present application;

[0065] Figure 4 A schematic diagram of a structure in which a second switch transistor is electrically connected to a third connection line according to an embodiment of the present application;

[0066] Figure 5 A schematic cross-sectional view of a display panel provided in an embodiment of the present application;

[0067] Figure 6 A cross-sectional schematic diagram of a display panel provided in an embodiment of the present application includes a packaging unit;

[0068] Figure 7 A cross-sectional schematic diagram of a display panel provided in an embodiment of the present application includes a second encapsulation layer and a third encapsulation layer.

[0069] Figure numerals: 1. substrate; 2. first connecting trace; 3. first semiconductor layer; 4. first top gate; 5. first bottom gate; 6. first drain; 7. first source; 8. second connecting trace; 9. second semiconductor layer; 10. third connecting trace; 11. third semiconductor layer; 12. driving trace layer; 13. pixel circuit; 14. first electrode; 15. pixel defining layer; 151. pixel opening; 16. isolation structure; 161. first isolation portion; 162. second isolation portion; 163. third isolation portion; 17. isolation opening; 18. light-emitting functional portion; 19. second electrode; 20. packaging unit; 21. second packaging layer; 22. third packaging layer; 23. array substrate; 24. second bottom gate; 25. second drain; 26. second source; 27. second top gate; 28. third bottom gate; 29. ​​third drain; 30. third source; 31. third top gate. DETAILED DESCRIPTION

[0070] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0071] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without making any creative efforts shall fall within the scope of protection of the present application.

[0072] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0073] In the description of this application, it should be noted that the terms "center," "upper," "lower," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the inventive product is typically placed when in use. These terms are intended solely to facilitate the description of this application and simplify the description, and are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third," etc., are used solely to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0074] It should be noted that, in the absence of conflict, different features in the embodiments of the present application can be combined with each other.

[0075] Increasing the density of light-emitting devices (i.e., pixel density) in display panels is a key approach to enhancing display quality. However, current display panels manufactured using fine metal mask (FMM) evaporation technology are currently limited by technical limitations and cannot achieve further increases in light-emitting device density. Long-term research has revealed that, to address this limitation, some display panels incorporate an isolation structure. During the full-layer evaporation deposition of the light-emitting functional layer and the second electrode, the light-emitting functional layer and the second electrode are disconnected at the isolation structure. Through multiple evaporation and etching processes (i.e., light-emitting device patterning), light-emitting devices of different colors can be formed in different isolation openings.

[0076] The array substrate in the related technology includes a driving wiring layer located on one side of the substrate, the driving wiring layer includes a pixel circuit, and the pixel circuit includes a driving transistor and multiple switching transistors, wherein the switching transistor plays the role of turning on and off the input signal, and the driving transistor plays the role of driving the corresponding light-emitting device to emit light.

[0077] In the related art, the positive bias thermal stress of the driving transistor and some switching transistors is relatively large. After a period of use (for example, half a year), the brightness and color of the corresponding light-emitting devices will become uneven, thereby causing the corresponding display panel to have uneven display problems, ultimately affecting the display effect of the corresponding display panel.

[0078] In order to solve the above-mentioned technical problems, the following technical solutions are innovatively designed. The specific implementation solutions of this application will be described in detail below with reference to the accompanying drawings. It should be noted that the defects existing in the solutions in the above-mentioned prior art are the results obtained after practice and careful study. Therefore, the discovery process of the above-mentioned technical problems and the solutions proposed in the following embodiments for the above-mentioned problems should all be contributions made to this application in the process of invention and creation, and should not be understood as technical contents known to those skilled in the art.

[0079] See Figure 1-Figure 3 and Figure 5 This embodiment provides an array substrate. The array substrate 23 includes a substrate 1 and a driving wiring layer 12 .

[0080] The drive wiring layer 12 is located on one side of the substrate 1. The drive wiring layer 12 includes a pixel circuit 13, a first voltage wiring VDD1 and a second voltage wiring VDD2. The pixel circuit 13 includes a drive transistor T1 and a first switch transistor T2. The drive transistor T1 and the first switch transistor T2 are both dual-gate transistors. The first gate of the drive transistor T1 is electrically connected to the first voltage wiring VDD1, and the first gate of the first switch transistor T2 is electrically connected to the second voltage wiring VDD2. The voltage value connected to the second voltage wiring VDD2 is less than the voltage value connected to the first voltage wiring VDD1.

[0081] The driving transistor T1 may be a PMOS double-gate transistor, the first switch transistor T2 may be an NMOS double-gate transistor, and the first gate of the driving transistor T1 is the bottom gate of the driving transistor T1, that is, Figure 3 The second bottom gate 24 shown; the first gate of the first switching transistor T2 is the bottom gate of the first switching transistor T2, that is, Figure 2 The first bottom gate 5 is shown.

[0082] After long-term research, it was found that after a voltage is connected to the bottom gate of the driving transistor T1 and the first switching transistor T2, the threshold voltage of the driving transistor T1 and the first switching transistor T2 can be adjusted, thereby reducing the positive bias heating stress of the driving transistor T1 and the first switching transistor T2, and ultimately improving the display uniformity of the corresponding display panel.

[0083] However, if the first gates of the driving transistor T1 and the first switching transistor T2 are connected to the same voltage, such as 0V, 2.8V, or 4.6V, certain problems may arise. Specifically, if the first gates of the driving transistor T1 and the first switching transistor T2 are both connected to 0V, the driving transistor T1 will cause the corresponding light-emitting device D1 to not meet the required brightness. For example, if the first gate of the driving transistor T1 is connected to 0V, the maximum brightness cannot be increased to above 1600 nits for a single-layer OLED device or above 3200 nits for a dual-layer device. Therefore, the first gates of the driving transistor T1 and the first switching transistor T2 cannot be connected to 0V.

[0084] If the first gates of the driving transistor T1 and the first switching transistor T2 are both connected to 2.8V or 4.6V, the threshold voltage of the first switching transistor T2 will be biased negative to -0.8V and -1.2V, respectively. This will not only cause a simultaneous increase in power consumption, but also increase the positive bias thermal stress of the first switching transistor T2, causing the turn-on current of the first switching transistor T2 to decrease, the brightness of the corresponding light-emitting device D1 to decrease, and the color to become uneven, which will ultimately cause the corresponding display panel to have a horizontal display unevenness problem.

[0085] Based on the above analysis, the study found that the first gate of the driving transistor T1 can be connected to the first voltage line VDD1. The first voltage line VDD1 can be connected to a voltage that can meet the required brightness of the corresponding light-emitting device D1, such as the 2.8V or 4.6V mentioned above.

[0086] At the same time, the first gate of the first switching transistor T2 is connected to the second voltage trace VDD2. The second voltage trace VDD2 is connected to a smaller voltage than the first voltage trace VDD1 for connecting the first gate of the first switching transistor T2. This can save energy on the one hand and reduce the positive bias heating stress of the first switching transistor T2 on the other hand. This ensures that the corresponding display panel will not have problems of uneven brightness and color after being used for a period of time, thereby improving the display uniformity of the corresponding display panel and ultimately improving the display effect of the corresponding display panel.

[0087] Based on the above design, this embodiment electrically connects the first gate of the driving transistor T1 to the first voltage trace VDD1, and the first gate of the first switching transistor T2 to the second voltage trace VDD2, and the voltage value connected to the second voltage trace VDD2 is less than the voltage value connected to the first voltage trace VDD1. This can reduce the positive bias heating stress of the first switching transistor T2, thereby improving the display uniformity of the corresponding display panel, and ultimately improving the display effect of the corresponding display panel.

[0088] For some possible implementations, see Figure 1 and Figure 4 and Figure 5 The pixel circuit 13 also includes a second switching transistor T3, which is a dual-gate transistor. The driving wiring layer 12 also includes a third voltage wiring VDD3. The first gate of the second switching transistor T3 is electrically connected to the third voltage wiring VDD3. The voltage value connected to the third voltage wiring VDD3 is less than the voltage value connected to the first voltage wiring VDD1.

[0089] The third voltage trace VDD3 and the second voltage trace VDD2 may both be electrically connected to a chip of the display panel, and the chip provides corresponding voltage values ​​for the third voltage trace VDD3 and the second voltage trace VDD2.

[0090] The second switch transistor T3 may be an NMOS double-gate transistor, and the first gate of the second switch transistor T3 is the bottom gate of the second switch transistor T3, that is, Figure 4 The third bottom gate 28 shown is the same as the first switching transistor T2. If the voltage connected to the first gate of the second switching transistor T3 is equal to the voltage connected to the first gate of the driving transistor T1, the positive bias thermal stress of the second switching transistor T3 will increase, the turn-on current of the second switching transistor T3 will decrease, the brightness of the corresponding light-emitting device D1 will decrease, the color will be uneven, and ultimately the corresponding display panel will have the problem of horizontal display unevenness.

[0091] In this embodiment, the first gate of the second switching transistor T3 is electrically connected to the third voltage line VDD3, and the voltage value connected to the third voltage line VDD3 is smaller than the voltage value connected to the first gate of the driving transistor T1. In this way, the positive bias heating stress of the second switching transistor T3 can be reduced, so that the corresponding display panel will not produce the problem of uneven brightness and color after being used for a period of time, thereby improving the display uniformity of the corresponding display panel and ultimately improving the display effect of the corresponding display panel.

[0092] In some possible implementations, the voltage value connected to the first voltage trace VDD1 is greater than or equal to 2.8V and less than or equal to 4.6V.

[0093] For example, the voltage value connected to the first voltage trace VDD1 can be 2.8V, 3V, 3.5V, 4V or 4.6V. Reasonable setting of the voltage value connected to the first voltage trace VDD1 can provide a more appropriate voltage value for the first gate of the driving transistor T1, while appropriately reducing the positive bias heating stress of the driving transistor T1, and at the same time, the brightness of the corresponding light-emitting device D1 can meet the requirements.

[0094] Optionally, the voltage value connected to the second voltage trace VDD2 is greater than or equal to -1V and less than or equal to 0V.

[0095] For example, the voltage value connected to the second voltage trace VDD2 can be -1V, -0.8V, -0.6V, -0.4V, -0.2V or 0V. Reasonable setting of the voltage value connected to the second voltage trace VDD2 can provide a more appropriate voltage value for the first gate of the first switching transistor T2, thereby effectively reducing the positive bias heating stress of the first switching transistor T2.

[0096] For example, the threshold voltage of the first switch transistor T2 can be greater than or equal to -0.2V and less than or equal to 0.2V. Specifically, the threshold voltage of the first switch transistor T2 can be -0.2V, -0.1V, 0V, 0.1V or 0.2V.

[0097] The forward bias heating stress of the first switch transistor T2 can be reduced to less than 0.5V. For example, the forward bias heating stress of the first switch transistor T2 can be reduced to 0.4V, 0.3V, or 0.2V.

[0098] Optionally, a voltage value connected to the third voltage trace VDD3 is greater than or equal to -1V and less than or equal to 0V.

[0099] For example, the voltage value connected to the third voltage trace VDD3 can be -1V, -0.8V, -0.6V, -0.4V, -0.2V or 0V. Reasonable setting of the voltage value connected to the third voltage trace VDD3 can provide a more appropriate voltage value for the first gate of the second switching transistor T3, thereby effectively reducing the positive bias heating stress of the second switching transistor T3.

[0100] For example, the threshold voltage of the second switch transistor T3 can be greater than or equal to -0.2V and less than or equal to 0.2V. Specifically, the threshold voltage of the second switch transistor T3 can be -0.2V, -0.1V, 0V, 0.1V or 0.2V.

[0101] Finally, the forward bias heating stress of the second switch transistor T3 can be reduced to less than 0.5V. For example, the forward bias heating stress of the second switch transistor T3 can be reduced to 0.4V, 0.3V or 0.2V.

[0102] Preferably, the voltage value connected to the third voltage line VDD3 is equal to the voltage value connected to the second voltage line VDD2.

[0103] Optionally, the third voltage line VDD3 reuses the second voltage line VDD2.

[0104] For example, the first gate of the first switching transistor T2 and the first gate of the second switching transistor T3 can be connected to 0V, 0.2V, 0.5V, 0.8V or 1V at the same time. In this way, there is no need to set corresponding different voltage lines for the first switching transistor T2 and the second switching transistor T3, thereby reducing the design difficulty of the driving wiring layer 12.

[0105] For some possible implementations, see again Figure 2 The first switch transistor T2 includes a first semiconductor layer 3 , and a first gate of the first switch transistor T2 is located on a side of the first semiconductor layer 3 close to the substrate 1 .

[0106] Optionally, the driving wiring layer 12 also includes a second connecting wiring 8 located between the substrate 1 and the first gate of the first switching transistor T2, and a first connecting wiring 2 located on the side of the second connecting wiring 8 away from the substrate 1, and the first gate of the first switching transistor T2 is electrically connected to the second voltage wiring VDD2 through the first connecting wiring 2.

[0107] Optionally, the material of the first semiconductor layer 3 includes metal oxide. For example, the material of the first semiconductor layer 3 may be indium gallium zinc oxide or indium zinc oxide.

[0108] The first connecting line 2 may be located on the first conductive layer of the array substrate 23 . The first connecting line 2 may facilitate electrical connection between the first gate of the first switching transistor T2 and the second voltage line VDD2 .

[0109] For some possible implementations, see again Figure 3 The driving transistor T1 includes a second semiconductor layer 9 , and a first gate of the driving transistor T1 is located on a side of the second semiconductor layer 9 close to the substrate 1 .

[0110] Optionally, the driving wiring layer 12 further includes a first connecting wiring 2 located between the substrate 1 and the second semiconductor layer 9 and a second connecting wiring 8 located between the first connecting wiring 2 and the substrate 1 , and the first gate of the driving transistor T1 is electrically connected to the first voltage wiring VDD1 through the second connecting wiring 8 .

[0111] The second connecting wire 8 can more easily electrically connect the first gate of the driving transistor T1 to the first voltage wire VDD1 .

[0112] Preferably, see again Figure 4 The second switch transistor T3 includes a third semiconductor layer 11 , and a first gate of the second switch transistor T3 is located on a side of the third semiconductor layer 11 close to the substrate 1 .

[0113] Optionally, the driving wiring layer 12 also includes a second connecting wiring 8 located between the substrate 1 and the first gate of the second switching transistor T3 and a third connecting wiring 10 located away from the substrate 1, and the first gate of the second switching transistor T3 is electrically connected to the third voltage wiring VDD3 through the third connecting wiring 10.

[0114] Preferably, the material of the third semiconductor layer 11 includes metal oxide. For example, the material of the third semiconductor layer 11 may be indium gallium zinc oxide or indium zinc oxide.

[0115] The third connection line 10 and the first connection line 2 can be arranged on the same layer, that is, the third connection line 10 can be located in the first conductive layer of the array substrate 23. The third connection line 10 can more conveniently electrically connect the first gate of the second switch transistor T3 to the third voltage line VDD3.

[0116] Preferably, see again Figure 2-Figure 4 The array substrate 23 includes a display area AA and a non-display area AB surrounding at least part of the display area AA. At least part of the first voltage line VDD1 is located in the non-display area AB. The first connecting line 2 extends to the non-display area AB and is electrically connected to the second voltage line VDD2.

[0117] Optionally, at least a portion of the second voltage line VDD2 is located in the non-display area AB, and the second connection line 8 extends to the non-display area AB and is electrically connected to the first voltage line VDD1 .

[0118] At least a portion of the third voltage line VDD3 is located in the non-display area AB, and the third connection line 10 extends to the non-display area AB and is electrically connected to the third voltage line VDD3 .

[0119] The first voltage line VDD1 , the second voltage line VDD2 and the third voltage line VDD3 are arranged in the non-display area AB so that the first voltage line VDD1 , the second voltage line VDD2 and the third voltage line VDD3 do not occupy the space of the display area and do not affect the arrangement space of the pixel circuit 13 .

[0120] For some possible implementations, see again Figure 1-Figure 3 and Figure 5 The present application also provides another array substrate, which includes a substrate 1 and a driving wiring layer 12.

[0121] The drive wiring layer 12 is located on one side of the substrate 1. The drive wiring layer 12 includes a pixel circuit 13, a first voltage wiring VDD1 and a third voltage wiring VDD3. The pixel circuit 13 includes a drive transistor T1 and a second switch transistor T3. The drive transistor T1 and the second switch transistor T3 are both dual-gate transistors. The first gate of the drive transistor T1 is electrically connected to the first voltage wiring VDD1, and the first gate of the second switch transistor T3 is electrically connected to the third voltage wiring VDD3. The voltage value connected to the third voltage wiring VDD3 is less than the voltage value connected to the first voltage wiring VDD1.

[0122] The driving transistor T1 may be a PMOS double-gate transistor, the second switch transistor T3 may be an NMOS double-gate transistor, and the first gate of the driving transistor T1 is the bottom gate of the driving transistor T1, that is, Figure 3The second bottom gate 24 shown; the first gate of the second switching transistor T3 is the bottom gate of the second switching transistor T3, that is, Figure 4 A third bottom gate 28 is shown.

[0123] After long-term research, it was found that after a voltage is connected to the bottom gate of the driving transistor T1 and the second switching transistor T3, the threshold voltage of the driving transistor T1 and the second switching transistor T3 can be adjusted, thereby reducing the positive bias heating stress of the driving transistor T1 and the second switching transistor T3, and ultimately improving the display uniformity of the corresponding display panel.

[0124] However, if the first gates of the driving transistor T1 and the second switching transistor T3 are connected to the same voltage, such as 0V, 2.8V, or 4.6V, certain problems may arise. Specifically, if the first gates of the driving transistor T1 and the second switching transistor T3 are both connected to 0V, the driving transistor T1 will cause the corresponding light-emitting device D1 to not meet the required brightness. For example, if the first gate of the driving transistor T1 is connected to 0V, the maximum brightness cannot be increased to above 1600 nits for a single-layer OLED device or above 3200 nits for a dual-layer device. Therefore, the first gates of the driving transistor T1 and the second switching transistor T3 cannot be connected to 0V.

[0125] If the first gates of the driving transistor T1 and the second switching transistor T3 are both connected to 2.8V or 4.6V, the threshold voltage of the second switching transistor T3 will be biased negative to -0.8V and -1.2V, respectively. This will not only cause a simultaneous increase in power consumption, but also increase the positive bias thermal stress of the second switching transistor T3, causing the turn-on current of the second switching transistor T3 to decrease, resulting in a decrease in the brightness of the corresponding light-emitting device D1 and uneven color. This will ultimately cause the corresponding display panel to have a horizontal display unevenness problem.

[0126] In this embodiment, the first gate of the second switching transistor T3 is electrically connected to the third voltage line VDD3, and the voltage value connected to the third voltage line VDD3 is smaller than the voltage value connected to the first gate of the driving transistor T1. In this way, the positive bias heating stress of the second switching transistor T3 can be reduced, so that the corresponding display panel will not produce the problem of uneven brightness and color after being used for a period of time, thereby improving the display uniformity of the corresponding display panel and ultimately improving the display effect of the corresponding display panel.

[0127] The remaining technical solutions of the array substrate in this embodiment are the same as those of the array substrate in the above embodiment and will not be described again here.

[0128] For some possible implementations, see again Figure 1-Figure 4The present application also provides a pixel circuit, the pixel circuit 13 includes a driving transistor T1, a first switching transistor T2, a second switching transistor T3 and a first storage capacitor C ST1 , the first storage capacitor C ST1 It includes a first electrode plate and a second electrode plate. The first electrode plate is located on a side of the second electrode plate close to the substrate 1 . The second gate of the driving transistor T1 is electrically connected to the first electrode plate.

[0129] Optionally, the driving wiring layer 12 further includes a power supply voltage wiring ELVDD, a first electrode of the driving transistor T1 is electrically connected to the power supply voltage wiring ELVDD, and a second electrode of the driving transistor T1 is electrically connected to a first electrode of the first switch transistor T2.

[0130] Optionally, the driving wiring layer 12 further includes a first scanning signal wiring Scan1 , the second gate of the first switching transistor T2 is electrically connected to the first scanning signal wiring Scan1 , and the second electrode of the first switching transistor T2 is electrically connected to the first electrode plate.

[0131] Optionally, the driving wiring layer 12 further includes a second scanning signal wiring Scan2 , the second gate of the second switching transistor T3 is electrically connected to the second scanning signal wiring Scan2 , and the first electrode of the second switching transistor T3 is electrically connected to the second electrode plate.

[0132] Optionally, the driving wiring layer 12 further includes a data voltage signal line Vdata, and the second electrode of the second switch transistor T3 is electrically connected to the data voltage signal line Vdata.

[0133] Optionally, the pixel circuit 13 further includes a second storage capacitor C ST2 , the second storage capacitor C ST2 It includes a third plate and a fourth plate. The third plate is located on a side of the fourth plate close to the substrate 1 . The third plate is electrically connected to the second plate and the first electrode of the second switch transistor T3 . The fourth plate is electrically connected to the power supply voltage line ELVDD.

[0134] Optionally, the pixel circuit 13 further includes a third switch transistor T4 , and a second electrode of the third switch transistor T4 is electrically connected to the second electrode of the driving transistor T1 and the first electrode of the first switch transistor T2 .

[0135] Optionally, the driving wiring layer 12 further includes a light emitting control signal line EM, a gate of the third switch transistor T4 is electrically connected to the light emitting control signal line EM, and a first electrode of the third switch transistor T4 is electrically connected to the first electrode 14 of the light emitting device D1.

[0136] Optionally, the pixel circuit 13 further includes a fourth switch transistor T5 , and a first electrode of the fourth switch transistor T5 is electrically connected to the first electrode of the third switch transistor T4 and the first electrode 14 of the light emitting device D1 .

[0137] Preferably, the driving wiring layer 12 further includes a third scanning signal wiring Scan3 and an initialization voltage signal line Vref, the gate of the fourth switch transistor T5 is electrically connected to the third scanning signal wiring Scan3, and the second electrode of the fourth switch transistor T5 is electrically connected to the initialization voltage signal line Vref.

[0138] Optionally, a reset line Vini is further included. A fifth switch transistor Mux1 is provided between the reset line Vini and the second electrode of the second switch transistor T3. When the fifth switch transistor Mux1 is turned on, the reset line Vini provides a reset signal to the second switch transistor T3 to reset the second switch transistor T3.

[0139] Optionally, a sixth switch transistor Mux2 is further provided between the second electrode of the second switch transistor T3 and the data voltage signal line Vdata. When the sixth switch transistor Mux2 is turned on, the data signal of the data voltage signal line Vdata is written into the second electrode of the second switch transistor T3.

[0140] In this embodiment, one of the first electrode and the second electrode of the transistor is a drain electrode, and the other is a source electrode. The semiconductor layer in the transistor includes a source region, a drain region, and a channel region. The drain electrode of the transistor is connected to the drain region, and the source electrode is connected to the source region. For example, Figure 2 The first drain electrode 6 of the first switching transistor T2 is connected to the drain region of the first semiconductor layer 3, and the first source electrode 7 of the first switching transistor T2 is connected to the source region of the first semiconductor layer 3; Figure 3 The second drain electrode 25 of the driving transistor T1 is connected to the drain region of the second semiconductor layer 9, and the second source electrode 26 of the driving transistor T1 is connected to the source region of the second semiconductor layer 9; Figure 4 The third drain electrode 29 of the second switching transistor T3 is connected to the drain region of the third semiconductor layer 11 , and the third source electrode 30 of the second switching transistor T3 is connected to the source region of the third semiconductor layer 11 .

[0141] The second gate of the first switch transistor T2 is located on the side of the first semiconductor layer 3 away from the substrate 1. The second gate of the first switch transistor T2 is the top gate of the first switch transistor T2, that is, Figure 2 The first top gate 4 shown; the second gate of the driving transistor T1 is located on the side of the second semiconductor layer 9 away from the substrate 1, and the second gate of the driving transistor T1 is the top gate of the driving transistor T1, that is, Figure 3The second top gate 27 shown; the second gate of the second switching transistor T3 is located on the side of the third semiconductor layer 11 away from the substrate 1, and the second gate of the second switching transistor T3 is the top gate of the second switching transistor T3, that is, Figure 4 The third top gate 31 is shown.

[0142] The pixel density of the display panel used with the array substrate 23 may be greater than 1000. When the pixel density of the display panel is greater than 1000, the pixel circuit 13 corresponding to the display panel is usually a 5T2C pixel circuit 13.

[0143] The working process of the pixel circuit 13 of the array substrate 23 generally includes an initialization phase, a data writing phase and a light emitting phase.

[0144] During the initialization phase, the third scan signal line Scan3 inputs a conduction level, such as a low level, to turn on the fourth switching transistor T5. The initialization voltage inputted by the initialization voltage signal line Vref is written to the first electrode 14 (e.g., the anode) of the light-emitting device D1, thereby initializing the first electrode 14 (e.g., the anode) of the light-emitting device D1. Furthermore, during the initialization phase, the first switching transistor T2 and the second gate of the driving transistor T1 are also initialized.

[0145] In the data writing stage, the second scanning signal line Scan2 and the second scanning signal line Scan1 input a conduction level, such as a low level, to control the second switch transistor T3 and the first switch transistor T2 to be turned on respectively. The data voltage input by the data voltage signal line Vdata is written to the second gate of the driving transistor T1 through the second switch transistor T3 and the first switch transistor T2. The voltage written to the second gate of the driving transistor T1 is the sum of the data voltage input by the data voltage signal line Vdata and the threshold voltage of the driving transistor T1. In the data writing stage, the first storage capacitor C ST1 and the second storage capacitor C ST2 Stores the written data voltage.

[0146] In the light emitting stage, the light emitting control signal line EM inputs a conduction level, such as a low level, to control the third switch transistor T4 to be turned on, the driving transistor T1 and the third switch transistor T4 form a driving current path, and the driving transistor T1 provides a driving current to make the light emitting device D1 emit light.

[0147] In summary, in the pixel circuit 13, the first gate of the driving transistor T1 and the first gate of the first switching transistor T2 and the first gate of the second switching transistor T3 are connected to differentiated voltages, that is, the first gate of the driving transistor T1 is connected to a relatively larger voltage, and the first gate of the first switching transistor T2 and the first gate of the second switching transistor T3 are connected to a relatively smaller voltage. This can not only make the corresponding light-emitting device D1 meet the required brightness, but also reduce the positive bias heating stress of the first switching transistor T2 and the second switching transistor T3, so that the corresponding display panel will still not have the problem of uneven brightness and color after being used for a period of time, thereby improving the display uniformity of the corresponding display panel, and at the same time saving energy consumption, so that the corresponding display panel has stronger market competitiveness.

[0148] For some possible implementations, see again Figure 1-Figure 4 The present application also provides another pixel circuit, which includes a driving transistor T1, a second switching transistor T3 and a first storage capacitor C ST1 .

[0149] The first storage capacitor C ST1 It includes a first electrode plate and a second electrode plate, the first electrode plate is located on the side of the second electrode plate close to the substrate 1, the second gate of the driving transistor T1 is electrically connected to the first electrode plate, the first electrode of the second switching transistor T3 is electrically connected to the second electrode plate, the voltage value connected to the first gate of the second switching transistor T3 is smaller than the voltage value connected to the first gate of the driving transistor T1, and the driving transistor T1 and the second switching transistor T3 are both dual-gate transistors.

[0150] In the pixel circuit 13, the first gate of the driving transistor T1 and the first gate of the second switching transistor T3 are connected to differentiated voltages, that is, the first gate of the driving transistor T1 is connected to a relatively larger voltage, and the first gate of the second switching transistor T3 is connected to a relatively smaller voltage. This not only enables the corresponding light-emitting device D1 to meet the required brightness, but also reduces the positive bias heating stress of the second switching transistor T3, so that the corresponding display panel will not have the problem of uneven brightness and color after being used for a period of time, thereby improving the display uniformity of the corresponding display panel, while also saving energy consumption, making the corresponding display panel more competitive in the market.

[0151] The remaining technical solutions of the pixel circuit in this embodiment are the same as those of the pixel circuit in the above embodiment and will not be described again here.

[0152] For some possible implementations, see again Figure 5 The present application also provides a display panel, which includes the array substrate 23, the isolation structure 16 and a plurality of light-emitting devices D1 in the present application.

[0153] The isolation structure 16 is located on one side of the array substrate 23 . The isolation structure 16 encloses a plurality of isolation openings 17 . At least a portion of the light emitting device D1 is located in a corresponding isolation opening 17 .

[0154] The light-emitting device D1 includes a first electrode 14, a light-emitting functional portion 18 and a second electrode 19 stacked in sequence along the thickness direction of the array substrate 23. The isolation structure 16 includes a conductive material. The second electrode 19 is electrically connected to the isolation structure 16. The display panel also includes a pixel defining layer 15 located between the first electrode 14 and the isolation structure 16. The pixel defining layer 15 includes a pixel opening 151 that exposes a portion of the first electrode 14. The pixel opening 151 is connected to the isolation opening 17. The orthographic projection of the pixel opening 151 on the array substrate 23 is located within the orthographic projection of the isolation opening 17 on the array substrate 23.

[0155] The provision of isolation structure 16 enables the display panel to form film layers of light-emitting devices D1 of different colors in different isolation openings 17 without the need for a fine mask. When forming the light-emitting material layer, the light-emitting material layer is separated by isolation structure 16 to form multiple spaced light-emitting functional units 18. When forming the second electrode material layer, the second electrode material layer is separated by isolation structure 16 to form multiple spaced second electrodes 19. Isolation structure 16 comprises a conductive material, and second electrodes 19 are electrically connected to isolation structure 16. One first electrode 14, one light-emitting functional unit 18, and one second electrode 19 form one light-emitting device D1. The first electrode 14 can be an anode, and the second electrode 19 can be a cathode.

[0156] In this way, different light-emitting devices D1 can be made independent of each other, thereby reducing crosstalk between adjacent light-emitting devices D1 and improving the display quality of the display panel. At the same time, due to the presence of the isolation structure 16, the light-emitting material layer and the second electrode material layer in each color light-emitting device D1 in the display panel can be first prepared on the entire surface and then patterned, thereby eliminating the need for a fine mask and reducing the production cost of the display panel.

[0157] For some possible implementations, see Figure 6 The display panel also includes a plurality of packaging units 20, which are located on the side of the corresponding light-emitting device D1 away from the array substrate 23, and a portion of the packaging unit 20 extends from the side of the isolation structure 16 toward the isolation opening 17 to the side of the isolation structure 16 away from the array substrate 23.

[0158] Optionally, the packaging units 20 corresponding to the multiple light-emitting devices D1 with the same light emission are arranged at intervals, and there is a gap between the packaging unit 20 located on the side of the isolation structure 16 away from the array substrate 23 and the side of the isolation structure 16 away from the array substrate 23.

[0159] During the patterning process of the light-emitting device D1 , the first packaging material layer is disconnected at the isolation structure 16 to form the packaging unit 20 . The packaging unit 20 can completely and independently package the corresponding light-emitting device D1 , thereby improving the display characteristics of the display panel.

[0160] For some possible implementations, see Figure 7 The display panel further includes a second encapsulation layer 21 located on a side of the encapsulation unit 20 away from the array substrate 23 and a third encapsulation layer 22 located on a side of the second encapsulation layer 21 away from the array substrate 23 .

[0161] Preferably, the materials of the encapsulation unit 20 and the third encapsulation layer 22 both include inorganic materials, and the material of the second encapsulation layer 21 includes organic materials.

[0162] For example, the encapsulation unit 20 and the third encapsulation layer 22 can be formed by chemical vapor deposition (CVD), and the second encapsulation layer 21 can be formed by inkjet printing (IJP). The second encapsulation layer 21 and the third encapsulation layer 22 can provide a better encapsulation effect for the light-emitting device D1, thereby further improving the encapsulation quality of the display panel.

[0163] For some possible implementations, see again Figure 6 The isolation structure 16 includes a first isolation portion 161 and a second isolation portion 162 which are stacked in sequence in a direction away from the array substrate 23. The orthographic projection of the side of the first isolation portion 161 away from the array substrate 23 on the array substrate 23 is located within the orthographic projection of the second isolation portion 162 on the array substrate 23. The orthographic projection area of ​​the side of the first isolation portion 161 away from the array substrate 23 on the array substrate 23 is smaller than the orthographic projection area of ​​the second isolation portion 162 on the array substrate 23.

[0164] Because the second isolation portion 162 is located on a side of the first isolation portion 161 away from the array substrate 23, and the lateral width of the second isolation portion 162 is greater than the lateral width of the first isolation portion 161 in a plane parallel to the array substrate 23, the second isolation portion 162 disconnects the light-emitting material layer and the second electrode material layer at the isolation structure 16. Thus, the isolation structure 16 formed by the first isolation portion 161 and the second isolation portion 162 makes it easier to independently package each light-emitting device D1, thereby improving the packaging yield of the display panel.

[0165] Optionally, the second electrode 19 is electrically connected to the first isolation portion 161. The first isolation portion 161 includes a conductive material, and the second electrode 19 corresponding to the light-emitting device D1 extends to contact the sidewall of the first isolation portion 161 to achieve electrical connection between the second electrode 19 corresponding to the light-emitting device D1 and the first isolation portion 161.

[0166] Optionally, see again Figure 7 The isolation structure 16 further includes a third isolation portion 163 located on a side of the first isolation portion 161 facing the array substrate 23 , and the second electrode 19 is electrically connected to the third isolation portion 163 .

[0167] The third isolation portion 163 includes a conductive material. The second electrode 19 corresponding to the light emitting device D1 extends to contact the sidewall of the third isolation portion 163 to achieve electrical connection between the second electrode 19 corresponding to the light emitting device D1 and the third isolation portion 163 .

[0168] Specifically, the third isolation portion 163 is made of molybdenum or titanium; and / or the first isolation portion 161 is made of aluminum, silver, or copper; and / or the second isolation portion 162 is made of titanium or molybdenum. Thus, when the isolation structure 16 separates the second electrode material layer into the second electrode 19, the second electrode 19 is more easily electrically connected to the third isolation portion 163.

[0169] The orthographic projection of the light emitting functional portion 18 on the array substrate 23 is outside the orthographic projection of the third isolation portion 163 on the array substrate 23. In this way, the light emitting functional portion 18 does not overlap with the isolation structure 16, thereby effectively improving the crosstalk problem between the light emitting devices D1.

[0170] In some possible implementations, the present application further provides an electronic device including the display panel described herein. The electronic device may include a device with image processing capabilities, such as a server, a personal computer, a laptop computer, a mobile phone, a tablet computer, a wearable device, or an in-vehicle display device. Because the electronic device includes the display panel described herein, the electronic device exhibits a better display quality.

[0171] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0172] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. An array substrate, characterized in that: The array substrate includes: substrate; A drive wiring layer is located on one side of the substrate, the drive wiring layer includes a pixel circuit, a first voltage wiring and a second voltage wiring, the pixel circuit includes a drive transistor and a first switch transistor, the drive transistor and the first switch transistor are both dual-gate transistors, the first gate of the drive transistor is electrically connected to the first voltage wiring, the first gate of the first switch transistor is electrically connected to the second voltage wiring, the voltage value connected to the second voltage wiring is less than the voltage value connected to the first voltage wiring, and the positive bias heating stress of the first switch transistor is less than 0.5V.

2. The array substrate according to claim 1, wherein: The voltage value connected to the second voltage trace is greater than or equal to -1V and less than or equal to 0V; The voltage value connected to the first voltage line is greater than or equal to 2.8V and less than or equal to 4.6V.

3. The array substrate according to claim 1, wherein: The first switch transistor includes a first semiconductor layer, and a first gate of the first switch transistor is located on a side of the first semiconductor layer close to the substrate; The driving wiring layer further includes a second connecting wiring located between the substrate and the first gate of the first switching transistor, and a first connecting wiring located on a side of the second connecting wiring away from the substrate, wherein the first gate of the first switching transistor is electrically connected to the second voltage wiring via the first connecting wiring; The array substrate includes a display area and a non-display area surrounding at least part of the display area. At least part of the second voltage line is located in the non-display area. The first connection line extends to the non-display area and is electrically connected to the second voltage line.

4. The array substrate according to claim 1, wherein: The driving transistor includes a second semiconductor layer, and the first gate of the driving transistor is located on a side of the second semiconductor layer close to the substrate; The driving wiring layer further includes a first connecting wiring located between the substrate and the second semiconductor layer and a second connecting wiring located between the first connecting wiring and the substrate, and the first gate of the driving transistor is electrically connected to the first voltage wiring through the second connecting wiring; The array substrate includes a display area and a non-display area surrounding at least part of the display area. At least part of the first voltage line is located in the non-display area. The second connection line extends to the non-display area and is electrically connected to the first voltage line.

5. The array substrate according to any one of claims 1 to 4, characterized in that: The pixel circuit further includes a second switch transistor, which is a dual-gate transistor. The drive wiring layer further includes a third voltage wiring. The first gate of the second switch transistor is electrically connected to the third voltage wiring. The voltage value connected to the third voltage wiring is lower than the voltage value connected to the first voltage wiring. The second switch transistor includes a third semiconductor layer, and the first gate of the second switch transistor is located on a side of the third semiconductor layer close to the substrate; The driving wiring layer further includes a second connecting wiring located between the substrate and the first gate of the second switching transistor, and a third connecting wiring located on a side of the second connecting wiring away from the substrate, the first gate of the second switching transistor being electrically connected to the third voltage wiring via the third connecting wiring; The array substrate includes a display area and a non-display area surrounding at least part of the display area. At least part of the third voltage line is located in the non-display area. The third connection line extends to the non-display area and is electrically connected to the third voltage line.

6. The array substrate according to claim 5, wherein: The voltage value connected to the third voltage line is greater than or equal to -1V and less than or equal to 0V; The voltage value connected to the third voltage wiring is equal to the voltage value connected to the second voltage wiring.

7. An array substrate, characterized in that: The array substrate includes: substrate; A drive wiring layer is located on one side of the substrate, and the drive wiring layer includes a pixel circuit, a first voltage wiring and a third voltage wiring. The pixel circuit includes a drive transistor, a first storage capacitor and a second switch transistor. The drive transistor and the second switch transistor are both dual-gate transistors. The first storage capacitor includes a first electrode plate and a second electrode plate. The second gate of the drive transistor is electrically connected to the first electrode plate, and the first electrode of the second switch transistor is electrically connected to the second electrode plate. The first gate of the drive transistor is electrically connected to the first voltage wiring, and the first gate of the second switch transistor is electrically connected to the third voltage wiring. The voltage value connected to the third voltage wiring is less than the voltage value connected to the first voltage wiring, and the positive bias heating stress of the second switch transistor is less than 0.5V.

8. The array substrate according to claim 7, wherein: The voltage value connected to the first voltage line is greater than or equal to 2.8V and less than or equal to 4.6V; The voltage value connected to the third voltage wiring is greater than or equal to -1V and less than or equal to 0V.

9. The array substrate according to claim 7, wherein: The pixel circuit further includes a first switch transistor, which is a dual-gate transistor. The drive wiring layer further includes a second voltage wiring. The first gate of the first switch transistor is electrically connected to the second voltage wiring. The voltage value connected to the second voltage wiring is lower than the voltage value connected to the first voltage wiring. The voltage value connected to the second voltage wiring is equal to the voltage value connected to the third voltage wiring.

10. A pixel circuit, characterized in that: The pixel circuit comprises: a driving transistor, wherein the driving transistor is a dual-gate transistor; a first switch transistor, wherein the first switch transistor is a double-gate transistor; a first storage capacitor, the first storage capacitor comprising a first electrode plate and a second electrode plate; In which, the second gate of the driving transistor is electrically connected to the first electrode plate, the second electrode of the driving transistor is electrically connected to the first electrode of the first switching transistor, the second electrode of the first switching transistor is electrically connected to the first electrode plate, the voltage value connected to the first gate of the first switching transistor is less than the voltage value connected to the first gate of the driving transistor, and the positive bias heating stress of the first switching transistor is less than 0.5V.

11. The pixel circuit according to claim 10, wherein: The pixel circuit further includes a second switch transistor, the second switch transistor being a dual-gate transistor, the first electrode of the second switch transistor being electrically connected to the second electrode plate, and the voltage value connected to the first gate of the second switch transistor being smaller than the voltage value connected to the first gate of the driving transistor; The pixel circuit further includes a second storage capacitor, the second storage capacitor including a third plate and a fourth plate, the third plate being electrically connected to the first electrode of the second switch transistor, and the fourth plate being electrically connected to the power supply voltage line; The second electrode of the second switch transistor is electrically connected to the data voltage signal line; The first electrode of the driving transistor is electrically connected to the power supply voltage line; The second gate of the first switch transistor is electrically connected to the first scan signal wiring; The second gate of the second switch transistor is electrically connected to the second scan signal line.

12. The pixel circuit according to claim 10, wherein: The pixel circuit further includes a third switch transistor, wherein a second electrode of the third switch transistor is electrically connected to the second electrode of the driving transistor and the first electrode of the first switch transistor; A gate of the third switch transistor is electrically connected to the light emitting control signal line, and a first electrode of the third switch transistor is electrically connected to the first electrode of the light emitting device.

13. The pixel circuit according to claim 12, wherein: The pixel circuit further includes a fourth switch transistor, wherein a first electrode of the fourth switch transistor is electrically connected to the first electrode of the third switch transistor and the first electrode of the light emitting device; A gate of the fourth switch transistor is electrically connected to the third scan signal line, and a second electrode of the fourth switch transistor is electrically connected to the initialization voltage signal line.

14. A pixel circuit, characterized in that: The pixel circuit comprises: a driving transistor, wherein the driving transistor is a dual-gate transistor; a second switch transistor, wherein the second switch transistor is a double-gate transistor; a first storage capacitor, the first storage capacitor comprising a first electrode plate and a second electrode plate; In which, the second gate of the driving transistor is electrically connected to the first electrode plate, the first electrode of the second switching transistor is electrically connected to the second electrode plate, the voltage value connected to the first gate of the second switching transistor is smaller than the voltage value connected to the first gate of the driving transistor, and the positive bias heating stress of the second switching transistor is smaller than 0.5V.

15. The pixel circuit according to claim 14, wherein: The pixel circuit further includes a first switch transistor, the first switch transistor being a dual-gate transistor, the second electrode of the driving transistor being electrically connected to the first electrode of the first switch transistor, the second electrode of the first switch transistor being electrically connected to the first electrode plate, and the voltage value connected to the first gate of the first switch transistor being smaller than the voltage value connected to the first gate of the driving transistor; The pixel circuit further includes a second storage capacitor, the second storage capacitor including a third plate and a fourth plate, the third plate being electrically connected to the first electrode of the second switch transistor, and the fourth plate being electrically connected to the power supply voltage line; The second electrode of the second switch transistor is electrically connected to the data voltage signal line; The first electrode of the driving transistor is electrically connected to the power supply voltage line; The second gate of the first switch transistor is electrically connected to the first scan signal wiring; The second gate of the second switch transistor is electrically connected to the second scan signal line.

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