Array substrate, display panel and mask

Abstract

The invention discloses an array substrate, a display panel and a mask, the array substrate comprises a substrate, a first auxiliary layer and a plurality of pixel structures, the first auxiliary layer and the pixel structures are arranged on the substrate, and at least one pixel structure comprises a transistor located between the first auxiliary layer and the substrate; the first switching electrode comprises a first switching part and a second switching part which are connected, the first switching part is located on the side, away from the substrate, of the first auxiliary layer, and the second switching part is arranged in a first via hole penetrating through the first auxiliary layer and electrically connected with the transistor; the auxiliary part is located in the first via hole; the first electrode comprises a contact part and a main body part which are connected, the contact part is electrically connected with the first switching part, and the orthographic projection of the first electrode on the substrate covers the orthographic projection of the first via hole on the substrate; the orthographic projection of the first switching part on the substrate is overlapped with the orthographic projection of the contact part on the substrate.

Description

Array substrate, display panel and mask Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a mask. Background Art

[0002] Virtual reality / augmented reality (VR / AR) technology is currently a popular display technology. Currently, the display resolution of most VR products ranges from 2k to 4k. Higher-resolution screens are an inevitable requirement for future product development. LCD (Liquid Crystal Display) technology is easier to achieve high resolution than Organic Light-Emitting Diode (OLED) display technology and is currently one of the mainstream display technologies used in VR / AR products.

[0003] Summary of the Invention

[0004] In a first aspect, the present disclosure provides an array substrate comprising: a base substrate, a first auxiliary layer disposed on the base substrate, and a plurality of pixel structures, at least one of the pixel structures comprising:

[0005] a transistor, located between the first auxiliary layer and the base substrate;

[0006] a first transfer electrode, the first transfer electrode comprising a first transfer portion and a second transfer portion connected to each other, the first transfer portion being located on a side of the first auxiliary layer away from the base substrate, the second transfer portion being disposed in a first via hole penetrating the first auxiliary layer and electrically connected to the transistor;

[0007] an auxiliary component, located in the first through hole;

[0008] a first electrode, the first electrode comprising a contact portion and a main portion connected to each other, the contact portion being electrically connected to the first transition portion, and an orthographic projection of the first electrode on the base substrate covering an orthographic projection of the first via hole on the base substrate;

[0009] The orthographic projection of the first transition portion on the base substrate overlaps with the orthographic projection of the contact portion on the base substrate.

[0010] In some embodiments, the contact portion contacts the surface of the first transfer portion away from the base substrate, at least part of the main portion is located on the surface of the auxiliary part away from the base substrate, and the second transfer portion of the first transfer electrode is closer to the base substrate than the auxiliary part.

[0011] In some embodiments, at least one side boundary of an orthographic projection of the first transition portion on the base substrate exceeds an orthographic projection of the contact portion on the base substrate.

[0012] In some embodiments, from a perspective perpendicular to the base substrate and along a first direction, a boundary of an orthographic projection of the first transition portion on the base substrate exceeds a boundary of an orthographic projection of the contact portion on the base substrate.

[0013] In some embodiments, the array substrate further includes: a second auxiliary layer located between the first auxiliary layer and the transistor; the pixel structure further includes: a second transfer electrode, the second transfer electrode being electrically connected to the transistor through a second via hole penetrating the second auxiliary layer;

[0014] The second via hole is connected to the first via hole, and the first transfer electrode and the second transfer electrode are connected to form an integrated structure.

[0015] In some embodiments, an orthographic projection of an opening of the first via hole facing toward the base substrate and an orthographic projection of an opening of the second via hole facing away from the base substrate on the base substrate do not overlap.

[0016] In some embodiments, the array substrate has a plurality of pixel areas, each of which corresponds to a pixel structure; a size of the pixel area in a first direction is larger than a size of the pixel area in a second direction, and the first direction is perpendicular to the second direction;

[0017] The contact portion is located on one side of the main body portion along the first direction.

[0018] In some embodiments, the first transition portion includes a first portion and a second portion, wherein the orthographic projection of the first portion on the substrate is located within the orthographic projection range of the contact portion on the substrate, and the second portion is located on one side of the first portion along the first direction, and the orthographic projection of the second portion on the substrate is located outside the orthographic projection of the contact portion on the substrate.

[0019] A ratio of a size of the first portion to a size of the pixel area in the first direction is between 0.1 and 0.5.

[0020] In some embodiments, along a direction perpendicular to the base substrate, a height of the auxiliary member is greater than or equal to a depth of the first via hole.

[0021] In some embodiments, along a direction perpendicular to the base substrate, a distance between the main portion of the first electrode and the base substrate is greater than a distance between the contact portion and the base substrate.

[0022] In some embodiments, a width of the second portion in the first direction is less than or equal to 1.5 μm.

[0023] In some embodiments, at least three pixel structures include an electrode assembly, the electrode assembly including the first switching electrode and the connected first electrode in the corresponding pixel area, there is a first spacing between the electrode assemblies of two adjacent pixel structures arranged in the first direction, and the ratio of the first spacing to the length of the electrode assembly in the first direction is between 0.05 and 0.15.

[0024] In some embodiments, the main body includes a first edge and a second edge arranged opposite to each other in the first direction, the first edge is located on the side of the main body away from the contact portion, and the second edge is adjacent to the contact portion. The size of the pixel area in the first direction is between 6 and 10 μm; the distance between the first edge and the opening of the first via toward the substrate in the first direction is between 0 and 1.5 μm.

[0025] In some embodiments, along a top-down perspective from the first auxiliary layer to the base substrate, an opening of the first via hole away from the base substrate has a plurality of first straight edges and a first arc edge connected between every two adjacent first straight edges; an opening of the first via hole close to the base substrate has a plurality of second straight edges and a second arc edge connected between every two adjacent second straight edges;

[0026] The first switching electrode has no contact with the first arc edge and the second arc edge.

[0027] In some embodiments, the second transition portion contacts a second straight side and a first straight side, and a width of the second transition portion is 0.5 to 0.9 times the length of the second straight side in contact with the second transition portion.

[0028] In some embodiments, the pixel structures correspond one-to-one to the first via holes on the first auxiliary layer; or,

[0029] The multiple pixel structures are arranged in multiple rows, and the first via holes corresponding to the multiple pixel structures in the same row are connected.

[0030] In some embodiments, the first via holes corresponding to multiple pixel structures in the same row are connected; and the spacing in the row direction between the second transfer portions of two adjacent first transfer electrodes in the same row is 0.5 to 10 times the width of the second transfer portions.

[0031] In some embodiments, the array substrate further includes a second electrode layer, the second electrode layer having a slit formed thereon, the slit including a main slit portion, and a first corner portion and a second corner portion located at both ends of the main slit portion and connected to the main slit portion, the main slit portion extending along a third direction; the first corner portion and the second corner portion respectively bend toward opposite sides of the main slit portion;

[0032] The first switching electrode and the corresponding first electrode constitute an electrode assembly, the orthographic projection of the main gap portion on the base substrate is located within the orthographic projection range of the electrode assembly on the base substrate, and the orthographic projections of the first corner portion and the second corner portion on the base substrate both overlap with the orthographic projection of the electrode assembly on the base substrate.

[0033] In some embodiments, a width of the main slit portion in a direction perpendicular to the third direction is between 0.5 μm and 3 μm.

[0034] In some embodiments, the main slit portion includes a first side and a second side arranged along its width direction, the first corner portion is bent toward the first side away from the second side, and the second corner portion is bent toward the second side away from the first side;

[0035] The first corner portion includes a first connecting edge connected to the first side edge, and the tangent at the connection between the first connecting edge and the first side edge forms an angle of 30° to 60° with the second direction; the second corner portion includes a second connecting edge connected to the first side edge, and a third connecting edge connected to the second connecting edge, and the tangent of the third connecting edge away from one end of the second connecting edge forms an angle of 15° to 30° with the second direction; the second direction is perpendicular to the first direction.

[0036] In some embodiments, the angle between the third direction and the first direction is in the range of [0°, 30°].

[0037] In some embodiments, the second electrode layer is provided with the slit at a position corresponding to each of the electrode assemblies.

[0038] Multiple pixel structures are arranged in multiple rows along the first direction, each row includes multiple pixel structures arranged along the second direction, the first corner portion of the slit corresponding to at least one pixel structure is connected to the second corner portion of the slit corresponding to one of the pixel structures in the previous row, and the second corner portion of the slit corresponding to at least one pixel structure is connected to the first corner portion of the slit corresponding to one of the pixel structures in the next row.

[0039] In some embodiments, the plurality of slits on the second electrode layer are divided into a plurality of slit groups, the slits in the same slit group are connected to each other to form dividing grooves, and the plurality of dividing grooves corresponding to the plurality of slit groups divide the second electrode layer into a plurality of second electrode strips;

[0040] The array substrate further includes a plurality of connecting electrodes, which extend along the second direction and are electrically connected to the plurality of second electrode strips.

[0041] In some embodiments, the connecting electrode and the main slit portion of the slit have no overlap in their orthographic projections on the base substrate.

[0042] In some embodiments, a width of the connecting electrode in a direction perpendicular to the second direction is between 1.2 μm and 2.4 μm.

[0043] In a second aspect, the present disclosure further provides a display panel comprising the above-mentioned array substrate.

[0044] In some embodiments, the display panel also includes a matching box substrate arranged opposite to the array substrate, the matching box substrate includes a black matrix, and the orthographic projections of the main body and the first adapter on the base substrate overlap with the orthographic projection of the black matrix on the base substrate.

[0045] In some embodiments, the display panel further includes a cell substrate disposed opposite to the array substrate, the cell substrate includes a black matrix, and the first via hole and the orthographic projection of the black matrix on the base substrate do not overlap.

[0046] In the third aspect, the present disclosure also provides a mask plate for use in a method for manufacturing an array substrate, wherein the array substrate is the above-mentioned array substrate, and the mask plate includes: a light-transmitting area for forming the first via hole, the orthographic projection of the first via hole on the base substrate is roughly a polygon, and the light-transmitting area includes a main light-transmitting area and a compensation light-transmitting area that are connected, the main light-transmitting area is a polygon, the compensation light-transmitting area is located at the corner of the main light-transmitting area, and the compensation light-transmitting area protrudes from the edge of the main light-transmitting area in both the length and width directions of the main light-transmitting area.

[0047] In some embodiments, the dimension of the compensation light-transmitting area that exceeds the main light-transmitting area in the length direction of the main light-transmitting area is 0.02 to 0.2 times the length of the main light-transmitting area; the dimension of the compensation light-transmitting area that exceeds the main light-transmitting area in the width direction of the main light-transmitting area is 0.02 to 0.2 times the width of the main light-transmitting area. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0049] FIG1 is a schematic diagram of a partial structure of an array substrate provided in some embodiments.

[0050] FIG. 2 is a schematic diagram showing the positional relationship among a data line, a first electrode, a first switching electrode, and a light shielding layer provided in some embodiments.

[0051] FIG3 is a schematic diagram of a partial structure of an array substrate provided in some embodiments of the present disclosure.

[0052] FIG. 4 is a schematic diagram of relevant dimensions of the array substrate shown in FIG. 3 .

[0053] FIG5 is a plan view of the first transfer electrode, the first electrode, the first via hole, and the second via hole in the array substrate shown in FIG3 .

[0054] FIG6 is a schematic diagram of a pixel region provided in some embodiments of the present disclosure.

[0055] FIG. 7 is a comparison diagram of electrode assemblies according to a comparative example and an embodiment of the present disclosure.

[0056] FIG8 is a schematic diagram of a partial structure of an array substrate provided in some other embodiments of the present disclosure.

[0057] FIG. 9 is a schematic diagram of relevant dimensions of the array substrate shown in FIG. 8 .

[0058] FIG10 is a plan view of the first transfer electrode, the first electrode, the first via hole, and the second via hole in the array substrate shown in FIG8 .

[0059] FIG11 is a schematic diagram of the light leakage position of the first via hole.

[0060] 12 and 13 are two plan views of a first switching electrode, a first via hole, and a second via hole provided in some embodiments of the present disclosure.

[0061] FIG. 14 is a plan view of a plurality of first switching electrodes and first via holes in the same row provided in some embodiments of the present disclosure.

[0062] FIG. 15 is a plan view of a plurality of first switching electrodes and first via holes in the same row provided in some other embodiments of the present disclosure.

[0063] FIG16 is a schematic diagram of an array substrate provided with a second electrode layer in some embodiments of the present disclosure.

[0064] FIG17 is a plan view of the second electrode layer, the first electrode, and the first switching electrode in a single pixel area.

[0065] FIG18 is a schematic diagram of brightness distribution of the pixel area corresponding to FIG17 .

[0066] FIG19 is a plan view of the second electrode layer, the first electrode, and the first switching electrode in a single pixel area provided in some other embodiments of the present disclosure.

[0067] FIG20 is a schematic diagram of brightness distribution of the pixel area corresponding to FIG19.

[0068] FIG21 is a schematic diagram showing the state in which there is no alignment deviation and the state in which there is alignment deviation between the slit of the second electrode layer and the electrode assembly.

[0069] FIG22 is a schematic diagram of a second electrode layer provided in some embodiments of the present disclosure.

[0070] FIG23 is a schematic diagram of the superposition of multiple electrode assemblies, a second electrode layer, and connecting electrodes provided in some embodiments of the present disclosure.

[0071] FIG24 is a simulation diagram of the transmittance of the pixel area under different conditions.

[0072] FIG. 25 is a plan view of a semiconductor layer provided in some embodiments of the present disclosure.

[0073] FIG26 is a plan view of a gate metal layer provided in some embodiments of the present disclosure.

[0074] FIG. 27 is a plan view of a first interlayer dielectric layer provided in some embodiments of the present disclosure.

[0075] FIG28 is a plan view of a source-drain metal layer provided in some embodiments of the present disclosure.

[0076] FIG. 29 is a plan view of a second interlayer dielectric layer provided in some embodiments of the present disclosure.

[0077] Figure 30 is a schematic diagram of the superposition of the gate metal layer, the first interlayer dielectric layer, the source-drain metal layer and the second interlayer dielectric layer provided in some embodiments of the present disclosure.

[0078] FIG31 is a plan view of a first transparent conductive layer provided in some embodiments of the present disclosure.

[0079] Figure 32 is a schematic diagram of the superposition of the first transparent conductive layer and the second interlayer dielectric layer provided in some embodiments of the present disclosure.

[0080] FIG33 is a plan view of a planarization layer provided in some embodiments of the present disclosure.

[0081] FIG34 is a schematic diagram showing the superposition of a second interlayer dielectric layer, a first transparent conductive layer, and a planarization layer provided in some embodiments of the present disclosure.

[0082] FIG35 is a plan view of a second transparent conductive layer provided in some embodiments of the present disclosure.

[0083] FIG36 is a schematic diagram showing the superposition of a second interlayer dielectric layer, a first transparent conductive layer, a second transparent conductive layer, and a planarization layer provided in some embodiments of the present disclosure.

[0084] FIG37 is a plan view of a third transparent conductive layer provided in some embodiments of the present disclosure.

[0085] 38 is a schematic diagram of the superposition of a second interlayer dielectric layer, a first transparent conductive layer, a second transparent conductive layer, a planarization layer, and a third transparent conductive layer provided in some embodiments of the present disclosure.

[0086] Figure 39 is a plan view of the second electrode layer provided in some embodiments of the present disclosure.

[0087] Figure 40 is a schematic diagram of the superposition of the second interlayer dielectric layer, the first transparent conductive layer, the second transparent conductive layer, the planarization layer, the third transparent conductive layer, and the second electrode layer provided in some embodiments of the present disclosure.

[0088] Figure 41 is a plan view of the black matrix, the first electrode, and the first switching electrode provided in some embodiments of the present disclosure.

[0089] Figure 42 is a plan view of the black matrix and the second electrode layer provided in some embodiments of the present disclosure.

[0090] Figure 43 is a partial schematic diagram of a mask provided in some embodiments of the present disclosure.

[0091] FIG44 is a partial schematic diagram of a mask provided in some other embodiments of the present disclosure.

[0092] FIG45 is a partial schematic diagram of a mask provided in some further embodiments of the present disclosure.

[0093] FIG46 is a partial schematic diagram of a mask provided in some other embodiments of the present disclosure.

[0094] Figure 47 is a schematic diagram of a display panel and a flexible circuit board provided in some embodiments of the present disclosure.

[0095] FIG48 is a schematic diagram of an application scenario of a display panel provided in some embodiments of the present disclosure.

[0096] Figure 49 is a schematic diagram of a near-eye display device. DETAILED DESCRIPTION

[0097] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0098] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0099] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0100] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0101] As used herein, "parallel" and "perpendicular" include the conditions described and conditions similar to the conditions described, and the range of the similar conditions is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range for approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 5°.

[0102] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0103] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0104] In this article, circles, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but can be approximate circles, triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0105] In each embodiment of the present invention, the direction from the base substrate toward the first auxiliary layer is referred to as up or above. Conversely, the direction from the first auxiliary layer toward the base substrate is referred to as down or below. Like this, for the sake of convenience, the phrase "above" or "below" is used for explanation, but for example, the base substrate and the first auxiliary layer may be configured in a manner opposite to that shown in the figure. The above description is only used to illustrate the up-and-down relationship between the base substrate and the first auxiliary layer, and other components may be arranged between the two. Above or below refers to the stacking order in a structure with multiple layers stacked, and when expressed as the first electrode above the transistor, it may also be a positional relationship in which the transistor and the first electrode do not overlap when viewed from above. On the other hand, when expressed as the first electrode vertically above the transistor, it refers to a positional relationship in which the transistor and the first electrode overlap when viewed from above.

[0106] A liquid crystal display panel includes an array substrate and a cell substrate disposed opposite each other, and a liquid crystal layer located therebetween. Figure 1 is a schematic diagram of a partial structure of an array substrate provided in some embodiments, and Figure 2 is a schematic diagram of the positional relationship among a data line, a first electrode, a first transfer electrode, and a light shielding layer provided in some embodiments. The display panel includes multiple pixel regions, and Figure 1 only illustrates the structure corresponding to one pixel region. The structure shown in Figure 1 can be applied to display products with a higher pixel density, such as products with a pixel density (PPI) in the range of 1000-1500.

[0107] As shown in Figure 1, the array substrate includes multiple pixel structures located on a base substrate 95. Each pixel structure includes a thin film transistor, a transfer electrode, and a first electrode 20. Taking a top-gate thin film transistor as an example, the gate electrode 12 of the thin film transistor is located on the side of the active layer 11 away from the base substrate 95. The active layer 11 includes a channel region 11a and a source region 11s and a drain region 11d located on either side of the channel region 11a. A gate insulating layer 94 is provided between the gate electrode 12 and the active layer 11. A first sub-auxiliary layer 921 is provided on the side of the gate electrode 12 away from the base substrate 95. A second sub-auxiliary layer 922 is provided on the side of the layer containing the data line DL away from the base substrate 95. The first auxiliary layer 91 is provided on the side of the second sub-auxiliary layer 922 away from the base substrate 95.

[0108] The data line DL is connected to the source region 11s via a via extending through the first sub-auxiliary layer 921 and the gate insulating layer 94, and the transfer electrode is connected to the drain region 11d via a via extending through the second sub-auxiliary layer 922, the first sub-auxiliary layer 921, and the gate insulating layer 94. The first electrode 20 is located on the side of the first auxiliary layer 91 away from the base substrate 95 and is electrically connected to the first transfer electrode 30 through the via Va in the first auxiliary layer 91. An insulating spacer layer 70 is provided on the side of the first electrode 20 away from the base substrate 95, and the second electrode layer 50 is provided on the side of the insulating spacer layer 70 away from the base substrate 95. The first transfer electrode 30 is made of a transparent material such as indium tin oxide (ITO), which can reduce the impact on the aperture ratio of the pixel area. In addition, due to the large depth of the via Va, there is a large step difference between the portion of the first electrode 20 located inside the via Va and the portion located outside the via Va, which affects the orientation of the liquid crystal above the via Va and causes light leakage. In order to prevent the influence of the liquid crystal alignment caused by the large depth of the via hole Va, as shown in FIG1 and FIG2 , a light shielding layer 93 is provided on the base substrate 95 to shield the via hole Va.

[0109] However, for products with higher pixel densities (e.g., pixel densities greater than or equal to 2000 PPI), the pixel area is very small, and the provision of the light shielding layer 93 will significantly affect the aperture ratio of the pixel area. Furthermore, due to the limited size of the pixel area, the size of the first electrode 20 is also limited, and the electric field area formed by the first electrode 20 and the second electrode layer 50 is limited, resulting in low liquid crystal efficiency.

[0110] The present disclosure provides an array substrate. FIG3 is a schematic diagram of a partial structure of an array substrate provided in some embodiments of the present disclosure. FIG4 is a schematic diagram of relevant dimensions in the array substrate shown in FIG3. FIG5 is a plan view of the first transfer electrode, the first electrode, the first via hole, and the second via hole in the array substrate shown in FIG3. The array substrate may include a plurality of gate lines and a plurality of data lines disposed on a base substrate 95. The plurality of gate lines and the plurality of data lines define a plurality of pixel areas. FIG3 only shows the structure corresponding to one of the pixel areas. As shown in FIG3, the array substrate includes: a base substrate 95, a first auxiliary layer 91 disposed on the base substrate 95, and a plurality of pixel structures, each pixel structure corresponding to a pixel area. At least one pixel structure includes: a transistor, a first transfer electrode 30, a light-transmitting filling portion 60, and a first electrode 20.

[0111] Among them, the transistor may include a thin film transistor (TFT) or a field effect transistor such as a MOS tube (metal-oxide-semiconductor). In this disclosure, the thin film transistor is used as an example for description. The thin film transistor is located between the first auxiliary layer 91 and the base substrate 95. The first transfer electrode 30 includes a first transfer portion 31 and a second transfer portion 32 connected to each other. The first transfer portion 31 is located on the side of the first auxiliary layer 91 away from the base substrate 95; the second transfer portion 32 is disposed in the first via V1 and is electrically connected to the thin film transistor. The first via V1 passes through the first auxiliary layer 91.

[0112] The auxiliary member 60 is located within the first via hole V1. In one example, the surface of the auxiliary member 60 away from the base substrate 95 can be substantially flush with the surface of the first auxiliary layer 91 away from the base substrate 95. For example, the height difference between the two surfaces is less than or equal to the thickness of the first electrode 20. In one example, the auxiliary member 60 can be made of a light-transmitting material.

[0113] In the embodiment of the present disclosure, the first electrode 20 is taken as an example of a pixel electrode. The first electrode 20 includes a contact portion 22 and a main body portion 21 connected to each other, and the contact portion 22 is electrically connected to the first adapter portion 31. For example, the contact portion 22 contacts the surface of the first adapter portion 31 away from the base substrate 95, and at least part of the main body portion 21 is located on the surface of the auxiliary component 60 away from the base substrate 95. The orthographic projection of the first electrode 20 on the base substrate 95 covers the orthographic projection of the first via V1 on the base substrate 95. The orthographic projection of the first adapter portion 31 on the base substrate 95 overlaps with the orthographic projection of the contact portion 22 on the base substrate 95. Both the first adapter electrode 30 and the first electrode 20 can be made of transparent conductive materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc tin oxide (ZTO), etc.

[0114] In the embodiment of the present disclosure, the translucent auxiliary component 60 is filled in the first via hole V1, so that the first electrode 20 can be located on a substantially flat surface, preventing the first electrode 20 from having a large step difference at the position of the first via hole V1 and affecting the electric field distribution. In this case, there is no need to set the light-shielding layer 93 in Figures 1 and 2, which is beneficial to improving the aperture ratio of the pixel area.

[0115] In some embodiments, the active layer 11 may be made of a material with high light stability, thereby eliminating the need for a separate light shielding layer 93 and further increasing the aperture ratio of the pixel area.

[0116] In some embodiments, the contact portion 22 of the first electrode 20 contacts the surface of the first transfer portion 31 of the first transfer electrode 30 away from the base substrate 95, and at least a portion of the main body 21 is located on the surface of the auxiliary component 60 away from the base substrate 95; the second transfer portion 32 is closer to the base substrate 95 than the auxiliary component 60.

[0117] In some embodiments, as shown in Figures 3 to 5 , at least one side of the orthographic projection of the first transition portion 31 on the base substrate 95 extends beyond the orthographic projection of the contact portion 22 on the base substrate 95. Because the first electrode 20 is electrically connected to the first transition portion 31, it is the electrode assembly formed by the connection of the first electrode 20 and the first transition portion 31 that acts on the liquid crystal in the pixel area. Furthermore, at least one side of the orthographic projection of the first transition portion 31 on the base substrate 95 extends beyond the orthographic projection of the contact portion 22 on the base substrate 95. Therefore, compared to the first electrode 20, the electrode assembly formed by the connection of the first electrode 20 and the first transition portion 31 is longer in total length. This improves the efficiency of the liquid crystal at the edge of the pixel area while shielding the liquid crystal from the electric field of the underlying metal wire.

[0118] As shown in Figures 3 to 5 , from a perspective perpendicular to the base substrate 95, along a first direction, the boundary of the orthographic projection of the first adapter portion 31 on the base substrate 95 exceeds the boundary of the orthographic projection of the contact portion 22 on the base substrate 95. However, along a fourth direction, parallel to and opposite to the first direction, the boundary of the orthographic projection of the first adapter portion 31 on the base substrate 95 does not exceed the boundary of the orthographic projection of the contact portion 22 on the base substrate 95. For example, in the first direction (from bottom to top in Figure 5 ), and the fourth direction (from top to bottom in Figure 5 ), the upper boundary of the orthographic projection of the first adapter portion 31 exceeds the boundary of the orthographic projection of the contact portion 22; while the lower boundary of the orthographic projection of the first adapter portion 31 does not exceed the boundary of the orthographic projection of the contact portion 22.

[0119] In some embodiments, as shown in Figures 3 and 4 , the height of the auxiliary member 60 is greater than or equal to the depth of the first via hole V1 in a direction perpendicular to the base substrate 95. Specifically, the distance from the surface of the auxiliary member 60 away from the base substrate 95 to the base substrate 95 is greater than or equal to the distance from the top opening of the first via hole V1 away from the base substrate 95 to the base substrate 95, to ensure that the auxiliary member 60 fully fills the first via hole V1.

[0120] In some embodiments, in a direction perpendicular to the base substrate 95, the distance between the main portion 21 and the base substrate 95 is greater than the distance between the contact portion 22 and the base substrate 95. The distance between the main portion 21 and the base substrate 95 refers to the distance from the surface of the main portion 21 facing the auxiliary component 60 to the base substrate 95; the distance between the contact portion 22 and the base substrate 95 refers to the distance from the surface of the contact portion 22 facing the first transition portion 31 to the base substrate 95.

[0121] 3 , a buffer layer 96 is disposed on a base substrate 95 to prevent or reduce diffusion of metal atoms and / or impurities from the base substrate 95 into the active layer 11. In one example, the buffer layer 96 may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), and / or silicon oxynitride (SiON), and may be formed as a multilayer or single layer.

[0122] The active layer 11 is disposed on the side of the buffer layer 96 away from the base substrate 95. In the embodiment of the present disclosure, the active layer 11 can be made of one or more materials selected from the group consisting of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), and rare earth doped oxide (Ln-OS). The material of the active layer 11 can be amorphous, partially crystalline, single crystal, or polycrystalline, and can also be a single layer or multilayer structure, so that the active layer 11 can achieve a higher mobility, thereby facilitating a reduction in the size of the thin film transistor and improving the pixel density of the display substrate. The active layer 11 includes a channel region 11a and a source region (not shown) and a drain region 11d located on both sides of the channel region 11a. Both the source region and the drain region 11d can include impurities with a higher impurity concentration than the channel region 11a.

[0123] The gate insulating layer 94 is provided on the side of the active layer 11 away from the base substrate 95. The gate insulating layer 94 may be a whole layer structure; alternatively, the gate insulating layer 94 only covers the channel region 11a. The gate 12 insulating layer may include, for example, a silicon compound or a metal oxide. For example, the gate insulating layer 94 may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The gate insulating layer 94 may be formed as a single layer or multiple layers.

[0124] The second auxiliary layer 92 is located on a side of the gate insulating layer 94 away from the base substrate 95. The material of the second auxiliary layer 92 can be selected from the materials of the gate insulating layer 94 listed above, which will not be repeated here.

[0125] The first auxiliary layer 91 is located on a side of the second auxiliary layer 92 away from the base substrate 95. The first auxiliary layer 91 may include an organic insulating material, such as a resin material such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, or silicone. For another example, the organic insulating material may include an elastic material such as urethane or thermoplastic polyurethane (TPU).

[0126] The first transfer electrode 30 includes a first transfer portion 31 and a second transfer portion 32 connected to each other. The first transfer portion 31 is located on the side of the first auxiliary layer 91 away from the base substrate 95, and the second transfer portion 32 is disposed within the first via hole V1. As shown in FIG3 , the pixel structure also includes a second transfer electrode 40, which is electrically connected to the drain region 11d of the thin film transistor through a second via hole V2. The second via hole V2 at least penetrates the second auxiliary layer 92. For example, if the gate insulating layer 94 only covers the channel region 11a of the active layer 11, the second via hole V2 only penetrates the second auxiliary layer 92. If the gate insulating layer 94 is a single layer structure, the second via hole V2 penetrates both the second auxiliary layer 92 and the gate insulating layer 94.

[0127] 3 , the first via V1 is connected to the second via V2 , for example, the first via V1 and the second via V2 are coaxially arranged. The orthographic projection of the second via V2 on the base substrate 95 is within the orthographic projection of the first via V1 on the base substrate 95 .

[0128] As shown in Figure 3, both the first via V1 and the second via V2 have an opening facing the substrate 95 and an opening away from the substrate 95. For ease of description, the opening of each via facing the substrate 95 is referred to as the bottom opening of the via, and the opening away from the substrate 95 is referred to as the top opening of the via. In one example, the orthographic projection of the bottom opening of the same via on the substrate 95 is within the orthographic projection of its top opening on the substrate 95. As shown in Figure 3, the orthographic projection of the top opening of the second via V2 on the substrate 95 is within the orthographic projection of the bottom opening of the first via V1 on the substrate 95.

[0129] FIG6 is a schematic diagram of a pixel region provided in some embodiments of the present disclosure. As shown in FIG6 , in some embodiments, a plurality of gate lines GL and a plurality of data lines DL are further provided on the substrate 95. The plurality of gate lines GL and the plurality of data lines DL intersect to define a plurality of pixel regions P. The plurality of pixel regions P may, for example, include a plurality of red pixel regions, a plurality of green pixel regions, and a plurality of blue pixel regions. Each pixel region P is provided with a pixel structure. At least three pixel structures (for example, pixel structures in at least one red pixel region, at least one green pixel region, and at least one blue pixel region) include an electrode assembly, and the electrode assembly includes a first transfer electrode 30 and a connected first electrode 20 within the corresponding pixel region P. The size of the pixel region P in the first direction is greater than the size of the pixel region P in the second direction, and the first direction is perpendicular to the second direction. For example, the first direction is the arrangement direction of the plurality of gate lines GL, and the second direction is the extension direction of the gate lines GL. The contact portion 22 is located on one side of the main portion 21 along the first direction, and a portion of the first transfer electrode 30 extends beyond the first electrode 20, with the extending portion being located on one side of the first electrode 20 along the first direction.

[0130] In some embodiments, the pixel density of the array substrate is greater than or equal to 2000PPI, and the size of the pixel area P in the first direction is between 6 and 10μm, for example, 8μm; the size of the pixel area P in the second direction is between 5 and 7μm, for example, 6μm. The size of the pixel area P in the first direction is equal to the distance between the center lines of two adjacent gate lines GL; the size of the pixel area P in the second direction is equal to the distance between the center lines of two adjacent data lines DL. It should be noted that Figure 6 is only an exemplary description using the gate line GL and the data line DL as straight lines. In other embodiments, either the gate line GL or the data line DL can also be a meander line. The following takes the horizontal and vertical dimensions of the pixel area P as 6μm*8μm as an example to introduce the relevant parameters in Figure 3.

[0131] As shown in Figures 3 to 5, the bottom opening of the first via V1 is generally rectangular, with its length and width oriented in the first and second directions, respectively. In one example, the dimension a of the bottom opening of the first via V1 in the first direction is between 2.5 and 4 μm, for example, 2.5 μm, 3 μm, 3.5 μm, or 4 μm. The dimension a of the bottom opening of the first via V1 in the second direction can be equal to, that is, the bottom opening of the first via V1 is a rectangular square or a rounded square.

[0132] As shown in Figures 3 to 5, the bottom opening of the second via V2 is generally rectangular, with its length and width being in the first and second directions, respectively. In one example, the dimension b of the bottom opening of the second via V2 in the first direction is between 1.0 and 2.0 μm, for example, 1.0 μm, 1.5 μm, 1.8 μm, or 2 μm. The dimension b of the bottom opening of the second via V2 in the second direction can be equal to, that is, the bottom opening of the second via V2 is a rectangular square or a rounded square.

[0133] 3 to 5 , the spacing c between the bottom opening of the first via hole V1 and the bottom opening of the second via hole V2 in the first direction is less than 1 μm, for example, c is 0.2 μm, or 0.4 μm, or 0.6 μm, or 0.8 μm, or 1 μm.

[0134] As shown in Figures 3 to 5, the first transition portion 31 includes a first portion 311 and a second portion 312. The first portion 311 is the area of ​​the first transition portion 31 that directly contacts the contact portion 22 of the first electrode 20. The second portion 312 is the area of ​​the first transition portion 31 that extends beyond the first electrode 20 in the first direction. The orthographic projection of the first portion 311 on the substrate 95 is within the orthographic projection of the contact portion 22 on the substrate 95. The second portion 312 is located to one side of the first portion 311 along the first direction, and its orthographic projection on the substrate 95 is outside the orthographic projection of the contact portion 22 on the substrate 95.

[0135] The ratio of the first portion 311 to the pixel area P in the first direction is between 0.1 and 0.5, thereby ensuring the connection stability between the first electrode 20 and the first transition electrode 30 and maximizing the length of the electrode assembly consisting of the first electrode 20 and the first transition electrode 30. For example, the ratio is 0.1, 0.2, 0.3, 0.4, or 0.5.

[0136] In one example, the size of the pixel region P in the first direction is between 6 and 10 μm, and the size e of the first portion 311 in the first direction is between 1 and 3 μm, thereby ensuring the connection stability between the first electrode 20 and the first transition electrode 30 and maximizing the length of the electrode assembly consisting of the first electrode 20 and the first transition electrode 30. For example, e is 1 μm, 1.5 μm, 2 μm, 2.5 μm, or 3 μm.

[0137] The distance d between the first portion 311 and the top opening of the first via hole V1 in the first direction is 0 to 2 μm, thereby ensuring that the auxiliary member 60 can fully fill the first via hole V1 without affecting the width e of the first portion 311. For example, d is 0 μm, 0.5 μm, 1 μm, 1.5 μm, or 2 μm.

[0138] The width g of the second portion 312 in the first direction is less than or equal to 1.5 μm. This maximizes the contact area between the first electrode 20 and the first transition electrode 30 while maintaining a constant length of the electrode assembly, ensuring connection stability between the first electrode 20 and the first transition electrode 30. In one example, g is between 0.5 and 1.5 μm. For example, g is 0.5 μm, 0.7 μm, 0.9 μm, 1.1 μm, 1.3 μm, or 1.5 μm.

[0139] There is a first spacing h between the electrode assemblies of two adjacent pixel structures arranged in the first direction, and the ratio of the first spacing h to the length h1 of the electrode assembly in the first direction is between 0.05 and 0.15, so that the electrode assembly has sufficient length and prevents short circuits between the two adjacent electrode assemblies in the first direction. For example, the ratio of h to h1 is 0.05, or 0.07, or 0.09, or 0.1, or 0.11, or 0.13, or 0.15.

[0140] For example, the size of the pixel area P in the first direction is 8 μm, and the first interval h is between 0.5 and 2 μm, for example, between 0.5 μm and 1.5 μm, for example, h is 0.5 μm, or 0.75 μm, or 1 μm, or 1.25 μm, or 1.5 μm. h1 is between 6.5 and 7.5 μm, for example, h1 is 6.5 μm, or 7 μm, or 7.25 μm, or 7.5 μm. Figure 7 compares the electrode assemblies of a comparative example and the embodiment of the present disclosure. In the comparative example, the orthographic projection of the first transition electrode 30 on the base substrate 95 is within the orthographic projection of the first electrode 20 on the base substrate 95. The length of the first electrode 20 in the first direction is b', and the spacing between two adjacent electrode assemblies arranged in the first direction is a'. In the embodiment of the present disclosure, the first electrode 20 and the first transition electrode 30 adopt the design shown in Figure 3. The dimension of the electrode assembly composed of the first electrode 20 and the first transition electrode 30 in the first direction is denoted as h1, and the spacing between two adjacent electrode assemblies in the first direction is denoted as h. The liquid crystal efficiency of the comparative example and the embodiment of the present disclosure is shown in Table 1. It can be seen that the staggered design of the first electrode 20 and the first transition electrode 30 in the embodiment of the present disclosure can improve liquid crystal efficiency.

[0141] As shown in Figures 3 to 5, the first via hole V1 has an opening facing the base substrate 95 and an opening away from the base substrate 95. For ease of description, the opening of each via hole facing the base substrate 95 is referred to as the bottom opening of the via hole, and the opening of the via hole away from the base substrate 95 is referred to as the top opening of the via hole. The orthographic projection of the bottom opening of the first via hole V1 on the base substrate 95 is within the range of the orthographic projection of the top opening on the base substrate 95.

[0142] As shown in Figures 3 to 5 , the main body 21 includes a first edge E01 and a second edge E02 that are opposite each other in the first direction. The first edge E01 is located on the side of the main body 21 away from the contact portion 22, and the second edge E02 is adjacent to the contact portion 22. The size of the pixel area P in the first direction is between 6 and 10 μm. The spacing f between the first edge E01 and the bottom opening of the first via V1 in the first direction is between 0 and 1.5 μm. For example, f is 0 μm, 0.5 μm, 1.0 μm, or 1.5 μm.

[0143] The orthographic projection of the first transfer electrode 30 on the base substrate 95 in the embodiment of the present disclosure may be a rectangle, or may be a T-shape or other shapes.

[0144] FIG8 is a schematic diagram of a partial structure of an array substrate provided in some other embodiments of the present disclosure. The array substrate shown in FIG8 is similar to that shown in FIG3 and includes the aforementioned thin-film transistor, first auxiliary layer 91, second auxiliary layer 92, first electrode 20, and other structures. The difference is that in FIG8 , the first via V1 and second via V2 are staggered, and the orthographic projections of the bottom opening of the first via V1 and the top opening of the second via V2 on the base substrate 95 do not overlap. The second transfer electrode 40 is electrically connected to the thin-film transistor via the second via V2 that penetrates the second auxiliary layer 92. The second transfer portion 32 of the first transfer electrode 30 is electrically connected to the second transfer electrode 40 via the first via V1, thereby electrically connecting the first transfer electrode 30 to the drain region 11d of the thin-film transistor via the second transfer electrode 40. Furthermore, in FIG8 , the second auxiliary layer 92 may include a first sub-auxiliary layer 921 and a second sub-auxiliary layer 922 located on the side of the first sub-auxiliary layer 921 away from the base substrate 95. The data line DL may be located between the first sub-auxiliary layer 921 and the second sub-auxiliary layer 922 .

[0145] In Figure 3, since the first and second vias V1 and V2 are connected, forming a deep hole with a relatively large depth, the auxiliary component 60 needs to fill the entire deep hole, which can be affected by process fluctuations in the surface flatness of the auxiliary component 60. In Figure 8, after the first and second vias V1 and V2 are offset, the auxiliary component 60 only needs to fill the first via V1, which helps improve the surface flatness of the auxiliary component 60. Furthermore, the first and second transfer electrodes 30 and 40 can be formed through two patterning processes, which reduces the possibility of fracture in the first and second transfer electrodes 30 and 40.

[0146] Figure 9 is a schematic diagram of relevant dimensions in the array substrate shown in Figure 8, and Figure 10 is a plan view of the first transfer electrode, the first electrode, the first via hole, and the second via hole in the array substrate shown in Figure 8. The following takes the pixel area P of 6μm*8μm as an example to introduce the relevant parameters in Figure 8.

[0147] As shown in Figures 8 to 10, the bottom opening of the first via V1 is generally rectangular, with its length and width oriented in the first and second directions, respectively. In one example, the dimension a1 of the bottom opening of the first via V1 in the first direction is between 1.5 and 4 μm, for example, 1.5 μm, 2.0 μm, 2.5 μm, 3 μm, 3.5 μm, or 4 μm. The dimension a1 of the bottom opening of the first via V1 in the second direction can be equal to a1, i.e., the bottom opening of the first via V1 is a rectangular square or a rounded square.

[0148] As shown in Figures 8 to 10, the bottom opening of the second via V2 is generally rectangular, with its length and width oriented in the first and second directions, respectively. In one example, the dimension b1 of the bottom opening of the second via V2 in the first direction is between 1.0 and 2.0 μm, for example, 1.0 μm, 1.5 μm, 1.8 μm, or 2 μm. The dimension of the bottom opening of the second via V2 in the second direction can be equal to b1, i.e., the bottom opening of the second via V2 is a rectangular square or a rounded square.

[0149] Similar to FIG3 , in FIG8 , the first transition portion 31 also includes a first portion 311 and a second portion 312. The width e of the first portion 311 in the first direction is between 1 and 3 μm, thereby ensuring the connection stability between the first electrode 20 and the first transition electrode 30 and maximizing the length of the electrode assembly consisting of the first electrode 20 and the first transition electrode 30. For example, e is 1 μm, 1.5 μm, 2 μm, 2.5 μm, or 3 μm.

[0150] As shown in Figure 9, the distance d between the first portion 311 and the top opening of the first via hole V1 in the first direction is 0 to 3 μm, thereby ensuring that the auxiliary member 60 can fully fill the first via hole V1 without affecting the width e of the first portion 311. For example, d is 0 μm, or 0.5 μm, or 1 μm, or 1.5 μm, or 2 μm, or 2.5 μm, or 3 μm.

[0151] Compared with Figure 3, in Figure 8, the first via V1 and the second via V2 adopt a staggered design. The orthographic projection of the bottom opening of the first via V1 on the base substrate 95 does not need to cover the orthographic projection of the top opening of the second via V2 on the base substrate 95. Therefore, the size of the first via V1 can be set smaller, so that d can be appropriately increased, thereby increasing the process window.

[0152] As shown in FIG9 , a distance c1 between the bottom opening of the first via hole V1 and the top opening of the second via hole V2 in the first direction is between 0 and 1 μm. For example, c1 is 0.1 μm, 0.3 μm, 0.5 μm, 1.7 μm, 0.8 μm, or 1.0 μm.

[0153] As shown in Figure 9, the width g1 of the second portion 312 in the first direction is less than or equal to 1.5 μm. This allows the width e to be as large as possible given a given electrode assembly length, thereby maximizing the contact area between the first electrode 20 and the first transition electrode 30 and ensuring the connection stability between the first electrode 20 and the first transition electrode 30. In one example, g1 is between 0.5 and 1.5 μm. For example, g1 is 0.5 μm, 0.7 μm, 0.9 μm, 1.1 μm, 1.3 μm, or 1.5 μm.

[0154] As shown in Figures 9 and 10, there is a first spacing h2 between the electrode assemblies of two adjacent pixel structures arranged in the first direction, and the ratio of the first spacing h2 to the length h1 of the electrode assembly in the first direction is between 0.05 and 0.15. For example, the ratio of h2 to h1 is 0.05, or 0.07, or 0.09, or 0.1, or 0.11, or 0.13, or 0.15.

[0155] For example, in Figures 9 and 10, the first spacing h2 is between 0.5 and 1.5 μm, for example, h2 is 0.5 μm, or 0.75 μm, or 1 μm, or 1.25 μm, or 1.5 μm. For example, h1 is 6.5 μm, or 7 μm, or 7.25 μm, or 7.5 μm.

[0156] As shown in Figures 8 and 9, the main body 21 includes a first edge E01 and a second edge E02 that are opposite each other in a first direction. The first edge E01 is located on the side of the main body 21 away from the contact portion 22, and the second edge E02 is adjacent to the contact portion 22. The size of the pixel area in the first direction is between 6 and 10 μm. The spacing f1 between the first edge E01 and the bottom opening of the first via V1 in the first direction is between 0.4 and 1.9 μm. For example, f1 is 0.4 μm, 1.0 μm, 1.5 μm, or 1.9 μm.

[0157] Figure 11 is a schematic diagram illustrating the light leakage location of the first via hole, and Figures 12 and 13 are two plan views of the first via hole, the first via hole, and the second via hole provided in some embodiments of the present disclosure. As shown in Figure 11, when the light-transmitting area of ​​the mask used to form the first via hole V1 is a rectangular shape, exposure accuracy issues result in the top and bottom openings of the resulting first via hole V1 being rounded rectangles. When the first via hole 30 is aligned with the rounded corners of the top and bottom openings, light diffracts at the rounded corners, resulting in light leakage. To address this issue, as shown in Figures 12 and 13, in some embodiments of the present disclosure, when viewed from a top perspective from the first auxiliary layer 91 to the base substrate 95, the top and bottom openings of the first via hole V1 are both rounded rectangles. The top opening includes multiple first straight edges SL1 and a first curved edge BL1 connecting two adjacent first straight edges SL1. The bottom opening includes multiple second straight edges SL2 and a second curved edge BL2 connecting two adjacent second straight edges SL2. Among them, the first conversion electrode 30 can contact a first straight edge SL1 and a second straight edge SL2, and has no contact with any first arc edge BL1 and any second arc edge BL2, thereby preventing the first conversion electrode 30 from climbing from the rounded corner position of the first via hole V1 and causing light leakage.

[0158] As shown in Figure 12, when the first via V1 and the second via V2 are coaxially arranged and connected, the second transition portion 32 of the first transition electrode 30 contacts a first straight line side SL1 and a second straight line side SL2 of the first via V1, but does not contact the first curved side BL1 and the second curved side BL2. In one example, the width a3 of the second transition portion 32 in the second direction is 0.25 to 0.9 times the length of the second straight line side SL2 in contact with the second transition portion 32. For example, a3 is 0.5 to 1.8 μm, and the length of the second straight line side SL2 at the point of contact with the second transition portion 32 is 2 to 3 μm. In one example, the orthographic projection of the first transition electrode 30 on the base substrate 95 includes a first projected area and a second projected area. The width of the first projected area in the second direction is a3, and the width of the second projected area in the second direction is greater than a3. The spacing b3 between the second projected area and the first via V1 in the first direction is between 0 and 1 μm.

[0159] Among them, when the width of the second projection area in the second direction is greater than a3, the orthographic projection shape of the first conversion electrode 30 on the base substrate 95 is T-shaped; of course, in other examples, the width of the second projection area in the second direction can also be equal to a3, that is, the orthographic projection shape of the first conversion electrode 30 on the base substrate 95 is rectangular.

[0160] As shown in Figure 13, when the first via V1 and the second via V2 are staggered, the width c3 of the second transition portion 32 in the second direction is the same as the above-mentioned a3, and the orthographic projection of the first transition electrode 30 on the base substrate 95 includes a first projection area and a second projection area. The width of the first projection area in the second direction is c3, and the width of the second projection area in the second direction is c3+2*e3, e3 is between 0.5 and 1.5 μm, and the distance d3 between the second projection area and the first via V1 in the first direction is between 0 and 1 μm.

[0161] Figure 14 is a plan view of multiple first transfer electrodes and first vias in the same row, provided in some embodiments of the present disclosure. Figure 15 is a plan view of multiple first transfer electrodes and first vias in the same row, provided in other embodiments of the present disclosure. As shown in Figure 14 , in some embodiments, multiple pixel structures are arranged in multiple rows, and the first transfer electrodes 30 of the pixel structures correspond one-to-one with the first vias V1. That is, each first transfer electrode 30 is directly or indirectly connected to the drain region 11d of the thin-film transistor through one first via V1. In other embodiments, as shown in Figure 15 , the first vias V1 corresponding to the first transfer electrodes 30 of multiple pixel structures in the same row are connected, forming an elongated via. This increases the length of the straight edge of the via, thereby preventing the first transfer electrodes 30 from contacting the rounded corners of the first vias V1.

[0162] In one example, as shown in Figure 15 , the row-direction spacing i4 between the second transition portions 32 of two adjacent first transition electrodes 30 in the same row is 0.5 to 10 times the width h4 of the second transition portions 32. This ensures the connection stability of the second transition portions 32 while preventing short circuits between the two adjacent second transition portions 32 in the same row. For example, i4 is 0.5 to 2 times, 2 to 5 times, 3 to 8 times, or 6 to 10 times h4. The width h4 of the second transition portion 32 is the dimension of the second transition portion 32 in the second direction.

[0163] In one example, h4 is between 0.5 and 4 μm, for example, h4 is 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, or 4 μm. i4 is between 2 and 5 μm, for example, i4 is 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, or 5 μm.

[0164] In one example, a dimension j4 of the bottom opening of the elongated via formed by connecting the plurality of first vias V1 in the first direction is between 1.5 and 3.5 μm, for example, j4 is 1.5 μm, or 2 μm, or 2.5 μm, or 3 μm, or 3.5 μm.

[0165] Figure 16 is a schematic diagram of an array substrate provided with a second electrode layer provided in some embodiments of the present disclosure, Figure 17 is a plan view of the second electrode layer, the first electrode, and the first switching electrode in a single pixel area, and Figure 18 is a schematic diagram of the brightness distribution of the pixel area corresponding to Figure 17; Figure 19 is a plan view of the second electrode layer, the first electrode, and the first switching electrode in a single pixel area provided in other embodiments of the present disclosure, and Figure 20 is a schematic diagram of the brightness distribution of the pixel area corresponding to Figure 19.

[0166] As shown in Figure 16, an insulating spacer layer 70 is provided on the side of the first electrode 20 away from the base substrate 95. The material of the insulating spacer layer 70 can be selected from the materials of the second auxiliary layer 92 listed above. The second electrode layer 50 is located on the side of the insulating spacer layer 70 away from the base substrate 95. The embodiment of the present disclosure is described by taking the second electrode layer 50 as a common electrode layer as an example. As shown in Figures 17 and 19, a slit 51 is provided on the second electrode layer 50. The slit 51 includes a main slit portion 510, and a first corner portion 511 and a second corner portion 512 respectively located at both ends of the main slit portion 510 and connected to the main slit portion 510. The main slit portion 510 extends along the third direction. The first corner portion 511 and the second corner portion 512 are bent to the opposite sides of the first main slit portion 510, respectively.

[0167] Among them, the first transition electrode 30 and the first electrode 20 electrically connected to it constitute an electrode assembly, the orthographic projection of the first main gap portion 510 on the base substrate 95 is located within the orthographic projection range of the electrode assembly on the base substrate 95, and the orthographic projections of the first corner portion 511 and the second corner portion 512 on the base substrate 95 both overlap with the orthographic projection of the electrode assembly on the base substrate 95.

[0168] As shown in Figures 18 and 20, since the liquid crystal light efficiency at the edge of the pixel area is relatively low, dark areas are likely to appear at the edge of the pixel area. By setting a first corner portion 511 and a second corner portion 512 at both ends of the slit 51, the position of the dark area can be transferred to the corner position of the pixel area, so that this part of the dark area can be blocked by the black matrix in the display panel, thereby reducing the dark area range of the opening area and improving the transmittance.

[0169] In some examples, as shown in FIG17 , a width a5 of the main slit portion 510 in a direction perpendicular to the third direction is between 0.5 and 3 μm, for example, a5 is 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.2 μm, 2.7 μm, or 3 μm. The main slit portion 510 includes a first side E1 and a second side E2 arranged along its width direction, a first corner portion 511 bends toward the first side E1 away from the second side E2, and a second corner portion 512 bends toward the second side E2 away from the first side E1.

[0170] In some examples, as shown in FIG17 , a dimension b5 of the first corner portion 511 in the first direction is between 1 and 1.5 μm, for example, b5 is 1 μm, 1.25 μm, or 1.5 μm. A width c4 of the second corner portion 512 extending beyond the main slit portion 510 in the second direction is between 0.5 and 1 μm, for example, c4 is 0.5 μm, 0.65 μm, 0.75 μm, 0.85 μm, or 1 μm.

[0171] In some examples, the first corner portion 511 includes a first connecting edge connected to the first side edge, and a tangent at a connection between the first connecting edge and the first side edge E1 forms an angle α of 30° to 60° with the second direction; the second corner portion 512 includes a second connecting edge connected to the first side edge E1, and a third connecting edge connected to the second connecting edge, and a tangent at an end of the third connecting edge away from the second connecting edge forms an angle β of 15° to 30° with the second direction; the second direction is perpendicular to the first direction.

[0172] In some examples, as shown in FIG17 , the extension direction of the main slit portion 510 is parallel to the first direction; in other examples, as shown in FIG19 , the extension direction of the main slit portion 510 intersects the first direction. The angle γ between the extension direction of the main slit portion 510 and the first direction is between 0° and 30°, for example, γ is 0°, 10°, 20°, or 30°.

[0173] In some embodiments, a slit 51 is provided on the second electrode layer 50 at a position corresponding to each electrode assembly, and the slits 51 corresponding to different electrode assemblies are not connected. However, in products with a higher pixel density, the size of the pixel area is smaller, and the alignment process between the second electrode layer 50 and the first electrode 20 is limited, and the alignment deviation often reaches about 1 μm. Figure 21 is a schematic diagram of the slit 51 of the second electrode layer 50 and the electrode assembly with and without alignment deviation. As shown in Figure 21, when the slit 51 and the electrode assembly have alignment deviation, the first corner portion 511 moves toward the middle of the electrode assembly, which will cause the transmittance of the pixel area to decrease. Tests have found that after the alignment deviation occurs, the transmittance of the pixel area drops from 9.4% to 7.1%.

[0174] In order to improve the transmittance of the pixel area after the alignment deviation occurs between the slit 51 and the electrode assembly, in some embodiments of the present disclosure, the slit 51 corresponding to the pixel area can be connected. Figure 22 is a schematic diagram of the second electrode layer provided in some embodiments of the present disclosure, and Figure 23 is a schematic diagram of the superposition of multiple electrode assemblies, the second electrode layer and the connecting electrode provided in some embodiments of the present disclosure. As shown in Figures 22 and 23, in some embodiments of the present disclosure, multiple pixel structures are arranged in multiple rows along the first direction, and each row includes multiple pixel structures arranged along the second direction, and the electrode assemblies of the pixel structures in two adjacent rows are staggered. Among them, the first corner portion 511 of the slit 51 corresponding to at least one pixel structure is connected to the second corner portion 512 of the slit 51 corresponding to a pixel structure in the previous row, and the second corner portion 512 of the slit 51 corresponding to at least one pixel structure is connected to the first corner portion 511 of the slit 51 corresponding to a pixel structure in the next row. When the second electrode layer 50 is misaligned with the electrode assembly, an electric field of a certain intensity can still be formed at the first corner portion 511 and the second corner portion 512 of the slit 51 , thereby increasing the transmittance after the misalignment.

[0175] As shown in FIG22 , for two interconnected slits 51 corresponding to two electrode assemblies in two adjacent rows, the main slit portion 510 in the next row is located on the side of the main slit portion 510 in the previous row that is farther away from the extension line of the first side E1 than the extension line of the second side E2. That is, for two connected slits 51, the main slit portion 510 in the next row is located to the lower left of the main slit portion 510 in the previous row.

[0176] As shown in Figure 22, the multiple slits 51 are divided into multiple slit groups. The slits 51 in the same slit group are connected to each other to form dividing grooves 51s. The multiple dividing grooves 51s corresponding to the multiple slit groups 51 divide the second electrode layer 50 into multiple second electrode strips 50a. The array substrate also includes multiple connecting electrodes 80, each of which extends along the second direction and is electrically connected to the multiple second electrode strips 50a. The multiple connecting electrodes 80 can electrically connect all the second electrode strips 50a and reduce the resistance of the second electrode layer 50. The connecting electrodes 80 can be made of metal.

[0177] In some embodiments, the connecting electrode 80 does not overlap with the orthographic projection of the main slit portion 510 of the slit 51 on the base substrate 95. In some embodiments, the width of the connecting electrode 80 can be between 1.2 and 2.4 μm, for example, 1.2 μm, 1.3 μm, 1.5 μm, 1.8 μm, 2.0 μm, 2.2 μm, or 2.4 μm. The width of the connecting electrode 80 refers to the dimension of the connecting electrode 80 in a direction perpendicular to the second direction.

[0178] In some embodiments, for any two connected slits 51, the second corner portion 512 of the slit 51 in the previous row and the first corner portion 511 of the slit 51 in the next row are connected to form a curved portion, which includes a first curved edge B1 and a second curved edge B2. As shown in Figure 22, the first curved edge B1 connects to the first side E1 of two adjacent main slit portions 510, and the second curved edge B2 connects to the second side E2 of two adjacent main slit portions 51. The first curved edge B1 includes a first sub-connecting edge B11, a second sub-connecting edge B12, and a third sub-connecting edge B13. The first sub-connecting edge B11 connects to the first side E1 of the slit 51 in the next row, the third sub-connecting edge B13 connects to the first side E1 of the slit 51 in the previous row, and the second sub-connecting edge B12 connects between the first sub-connecting edge B11 and the third sub-connecting edge B13. The second curved edge B2 includes: a fourth sub-connecting edge B24, a fifth sub-connecting edge B25 and a sixth sub-connecting edge B26; wherein, the fourth sub-connecting edge B24 is connected to the second side E2 of the slit 51 in the next row, the sixth sub-connecting edge B26 is connected to the second side E2 of the slit 51 in the previous row, and the fifth sub-connecting edge B25 is connected between the fourth sub-connecting edge B24 and the sixth sub-connecting edge B26.

[0179] The tangent at the intersection of the second sub-connecting edge B12 and the first sub-connecting edge B11 forms an angle β1 with the second direction, and β1 is between 15° and 30°. The tangent at the intersection of the second sub-connecting edge B12 and the third sub-connecting edge B13 forms an angle α1 with the second direction, and α1 is between 30° and 60°. The tangent at the intersection of the fifth sub-connecting edge B25 and the fourth sub-connecting edge B24 forms the aforementioned angle α1 with the second direction. The tangent at the intersection of the sixth sub-connecting edge B26 and the fifth sub-connecting edge B25 forms the aforementioned angle β1 with the second direction.

[0180] FIG24 is a simulation diagram of the transmittance of the pixel area under different conditions. As shown in FIG24 , when there is no alignment deviation in the second electrode layer 50, when the slits 51 in different pixel areas are not connected, the transmittance of the pixel area is 9.3%; after the slits 51 in the pixel area are connected with the slits 51 in other pixel areas, the transmittance of the pixel area increases to 9.5%; when there is an alignment deviation of 0.8 μm in the second electrode layer 50, when the slits 51 in different pixel areas are not connected, the transmittance of the pixel area is 7.1% (a decrease of 23% compared to the case without alignment deviation); when the slits 51 in the pixel area are connected with the slits 51 in other pixel areas, the transmittance of the pixel area is 7.7% (a decrease of 19% compared to the case without alignment deviation). It can be seen that connecting the slits 51 in the pixel area with the other slits 51 is beneficial to improving the transmittance of the pixel area.

[0181] Figure 25 is a plan view of a semiconductor layer provided in some embodiments of the present disclosure, Figure 26 is a plan view of a gate metal layer provided in some embodiments of the present disclosure, Figure 27 is a plan view of a first sub-auxiliary layer provided in some embodiments of the present disclosure, Figure 28 is a plan view of a source-drain metal layer provided in some embodiments of the present disclosure, Figure 29 is a plan view of a second sub-auxiliary layer provided in some embodiments of the present disclosure, Figure 30 is a schematic diagram of the superposition of the gate metal layer, the first sub-auxiliary layer, the source-drain metal layer, and the second sub-auxiliary layer provided in some embodiments of the present disclosure, Figure 31 is a plan view of a first transparent conductive layer provided in some embodiments of the present disclosure, Figure 32 is a schematic diagram of the superposition of the first transparent conductive layer and the second sub-auxiliary layer provided in some embodiments of the present disclosure, Figure 33 is a plan view of the first auxiliary layer provided in some embodiments of the present disclosure, and Figure 34 is a schematic diagram of the superposition of the gate metal layer, the first sub-auxiliary layer, the source-drain metal layer, and the second sub-auxiliary layer provided in some embodiments of the present disclosure. Figure 35 is a schematic diagram of the superposition of the second sub-auxiliary layer, the first transparent conductive layer and the first auxiliary layer. Figure 36 is a schematic diagram of the superposition of the second sub-auxiliary layer, the first transparent conductive layer, the second transparent conductive layer and the first auxiliary layer provided in some embodiments of the present disclosure. Figure 37 is a plan view of the third transparent conductive layer provided in some embodiments of the present disclosure. Figure 38 is a schematic diagram of the superposition of the second sub-auxiliary layer, the first transparent conductive layer, the second transparent conductive layer, the first auxiliary layer and the third transparent conductive layer provided in some embodiments of the present disclosure. Figure 39 is a plan view of the second electrode layer provided in some embodiments of the present disclosure. Figure 40 is a schematic diagram of the superposition of the second sub-auxiliary layer, the first transparent conductive layer, the second transparent conductive layer, the first auxiliary layer, the third transparent conductive layer and the second electrode layer provided in some embodiments of the present disclosure.

[0182] Among them, the pixel areas in the embodiment of the present disclosure are arranged in multiple rows, and the pixel areas of two adjacent rows are staggered. Each pixel area corresponds to a thin film transistor, a first electrode 20, a first transfer electrode 30, and a second transfer electrode 40. As shown in Figure 25, the active layer 11 of each thin film transistor is located in the semiconductor layer ACT. The active layer 11 includes a groove area 11a and a source area 11s and a drain area 11d located on both sides of the channel area 11a. As shown in Figure 26, the gate metal layer G1 includes a plurality of gate lines GL, and the plurality of gate lines GL are arranged along the first direction, and each gate line GL extends along the second direction. As shown in Figures 27 to 30, the first sub-auxiliary layer 921 is located on the side of the gate metal layer G1 away from the base substrate 95. A plurality of third vias V3 are provided on the first sub-auxiliary layer 921. The source area 11s of each thin film transistor is connected to the data line DL through the third via V3. Multiple data lines DL are located in the source / drain metal layer SD. The multiple data lines DL are arranged along the second direction. Each data line DL includes a first extension portion DL1 extending along the first direction and a second extension portion DL2 extending along the second direction. The orthographic projection of the second extension portion DL2 on the base substrate 95 overlaps with the orthographic projection of the gate line GL on the base substrate 95. The second auxiliary sub-layer 922 is located on a side of the source / drain metal layer SD away from the base substrate 95 and has a plurality of second vias V2.

[0183] As shown in Figures 31 to 40, the first transparent conductive layer TL1 is located on the side of the second auxiliary sub-layer 922 away from the base substrate 95 and includes a plurality of second transfer electrodes 40, each corresponding to a plurality of pixel regions. The second transfer electrodes 40 are electrically connected to the drain region of the thin film transistor via a second via V2. The first auxiliary layer 91 is located on the side of the first transparent conductive layer TL1 away from the base substrate 95 and includes a plurality of first vias V1, each corresponding to a plurality of pixel regions. The second transparent conductive layer TL2 is located on the side of the flat layer 91 away from the base substrate and includes a plurality of first transfer electrodes 30, each corresponding to a plurality of pixel regions. Each first transfer electrode 30 is electrically connected to a second transfer electrode 40 via a first via V1. The shape of the first transfer electrodes 30 is not limited; for example, the first transfer electrodes 30 can be rectangular or trapezoidal. The third transparent conductive layer TL3 is located on a side of the second transparent conductive layer TL2 away from the base substrate 95 and includes a plurality of first electrodes 20. The plurality of first electrodes 20 correspond one-to-one to a plurality of pixel regions, and each first electrode 20 is electrically connected to a corresponding first switching electrode 30. The second electrode layer 50 is located on a side of the third transparent conductive layer TL3 away from the base substrate 95 and has a plurality of dividing grooves 51s, as described above for details.

[0184] An embodiment of the present disclosure further provides a display panel, which includes the array substrate in the above embodiment and a cell-aligning substrate arranged opposite to the array substrate.

[0185] The cell substrate may include a color filter layer and a black matrix, wherein the color filter layer includes color filter portions corresponding one-to-one to the pixel areas, wherein the multiple color filter portions of the color filter layer may be divided into multiple repeating units, each repeating unit including color filter portions of multiple colors (e.g., red, green, and blue), so that light from multiple pixel areas can emit multiple different colors after passing through the color filter layer.

[0186] The orthographic projections of the gate lines GL, the data lines DL, and the connecting electrodes 80 on the base substrate 95 are all located within the orthographic projection range of the black matrix on the base substrate 95 .

[0187] FIG41 is a plan view of the black matrix, first electrode, and first transfer electrode provided in some embodiments of the present disclosure, and FIG42 is a plan view of the black matrix and second electrode layer provided in some embodiments of the present disclosure. As shown in FIG41 , the orthographic projection of the main portion 21 of the first electrode 20 on the substrate 95 overlaps with the orthographic projection of the black matrix BM on the substrate 95. The orthographic projection of the first transfer portion 31 on the substrate 95 overlaps with the orthographic projection of the black matrix BM on the substrate 95. Specifically, the orthographic projection of the portion of the first transfer portion 31 extending beyond the first electrode 20 on the substrate 95 overlaps with the orthographic projection of the black matrix BM on the substrate 95.

[0188] The portion of the pixel area not blocked by the black matrix BM serves as an opening area. The first via hole V1 is located in the opening area. That is, the first via hole V1 does not overlap with the orthographic projection of the black matrix BM on the base substrate 95, thereby reducing the area blocked by the black matrix BM and improving the aperture ratio of the pixel area.

[0189] As shown in FIG42 , the black matrix BM includes a first blocking portion BM1 extending along a first direction and a second blocking portion BM2 extending along a second direction, wherein the width of the second blocking portion BM2 can be between 2.2 and 2.6 μm, for example, 2.2 μm, 2.4 μm, or 2.8 μm. The width of the first blocking portion BM1 can be between 1.8 and 2.2 μm, for example, 1.8 μm, 2 μm, or 2.2 μm. The orthographic projection of the first blocking portion BM1 on the substrate SUB overlaps with the orthographic projection of the curved portion of the dividing groove 51s on the substrate SUB, and the orthographic projection of the first blocking portion BM1 on the substrate 95 is located between the orthographic projections of the main slit portions 510 of two adjacent rows on the substrate 95.

[0190] FIG47 is a schematic diagram of a display panel and a flexible circuit board provided in some embodiments of the present disclosure. As shown in FIG47 , the display panel has a display area AA, which includes a plurality of pixel areas P arranged in an array. The display panel includes an array substrate 100 and a mating substrate 200. The array substrate 100 and the mating substrate 200 are bonded together with a sealant (not shown), which surrounds the display area AA. A bonding area WA is provided on one side of the display area AA. The bonding area WA is provided with bonding pads. The flexible circuit board 300 is bonded to the bonding pads. A driver chip 400 is provided on the flexible circuit board 300 to provide drive signals to each pixel area P.

[0191] FIG48 is a schematic diagram of an application scenario in which a display panel is provided in some embodiments of the present disclosure, and FIG49 is a schematic diagram of a near-eye display device. As shown in FIG48 and FIG49 , the display panel can be used in a near-eye display device, which includes a housing 501, a wearing portion 502 connected to the housing 501, and a display portion 502 and an optical system 504 disposed in the housing 501. The wearing portion 502 is used to be worn on the head of the user 600, and the display portion 502 may include the display panel in the above-mentioned embodiment. The optical system 504 is used to receive light from the display portion 502, and after refraction, reflection, and other processing, the light is projected into the user's eye 601, so that the user 600 can see the image.

[0192] The present disclosure also provides a mask for use in the aforementioned method for manufacturing the array substrate and for forming the aforementioned first via V1. Figure 43 is a partial schematic diagram of a mask provided in some embodiments of the present disclosure, Figure 44 is a partial schematic diagram of a mask provided in other embodiments of the present disclosure, Figure 45 is a partial schematic diagram of a mask provided in still other embodiments of the present disclosure, and Figure 46 is a partial schematic diagram of a mask provided in yet other embodiments of the present disclosure.

[0193] As shown in Figures 43 to 46, the mask M1 includes a light-transmitting area TA for forming the first via V1 and a light-shielding area TA located outside the light-transmitting area TA. The orthographic projection of the first via V1 on the substrate 95 is roughly polygonal, for example, roughly rectangular. The "roughly" polygonal here refers to a shape that is polygonal overall, for example, a shape in which two adjacent sides are directly connected or connected by rounded corners. Roughly rectangular can refer to: a rounded rectangle or a right-angled rectangle. Of course, regardless of the polygonal shape, its sides are not necessarily strictly straight edges and may also fluctuate due to process limitations. The light-transmitting area TA includes a main light-transmitting area TA1 and a compensation light-transmitting area TA2 that are connected. The main light-transmitting area TA1 is polygonal, and the compensation light-transmitting area TA2 is located at the corner of the main light-transmitting area TA1. The compensation light-transmitting area TA2 protrudes from the edge of the main light-transmitting area TA1 in both the length and width directions of the main light-transmitting area TA1.

[0194] Among them, the step of forming the first via hole V1 using the mask plate M1 includes: exposing the first auxiliary layer 91 using the mask plate M1 to denature the portion of the first auxiliary layer 91 corresponding to the light-transmitting area, and then developing the first auxiliary layer 91 to remove the denatured portion of the first auxiliary layer 91 to form the first via hole V1.

[0195] When the first via hole V1 is formed into a rectangular shape, if the light-transmitting area is also a rectangular shape, less light will pass through the corners of the rectangular shape compared to the center of the rectangular shape. Therefore, the final pattern will be a rounded rectangle. For a first via hole V1 with rounded corners, the first transfer electrode 30 is prone to breakage when it slopes up at the rounded corners of the first via hole V1.

[0196] In the mask M1 provided in the embodiment of the present disclosure, a compensation light-transmitting area TA2 is provided at the corner of the main light-transmitting area TA1. The compensation light-transmitting area TA2 protrudes from the edge of the main light-transmitting area TA1 in both the length and width directions of the main light-transmitting area TA1, thereby increasing the amount of light passing through the corner of the main light-transmitting area TA1, and further making the first via hole V1 finally formed closer to a right-angled rectangle.

[0197] Among them, the size of the compensation light-transmitting area TA2 exceeding the main light-transmitting area TA1 in the length direction is 0.02 to 0.2 times the length of the main light-transmitting area TA1; the size of the compensation light-transmitting area TA2 exceeding the main light-transmitting area TA1 in the width direction is 0.02 to 0.2 times the width of the main light-transmitting area TA1.

[0198] For example, the length and width of the main light-transmitting area TA1 are both between 2 and 3 μm, the length of the compensating light-transmitting area TA2 exceeds the main light-transmitting area TA1 by between 0.05 and 0.4 μm, and the width of the compensating light-transmitting area TA2 exceeds the main light-transmitting area TA1 by between 0.05 and 0.4 μm. For example, the main light-transmitting area TA1 is square, i.e., the length and width are the same.

[0199] For example, the main light-transmitting area TA1 is a square with a side length between 2 μm and 3 μm. As shown in FIG43 , the compensating light-transmitting area TA2 can be a square, with the intersection of two adjacent sides of the main light-transmitting area TA1 coinciding with the center of the compensating light-transmitting area TA2. The side length a6 of the compensating light-transmitting area TA2 is between 0.2 μm and 0.8 μm.

[0200] For example, the main light-transmitting area TA1 is a square with a side length between 2 μm and 3 μm. As shown in FIG44 , the compensating light-transmitting area TA2 can be a circle, with the intersection of two adjacent sides of the main light-transmitting area TA1 coinciding with the center of the compensating light-transmitting area TA2. The diameter b6 of the compensating light-transmitting area TA2 is between 0.2 μm and 0.8 μm.

[0201] For example, the main light-transmitting area TA1 is a square with a side length between 2 μm and 3 μm. As shown in FIG45 , the compensating light-transmitting area TA2 can be a trapezoid, with the intersection of two adjacent sides of the main light-transmitting area TA1 coinciding with the center of the compensating light-transmitting area TA2. The diameter b6 of the compensating light-transmitting area TA2 is between 0.2 μm and 0.8 μm.

[0202] For example, the main light-transmitting area TA1 is a square with a side length between 2 μm and 3 μm; as shown in FIG46 , the compensating light-transmitting area TA2 can be L-shaped. The L-shaped compensating light-transmitting area TA2 includes a first strip portion and a second strip portion, wherein the intersection of the midline of the first strip portion and the midline of the second strip portion coincides with the intersection of two adjacent sides of the main light-transmitting area TA1, the side length f6 of the first strip portion and the side length e6 of the second strip portion are both between 0.4 and 0.8 μm, and the width of the first strip portion and the width of the second strip portion are both g6, and g6 is between 0.1 and 0.4 μm.

[0203] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. An array substrate, comprising: A base substrate, a first auxiliary layer disposed on the base substrate, and a plurality of pixel structures, at least one of the pixel structures comprising: A transistor, located between the first auxiliary layer and the base substrate; a first transfer electrode, the first transfer electrode comprising a first transfer portion and a second transfer portion connected to each other, the first transfer portion being located on a side of the first auxiliary layer away from the base substrate, the second transfer portion being disposed in a first via hole penetrating the first auxiliary layer and electrically connected to the transistor; an auxiliary member, located in the first through hole; A first electrode, the first electrode comprising a contact portion and a main body portion connected to each other, the contact portion being electrically connected to the first transition portion, and an orthographic projection of the first electrode on the base substrate covering an orthographic projection of the first via hole on the base substrate; The orthographic projection of the first transition portion on the base substrate overlaps with the orthographic projection of the contact portion on the base substrate.

2. The array substrate according to claim 1, wherein: The contact portion contacts the surface of the first transfer portion away from the base substrate, at least part of the main portion is located on the surface of the auxiliary component away from the base substrate, and the second transfer portion of the first transfer electrode is closer to the base substrate than the auxiliary component.

3. The array substrate according to claim 1, wherein: At least one side boundary of the orthographic projection of the first transition portion on the base substrate exceeds the orthographic projection of the contact portion on the base substrate.

4. The array substrate according to claim 3, wherein: From a perspective perpendicular to the base substrate and along a first direction, a boundary of an orthographic projection of the first transition portion on the base substrate exceeds a boundary of an orthographic projection of the contact portion on the base substrate.

5. The array substrate according to claim 1, wherein: The array substrate further includes: a second auxiliary layer located between the first auxiliary layer and the transistor; the pixel structure further includes: a second switching electrode, the second switching electrode being electrically connected to the transistor via a second via hole penetrating the second auxiliary layer; The second via hole is connected to the first via hole, and the first switching electrode and the second switching electrode are connected to form an integrated structure.

6. The array substrate according to claim 5, wherein: The orthographic projections of the opening of the first via hole facing toward the base substrate and the opening of the second via hole facing away from the base substrate on the base substrate do not overlap.

7. The array substrate according to any one of claims 1 to 6, wherein: The array substrate has a plurality of pixel areas, each of which corresponds to a pixel structure; the size of the pixel area in a first direction is greater than the size of the pixel area in a second direction, and the first direction is perpendicular to the second direction; The contact portion is located at one side of the main body portion along the first direction.

8. The array substrate according to claim 7, wherein: The first transition portion includes a first part and a second part, the orthographic projection of the first part on the base substrate is located within the orthographic projection range of the contact portion on the base substrate, the second part is located on one side of the first part along the first direction, and the orthographic projection of the second part on the base substrate is located outside the orthographic projection of the contact portion on the base substrate; A ratio of a size of the first portion to a size of the pixel region in the first direction is between 0.1 and 0.

5.

9. The array substrate according to claim 2, wherein: Along a direction perpendicular to the base substrate, a height of the auxiliary member is greater than or equal to a depth of the first via hole.

10. The array substrate according to claim 2, wherein: Along a direction perpendicular to the base substrate, a distance between the main portion of the first electrode and the base substrate is greater than a distance between the contact portion and the base substrate.

11. The array substrate according to claim 8, wherein: A width of the second portion in the first direction is less than or equal to 1.5 μm.

12. The array substrate according to claim 7, wherein: At least three pixel structures include an electrode assembly, the electrode assembly includes the first switching electrode and the connected first electrode in the corresponding pixel area, there is a first spacing between the electrode assemblies of two adjacent pixel structures arranged in the first direction, and the ratio of the first spacing to the length of the electrode assembly in the first direction is between 0.05 and 0.

15.

13. The array substrate according to claim 7, wherein: The main body portion includes a first edge and a second edge arranged opposite to each other in the first direction, the first edge is located on a side of the main body portion away from the contact portion, and the second edge is adjacent to the contact portion, and a size of the pixel area in the first direction is between 6 and 10 μm; a spacing between the first edge and an opening of the first via hole toward the substrate in the first direction is between 0 and 1.5 μm.

14. The array substrate according to any one of claims 1 to 11, wherein: Along the top view from the first auxiliary layer to the base substrate, the opening of the first via hole away from the base substrate has a plurality of first straight edges and a first arc edge connected between every two adjacent first straight edges; the opening of the first via hole close to the base substrate has a plurality of second straight edges and a second arc edge connected between every two adjacent second straight edges; The first switching electrode has no contact with the first arc edge and the second arc edge.

15. The array substrate according to claim 14, wherein: The second transition portion contacts a second straight line side and a first straight line side, and a width of the second transition portion is 0.5 to 0.9 times the length of the second straight line side contacting the second transition portion.

16. The array substrate according to any one of claims 1 to 15, wherein: The pixel structures correspond one to one with the first via holes on the first auxiliary layer; or, The multiple pixel structures are arranged in multiple rows, and the first via holes corresponding to the multiple pixel structures in the same row are connected.

17. The array substrate according to claim 16, wherein: The first via holes corresponding to the multiple pixel structures in the same row are connected; the spacing between the second switching parts of two adjacent first switching electrodes in the same row in the row direction is 0.5 to 10 times the width of the second switching parts.

18. The array substrate according to claim 7, wherein: The array substrate further includes a second electrode layer, a slit is formed on the second electrode layer, the slit includes a main slit portion, and a first corner portion and a second corner portion located at both ends of the main slit portion and connected to the main slit portion, the main slit portion extends along a third direction; the first corner portion and the second corner portion are bent toward opposite sides of the main slit portion respectively; The first switching electrode and the corresponding first electrode form an electrode assembly, the orthographic projection of the main gap portion on the base substrate is located within the orthographic projection range of the electrode assembly on the base substrate, and the orthographic projections of the first corner portion and the second corner portion on the base substrate overlap with the orthographic projection of the electrode assembly on the base substrate.

19. The array substrate according to claim 18, wherein: The width of the main gap in a direction perpendicular to the third direction is between 0.5 and 3 μm.

20. The array substrate according to claim 18, wherein: The main gap portion includes a first side and a second side arranged along the width direction thereof, the first corner portion is bent toward the first side and away from the second side, and the second corner portion is bent toward the second side and away from the first side; The first corner portion includes a first connecting edge connected to the first side edge, and a tangent at a connection point between the first connecting edge and the first side edge forms an angle of 30° to 60° with a second direction; the second corner portion includes a second connecting edge connected to the first side edge, and a third connecting edge connected to the second connecting edge, and a tangent at an end of the third connecting edge away from the second connecting edge forms an angle of 15° to 30° with the second direction; the second direction is perpendicular to the first direction.

21. The array substrate according to claim 18, wherein: An angle between the third direction and the first direction is in the range of [0°, 30°].

22. The array substrate according to claim 18, wherein: The second electrode layer is provided with the slit at a position corresponding to each of the electrode assemblies. A plurality of the pixel structures are arranged in a plurality of rows along a first direction, each row includes a plurality of the pixel structures arranged along the second direction, a first corner portion of a slit corresponding to at least one of the pixel structures is connected to a second corner portion of a slit corresponding to one of the pixel structures in the previous row, and a second corner portion of a slit corresponding to at least one of the pixel structures is connected to a first corner portion of a slit corresponding to one of the pixel structures in the next row.

23. The array substrate according to claim 22, wherein: The plurality of slits on the second electrode layer are divided into a plurality of slit groups, the slits in the same slit group are connected to each other to form dividing grooves, and the plurality of dividing grooves corresponding to the plurality of slit groups divide the second electrode layer into a plurality of second electrode strips; The array substrate further includes a plurality of connecting electrodes extending along the second direction and electrically connected to a plurality of the second electrode strips.

24. The array substrate according to claim 23, wherein: The connecting electrode and the main slit portion of the slit have no overlap in their orthographic projections on the base substrate.

25. The array substrate according to claim 22, wherein: The width of the connecting electrode in a direction perpendicular to the second direction is between 1.2 and 2.4 μm.

26. A display panel comprising the array substrate according to any one of claims 1 to 25.

27. The display panel according to claim 26, wherein: The display panel also includes a box substrate arranged opposite to the array substrate, the box substrate includes a black matrix, and the orthographic projections of the main body and the first adapter on the base substrate overlap with the orthographic projection of the black matrix on the base substrate.

28. The display panel according to claim 26, wherein: The display panel further includes a box substrate disposed opposite to the array substrate, the box substrate includes a black matrix, and the first via hole has no overlap with the orthographic projection of the black matrix on the base substrate.

29. A mask plate used in a method for manufacturing an array substrate, wherein the array substrate is the array substrate according to any one of claims 1 to 25, and the mask plate comprises: A light-transmitting area is used to form the first via hole, and the orthographic projection of the first via hole on the substrate is roughly a polygon. The light-transmitting area includes a main light-transmitting area and a compensation light-transmitting area that are connected to each other. The main light-transmitting area is a polygon, and the compensation light-transmitting area is located at a corner of the main light-transmitting area. The compensation light-transmitting area protrudes from the edge of the main light-transmitting area in both the length direction and the width direction of the main light-transmitting area.

30. The mask according to claim 29, wherein: The dimension of the compensating light-transmitting area exceeding the main light-transmitting area in the length direction of the main light-transmitting area is 0.02 to 0.2 times the length of the main light-transmitting area; the dimension of the compensating light-transmitting area exceeding the main light-transmitting area in the width direction of the main light-transmitting area is 0.02 to 0.2 times the width of the main light-transmitting area.

Images