Chip-on-wafer assembly including decoupling capacitor

Abstract

A microelectronic component is provided that includes a semiconductor structure (e.g., an integrated circuit (IC) chip) and an interposer (e.g., a silicon interposer) electrically connected to the semiconductor structure and including a semiconductor material. The assembly also includes a decoupling capacitor including an alternating plurality of dielectric layers and a plurality of internal electrode layers, the plurality of internal electrode layers including a first internal electrode layer and a second internal electrode layer. The capacitor also includes an external terminal disposed on a first surface of the capacitor and electrically connected to the interposer, and an external terminal disposed on a second surface of the capacitor and electrically connected to the circuit board.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 420,743, filed Oct. 31, 2022, which is hereby incorporated by reference in its entirety. BACKGROUND OF THE INVENTION

[0003] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density has come from the repeated reduction of the minimum feature size, which allows more components to be integrated into a given area. As the demand for ever-shrinking electronic devices has grown, there has been a need for smaller and more innovative packaging technologies for semiconductor chips. A specific example of such a device is a Chip-on-Wafer (CoW) structure. To form a CoW structure, multiple semiconductor chips can be attached to a wafer, and then a dicing process can be performed to separate the wafer into multiple interposers, where each of the multiple interposers has one or more semiconductor chips attached thereto. An interposer with one or more attached semiconductor chips is referred to as a Chip-on-Wafer (CoW) structure. Then, optionally, the CoW structure can be attached to a build-up packaging substrate to form a Chip-on-Wafer-on-Substrate (CoWoS) structure, and finally, the resulting package can be connected to a printed circuit board. One or more decoupling capacitors are also typically employed as part of the power delivery system to the chip to provide any suddenly required current while maintaining the voltage constant or near constant. However, unfortunately, the increasing switching speed in the chip has led to an increase in parasitic inductance. Accordingly, there is a current need for improved microelectronic components that employ decoupling capacitors. SUMMARY OF THE INVENTION

[0004] According to one embodiment of the present invention, a microelectronic component is disclosed. The microelectronic component includes a semiconductor structure, an interposer (e.g., a silicon interposer) electrically connected to the semiconductor structure and including semiconductor material, and a circuit board. The component further includes a decoupling capacitor having a first surface and an opposite second surface, wherein the decoupling capacitor includes a plurality of alternating dielectric layers and a plurality of internal electrode layers. The plurality of internal electrode layers includes a first internal electrode layer and a second internal electrode layer. The capacitor further includes a first external terminal, a second external terminal, a third external terminal, and a fourth external terminal. The first external terminal is electrically connected to the first internal electrode layer and is disposed on the first surface of the capacitor. The second external terminal is electrically connected to the first internal electrode layer and is disposed on the second surface of the capacitor. The third external terminal is electrically connected to the second internal electrode layer and is disposed on the first surface of the capacitor. The fourth external terminal is electrically connected to the second internal electrode layer and is disposed on the second surface of the capacitor. The first external terminal and the third external terminal are electrically connected to the interposer, and the second external terminal and the fourth external terminal of the decoupling capacitor are electrically connected to the circuit board.

[0005] Other features and aspects of the present invention are set forth in greater detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] A complete and enabling disclosure of the present invention, including the best mode thereof to one of ordinary skill in the art, is set forth more particularly in the remainder of the specification, including reference to the accompanying drawings in which:

[0007] Figure 1 is a cross-sectional view of one embodiment of the microelectronic component of the present invention;

[0008] Figure 2 is a cross-sectional view of another embodiment of the microelectronic component of the present invention;

[0009] Figure 3 is a cross-sectional view of yet another embodiment of the microelectronic component of the present invention;

[0010] Figure 4A is a perspective view of one embodiment of a decoupling capacitor that can be employed in the present invention;

[0011] Figure 4B Shows Figure 4A a side view of the internal electrode layer of the capacitor in;

[0012] Figure 5A is a perspective view of another embodiment of a decoupling capacitor that can be employed in the present invention;

[0013] Figure 5B Shows Figure 5A an end view of the capacitor in;

[0014] Figure 5C shows the Figure 5A side view of the capacitor in

[0015] Figure 6A perspective view of another embodiment of the decoupling capacitor that can be adopted in the present invention;

[0016] Figure 6B shows the Figure 6A side view of the internal electrode layer of the capacitor in

[0017] Figure 7A perspective view of another embodiment of the decoupling capacitor that can be adopted in the present invention;

[0018] Figure 7B shows the Figure 7A side view of the internal electrode layer of the capacitor in

[0019] Figure 7C shows the Figure 7A perspective view of the internal electrode layer of the capacitor in

[0020] Figure 7D shows the Figure 7A cross-sectional perspective view of the capacitor in

[0021] Figure 8A perspective view of another embodiment of the decoupling capacitor that can be adopted in the present invention;

[0022] Figure 8B shows the Figure 8A side view of the internal electrode layer of the capacitor in

[0023] Figure 8C shows the Figure 8A perspective view of the internal electrode layer of the capacitor in

[0024] Figure 8D shows the Figure 8A cross-sectional perspective view of the capacitor in

[0025] Figure 9A perspective view of another embodiment of the decoupling capacitor that can be adopted in the present invention;

[0026] Figure 9B shows the Figure 9A cross-sectional perspective view of the capacitor in

[0027] Figure 10A perspective view of yet another embodiment of the decoupling capacitor that can be adopted in the present invention;

[0028] Figure 10Bshows Figure 10A a side perspective view of a configuration of an internal electrode layer of a capacitor in

[0029] Figure 10C shows Figure 10A a side perspective view of another configuration of an internal electrode layer of a capacitor in

[0030] Reference numerals repeated in this specification and the drawings are intended to denote the same or similar features or elements of the present invention. DETAILED DESCRIPTION

[0031] Those of ordinary skill in the art will understand that this discussion is only a description of exemplary embodiments and is not intended to limit the broader aspects of the present invention.

[0032] Generally, the present invention relates to a microelectronic component that includes a semiconductor structure, an interposer layer that contains semiconductor material and is electrically connected to the semiconductor structure, and a circuit board that is electrically connected to the interposer layer. The component also includes a decoupling capacitor that has a first surface and an opposite second surface. The decoupling capacitor includes alternating dielectric layers and internal electrode layers, where the internal electrode layers include a first internal electrode layer and a second internal electrode layer. A first external terminal is electrically connected to the first internal electrode layers and is disposed on the first surface of the capacitor, and a second external terminal is electrically connected to the first internal electrode layer and is disposed on the second surface of the capacitor. Similarly, a third external terminal is electrically connected to the second internal electrode layer and is disposed on the first surface of the capacitor, and a fourth external terminal is electrically connected to the second internal electrode layer and is disposed on the second surface of the capacitor. Generally, the first external terminal and the second external terminal have the same polarity (e.g., positive), and the third external terminal and the fourth external terminal have the same polarity (e.g., negative). In any case, the first external terminal and the third external terminal of the decoupling capacitor are electrically connected to the interposer layer, and the second external terminal and the fourth external terminal of the decoupling capacitor are electrically connected to the circuit board (e.g., a printed circuit board).

[0033] Various embodiments of the present invention will be described in more detail below.

[0034] I. Semiconductor Structure

[0035] One or more semiconductor structures (e.g., dies, wafers, integrated circuit devices, etc.) can typically be employed within a microelectronic component. Generally, a semiconductor structure can include an insulating material (e.g., a dielectric material formed in multiple layers as known in the art) and multiple conductive paths formed through the insulating material. The insulating material can include dielectric materials such as silicon dioxide, silicon nitride, silicon oxynitride, polyimide materials, glass-reinforced epoxy matrix materials, or low-k or ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, photoimageable dielectrics, and / or benzocyclobutene-based polymers). The insulating material may also contain semiconductor materials such as silicon, germanium, or III-V materials (e.g., gallium nitride), as well as one or more additional materials. For example, the insulating material can include silicon oxide or silicon nitride. The conductive paths of a die can include conductive traces and / or conductive vias and can connect to any of the conductive contacts among the multiple conductive contacts in the die in any suitable manner. The semiconductor structure can include hybrid pitch dies (in the sense that the die has multiple sets of conductive contacts with different pitches), e.g., the die can have "rougher" conductive contacts for coupling to an interposer of the microelectronic component. The structure can also include single-sided dies (having conductive contacts only on a single surface) and / or double-sided dies (having conductive contacts on a first surface and an opposite second surface). The conductive paths in the die can be bounded by liner materials (e.g., adhesion liners and / or barrier liners) as the case may be. The semiconductor structure can also include wafers. In some embodiments, the semiconductor structure includes a monolithic silicon, fan-out or fan-in packaged die, or a die stack (e.g., a wafer stack, a die stack, or a multi-layer die stack).

[0036] The semiconductor structure may also have an integrated circuit (“IC”) structure such that it exists in the form of discrete IC devices or “chips”. Such IC devices may include one or more device layers disposed on a die substrate. The die substrate may be a semiconductor substrate composed of a semiconductor material system, which includes, for example, an n-type material system or a p-type material system (or a combination of both). The die substrate may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate may be formed using alternative materials, which may or may not be combined with silicon, and these alternative materials include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV may also be used to form the die substrate. The device layer may include one or more transistors (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)), support circuits for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other IC components. The device layer may include, for example, one or more source and / or drain (S / D) regions, a gate for controlling the current flow in the transistor between the S / D regions, and one or more S / D contacts for routing electrical signals to / from the S / D regions. Each transistor may include a gate formed by at least two layers (a gate dielectric and a gate electrode). The gate dielectric may include a stack of one or more layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used for the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when using a high-k material, an annealing process may be performed on the gate dielectric to improve the quality of the gate dielectric.

[0037] A gate electrode may be formed on a gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor is a P-channel metal oxide semiconductor (PMOS) transistor or an N-channel metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may be composed of a stack of two or more metal layers, where one or more of the metal layers are work function metal layers and at least one metal layer is a fill metal layer. Other metal layers for other purposes may be included, such as barrier layers. For PMOS transistors, metals available for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the various metals discussed below for NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals available for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the multiple metals discussed above for PMOS transistors (e.g., for work function tuning). Electrical signals (e.g., power supply and / or input / output (I / O) signals) may be routed to and / or from devices (e.g., transistors) in the device layer through one or more interconnect layers disposed on the device layer. For example, conductive features (e.g., gates and S / D contacts) in the device layer may be electrically coupled to interconnect structures, which may optionally form the metallization stack (also referred to as the “(ILD) interlayer dielectric stack”) of the IC device. The interconnect structures may include wires and / or vias filled with a conductive material (e.g., metal). These wires may be arranged to route electrical signals in a plane direction substantially parallel to the surface of the die substrate on which the device layer is formed. These vias may be arranged to route electrical signals in a plane direction substantially perpendicular to the surface of the die substrate on which the device layer is formed.

[0038] For example, an IC device may include a memory device (e.g., a random access memory (RAM) device such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, an erasable-programmable read-only memory (EPROM) chip, a non-volatile memory (e.g., three-dimensional cross-point (3D XPoint)), a volatile memory (e.g., high-bandwidth memory), a stacked memory, etc.); a logic device (e.g., an AND, OR, NAND, or NOR gate, a programmable logic device, etc.); a processor device (e.g., a central processing unit (CPU), a graphics processing unit (GPU), etc.); an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), and a platform controller hub (PCH), etc., and any other suitable memory device, logic device, and / or processor device. Multiple devices may be combined on a single structure. For example, a memory array formed of multiple memory devices may be formed on the same die as a processor device or other logic configured to store information in the memory device or execute instructions stored in the memory array.

[0039] A semiconductor structure can also be a "chiplet", which is a small integrated circuit (IC) that contains a well - defined subset of functions that is part of a processing module of a larger integrated circuit such as a computer processor. In some embodiments, one or more chiplets are coupled to a host chip in various ways, where each of the one or more chiplets includes its own cache (e.g., including a last - level cache (LLC) accessible to one or more cores of the host chip). The host chip can include one or more processor cores, each of which can operate as a consumer of memory resources, and the chiplet can include one or more memory arrays that are coupled to be accessible by the corresponding processor cores of the host chip. In this particular context, the terms "memory", "memory array", "memory resource" and related terms generally refer to cache memory or non - cache memory (e.g., such as system memory). Similarly, the term "memory controller" generally refers to controller circuitry that provides access to one of cache memory or non - cache memory. The host chip can contain a processor core that will operate as a consumer of memory resources. For example, the host chip can execute any one of an operating system, a binary input / output system (BIOS), and / or various other software processes. To facilitate the execution of such software, the chiplet can include one or more memory arrays that are coupled to be accessible by the processor core via a hardware interface. In one embodiment, the memory array includes static random - access memory (SRAM) cells or dynamic random - access memory (DRAM) cells. Additionally or alternatively, the processor core can be coupled to cache data into the memory array, e.g., where the processor core is coupled to access the last - level cache (LLC) of the memory array. In various other embodiments, the memory array can contain non - volatile memory (NVM) cells. The chiplet can also contain a memory controller coupled between the hardware interface and the memory array, which is used to control memory access on behalf of the processes executed by the core. By providing a memory array in the chiplet disposed between the hardware interface and the host chip, the locality of data can be improved for use by one or more cores of the packaged device. This improved data locality enables access to memory resources to be relatively more spatially efficient, temporally efficient, and / or power efficient.

[0040] One or more semiconductor structures may be arranged in a two-dimensional configuration or array as known in the art (e.g., 2D, 2.1D, 2.3D, or 2.5D heterogeneous integration), or stacked into a 3D configuration. When a stacked configuration is employed, the semiconductor structures may include two or more semiconductor substrates (e.g., chips, interposers, etc.) mounted on a circuit board. If implemented as semiconductor chips, these substrates may be any of numerous different types of circuit devices used in an electronic device, e.g., such circuit devices as microprocessors, graphics processors, combined microprocessor / graphics processors, application specific integrated circuits, or memory devices, etc., and may be single-core or multi-core. The substrates may be composed of bulk semiconductor (e.g., silicon or germanium) or semiconductor-on-insulator material (e.g., silicon-on-insulator material). The circuit board may be a semiconductor chip package substrate, a circuit card, or almost any other type of printed circuit board. The circuit board may use a monolithic structure, although a more typical configuration will use a stacked design. In this regard, the circuit board may consist of a central core, on which one or more stacked layers are formed, and one or more additional stacked layers are formed below the central core. The core itself may consist of a stack of one or more layers. An interconnect structure may provide circuit paths between the substrates and the circuit board, and between any of these substrates.

[0041] II. Interposer

[0042] As described above, the semiconductor structures are electrically connected to one or more interposers such that the resulting microelectronic assembly is considered a "package-on-interposer" structure. In other respects, the interposer may provide an intervening substrate to help bridge the circuit board and the semiconductor structures, and help extend the connections to wider pitches or reroute the connections to different connections. The semiconductor structures may be electrically connected to the interposer through one or more coupling components. The coupling components may electrically and mechanically couple the package-on-interposer structure to the circuit board, and may include, for example, solder bumps, solder balls, the protrusions and recesses of a socket, adhesives, underfill materials, and / or any other suitable electrical coupling structure and / or mechanical coupling structure. The underfill material may be an insulating material, e.g., a suitable epoxy resin material. In use, the underfill material may include capillary underfill, non-conductive film (NCF), or molded underfill. In some embodiments, the underfill material may include an epoxy flux that aids in soldering the semiconductor structures and then polymerizes and encapsulates the interconnects within the interposer.

[0043] The interposer layer generally includes a semiconductor material and one or more conductive paths (e.g., including conductive traces and / or conductive vias) passing through the semiconductor material. Suitable semiconductor materials can include, for example, silicon, germanium, and other Group III-V (e.g., gallium nitride) and Group IV materials. The conductive paths serve as means for electrically connecting the interposer layer to the semiconductor structure via coupling components. Such paths can include one or more metal interconnects and vias as known in the art. In one embodiment, for example, the interposer layer can be formed of silicon, and vias can be formed in the interposer layer, which can be referred to as "through-silicon vias" (TSV).

[0044] Regardless of how the interposer layer is formed, the interposer layer can be passive or active depending on the particular embodiment. By "passive" is generally meant that the interposer layer typically has no embedded electronic components. On the other hand, an "active" interposer layer generally contains one or more electronic components embedded in an insulating material. Examples of such electronic components can include, for example, capacitors (e.g., decoupling capacitors), resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices can also be formed in the interposer layer, such as radio frequency devices, power amplifiers, power management devices, antennas, and microelectromechanical system (MEMS) devices. For example, an active interposer layer can include an active layer and a bulk semiconductor layer. In this document, the front surface of the active layer can be referred to as the "active side", while the opposite surface of the bulk semiconductor layer can be referred to as the "back side". In one embodiment, the active layer can include one or more electronic components formed on the active side, such as level one (L1) storage elements, which serve as memory caches for storing configuration bit streams used to configure logical sectors in a coprocessor. The active layer can optionally include decryption / decompression circuitry for processing encrypted and / or compressed configuration bit streams. The semiconductor layer can include TSVs that connect the electronic components (e.g., L1 storage elements) in the active layer to coupling elements (e.g., solder balls). For example, the L1 cache can receive configuration bit streams from a host processor via solder balls and TSVs. In this way, the energy efficiency of transmitting signals and power between the active layer of the interposer layer and the package substrate can be improved.

[0045] III. Optional Component

[0046] In addition to the interposer and the semiconductor structure, the microelectronic component may further include other optional components and / or layers known in the art. For example, if desired, a "stacked" package substrate may be used between the interposer and the decoupling capacitor / circuit board to assist in bridging high-density interconnects and functions between the semiconductor structure, the interposer, and the circuit board. The package substrate generally includes an organic insulating material and one or more conductive paths (e.g., as shown, including conductive traces and / or conductive vias) passing through the insulating material. For example, the organic insulating material may include a bismaleimide triazine ("BT") resin material (e.g., BT, BT-epoxy resin, etc.), an epoxy resin material (e.g., glass fiber-reinforced epoxy resin (e.g., FR4)), a polyimide material, a low-k dielectric, and an ultra-low-k dielectric (e.g., carbon-doped dielectric, fluorine-doped dielectric, porous dielectric, and organic polymer dielectric). In some embodiments, the insulating material may be a laminate or a stacked film (e.g., Ajinomoto stacked film). The conductive paths may couple the semiconductor structure to the circuit board and the decoupling capacitor. Conductive paths having any suitable arrangement through any suitable number of insulating layers may generally be employed. The conductive paths may be made of any suitable conductive material (e.g., copper). The conductive paths may be bounded by a pad material (e.g., an adhesive pad and / or a barrier pad) as appropriate. In certain embodiments, the package substrate may be a lower-density medium, while the semiconductor structure and / or the interposer may be a higher-density medium. As used herein, the terms "lower density" and "higher density" are relative terms indicating that the conductive paths (e.g., including conductive wires and conductive vias) in the lower-density medium are larger and / or have a greater pitch than those in the higher-density medium. For example, an improved semi-additive process or a semi-additive stacking process utilizing advanced lithography may be used to fabricate the higher-density medium (utilizing smaller vertical interconnect features formed by an advanced laser or lithography process), while the lower-density medium may be a PCB fabricated using a standard PCB process (e.g., a standard subtractive process using an etching chemistry to remove unwanted copper regions, and utilizing rough vertical interconnect features formed by a standard laser process).

[0047] IV. Decoupling Capacitor

[0048] As described above, at least one decoupling capacitor is electrically connected to the interposer and the circuit board (e.g., printed circuit board). The electrical connection between the decoupling capacitor and the interposer can be a direct connection (e.g., physical connection to the interposer) or an indirect connection (e.g., through a stacked package substrate). In any case, the decoupling capacitor generally includes a body that includes a plurality of alternating dielectric layers and a plurality of internal electrode layers. The plurality of internal electrode layers includes at least a first internal electrode layer and a second internal electrode layer. For example, the capacitor can include at least two sets (e.g., at least three sets, e.g., at least four sets) of internal electrode layers. Of course, it should be understood that the capacitor can include any number of sets of alternating dielectric layers and internal electrode layers and is not necessarily limited.

[0049] Generally, the capacitor includes an upper surface (e.g., a first surface) and a lower surface (e.g., a second surface) opposite the upper surface. The capacitor also includes at least one side surface (especially at least two side surfaces) extending between the upper surface and the lower surface. The capacitor can also include at least one end surface (especially at least two end surfaces) extending between the upper surface and the lower surface. The side surface can extend in the length (L) direction and have a dimension that is generally longer than the end surface, and these end surfaces extend in the width (W) direction and have a generally shorter dimension. In one embodiment, the capacitor can have a parallelepiped shape, such as a rectangular parallelepiped shape. The overall dimensions of the capacitor may depend on the specific application. However, the height or thickness of the capacitor is generally from about 10 micrometers (μm) to about 5000 μm, in some embodiments from about 20 μm to about 2500 μm, in some embodiments from about 50 μm to about 1500 μm, and in some embodiments from about 100 μm to about 1000 μm. When surrounded by a ball grid array, the height of the capacitor can be within 10% of the height (or diameter) of the balls of the ball grid array, e.g., within 7%, e.g., within 5%, e.g., within 3%, e.g., within 2%, e.g., within 1%. For example, such a height can be the original height before any reflow soldering. Similarly, the length of the capacitor in the "L" direction can be from about 50 μm to about 10000 μm, in some embodiments from about 100 μm to about 7500 μm, and in some embodiments from about 1000 μm to about 5000 μm, and the width of the capacitor in the "W" direction can be from about 25 μm to about 5000 μm, in some embodiments from about 50 μm to about 3500 μm, and in some embodiments from about 500 μm to about 2500 μm.

[0050] The first internal electrode layer and the second internal electrode layer may be interleaved in a relative and spaced-apart relationship, wherein a dielectric layer is located between each internal electrode layer. Each set of alternating dielectric layers and internal electrode layers may be spaced apart from an adjacent set by a certain distance. For example, the distance may be greater than the thickness of a single dielectric layer in the set, such as at least 2 times the thickness of the dielectric layer in the set, at least 3 times in some embodiments, at least 5 times in some embodiments, and at least 10 times in some embodiments. Each set of internal electrode layers and / or the entire capacitor may include from about 10 to about 4000 internal electrode layers, from about 50 to about 2000 internal electrode layers in some embodiments, and from about 100 to about 1000 internal electrode layers in some embodiments. The thickness of the dielectric layer and / or the internal electrode layer is not limited and may be any desired thickness depending on performance characteristics. For example, the thickness of the internal electrode layer and / or a single dielectric layer may range from about 100 nanometers (nm) to about 10 μm, from about 500 nm to about 8 μm in some embodiments, and from about 1 μm to about 5 μm in some embodiments. In certain embodiments, if the capacitor includes a second set of alternating dielectric layers and internal electrode layers, the distance between the first internal electrode layer of one set and the last internal electrode layer of the other set may be greater than the distance between adjacent internal electrode layers within a given set. For example, the distance between the first internal electrode layer of the first set and the last internal electrode layer of the second set may be greater than the distance between the first internal electrode layer and the second internal electrode layer of the first set.

[0051] Although not necessary, the dielectric region of the decoupling capacitor may also include one or more holes. In this regard, the dielectric region may be a region that includes dielectric material but does not include internal electrode material. The dielectric region may thus constitute a region that does not include alternately arranged dielectric layers and internal electrode layers. Thus, the dielectric region may include dielectric material between groups of alternately arranged dielectric layers and internal electrode layers along the "W" direction. Additionally, the dielectric region may include dielectric material between the lateral edges of each electrode in a given group of alternately arranged dielectric layers and internal electrode layers and an adjacent end surface in the longitudinal direction, e.g., as long as such internal electrode layers do not extend to the end surface such that these internal electrode layers are offset with respect to the end surface. It should be understood that although such a dielectric region may be formed from the green sheet of alternately arranged dielectric layers and internal electrode layers, such a region does not include any internal electrode material or corresponding layers. Thus, air holes may be provided within these regions. Additionally, the dielectric region may include dielectric material present between the first internal electrode layer of each group of the capacitor and an adjacent side surface. The dielectric region may also include dielectric material present between the last internal electrode layer of each group of the capacitor and an adjacent side surface. The dielectric region may also include dielectric material between the lateral edges of adjacent lead tabs extending from the body of the internal electrode layer. In a particular embodiment, the dielectric region may include the region within the capacitor that exists between two external terminals. Additionally, it should be understood that the dielectric region may include any combination of the above regions.

[0052] As indicated above, the dielectric region includes regions that include dielectric material but do not include internal electrode material. Thus, disregarding pores, the dielectric region can include 90 volume percent (vol.%) or more of dielectric material, such as 93 vol.% or more, such as 95 vol.% or more, such as 97 vol.% or more, such as 98 vol.% or more, such as 99 vol.% or more, such as 100 vol.%. Such pores can be void of any material, particularly any dielectric material or internal electrode material. In one embodiment, the pores can be (e.g., partially or completely) enclosed by the housing material. In one embodiment, the pores can be partially enclosed by the housing material. By partially enclosing, the housing material is only partially present around the interior of the pore such that the pore is partially separated from the dielectric material. In this regard, at least some outer edge of the pore can be in direct contact with the dielectric material of the dielectric region. In another embodiment, the pores can be thoroughly or completely enclosed by the housing material. By completely enclosing, the housing material is present around the interior of the pore such that the pore is completely separated from the dielectric material. In any case, the housing material can be utilized as a barrier layer between the interior of the pore and the dielectric material of the dielectric region. In one embodiment, the housing material can be a non-conductive material. However, it should be understood that in one embodiment, the pores can be unenclosed by the housing material, or even not partially enclosed by the housing material.

[0053] These holes can be provided without any barrier layer between the air holes and the dielectric material of the dielectric region. The air holes can have any shape and need not be restricted. For example, the shape can be a sphere, a cylinder, etc. In one embodiment, the shape can be a sphere. The maximum size of the air holes (e.g., length, width, diameter, etc.) can be from about 5 μm to about 5000 μm, in some embodiments from about 50 μm to about 2500 μm, and in some embodiments from about 100 μm to about 1000 μm. Any known technique (e.g., by printing a specific pattern in a green ceramic sheet and then laminating and firing the stacked laminate) can be used to form these holes. Alternatively, various drilling techniques can be used to form these holes so as to provide any desired shape within the dielectric material of the dielectric region. One or more vias (e.g., through vias) can also be used to present these holes. These vias can be unfilled with material (e.g., any conductive or non-conductive material) such that air exists inside. Additionally, in one embodiment, the vias can be arranged such that they exist only within the dielectric region. In this regard, the vias can be arranged such that they do not contact any internal electrode layer. In one embodiment, the vias can extend from the upper surface of the capacitor to the lower surface of the capacitor. In this regard, the vias can be columnar extending through the thickness of the capacitor. Thus, the vias can be through-conductive vias. In another embodiment, the vias can only partially extend through the thickness of the capacitor. For example, the vias can only partially extend through the capacitor thickness, such as from about 10% to about 90% of the capacitor thickness, and in some embodiments from about 20% to about 80%.

[0054] In addition to the alternating internal electrode layers and dielectric layers, the decoupling capacitor further includes a first external terminal and a second external terminal. The first external terminal is electrically connected to the first internal electrode layer and is provided on the first surface (e.g., the upper surface) of the capacitor. The second external terminal is electrically connected to the first internal electrode layer and is provided on the second surface (e.g., the lower surface) of the capacitor. Similarly, a third external terminal is electrically connected to the second internal electrode layer and is provided on the first surface of the capacitor, and a fourth external terminal is electrically connected to the second internal electrode layer and is provided on the second surface of the capacitor. Generally, the first external terminal and the second external terminal have the same polarity (e.g., positive), while the third external terminal and the fourth external terminal have the same polarity (e.g., negative). In any case, the first external terminal and the third external terminal of the decoupling capacitor are electrically connected to the intermediate layer, and the second external terminal and the fourth external terminal of the decoupling capacitor are electrically connected to the printed circuit board.

[0055] The capacitor may also include external terminals on opposite end surfaces. For example, one or more of the plurality of external terminals may extend from the first surface (e.g., the upper surface) and / or the second surface (e.g., the lower surface) to the end surface. When present on the end surface, the external terminal may be only partially present on the end surface such that the external terminal does not cover the entire end surface. In another embodiment, the capacitor may not include any external terminals on opposite end surfaces. In a particular embodiment, no external terminals may be present on the side surface of the capacitor. In any case, the external terminals generally include at least one first-polarity terminal and at least one second opposite-polarity terminal. The capacitor may include on the upper surface of the capacitor the following number of first-polarity terminals and / or second opposite-polarity terminals: at least one, e.g., at least two, e.g., at least four, e.g., at least six, e.g., at least eight. Additionally, the capacitor may include on the lower surface of the capacitor the above-mentioned number of terminals.

[0056] The capacitor may include an equal number of first-polarity terminals and / or second-polarity terminals on the upper surface and the lower surface of the capacitor. On the upper surface of the capacitor, the number of first-polarity terminals may be equal to the number of second opposite-polarity terminals. On the lower surface of the capacitor, the number of first-polarity terminals may be equal to the number of second opposite-polarity terminals. The total number of terminals present on the upper surface of the capacitor may be equal to the total number of terminals present on the lower surface of the capacitor. The total number of first-polarity terminals present on the upper and lower surfaces of the capacitor may be equal to the total number of second opposite-polarity terminals present on the upper and lower surfaces of the capacitor. Generally, the terminals of similar polarity corresponding to a particular set of alternating dielectric layers and internal electrode layers on the lower surface of the capacitor are electrically connected to the terminals of similar polarity on the upper surface of the capacitor. The terminals of similar polarity located on the upper and lower surfaces of the capacitor may not be staggered. In this regard, the corresponding terminals of similar polarity on the upper and lower surfaces may not be offset in terms of terminal position, but instead may be directly positioned above or below another terminal of similar polarity on the opposite upper or lower surface. In other words, the corresponding terminals of similar polarity (and especially the corresponding lead tabs of this set) corresponding to a particular set of alternating dielectric layers and internal electrode layers may be substantially aligned. Substantially aligned means that the offset of a lateral edge of the polarity terminal on the upper surface relative to the lateral edge is within + / - 10%, e.g., within + / - 5%, e.g., within + / - 4%, e.g., within + / - 3%, e.g., within + / - 2%, e.g., within + / - 1%, e.g., within + / - 0.5% of the offset of the corresponding polarity terminal on the lower surface relative to the lateral edge.

[0057] The pitch of the external terminals (i.e., the nominal distance between the respective centers, also referred to as the center-to-center pitch) can be determined by a specific circuit board configuration. The pitch between the external terminals in one direction (i.e., the x-direction or the y-direction) can be the same as the pitch between adjacent external terminals in the other direction (i.e., the y-direction or the x-direction, respectively). That is to say, the pitch between any two adjacent external terminals can be substantially the same as the pitch between any other two adjacent external terminals. For example, the pitch can range from about 0.1 millimeters (mm) to about 2 mm, in some embodiments from about 0.2 mm to about 1.5 mm, and in some embodiments from about 0.4 mm to about 1.4 mm.

[0058] If desired, the external terminals can be positioned in a configuration similar to that of a ball grid array. For example, external terminals can be provided to form the contacts typically employed in a ball grid array (especially a peripheral ball grid array). In this regard, the pitch of the external terminals can be the same as the pitch of the peripheral ball grid array. That is to say, the pitch can be within 10% of the pitch of the peripheral ball grid array, such as within 5%, such as within 2%, such as within 1%, such as within 0.5%, such as within 0.1%. Additionally, like a ball grid array, the external terminals can be arranged in multiple rows and multiple columns. That is to say, the external terminals can be arranged such that they are present in at least one row and at least two columns. For example, the external terminals can be presented in at least two rows, such as at least three rows, such as at least four rows. The number of rows can be determined by the number of different alternating dielectric layers and internal electrode layers. Additionally, the external terminals can be presented in at least two columns, such as at least three columns, such as at least four columns. The number of columns can be determined by the number of different columnar tabs of the internal electrodes.

[0059] The length of the external terminals extending along the upper surface (i.e., extending from one end surface to the other end surface in the longitudinal direction) can be the same as the length of the corresponding external terminals extending along the lower surface. For example, the length of the external terminals can be from about 0.3 mm to about 1.1 mm, in some embodiments from about 0.4 mm to about 1 mm, and in some embodiments from about 0.5 mm to about 0.9 mm. The length of the external terminals can also be less than the length of the capacitor, for example 50% or less, such as 40% or less, such as 30% or less, such as 25% or less, such as 20% or less, such as 15% or less of the length of the capacitor. If desired, each external terminal can have a different length. For example, the length of the external terminal adjacent to the end surface can be greater than the length of the external terminal deviated from the end surface. In this regard, the ratio of the length of the external terminal adjacent to the end surface to the length of the external terminal deviated from the end surface can be from about 0.3 to about 5, in some embodiments from about 0.5 to about 4, and in some embodiments from about 0.7 to about 3. On the upper surface and the lower surface, the width of the external terminals extending from one side surface to the opposite side surface can be the same. For example, the width can range from about 0.3 mm to about 1.1 mm, in some embodiments from about 0.4 mm to about 1 mm, and in some embodiments from about 0.5 mm to about 0.9 mm.

[0060] Reference Figure 4A and Figure 4B , more particularly, shows a specific embodiment of the decoupling capacitor 10 that can be used in the microelectronic component of the present invention. The capacitor 10 generally has, for example, the thickness "T", width "W", and length "L" as described above. In addition, as shown, the capacitor 10 has a 1×2 configuration because the capacitor includes two external terminals along one dimension of the upper surface and the lower surface. That is, the capacitor 10 includes a first external terminal 12 and a second external terminal 14 on the upper surface, and two respectively corresponding third external terminals and fourth external terminals (not shown) on the lower surface. The first external terminal 12 and the third external terminal (not shown) can have the same polarity (i.e., positive), and the second external terminal 14 and the fourth external terminal (not shown) can also have the same polarity (i.e., negative). The width "BW" and length "BL" of the external terminal 12 and / or the external terminal 14 can be within the above ranges. Although not necessary, as described above, a hole 1350 can also be formed between the terminal 12 and the terminal 14 in the capacitor 10.

[0061] As Figure 4BAs shown, capacitor 10 further includes a dielectric layer (not shown) and an internal electrode layer 110. That is, internal electrode layer 110 includes a first internal electrode layer 105 and a second set of internal electrode layers 115. In the particular embodiment shown, internal electrode layers 105, 115 include at least one lead tab 120, 130, 140, 150 extending from the top and bottom edges of the body of the internal electrode layer. The lead tabs 120, 130, 140, 150 of internal electrode layers 105, 115 may extend to the upper and lower surfaces of the capacitor and assist in forming external terminals. In this regard, lead tabs 120, 130, 140, 150 may be exposed on the upper and lower surfaces of the capacitor and allow connection between the body of the internal electrode layer and the external terminals. For example, lead tabs 120, 130, 140, 150 may include front edges 123, 133, 143, 153 that extend to the edge of the dielectric layer and allow formation of the external terminals. The length of lead tabs 120, 130, 140, 150 may vary as needed, but is typically from about 0.3 mm to about 1.2 mm, in some embodiments from about 0.4 mm to about 1.1 mm, and in some embodiments from about 0.5 mm to about 1 mm. When there is more than one lead tab along an edge, each lead tab may have the same length. In another embodiment, each lead tab may have a different length. For example, a lead tab that is generally aligned with the side edge of the internal electrode layer may have a greater length than a lead tab that is offset from the side edge of the internal electrode layer. In this regard, the ratio of the length of the lead tab that is aligned with the side edge of the internal electrode layer to the length of the lead tab that is offset from the side edge of the internal electrode layer may be from about 0.3 to about 5, in some embodiments from about 0.5 to about 4, and in some embodiments from about 0.7 to about 3. Generally aligned typically means that the offset of one lateral edge of the first lead tab and / or the second lead tab on the top edge from the side edge is within + / - 10%, such as within + / - 5%, such as within + / - 4%, such as within + / - 3%, such as within + / - 2%, such as within + / - 1%, such as within + / - 0.5% of the offset of the corresponding lateral edge of the first lead tab and / or the second lead tab on the bottom edge from the side edge.

[0062] As Figure 4BAs shown, the first internal electrode layer 105 includes a lead tab 120, 130 extending along the top edge 105c and the bottom edge 105d and from the body 135. The second internal electrode layer 115 includes a lead tab 140, 150 extending along the top edge and the bottom edge and from the body 145. The lead tabs 120, 130 on the top edge and the bottom edge of the first internal electrode layer 105 may be aligned in the vertical direction. That is, the lateral edges 121, 122 of the first lead tab 120 along the top edge 105c may be aligned with the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite to the top edge 105c. Additionally, such lateral edges 121, 131 may be aligned with the side edge 105a of the internal electrode layer 105. However, it should be understood that the two lateral edges 121, 122 of the first lead tab 120 along the top edge 105c may be aligned with the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite to the top edge 105c. In other words, the two lateral edges 122, 132 may be aligned and deviate from the side edges 105a and 105b by the same distance along the bottom edge 105d and the top edge 105c. Similarly, the lead tabs 140, 150 on the top edge and the bottom edge of the second internal electrode layer 115 may be aligned in the vertical direction. That is, the lateral edges 141, 142 of the first lead tab 140 along the top edge may be aligned with the lateral edges 151, 152 of the first lead tab 150 along the bottom edge opposite to the top edge. In one embodiment, the two lateral edges 141, 142 of the first lead tab 140 along the top edge may be aligned with the lateral edges 151, 152 of the first lead tab 150 along the bottom edge opposite to the top edge. The relationship between the respective lateral edges of the first lead tab on the top edge and the respective lateral edges of the first lead tab on the bottom edge as mentioned with respect to the internal electrode layer 105 may also apply to the internal electrode layer 115. With this arrangement, a gap may be formed between the lead tab 120 of the first internal electrode layer 105 and the lead tab 140 of the second internal electrode layer 115. Similarly, a gap may be formed between the lead tab 130 of the first internal electrode layer 105 and the lead tab 150 of the second internal electrode layer 115. The sizes of the respective corresponding gaps may be substantially the same.

[0063] The lead tabs 120 and 140 may be arranged in parallel with the lead tabs 130 and 150 respectively, extending from the internal electrode layers 105 and 115 such that the respective lead tabs extending from the alternating electrode layers 105 and 115 may be aligned in the corresponding columns. For example, the lead tabs 120 and 130 of the internal electrode layer 105 may be arranged in a corresponding stacked configuration, while the lead tabs 140 and 150 of the internal electrode layer 115 may be arranged in a corresponding stacked configuration.

[0064] It will be understood that the lead tab 120 is connected to the external terminal 12, and the lead tab 140 is connected to the external terminal 14. Accordingly, the corresponding lead tab 120 will be staggered with the corresponding lead tab 140 in a manner similar to the external terminal 12 and the external terminal 14. The staggered lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0065] The distance between each adjacent exposed lead tab of the internal electrode layer in a given column can be specifically designed to help ensure the guiding formation of each termination portion. The range of the distance between each exposed lead tab of the internal electrode layer in a given column can be, for example, from about 0.25 μm to about 10 μm, in some embodiments from about 0.5 μm to about 5 μm, and in some embodiments from about 1 μm to about 4 μm. Additionally, the distance between adjacent columnar stacks of each electrode tab can (but is not limited to) be at least twice as large as the distance between adjacent lead tabs in a given column to ensure that different termination portions do not connect together. In some embodiments, the distance between adjacent columnar stacks of the exposed metallization can be about four times (4x) the distance between each adjacent exposed electrode tab in a particular stack. However, this distance can vary according to the desired capacitance performance and circuit board configuration. For example, as determined based on the center point of each lead tab or based on the distance between adjacent lateral edges of each lead tab, the distance can be from about 0.1 mm to about 1.5 mm, in some embodiments from about 0.2 mm to about 1.3 mm, and in some embodiments from about 0.3 mm to about 1 mm. Additionally, such a distance can correspond to the spacing distance of the balls on a ball grid array.

[0066] In Figure 4A and Figure 4B the illustrated embodiment, the capacitor includes two external terminals that extend to the ends of the capacitor. However, this is not necessary. Referring to Figures 5A to 5C, for example, shows an embodiment of a capacitor 10, in which the first external terminal 12, the second external terminal 14, and the third and fourth external terminals (not shown) do not extend to the ends of the capacitor. In this particular embodiment, to facilitate this construction, the capacitor 10 includes internal electrode layers 110, which include a first internal electrode layer 105 and a second internal electrode layer 115. The first internal electrode layer 105 may extend to the upper surface of the capacitor 10, while the second internal electrode layer 115 extends to the lower surface of the capacitor. These extensions help to form the external terminals. In this regard, the internal electrode layers may be exposed on the upper and lower surfaces of the capacitor and allow connection between the main body of the internal electrode layer and the external terminals. For example, the internal electrode layers 105, 115 extend to the edges of the dielectric layer and allow the formation of external terminals. The lateral edges or side edges of the internal electrode layers 105, 115 may be aligned in the vertical direction. That is, the lateral edge of the first internal electrode layer 105 may be aligned with the lateral edge of the second internal electrode layer 115. In one embodiment, the two lateral edges may be aligned. In another embodiment, the contact point of the first internal electrode layer 105 with the external terminal may be aligned with the contact point of the second internal electrode layer 115 with the external terminal. Additionally, Figure 5A the capacitor 10 includes at least one first-polarity terminal and at least one second opposite-polarity terminal on the upper surface. Although not shown, the lower surface includes at least a first-polarity terminal and a second opposite terminal.

[0067] In Figure 4A and Figure 4B as well as Figures 5A to 5C the embodiment shown, the capacitor includes two external terminals on each surface. However, as indicated above, the present invention is not limited by the number of external terminals and / or the number of lead tabs extending from the top edge and / or the bottom edge. Referring to Figure 6A and Figure 6B, for example, the illustrated capacitor 20 has a 1×4 array configuration and thus includes four external terminals on each surface. That is, the capacitor includes four terminals along two dimensions of the upper and lower surfaces. In this regard, the capacitor includes a total of four external terminals on the upper surface (i.e., the first external terminals 22a and 22b and the second external terminals 24a and 24b), and a corresponding set of third and fourth external terminals (not shown) on the lower surface. The first external terminals 22a, 22b and the third external terminal (not shown) generally have the same polarity (i.e., the positive pole), while the second external terminals 24a, 24b and the fourth external terminal (not shown) generally also have the same polarity (i.e., the negative pole). The capacitor 20 generally also has, for example, the thickness "T", width "W" and length "L" described above, and the width "BW" and lengths "BLA" and "BLB" of the external terminals 22a, 22b and / or 24a, 24b can be within the above ranges. Although not necessary, holes 1350 can also be formed between the external terminals 22a, 24b, 22b, and / or 24a in the capacitor 20 as described above.

[0068] The capacitor 20 further includes internal electrode layers 210, which include first internal electrode layers 205 and second internal electrode layers 215 arranged alternately. The internal electrode layers 205, 215 include at least one lead tab 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b extending from the top and bottom edges of the main body of the internal electrode layer. The lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b of the internal electrode layers 205, 215 extend to the upper and lower surfaces of the capacitor and help form external terminals. In this regard, the lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b can be exposed on the upper and lower surfaces of the capacitor and allow connection between the main body of the internal electrode layer and the external terminals. For example, the lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b can include front edges 223a and 223b, 233a and 233b, 243a and 243b, 253a and 253b that extend to the edge of the dielectric layer and allow the formation of external terminals. The internal electrode layers 205, 215 include at least two lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b along the top and bottom edges. The first internal electrode layer 205 includes two lead tabs 220a and 220b, 230a and 230b that each extend along the top edge 205c and the bottom edge 205d and from the main body 235. The second internal electrode layer 215 includes two lead tabs 240a and 240b, 250a and 250b that each extend along the top and bottom edges and from the main body 245.

[0069] The lead tabs 220a and 220b, 230a and 230b on the top edge 205c and the bottom edge 205d of the first internal electrode layer 205 can be aligned in the vertical direction. That is, the lateral edges 221a, 222a of the first lead tab 220 along the top edge 205c can be aligned with the lateral edges 231a, 232a of the first lead tab 230 along the bottom edge 205d opposite to the top edge 205c. Additionally, such lateral edges 221a, 231a can be aligned with the side edge 205a of the internal electrode layer 205. However, it should be understood that the two lateral edges 221a, 222a of the first lead tab 220a along the top edge 205c can be aligned with the lateral edges 231a, 232a of the first lead tab 230a along the bottom edge 205d opposite to the top edge 205c. In other words, the two lateral edges 222a, 232a can deviate from the side edges 205a and 205b by the same distance along the bottom edge 205d and the top edge 205c. When the top edge 205c and the bottom edge 205d include at least two lead tabs 220a and 220b, 230a and 230b, at least one lateral edge of each lead tab on the top edge 205c can be aligned with the corresponding lateral edge of the lead tab on the bottom edge 205d. Moreover, the two lateral edges of each lead tab on the top edge 205c can be aligned with the corresponding lateral edges of the lead tabs on the bottom edge 205d. Similarly, the lead tabs 240a and 240b, 250a and 250b on the top edge and the bottom edge of the second internal electrode layer 215 can be aligned in the vertical direction. That is, the lateral edges 241a, 242a of the first lead tab 240 along the top edge can be aligned with the lateral edges 251a, 252a of the first lead tab 250 along the bottom edge opposite to the top edge.

[0070] The two lateral edges 241a, 242a of the first lead tab 240 along the top edge can be aligned with the lateral edges 251a, 252a of the first lead tab 250 along the bottom edge opposite the top edge. The relationship between the respective lateral edges of the first lead tab on the top edge and the respective lateral edges of the first lead tab on the bottom edge as mentioned with respect to the internal electrode layer 205 can also apply to the internal electrode layer 215. With this arrangement, a gap can be formed between the lead tabs along the top edge 205c of the first internal electrode layer 205, the lead tabs along the top edge of the second internal electrode layer 215, or any of the lead tabs in both. For example, a gap can be formed between any of the lead tabs 220a and 220b, 240a and 240b extending from the top edge of each internal electrode layer. Additionally, a gap can be formed between the lead tabs along the top edge 205d of the first internal electrode layer 205, the lead tabs along the top edge of the second internal electrode layer 215, or any of the lead tabs in both. For example, a gap can be formed between any of the lead tabs 230a and 220b, 250a and 250b extending from the top edge of each internal electrode layer. Furthermore, whether from the same internal electrode layer or from adjacent internal electrode layers, the size of the gap between two corresponding tabs extending from the top edge can be substantially the same as the size of the gap between the corresponding two tabs extending from the bottom edge. For example, the gap between the lead tabs 220a and 220b can be substantially the same as the gap between the lead tabs 230a and 230b. Similarly, the gap between the lead tabs 220a and 240a can be substantially the same as the gap between the lead tabs 230 and 250a.

[0071] Any one or all of the lead tabs 220a and 220b, 240a and 240b may be arranged parallel to the lead tabs 230a and 230b, 250a and 250b, respectively, extending from the layers 205 and 215 such that the leads extending from the alternating electrode layers 205 and 215 can be aligned in corresponding columns. For example, the lead tabs 220a and 220b and 230a and 230b of the internal electrode layer 205 may be arranged in corresponding stacked configurations, while the lead tabs 240a and 240b and 250a and 250b of the internal electrode layer 215 may be arranged in corresponding stacked configurations. It will be understood that the lead tabs 220a and 220b are connected to the external terminals 22a and 22b, respectively, while the lead tabs 240a and 240b are connected to the external terminals 24a and 24b, respectively. Thus, in a manner similar to the external terminals 22a and 22b and the external terminals 24a and 24b, the corresponding lead tabs 220a and 220b will be staggered with the corresponding lead tabs 240a and 240b, respectively. The staggered lead tabs may provide multiple adjacent current injection points on the associated main electrode portion.

[0072] In the embodiments discussed above, the external terminals are arranged in a single dimension in a linear manner (e.g., 1×2 or 1×4 configuration). Of course, it should be understood that a multi-dimensional array of external terminals may also be employed. Referring Figures 7A to 7D , for example, a particular embodiment of the capacitor 10 having a 2×2 array configuration is shown. In such a configuration, the capacitor includes a total of four external terminals (the first external terminal 12 and the second external terminal 14) on the upper surface, and a corresponding number of external terminals (the third external terminal and the fourth external terminal, not shown) on the lower surface. The first external terminal 12 and the third external terminal (not shown) generally have the same polarity (i.e., positive), while the second external terminal 14 and the fourth external terminal (not shown) generally also have the same polarity (i.e., negative). Although not necessary, as described above, a hole 1350 may also be formed between the external terminal 12 and the external terminal 14 in the capacitor 10.

[0073] The capacitor 10 includes alternating dielectric layers and internal electrode layers 110, and these internal electrode layers 110 include a first internal electrode layer 105 and a second internal electrode layer 115 arranged alternately. Similar to the embodiments discussed above in Figure 4A and Figure 4B , the internal electrode layers 105, 115 also include at least one lead tab 120, 130, 140, 150 extending from the top and bottom edges of the body of the internal electrode layer. However, compared with Figure 4A and Figure 4BContrary to the internal electrodes, the lateral edges 121, 122 of the first lead tab 120 along the top edge 105c can be aligned with the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite to the top edge 105c. In other words, the lateral edge 121 of the first lead tab 120 along the top edge 105c can be offset from the lateral edge 105a by the same distance (indicated by "O") as the lateral edge 131 of the first lead tab 130 along the bottom edge 105d opposite to the top edge 105c, and the lateral edge 122 of the first lead tab 120 along the top edge 105c can be offset from the lateral edge 105b by the same distance as the lateral edge 132 of the first lead tab 130 along the bottom edge 105d opposite to the top edge 105c. However, it should be understood that the two lateral edges 121, 122 of the first lead tab 120 along the top edge 105c can be aligned with the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite to the top edge 105c. In other words, the two lateral edges 121, 122 of the first lead tab 120 along the top edge 105c can be offset from the lateral edges 105a and 105b by the same distance as the two lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite to the top edge 105c.

[0074] Similarly, the lead tabs 140, 150 on the top and bottom edges of the second internal electrode layer 115 can be aligned in the vertical direction. That is, the lateral edges 141, 142 of the first lead tab 140 along the top edge can be aligned with the lateral edges 151, 152 of the first lead tab 150 along the bottom edge opposite to the top edge. In one embodiment, the two lateral edges 141, 142 of the first lead tab 140 along the top edge can be aligned with the lateral edges 151, 152 of the first lead tab 150 along the bottom edge opposite to the top edge. The relationship between the respective lateral edges of the first lead tab on the top edge and the respective lateral edges of the first lead tab on the bottom edge as mentioned with respect to the internal electrode layer 105 can also apply to the internal electrode layer 115. With this arrangement, a gap can be formed between the lead tab 120 of the first internal electrode layer 105 and the lead tab 140 of the second internal electrode layer 115. A gap can be formed between the lead tab 130 of the first internal electrode layer 105 and the lead tab 150 of the second internal electrode layer 115. The sizes of the respective corresponding gaps can be substantially the same.

[0075] The lead tabs 120 and 140 can be arranged parallel to the lead tabs 130 and 150 respectively, extending from the internal electrode layers 105 and 115, such that the respective lead tabs extending from the alternating electrode layers 105 and 115 can be aligned in corresponding columns. For example, the lead tabs 120 and 130 of the internal electrode layer 105 can be arranged in a corresponding stacked configuration, while the lead tabs 140 and 150 of the internal electrode layer 115 can be arranged in a corresponding stacked configuration. It will be understood that the lead tab 120 is connected to the external terminal 12, and the lead tab 140 is connected to the external terminal 14. Thus, each lead tab 120 will be staggered with the corresponding lead tab 140 in a manner similar to the external terminal 12 and the external terminal 14. The staggered lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0076] As Figure 7D shown, multiple sets 110a and 110b of internal electrode layers 110 can be used to form Figure 7A the external terminal array shown in. Generally, the distance "t" between the respective sets 110a and 110b is from about 0.2 μm to about 10 μm, in some embodiments from about 0.5 μm to about 8 μm, and in some embodiments from about 1 μm to about 5 μm. Additionally, the distance "t" can be (but is not limited to) at least 2 times greater than the distance between adjacent lead tabs in a given column, in some embodiments at least about 3 times, and in some embodiments from about 4 times to 8 times, to ensure that different termination portions do not become connected together.

[0077] Referring Figures 8A to 8D , an embodiment of a capacitor 20 having a 2×4 array configuration is shown. In this configuration, the capacitor includes a total of 8 external terminals (first external terminals 22a, 22b and second external terminals 24a, 24b) on the upper surface, and a corresponding number of external terminals (third external terminal and fourth external terminal, not shown) on the lower surface. The first external terminals 22a, 22b and the third external terminal (not shown) generally have the same polarity (i.e., positive), and the second external terminals 24a, 24b and the fourth external terminal (not shown) generally also have the same polarity (i.e., negative). Although not necessary, holes 1350 can also be formed between the external terminals 22a, 22b, 24a, and / or 24b in the capacitor 20 as described above.

[0078] As Figure 8D shown, the capacitor 20 further includes two sets 210a and 210b of alternating internal electrode layers 210. As Figure 8B and Figure 8CAs shown, each set of alternating dielectric layers and internal electrode layers 210 includes a first internal electrode layer 205 and a second internal electrode layer 215 arranged alternately. The internal electrode layers 205, 215 include at least one lead tab 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b extending from the top and bottom edges of the body of the internal electrode layer. The lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b of the internal electrode layers 205, 215 extend to the upper and lower surfaces of the capacitor and help form the external terminals. In this regard, the lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b can be exposed on the upper and lower surfaces of the capacitor and allow connection between the body of the internal electrode layer and the external terminals. For example, the lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b can include front edges 223a and 223b, 233a and 233b, 243a and 243b, 253a and 253b that extend to the edges of the dielectric layer and allow the formation of the external terminals. The internal electrode layers 205, 215 include at least two lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b along the top and bottom edges. The first internal electrode layer 205 includes two lead tabs 220a and 220b, 230a and 230b that extend respectively along the top edge 205c and the bottom edge 205d and from the body 235. The second internal electrode layer 215 includes two lead tabs 240a and 240b, 250a and 250b that extend respectively along the top and bottom edges and from the body 245.

[0079] The lead tabs 220a and 220b, 230a and 230b on the top edge 205c and the bottom edge 205d of the first internal electrode layer 205 can be aligned in the vertical direction. That is, the lateral edges 221a, 222a of the first lead tab 220 along the top edge 205c can be aligned with the lateral edges 231a, 232a of the first lead tab 230 along the bottom edge 205d opposite to the top edge 205c. In other words, the lateral edge 221a of the first lead tab 220 along the top edge 205c can deviate from the side edge 205a by the same distance (indicated by "O") as the lateral edge 231a of the first lead tab 230 along the bottom edge 205d opposite to the top edge 205c, and the lateral edge 222a of the first lead tab 220 along the top edge 205c can deviate from the side edge 205b by the same distance as the lateral edge 232a of the first lead tab 230 along the bottom edge 205d opposite to the top edge 205c. In addition, the two lateral edges 221a, 222a of the first lead tab 220 along the top edge 205c can be aligned with the lateral edges 231a, 232a of the first lead tab 230 along the bottom edge 205d opposite to the top edge 205c. That is, the two lateral edges can deviate from the side edges 205a and 205b by the same distance. When the top edge 205c and the bottom edge 205d include at least two lead tabs 220a and 220b, 230a and 230b, at least one lateral edge of each lead tab on the top edge 205c can be aligned with the corresponding lateral edge of the lead tab on the bottom edge 205d. In addition, the two lateral edges of each lead tab on the top edge 205c can be aligned with the corresponding lateral edges of the lead tab on the bottom edge 205d.

[0080] Similarly, the lead tabs 240a and 240b, 250a and 250b on the top and bottom edges of the second internal electrode layer 215 can be aligned in the vertical direction. That is, the lateral edges 241a, 242a of the first lead tab 240 along the top edge can be aligned with the lateral edges 251a, 252a of the first lead tab 250 along the bottom edge opposite the top edge. The two lateral edges 241a, 242a of the first lead tab 240 along the top edge can be aligned with the lateral edges 251a, 252a of the first lead tab 250 along the bottom edge opposite the top edge. The relationship between the respective lateral edges of the first lead tab on the top edge and the respective lateral edges of the first lead tab on the bottom edge as mentioned for the internal electrode layer 205 can also apply to the internal electrode layer 215. With this arrangement, a gap can be formed between the lead tabs along the top edge 205c of the first internal electrode layer 205, the lead tabs along the top edge of the second internal electrode layer 215, or any of the lead tabs in both. For example, a gap can be formed between any of the lead tabs 220a and 220b, 240a and 240b extending from the top edge of the respective internal electrode layer. Additionally, a gap can be formed between the lead tabs along the top edge 205d of the first internal electrode layer 205, the lead tabs along the top edge of the second internal electrode layer 215, or any of the lead tabs in both. For example, a gap can be formed between any of the lead tabs 230a and 220b, 250a and 250b extending from the top edge of the respective internal electrode layer. Furthermore, the size of the gap between two corresponding tabs extending from the top edge, whether from the same internal electrode layer or from adjacent internal electrode layers, can be substantially the same as the size of the gap between the corresponding two tabs extending from the bottom edge. For example, the gap between the lead tabs 220a and 220b can be substantially the same as the gap between the lead tabs 230a and 230b. Similarly, the gap between the lead tabs 220a and 240a can be substantially the same as the gap between the lead tabs 230 and 250a.

[0081] Any one or all of the lead tabs 220a and 220b, 240a and 240b may be arranged parallel to the lead tabs 230a and 230b, 250a and 250b, respectively, extending from the respective layers 205 and 215 such that the leads extending from the alternating electrode layers 205 and 215 may be aligned in corresponding columns. For example, the lead tabs 220a and 220b and 230a and 230b of the internal electrode layer 205 may be arranged in corresponding stacked configurations, while the lead tabs 240a and 240b and 250a and 250b of the internal electrode layer 215 may be arranged in corresponding stacked configurations. It will be understood that the lead tabs 220a and 220b are connected to the external terminals 22a and 22b, respectively, while the lead tabs 240a and 240b are connected to the external terminals 24a and 24b, respectively. Thus, in a manner similar to the external terminals 22a and 22b and the external terminals 24a and 24b, the corresponding lead tabs 220a and 220b will be staggered with the corresponding lead tabs 240a and 240b, respectively. The staggered lead tabs may provide multiple adjacent current injection points on the associated main electrode portion.

[0082] As Figure 8D shown, multiple sets 210a and 210b of the internal electrode layers 110 may be used to form Figure 8A the external terminal array shown in. Generally, the distance "t" between the respective sets 110a and 110b is from about 0.2 μm to about 10 μm, in some embodiments from about 0.5 μm to about 8 μm, and in some embodiments from about 1 μm to about 5 μm. Additionally, the distance "t" may be (but is not limited to) at least 2 times greater than the distance between adjacent lead tabs in a given column, in some embodiments at least about 3 times greater, and in some embodiments from about 4 times to about 8 times greater, to ensure that different terminations do not become connected together.

[0083] Referring Figure 9A to Figure 9B and Figure 9BAs shown, the capacitor 30 further includes internal electrode layers 210 arranged in four groups 210a, 210b, 210c, and 210d. Similar to the embodiments discussed above, the distance "t" 1 ", "t" 2 ", and / or "t" 3 " can range from about 0.2 μm to about 10 μm, in some embodiments from about 0.5 μm to about 8 μm, and in some embodiments from about 1 μm to about 5 μm. Additionally, the distances "t" 1 ", "t" 2 ", and / or "t" 3 " can be (but are not limited to) at least 2 times greater than the distance between adjacent lead tabs in a given column, in some embodiments at least about 3 times, and in embodiments from about 4 times to about 8 times, to ensure that different terminations do not connect together.

[0084] In the embodiments referenced above, the internal electrode layers are typically oriented in a vertical configuration. Of course, this is not necessary, and other geometric configurations, such as a horizontal configuration, are equally suitable. Referring Figures 10A to 10C , for example, a capacitor 20 having a 4×4 configuration with external terminals 32 and external terminals 34 similar to Figure 9A and Figure 9B is shown, but this capacitor 20 employs a horizontal internal electrode configuration. That is, as Figure 10B and Figure 10C shown, the capacitor 20 includes a plurality of internal electrode layers 205 and 215 arranged alternately and a plurality of dielectric layers, wherein the electrode layers and the dielectric layers located between each adjacent electrode layer are interleaved in a relative and spaced-apart relationship. The internal electrode layers are electrically connected to the external terminals through conductive vias (e.g., a first conductive via 225 and a second conductive via 285). The conductive vias extend to the upper surface 235 and the lower surface 245 of the capacitor. In this regard, the conductive vias can be exposed on the upper surface 235 and the lower surface 245 of the capacitor. The exposure can help form the external terminals on the upper surface 235 and the lower surface 245 of the capacitor. Additionally, the internal electrode layers 205 and 215 have a rectangular configuration and are arranged such that these internal electrode layers do not extend to the side surfaces of the capacitor.

[0085] If desired, the capacitor 20 can further include a first shielding region 255 and a second shielding region 265, and each of these shielding regions can include one or more shielding electrode layers 275. As shown, the shielding regions are disposed above and below the active electrode region and the active electrode layers 205, 215. Similarly, Figure 10CThe use of a first anchor electrode 305 and a second anchor electrode 295 is shown. The first anchor electrode 305 is provided in the first active electrode layer 205 together with the first active electrode. In this regard, the first active electrode is electrically connected to the first conductive via 225, while the first anchor electrode is connected to the second conductive via 285. Similarly, the second anchor electrode 295 is provided in the second active electrode layer 215 together with the second active electrode. In this regard, the second active electrode is electrically connected to the second conductive via 285, while the second anchor electrode is connected to the first conductive via 225.

[0086] The first conductive via 225 extends through the first plurality of internal electrode layers 205 and makes electrical contact with the first plurality of internal electrode layers 205. However, the first conductive via 225 extends through the non-contact hole 105, where a gap 105 is formed between the first conductive via 225 and the electrodes of the second plurality of internal electrode layers 215. Such a gap 105 allows the second plurality of internal electrode layers 215 to be isolated from the first conductive via 225. Similarly, the second conductive via 285 extends through the second plurality of internal electrode layers 215 and makes electrical contact with the second plurality of internal electrode layers 215. However, the second conductive via 285 extends through the non-contact hole 115, where a gap 115 is formed between the second conductive via 285 and the electrodes of the first plurality of internal electrode layers 205. Such a gap 115 allows the first plurality of internal electrode layers 205 to be isolated from the second conductive via 285. When presenting the anchor (or dummy) electrodes as shown Figure 10C such a layer further includes gaps 125 and 135. The first conductive via 225 extends through the first plurality of internal electrode layers 205 and makes electrical contact with the first plurality of internal electrode layers 205, and makes contact with the second anchor tab 295. However, the second anchor tab 295 is isolated from the active electrode of the second plurality of internal electrode layers 215 via a gap 125 formed between the anchor tab 295 and the active electrode 215. Such a gap 125 allows the second plurality of internal electrode layers 215 to be isolated from the second anchor tab 295 and the first conductive via 225.

[0087] The dielectric layer of the decoupling capacitor described herein is typically formed of a ceramic material. The ceramic material may have a relatively high dielectric constant. For example, the dielectric constant may be 3 or greater, in some embodiments from about 10 to about 20,000, in some embodiments from about 50 to about 10,000, in some embodiments from about 60 to about 9,000, and in some embodiments from about 80 to about 8,000. Particularly suitable examples of ceramic materials having a high dielectric constant are those designated as NPO (COG) (up to about 100), X7R (from about 3,000 to about 7,000), X7S, Z5U, and / or Y5V according to the standard classification established by the Electronic Industries Alliance (EIA). Such materials may include perovskites, such as barium titanate ceramic materials (e.g., barium titanate, barium strontium titanate, barium calcium titanate, barium zirconate titanate, strontium barium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate ceramic materials (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), and sodium bismuth titanate, etc. In one particular embodiment, for example, barium strontium titanate (“BSTO”) having the chemical formula Ba x Sr 1-x TiO 3 may be used, where x ranges from 0 to 1, in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. Other suitable barium titanate ceramic materials may include, for example, Ba x Ca 1-x TiO 3 , where x ranges from about 0.2 to about 0.8, and in some embodiments from about 0.4 to about 0.6; barium calcium zirconium titanate (BaCaZrTiO 3 ); A[B1 1 / 3 B2 2 / 3 O 3 materials, where A is Ba x Sr 1-x (x may be a value from 0 to 1), B1 is Mg y Zn 1-y (y may be a value from 0 to 1), and B2 is Ta z Nb 1-z (z may be a value from 0 to 1); etc. Other suitable ceramic materials may include, for example, Pb x Zr 1-x TiO 3 (“PZT”), where x ranges from about 0.05 to about 0.4; lead lanthanum zirconium titanate (“PLZT”); lead titanate (PbTiO 3 ); etc.

[0088] The internal electrode layer can be formed of any one of a variety of different metals known in the art. The internal electrode layer can be made of a metal (e.g., a conductive metal). These materials can include noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and the like, as well as various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloy, as well as respective sputtered layers of chromium, nickel, and gold, may also be suitable. In a particular embodiment, the internal electrode layer can include nickel or an alloy thereof. Similarly, the external terminal can be formed of any one of a variety of different metals known in the art. The external terminal can be made of a metal (e.g., a conductive metal). These materials can include noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and the like, as well as various combinations thereof. In a particular embodiment, the external terminal can include copper or an alloy thereof. The average thickness of the external terminal can be about 100 μm or less, in some embodiments from about 1 μm to about 70 μm, and in some embodiments from about 5 μm to about 50 μm.

[0089] Any method known in the art can be used to form the external terminal. The external terminal can be formed using techniques such as sputtering, painting, printing, electroless plating, or fine copper termination (FCT), electroplating, plasma deposition, propellant spray / airbrushing, etc. The external terminal can be formed such that it is a thin film plating of a metal. Such a thin film plating can be formed by depositing a conductive material (e.g., a conductive metal) on the exposed portion of the internal electrode layer. For example, the front edge of the internal electrode layer can be exposed such that the front edge can allow the formation of a plated terminal. The plated terminal can be formed by techniques known in the art, such as electroless plating, electroplating, or a combination thereof. When the external terminal is formed using multiple layers, the external terminal can include an electroplated layer and an electroless plated layer. For example, electroless plating can be first used to deposit an initial material layer. Then the plating technique can be switched to an electroplating system, which can allow for faster material buildup. When forming the plated terminal using either plating method, the front edge of the lead tab of the internal electrode layer that is exposed from the body of the capacitor is subjected to the plating solution. In one embodiment, by being subjected, the capacitor can be immersed in the plating solution.

[0090] The plating solution used in the electroplating process may include a conductive material, such as a conductive metal. For example, the plating solution may be a nickel sulfamate bath solution or other nickel solution, such that the plating layer and the external terminals include nickel. Alternatively, the plating solution may be a copper acid bath or other suitable copper solution, such that the plating layer and the external terminals include copper. Additionally, it should be understood that the plating solution may include other additives known in the art. For example, the additives may include other organic additives and media that can assist in the plating process. Additionally, additives may be used to maintain the plating solution at a desired pH level. In one embodiment, a resistance-reducing additive may be employed in the solution to aid in complete plating coverage and bonding of the plating material to the exposed leading edges of the lead tabs of the capacitor and the internal electrode layer. The capacitor may be exposed, submerged, or immersed in the plating solution for a predetermined amount of time. The exposure time need not be limited, but may be for a sufficient amount of time to allow deposition of sufficient plating material to form the plated terminals. In this regard, the time should be sufficient to allow formation of a continuous connection between the desired exposed adjacent leading edges of the lead tabs of the corresponding internal electrode layers within a set of alternating dielectric layers and internal electrode layers.

[0091] The difference between electroplating and electroless plating is that electroplating (e.g., by using an external power source) employs an electrical bias. The electroplating solution can typically withstand a high current density range, e.g., ten to fifteen amperes per square foot (amp / ft 2 )(rated voltage of 9.4 volts). The connection can be formed by connecting the negative pole of the capacitor that needs to form the plated terminals and the positive pole of a solid material (e.g., copper in a copper plating solution) in the same plating solution. That is, the capacitor is biased to a polarity opposite to that of the plating solution. Using this method, the conductive material of the plating solution is attracted to the metal of the exposed leading edge of the lead tab of the internal electrode layer.

[0092] Before submerging the capacitor into the plating solution or subjecting the capacitor to the plating solution, various pretreatment steps may be employed. These steps may be carried out for various purposes, including catalyzing, accelerating, and / or improving the adhesion of the plating material to the leading edge of the lead tab. Additionally, an initial cleaning step may be employed before plating or any other pretreatment step. This step may be used to remove any oxide buildup formed on the exposed lead tabs of the internal electrode layer. When the internal electrode or other conductive element is formed of nickel, this cleaning step can be particularly helpful in assisting in the removal of any buildup of nickel oxide. Component cleaning can be achieved by complete immersion in a pre-cleaning bath (e.g., a bath including an acidic cleaner). In one embodiment, the exposure may be for a predetermined time, e.g., on the order of about 10 minutes. Cleaning may alternatively be achieved by a chemical polishing or harperizing step.

[0093] Additionally, a step of activating the exposed metal front edge of the lead tab of the internal electrode layer can be performed to facilitate the deposition of the conductive material. Activation can be achieved by immersion in a palladium salt, (through a mask or laser) photo-patterning of a palladium organometallic precursor, screen printing or inkjet deposition of a palladium compound, or electrophoretic palladium deposition. It should be recognized that currently only palladium-based activation is disclosed as an example of an activation scheme, which generally works well in conjunction with the activation of the exposed tab portion formed of nickel or its alloy. However, it should be understood that other activation schemes can also be used and thus need not be limited. Additionally, instead of or in addition to the foregoing activation step, when forming the internal electrode layer of the capacitor, an activation dopant can be introduced into the conductive material. For example, when the internal electrode layer comprises nickel and the activation dopant comprises palladium, the palladium dopant can be introduced into the nickel ink or composition forming the internal electrode layer. Doing so can eliminate the palladium activation step. It should also be recognized that some of the above activation methods (such as organometallic precursors) also contribute to the co-deposition of glass formers to increase adhesion to the general ceramic body of the capacitor. When the activation step is taken as described above, trace amounts of activator material may often remain at the exposed conductive portions before and after termination plating. Additionally, post-treatment steps after plating can also be employed as needed or necessary. These steps can be performed for various purposes, including enhancing and / or improving the adhesion of the materials. For example, a heating (or annealing) step can be employed after performing the plating step. Such heating can be carried out by baking, laser irradiation, ultraviolet exposure, microwave exposure, arc welding, etc.

[0094] Thus, as described above, the external terminals used in the capacitor can include at least one plating layer. In one embodiment, the external terminal can include only one plating layer. However, it should be understood that the external terminal can include multiple plating layers. For example, the external terminal can include a first plating layer and a second plating layer. Additionally, the external terminal can further include a third plating layer. Moreover, the materials of these plating layers can be any of those described above and well-known in the art. For example, one plating layer (e.g., the first plating layer) can include copper or its alloy. Another plating layer (e.g., the second plating layer) can include nickel or its alloy. Alternatively, another plating layer (e.g., the second plating layer) can include copper or its alloy. Another plating layer (e.g., the third plating layer) can include tin, lead, gold, or a combination (e.g., alloy). Alternatively, the initial plating layer can include nickel, followed by a plating layer of tin or gold. In another embodiment, an initial plating layer of copper can be formed, followed by a nickel layer.

[0095] In one embodiment, the initial or first plating layer may be a conductive metal (e.g., copper). The area may then be covered with a second layer comprising a resistive polymeric material for sealing. The area may then be polished to selectively remove the resistive polymeric material and then plated again with a third layer comprising a conductive metal material (e.g., copper). The aforementioned second layer above the initial plating layer may correspond to a solder mask layer, such as a nickel solder mask layer. In some embodiments, the aforementioned layer may be formed by electroplating an additional metal (e.g., nickel or copper) layer on top of an initially electrolessly or electrolytically plated layer (e.g., plated copper). Other exemplary layer materials for the solder mask layer include nickel-phosphorus, gold, and silver. In some embodiments, the third layer on the solder mask layer may correspond to a conductive layer, such as plated nickel (Ni), nickel / chromium (Ni / Cr), silver (Ag), palladium (Pd), tin (Sn), lead / tin (Pb / Sn), or other suitable plated solder. Additionally, a layer of metal plating may be formed and then an electroplating step may be performed to provide a resistive alloy or a higher-resistance metal alloy coating on such metal plating, such as electroless Ni-P alloy. However, it should be understood that any metal coating may be included, as would be understood by one of ordinary skill in the art from the entire disclosure herein. It should be recognized that any of the aforementioned steps may be performed as a batch processing operation, such as barrel plating, fluidized bed plating, and / or flow-through plating termination processes, all of which are well known in the art. Such batch processing operations are capable of processing multiple components at once, thereby providing an efficient and rapid termination process. This is a particular advantage over traditional termination methods (e.g., printing of thick film terminals that require individual component processing).

[0096] V. Microelectronic Component

[0097] Semiconductor structures, interposers, optional package substrates, and decoupling capacitors can generally be arranged on a circuit board in a variety of different configurations. For example, referring to Figure 1, shows an embodiment of a microelectronic component 600 that includes semiconductor structures 610, 620, and 630 electrically connected to an interposer 650 and a package substrate 680 electrically connected to the interposer. The semiconductor structures can be any type of structure as described above. For example, in one embodiment, structures 610 and 630 can be high-bandwidth memory structures, field-programmable gate arrays. As shown, semiconductor structures 610, 620, and 630 can be electrically connected to the interposer 650 via first-level coupling components 611, 621, and 631, respectively. In the illustrated embodiment, coupling component 621 can be a solder ball or solder bump, while coupling components 611 and 631 can be conductive adhesives or underfill materials. Although not required, an overmold material 760 can also be employed. The overmold material can be, for example, the insulation material described above (e.g., an epoxy resin material). Similarly, the interposer 650 includes conductive paths 652 formed within an insulating dielectric material 654. The conductive paths 652 allow the interposer 650 to be electrically connected to the package substrate 680 via second-level coupling components 656 (e.g., solder balls or solder bumps). Similarly, the package substrate 680 includes conductive paths 682 (e.g., vias) within an insulating dielectric material 684. The conductive paths 682 allow the package substrate 680 to be electrically connected to a circuit board 800 (e.g., a printed circuit board) via third-level coupling components 704 (e.g., solder balls).

[0098] It should be noted that decoupling capacitor 10 (e.g., see Figure 4A and Figure 4B) is also located between at least a portion of the encapsulation substrate 680 and the circuit board 800. Although only one capacitor is shown, it should of course be understood that multiple decoupling capacitors may be employed between the encapsulation substrate 680 and the circuit board 800. The external terminals of one or more decoupling capacitors may be in electrical communication with corresponding current paths of the circuit board and may be connected to the circuit board using any method known in the art. For example, the decoupling capacitor 10 may be directly electrically connected to the encapsulation substrate 680 and the circuit board 800, or at least a coupling component 702 (e.g., a solder bump or solder ball) may be employed instead of the solder ball 704, and the coupling component 702 is smaller in size than the coupling component 704. The capacitor 10 may permit an alternating current (AC) signal to pass through or be transmitted while generally blocking a direct current (DC) signal. That is, the capacitor may be used to block low-frequency signals and transmit high-frequency signals. Additionally, by arranging the capacitor 10 in the manner shown, certain conductive paths directly above the capacitor may be eliminated, thereby further improving performance. Using the decoupling capacitor in this manner may also significantly reduce inductance. Specifically, minimizing the distance or path of the ground connection may help reduce inductance. For example, the inductance generated by using the decoupling capacitor may be about 1 nanohenry or less, in some embodiments from about 25 femtohenry to about 900 picohenry, in some embodiments from about 100 femtohenry to about 500 picohenry, and in some embodiments from about 250 femtohenry to about 100 picohenry. The decoupling capacitor may also exhibit a low equivalent series resistance, which is, for example, about 100 milliohms (mOhm) or less, in some embodiments from about 0.01 mOhm to about 50 mOhm, in some embodiments from about 0.1 mOhm to about 40 mOhm, and in some embodiments from about 0.5 mOhm to about 30 mOhm. A low inductance and / or a low equivalent series resistance may be achieved while still exhibiting a customized capacitance value, which is, for example, from about 1 picofarad (pF) to about 1000 microfarads (μF), in some embodiments from about 500 pF to about 500 μF, and in some embodiments from about 1 μF to about 100 μF.

[0099] In Figure 1 the illustrated embodiment, the interposer 650 is generally considered a “passive” interposer because the interposer does not include any integrated electronic components. However, it should be understood that an “active” interposer may also be suitably used in the microelectronic assemblies of the present invention. For example, referring to Figure 2, shows an embodiment of a microelectronic component 100 that includes semiconductor structures 114-3, 114-1, and 114-2 electrically connected to an interposer 102 and a package substrate 104 electrically connected to the interposer 102. In the illustrated embodiment, a bridge 110 is also embedded in the interposer 102. More specifically, the interposer 102 may have a first surface 170-1 and an opposite second surface 170-2, and the surface of the bridge 110 may be flush with the second surface 170-2 of the interposer 102. The bridge 110 may include a substrate 111a and one or more routing layers 111b having high-density conductive paths 118 (e.g., traces and / or vias) through an insulating material (e.g., a dielectric material formed in multiple layers), and the conductive paths 118 are for routing electrical signals between dies 114-1 and 114-2. The bridge 110 may be made of any suitable material. For example, in some embodiments, the insulating material may be a semiconductor material (e.g., silicon or germanium), a III-V material (e.g., gallium nitride), silicon oxide, or glass. Although not required, the bridge 110 may include one or more integrated electronic components 112 (e.g., resistors and / or capacitors). The bridge 110 may include multiple integrated electronic components 112 disposed at different distances from the surface of the bridge 110 (i.e., in the z-direction) and at different lateral positions in the bridge 110 (e.g., in the x-direction). The bridge 110 may also include conductive paths 115 and 118 through the insulating material that couple the integrated electronic components 112 to the semiconductor structures 114-3, 114-1, and 114-2. As shown, the semiconductor structures may be coupled to the second surface 170-2 of the interposer 102 via first-stage conductive paths 108-1, 108-2, 108-3. The interposer 102 may also include conductive paths 119 to electrically connect the semiconductor structures 114-3, 114-1, and 114-2 to the package substrate 104 (e.g., via first-stage interconnects 108-3, 108-1, 108-2 and second-stage interconnects 109). As needed, any suitable arrangement of the conductive paths 119 may couple the semiconductor structures to each other (e.g., conductive path 117 couples structure 114-1 to structure 114-3) and couple these structures to the substrate 104. Although not explicitly shown herein, the package substrate 104 is also connected to a circuit board and decoupling capacitors in a manner such as described above.

[0100] Figure 3Another embodiment of a microelectronic component 800 including an active interposer 802 is also shown. In this embodiment, the interposer 802 is directly connected to a circuit board 832, and a semiconductor structure 310 (e.g., a coprocessor) is electrically connected to the interposer 802. The semiconductor structure 310 may include an active layer 392 and a bulk semiconductor layer 390 (sometimes referred to herein as a non-active layer 390). The active layer 392 may include circuit elements and a register file 394, and the register file may act as on-chip memory for the structure 310. Similarly, the active interposer 802 may include an active layer 806 and a bulk semiconductor layer 804 (sometimes referred to as a non-active layer 804). The active layer 806 may include a plurality of level one (L1) storage elements 808 formed on the active side and usable as a memory cache, and these L1 storage elements are used to store configuration bitstreams for configuring logical sectors in the structure 310. The active interposer 802 may be electrically connected to the circuit board 832 through coupling components 822 (e.g., solder bumps or solder balls), and the non-active layer 804 may include through-silicon vias (TSVs) 810, and these TSVs may connect components (e.g., the L1 storage elements 808 in the active layer 806) to the coupling components 822. The active layer 806 may face the active layer 392 of the semiconductor structure 310 and may be electrically connected to components in the active layer 392 through coupling components 820 (e.g., solder bumps).

[0101] If desired, an additional semiconductor structure 812 (e.g., an auxiliary chip) may be directly electrically connected to the circuit board 832. The structure 812 may include an active layer 816 and a bulk semiconductor layer 814 (sometimes referred to as a non-active layer 814). The active layer 816 may include level two (L2) storage elements 809 formed on the active side and usable as a memory cache, and these L2 storage elements are used to store configuration bitstreams. For example, the configuration bitstreams stored in the L1 storage elements 808 on the interposer 802 may be transmitted to the L2 storage elements 809 to make room on the L1 storage elements 808 for newly incoming configuration bitstreams (e.g., from a host processor received at the L1 storage elements 808). The active layer 816 may face the package substrate 832 and may be electrically connected to the package substrate 832 through coupling components 822 and 824 (e.g., solder balls or solder bumps). A bridge 826 may also be used to connect the semiconductor structure 812 to the interposer 802. The bridge 826 may include an interconnect 828 formed in a silicon substrate, and the silicon substrate is embedded in the circuit board 832. The interconnect 828 may electrically connect the portion of the coupling component 824 connected to the semiconductor structure 812 to the portion of the coupling component 824 connected to the interposer 802. As is known in the art, a heat sink 830 may also be placed in contact with the semiconductor structures 310 and 812.

[0102] It should be noted that the decoupling capacitor 20 (for example, see Figure 6A and Figure 6B ) is also located between at least a portion of the interposer 802 and the circuit board 832. Although only one capacitor is shown, it should of course be understood that multiple decoupling capacitors may be employed between the interposer 802 and the circuit board 832. The external terminals of one or more decoupling capacitors may be in electrical communication with the corresponding current paths of the circuit board and may be connected to the circuit board using any method known in the art. For example, the decoupling capacitor 20 may be directly electrically connected to the interposer 802 and the circuit board 832, or at least coupling components 205 (such as solder bumps or solder balls) rather than solder balls 822 may be employed, and these coupling components are smaller in size than the coupling components 822.

[0103] Those of ordinary skill in the art may practice these and other modifications and variations of the present invention without departing from the spirit and scope of the present invention. Additionally, it should be understood that aspects of the various embodiments may be interchanged in whole or in part. Furthermore, those of ordinary skill in the art will understand that the foregoing description is by way of example only and is not intended to limit the present invention as further described in the appended claims.

Claims

1. A microelectronic component, the microelectronic component comprises: a semiconductor structure; an interposer, the interposer being electrically connected to the semiconductor structure and containing semiconductor material; a decoupling capacitor, the decoupling capacitor having a first surface and an opposite second surface, wherein the decoupling capacitor comprises a plurality of alternating dielectric layers and a plurality of internal electrode layers, the plurality of internal electrode layers comprising a first internal electrode layer and a second internal electrode layer, wherein the capacitor further comprises a first external terminal, a second external terminal, a third external terminal and a fourth external terminal, the first external terminal being electrically connected to the first internal electrode layer and disposed on the first surface of the capacitor, the second external terminal being electrically connected to the first internal electrode layer and disposed on the second surface of the capacitor, the third external terminal being electrically connected to the second internal electrode layer and disposed on the first surface of the capacitor, the fourth external terminal being electrically connected to the second internal electrode layer and disposed on the second surface of the capacitor, wherein the first external terminal and the third external terminal are electrically connected to the package substrate; and a circuit board, wherein the second external terminal and the fourth external terminal of the decoupling capacitor are electrically connected to the circuit board.

2. The microelectronic component according to claim 1, wherein, the semiconductor structure is an integrated circuit device.

3. The microelectronic component according to claim 2, wherein, the integrated circuit device comprises a memory device, a logic device, a processor device or a combination thereof.

4. The microelectronic component according to claim 1, wherein, the component comprises a plurality of semiconductor structures.

5. The microelectronic component according to claim 4, wherein, the plurality of semiconductor structures are arranged in an array.

6. The microelectronic component according to claim 4, wherein, the plurality of semiconductor structures are stacked.

7. The microelectronic component according to claim 1, wherein, the semiconductor structure is electrically connected to the interposer via one or more coupling components.

8. The microelectronic component according to claim 1, wherein, one or more conductive paths are formed through the semiconductor material of the interposer.

9. The microelectronic component according to claim 8, wherein, the conductive paths of the interposer include through-silicon vias.

10. The microelectronic component according to claim 1, wherein, electronic components are embedded within the interposer.

11. The microelectronic component according to claim 10, wherein, the electronic components include capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge devices, memory devices, radio frequency devices, power amplifiers, power management devices, antennas, microelectromechanical systems or combinations thereof.

12. The microelectronic component according to claim 1, wherein, the second external terminal and the fourth external terminal of the decoupling capacitor are directly connected to the circuit board.

13. The microelectronic component according to claim 1, further comprising a package substrate, the package substrate being electrically connected to the interposer, wherein, The second external terminal and the fourth external terminal of the decoupling capacitor are directly connected to the circuit board.

14. The microelectronic component according to claim 13, wherein, the encapsulation substrate includes an insulating material, and one or more conductive paths are formed through the insulating material.

15. The microelectronic component according to claim 14, wherein, the insulating material is an organic material.

16. The microelectronic component according to claim 1, wherein, the first external terminal and the second external terminal have a positive polarity, and the third external terminal and the fourth external terminal have a negative polarity.

17. The microelectronic component according to claim 1, wherein, at least one of the first external terminal, the second external terminal, the third external terminal, or the fourth external terminal extends to an end surface of the capacitor.

18. The microelectronic component according to claim 1, wherein, the first external terminal, the second external terminal, the third external terminal, and the fourth external terminal do not extend to an end surface of the capacitor.

19. The microelectronic component according to claim 1, wherein, the decoupling capacitor includes only the first external terminal and the third external terminal on the first surface, and includes only the second external terminal and the fourth external terminal on the second surface.

20. The microelectronic component according to claim 1, wherein, the capacitor includes at least four external terminals on the first surface and at least four external terminals on the second surface.

21. The microelectronic component according to claim 20, wherein, the external terminals are arranged linearly on the first surface and the second surface.

22. The microelectronic component according to claim 20, wherein, the external terminals are arranged in a multi-dimensional array on the first surface and the second surface.

23. The microelectronic component according to claim 1, wherein, the first internal electrode layer and the second internal electrode layer are arranged vertically.

24. The microelectronic component according to claim 23, wherein, the first internal electrode layer includes lead tabs extending to the first surface to contact the first external terminal, and lead tabs extending to the second surface to contact the third external terminal, and further, wherein the second internal electrode layer includes lead tabs extending to the first surface to contact the second external terminal, and lead tabs extending to the second surface to contact the fourth external terminal.

25. The microelectronic component according to claim 1, wherein, the first internal electrode layer and the second internal electrode layer are arranged horizontally.

26. The microelectronic component according to claim 25, wherein, the first internal electrode layer and the second internal electrode layer are connected to the first external terminal, the second external terminal, the third external terminal, and the fourth external terminal through conductive vias.

27. The microelectronic component according to claim 1, wherein, the plurality of dielectric layers of the decoupling capacitor include a ceramic material.

28. The microelectronic component according to claim 27, wherein, the ceramic material is a barium titanate ceramic material.

29. The microelectronic component according to claim 1, wherein, the first external terminal, the second external terminal, the third external terminal and the fourth external terminal comprise at least one plating layer.

30. The microelectronic component according to claim 29, wherein, the plating layer is formed by a process including electroless plating, electroplating or a combination thereof.

31. The microelectronic component according to claim 1, wherein, the circuit board is electrically connected to the interposer via a coupling component.

32. The microelectronic component according to claim 31, wherein, the coupling component includes solder.

33. The microelectronic component according to claim 1, wherein, the first external terminal and the third external terminal of the decoupling capacitor are electrically connected to the interposer via a coupling component.

34. The microelectronic component according to claim 1, wherein, the second external terminal and the fourth external terminal of the decoupling capacitor are electrically connected to the circuit board via a coupling component.

Images