Optical signal receiver comprising multi-tap prime

Abstract

Examples related to the use of an optical data receiver that includes multi-tap image sensor pixels for optical communication are disclosed. The multi-tap pixel includes a photodetector and a plurality of taps. The optical data receiver also includes a controller including executable instructions to control the multi-tap prime to perform a first integration on the photodetector for a first period of time and to read out charge stored on the floating diffusion capacitor of a first tap of the plurality of taps using readout circuitry of the first tap. The controller also includes executable instructions to control the multi-tap prime to perform a second integration on the photodetector for a second time period and to read out charge stored on a floating diffusion capacitor of a second tap of the plurality of taps using readout circuitry of the second tap.

Description

Background Art

[0001] A data center is a facility that houses computer systems and related components in a dedicated environment for the purpose of telecommunications and data storage. A data center centralizes the information technology (IT) operations and equipment of an entity for the purpose of storing, processing, and disseminating data and applications. For example, a data center can provide backup components and infrastructure for power, data communication connections, environmental control, and security equipment. There are data centers of different scales, which vary in floor area and power requirements. Summary of the Invention

[0002] Examples related to an optical data receiver are disclosed. The optical data receiver includes multi-tap image sensor pixels for optical communication. The multi-tap pixel includes a photodetector and multiple taps. Each tap includes a floating diffusion capacitor, a transfer gate for controlling the charge flow between the photodetector and the floating diffusion capacitor, and a readout circuit system. The optical data receiver further includes a controller that includes executable instructions for controlling the multi-tap pixel to perform a first integration on the photodetector during a first time period and read out the charge stored on the floating diffusion capacitor of the first tap among the multiple taps using the readout circuit system of the first tap. The controller further includes executable instructions for controlling the multi-tap pixel to perform a second integration on the photodetector during a second time period and read out the charge stored on the floating diffusion capacitor of the second tap among the multiple taps using the readout circuit system of the second tap.

[0003] The purpose of providing this summary of the invention is to introduce some concepts in a simplified form, which will be further described in the "Detailed Description" below. This summary of the invention is not intended to identify the key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. In addition, the claimed subject matter is not limited to embodiments that solve any or all of the disadvantages mentioned in any part of this disclosure. Brief Description of the Drawings

[0004] Figure 1 A schematic diagram is shown, schematically illustrating an example array transceiver data link.

[0005] Figure 2 A schematic diagram is shown, schematically illustrating an example stacked complementary metal oxide semiconductor image sensor.

[0006] Figure 3A and Figure 3B A schematic diagram is shown, schematically illustrating an example multi-tap pixel implemented with four taps.

[0007] Figure 4Shows a timing diagram, schematically illustrating an example operation of a four-tap pixel over four different time slots.

[0008] Figure 5A and Figure 5B Shows a timing diagram, schematically illustrating an example operation of a two-tap pixel over two different time slots.

[0009] Figure 6A and Figure 6B Is a flowchart showing an example method for operating a four-tap pixel.

[0010] Figure 7 Shows a schematic diagram, schematically illustrating an example optical glass storage read system using a sensor including multi-tap pixels.

[0011] Figure 8 Shows a flowchart illustrating an example method for reading an optical glass storage system using a sensor including multi-tap pixels.

[0012] Figure 9 Schematically shows a block diagram of an example computing system. Detailed Description

[0013] Inside a data center, computing devices are connected via data links. The speed of these data links and the power required to operate them are constantly increasing. Data links can be classified into different types, including optical data links and electrical data links. Optical communication is generally faster and has a longer transmission distance than wires, so it is more suitable for use within a data center. Optical communication also has the characteristic of higher power for short-distance transmission. High-speed optical links can be created using optical fibers sourced by high-speed optical transmitters and terminated by high-speed optical receivers. However, for some applications, this implementation may be economically inefficient. For example, due to the relatively short distances within a data center, the relative cost and power of such transmitters and receivers (adjusted according to distance) are high, while the cost of short optical fibers is low.

[0014] In view of the above observations, the present disclosure describes examples of optical sensors including multi-tap pixels for use in data links and other applications to achieve low-cost, low-power implementations. In some implementations, a low-speed fiber optic bundle operating in parallel is used instead of a single high-speed fiber, enabling lower cost and power consumption at an acceptable data rate. Operating at a lower speed compared to typical high-speed data links, in some cases, lower power enables different thermodynamics. The lower power transmission rate generates less heat, enabling different chip designs and implementations in more challenging environments. This mode of operation allows for the use of different transmitters and receivers compared to high-speed optical links. Using low-speed fiber optics, complementary metal oxide semiconductor (CMOS) image sensor (CIS) technology becomes viable in terms of speed. For example, CMOS multi-tap pixels can be used as optical receivers. The fiber optic bundle can be sourced by an array of light sources at one end and terminated by an array of photoelectric sensors implemented using the CMOS technology at the other end. Example light sources include micro light-emitting diodes (μLEDs) and vertical-cavity surface-emitting lasers (VCSELs). In some examples, using integrated circuit technology, the light source array can be monolithically fabricated from a single substrate (e.g., a VCSEL array), while the photoelectric sensor array can be multiple pixels on a CMOS substrate. Such implementations can significantly reduce the cost and power consumption requirements for data link applications compared to typical high-speed fiber optic data links.

[0015] Figure 1 A schematic diagram is shown schematically illustrating an example array transceiver data link 100. The data link 100 includes a receiver 102 and a transmitter 104. The receiver 102 includes a plurality of receiving bundles 106, each receiving bundle 106 including a plurality of receiving optical fibers 108. Similarly, the transmitter 104 includes a plurality of transmitting bundles 110, each transmitting bundle 110 including a plurality of transmitting optical fibers 112. The receiving optical fibers 108 optically communicate with a photoelectric sensor (e.g., an image sensor including multi-tap pixels) located on the data link 100. The transmitting optical fibers 110 optically communicate with a light source (e.g., a VCSEL) also located on the data link 100.

[0016] The data link 100 can be designed to operate as a network switch, receiving a data signal 114 using any of the receiving bundles 106 and forwarding the data signal using any of the transmitting bundles 110. For example, the data signal can be transmitted 116 via a transmitting bundle 110 communicating with a selected downstream system to the selected downstream system. In such systems, higher bandwidth can be achieved by encoding more than one bit of information in a symbol for transmission and reception. Different modulation schemes can be implemented to encode the optical signal as a symbol. Example modulation schemes include phase modulation, amplitude modulation, polarization modulation, and combinations thereof.

[0017] In a data link, including a data link employing a single high-speed optical fiber, due to the response speed of the receiver, an optical signal can parasitically leak from one signal to another. In an embodiment utilizing multi-tap pixels, an example correction method for such a problem includes storing the values of previous taps and determining an error through a linear combination of the stored values.

[0018] By utilizing a low-speed data link, certain technologies and their corresponding manufacturing processes and techniques become feasible for implementation. The optoelectronic sensors in such a data link can be implemented using multi-tap pixels similar to indirect time-of-flight (iToF) pixels with CIS technology. In some embodiments, stacking techniques can be used to form a CIS chip with enhanced functionality. For example, a CIS chip can be formed using a multi-layer wafer having various components and circuitry to achieve different functions.

[0019] Figure 2 A schematic diagram is shown, schematically illustrating an example stacked CIS 200. Stacked CIS technology can be used to form a chip made of multiple wafer layers, each wafer layer being formed using independent back-end-of-line (BEOL) and front-end-of-line (FEOL) manufacturing processes. In Figure 2 the example, the stacked CIS chip 200 includes two different wafer layers. The wafer layers include a sensor layer 202 and a circuit layer 204. Metal-to-metal bonding can be used to connect the two wafer layers 202 and 204. The stacked CIS chip 200 further includes an optoelectronic sensor 206 (e.g., a multi-tap pixel) and a light source 208 (e.g., a VCSEL) disposed on the sensor layer 202. Stacked CIS technology can be used to integrate more electronic components and assemblies on the same chip, thereby enhancing functionality - for example, integrating a switching fabric into the chip to create a router-like function on the sensor chip. Additional components and circuitry can be implemented in the circuit layer 204 to provide various functions. Depending on the application, a chip having more than two wafer layers can also be implemented. For example, additional circuit layers can be added to provide more functions. In such an implementation, through-silicon vias can also be used to connect the wafers oriented in the same direction.

[0020] Compared with a high-speed optical link, using CIS technology reduces the power requirements of the data link. For a typical high-speed optical link, an optical communication receiver operates in a current mode and feeds into a transimpedance amplifier (TIA), which keeps the voltage of the optical receiver constant, thereby generating an output equivalent to the photon signal impinging on the receiver. Figure 3AA schematic diagram is shown, schematically illustrating an optical communication receiver 300 operating in current mode. The optical communication receiver 300 includes a photodiode 302 coupled to a TIA 304. This setup allows the use of high-speed TIAs and other analog circuits implemented with advanced processes, which are not typically used for CIS pixels. The cost and power consumption of this strategy (pixels with TIAs) are reasonable for long-distance transmission, but may be inefficient for short-distance transmission (such as typical distances within a data center).

[0021] Compared with the current-mode operation of these optical communication receivers, the multi-tap pixels in a CMOS image sensor can operate in voltage mode, where the photocurrent from the sensor accumulates in a capacitor, and the voltage of the capacitor is read out periodically. Figure 3B A schematic diagram is shown, schematically illustrating an optical communication receiver 350 operating in voltage mode. The optical communication receiver 350 includes a multi-tap pixel 352 coupled to a comparator 354. Operating in voltage mode can save power consumption in the operation of the multi-tap pixel array as well as the light source array (e.g., VCSEL array). In voltage mode, the multi-tap pixel is more sensitive to optical signals compared to pixels operating with a TIA in current mode. Additionally, due to the absence of a TIA, the multi-tap pixel in voltage mode is generally more efficient than pixels operating in current mode. Since there is no high-speed TIA, more standard CMOS image sensor processes (CIS processes) can be used during manufacturing.

[0022] Unlike continuous operation in current operation mode using TIA, CMOS-based voltage mode operates in discrete phases, typically including reset-pixel (reset), read-reset-value (read reset), integration, and readout phases. Optical signal transmission occurs during integration. Thus, the optical transmission data rate of CIS pixels operating in discrete phases is lower compared to pixels operating in current mode using TIA. However, pixels operating in voltage mode can compensate for the lower optical transmission data rate by implementing multiple taps. By operating multiple low-speed optical fibers in parallel (instead of a single high-speed optical fiber), the slower operation of voltage-domain pixels can be further compensated. Higher data rates can be achieved through various modulation schemes, and further data rate compensation can be achieved by implementing an image sensor including multiple-tap pixels as an optical receiver. Multiple-tap pixels can be implemented and operated such that the dead time between integration phases associated with voltage-domain pixels is reduced or eliminated - for example, multiple-tap pixels can be implemented such that the optical channel is available for optical signals for 100% or nearly 100% of the operating time. Thus, each optical fiber in the received beam can be associated with a photodetector operating in an efficient voltage-based mode 100% of the time. Therefore, full data rate can be achieved through each optical fiber, and significant power levels can be obtained via voltage-mode operation.

[0023] Figure 4 A schematic diagram is shown that schematically illustrates an example multiple-tap pixel 400 implemented with four taps 402. The multiple-tap pixel 400 includes a photodetector 404 shared among the four taps 402. The photodetector 404 operates to accumulate charge in response to incident photons. Each tap 402 includes a floating diffusion capacitor 406 and a transfer gate 408 for controlling the flow of charge between the photodetector 404 and the floating diffusion capacitor 406. Each tap 402 also includes readout circuitry for reading out the charge stored on the associated floating diffusion capacitor 406. The area of each tap 402 is relatively small compared to the photodetector 404. Thus, adding taps can be done at a lower cost compared to adding more pixels using a single photodetector. Additionally, using multiple taps helps utilize more incident light compared to using more pixels. In the case of using more pixels, photons hitting pixels that are not integrating light at that time are lost. In contrast, a pixel with multiple taps integrates more total light because it integrates light for a larger portion of the total time. Other designs can also be implemented. For example, the multiple-tap pixel 400 can include more or fewer than four taps.

[0024] During operation, each tap 402 works in a chronological order in a "reset - read reset - integrate - readout" cycle. In some embodiments, each tap 404 works in different steps in the cycle. For example, within a given time period, the first tap 402A may be in the integration step. The second tap 402B may be in the "read reset" step. The third tap 402C may be in the "reset" step, and the fourth tap 402D may be in the "readout" step.

[0025] During the reset phase, the floating diffusion capacitor 406 is reset and emptied of its charge. During the read reset phase, the reset level of the floating diffusion capacitor 406 is read. During the integration phase, the photodetector 404 accumulates charge in response to incident photons (such as photon signals from an optical fiber in a received beam). Then, the charge is transferred to the floating diffusion capacitor 406 of the associated tap 402 using the transfer gate 408 associated with the tap 402. During the readout phase, the transferred charge is read using the readout circuitry associated with the floating diffusion capacitor 406 on which the readout is performed.

[0026] Although each tap 402 undergoes a "reset - read reset - integrate - readout" cycle, the photodetector 404 can provide an optical charge signal to one of the taps 404 at any given moment. For example, at any given moment, one of the taps 402 is working in the integration step, and the optical charge signal from the photodetector 404 is directed to that tap. Thus, the photodetector 404 can be configured to always perform integration and can make full use of the optical fiber associated with the photodetector 404.

[0027] Figure 5A A timing diagram 500 is shown, schematically illustrating an example operation of a four - tap pixel across four different time slots 502 - 508. Each tap of the four - tap pixel works in a chronological order in a "reset - read reset - integrate - readout" cycle. In the first time slot 502, a readout process is performed on the floating diffusion capacitor of the first tap (FD1) using the readout circuitry associated with FD1. Also in the first time slot 502, the photodetector of the multi - tap pixel is performing a first integration. This integration can include accumulating charge on the photodetector and directing the charge to the floating diffusion capacitor of a specific tap using the associated transfer gate. In an exemplary example, for the first integration, the charge is directed to the floating diffusion capacitor of the second tap (FD2) using the transfer gate of the second tap. Additionally, in the first time slot 502, a read reset process is performed on the floating diffusion capacitor of the third tap (FD3), and a reset process is performed on the floating diffusion capacitor of the fourth tap (FD4).

[0028] In the next consecutive time step, each tap advances to the next stage. In the second time slot 504, a reset process is performed on FD1. A read process is performed on FD2. A second integration is performed on the photodetector and the charge is directed to FD3. A read-reset process is performed on FD4.

[0029] In the third time slot 506, a read-reset process is performed on FD1. A reset process is performed on FD2. A read process is performed on FD3. A third integration is performed on the photodetector and the charge is directed to FD4.

[0030] In the fourth time slot 508, a fourth integration is performed on the photodetector and the charge is directed to FD1. A read-reset process is performed on FD2. A reset process is performed on FD3. A read process is performed on FD4.

[0031] Although Figure 5A the figure illustrates the discrete steps performed on a given tap in each time slot, other steps besides the integration step can be performed across time slots. Generally, the longest step in the operating cycle is the integration step. Thus, the time period of each time slot can be set to the time period for performing the integration step. This enables the multi-tap pixel to operate using the optical channels available for the optical signal for 100% or nearly 100% of the operating time. The remaining three steps for a given tap can be performed in any time slot, including in a single time slot, or can be performed across multiple time slots (such as during the transition between time slots) where no integration is performed on the tap.

[0032] The number of cyclic time slots and the time period of each time slot depend on multiple aspects. The time period of each time slot depends on the number of taps being operated and / or the number of cyclic time slots. The number of cyclic time slots depends on the number of working taps. For example, for a four-tap pixel, the number of cyclic time slots can be set to be the same as the number of working taps (i.e., four), since the operating cycle for each tap includes four discrete steps. In some embodiments, the time period of each time slot is set to the time period for performing the integration step, which is typically the longest step in the operating cycle. The multi-tap pixel can be implemented to include more or fewer than four taps. For a multi-tap pixel with more than four taps, a number of cyclic time slots similar to the number of working taps can be used for implementation. For the implementation of a multi-tap pixel with fewer than four taps, the number of cyclic time slots and the time period of each time slot can depend on the speed of performing the four discrete steps in the operating cycle. For example, for a two-tap pixel, at least two cyclic time slots can be implemented. Additional time slots can be implemented according to the time lengths required for performing "read", "reset", and "read-reset". In some embodiments, the total time for performing the "read", "reset", and "read-reset" steps is less than the time period for performing the "integration" step. In this case, the two-tap pixel can operate in two cyclic time slots.

[0033] Figure 5B A timing diagram 550 is shown, which schematically shows an example operation of a dual-tap pixel spanning two different time slots 552 - 554. In the first time slot 552, the floating diffusion capacitor of the first tap (FD1) is performing readout, reset, and read-reset steps. In the same time slot 552, the photodetector of the dual-tap pixel is performing a first integration and directing the accumulated charge to the floating diffusion capacitor of the second tap (FD2) using the transfer gate of the second tap. In the second time slot 554, FD2 is performing readout, reset, and read-reset steps. In the same time slot 554, the photodetector of the dual-tap pixel is performing a second integration and directing the accumulated charge to FD1 using the transfer gate of the second tap.

[0034] FIG. 3 - Figure 5B The multi-tap pixel and its associated operation scheme shown can be modified to implement pixels with different numbers of taps. The operation scheme is generally designed to reduce downtime by keeping the photodetector of the pixel always operating.

[0035] Figure 6A and Figure 6B are flowcharts illustrating an example method 600 for operating a four-tap pixel. Figure 6A and Figure 6B The method 600 in and describes an operation loop that can be iteratively repeated. In step 602, method 600 includes performing a first integration on the photodetector of the multi-tap pixel during a first time period. In step 604, method 600 includes reading out the charge stored on the floating diffusion capacitor of the first tap of the multi-tap pixel during the first time period. The charge can be read out using the readout circuitry of the first tap.

[0036] During the first integration, in step 602A, a first charge is accumulated in response to incident photons representing transmitted data. In step 602B, the accumulated first charge is directed to the floating diffusion capacitor of the second tap of the multi-tap pixel. The first charge is manipulated by transferring the first charge to the floating diffusion capacitor of the second tap using the transfer gate of the second tap.

[0037] In step 606, method 600 includes reading the reset level of the floating diffusion capacitor of the third tap during the first time period. In step 608, method 600 includes resetting the floating diffusion capacitor of the fourth tap during the first time period. Steps 602 - 608 are performed during the first time period and can thus be performed simultaneously or in any order.

[0038] In step 610, method 600 includes performing a second integration on the photodetector during a second time period. In a four-tap pixel, the second integration includes: in step 610A, accumulating a second charge on the photodetector; and in step 610B, directing the second charge to the floating diffusion capacitor of the third tap using the transfer gate of the third tap.

[0039] The particular tap on which the second integration is performed depends on the total number of taps in the operation of the multi-tap pixel. For a two-tap pixel, the second integration includes accumulating a second charge on the photodetector and directing the second charge to the first tap of the multi-tap pixel. In this case, method 600 may further include: during a first time period, after reading out the charge and reading the reset floating diffusion capacitor of the first tap, resetting the floating diffusion capacitor of the first tap. Method 600 may further include: during a second time period, after reading out the charge and reading the reset floating diffusion capacitor of the second tap, resetting the floating diffusion capacitor of the second tap.

[0040] Review Figure 6A , in step 612, method 600 includes reading out the charge stored on the floating diffusion capacitor of the second tap during a second time period. The charge can be read out using the readout circuitry of the second tap. In step 614, method 600 includes reading the reset level of the floating diffusion capacitor of the fourth tap during a second time period. In step 616, method 600 includes resetting the floating diffusion capacitor of the first tap during a second time period. Steps 610 - 616 are performed during the second time period and thus can be performed simultaneously or in any order.

[0041] In step 618, method 600 includes performing a third integration on the photodetector during a third time period. The third integration includes: in step 618A, accumulating a third charge on the photodetector; and in step 618B, directing the third charge to the floating diffusion capacitor of the fourth tap using the transfer gate of the fourth tap. In step 620, method 600 includes reading out the charge stored on the floating diffusion capacitor of the third tap during a third time period. The charge can be read out using the readout circuitry of the third tap. In step 622, method 600 includes reading the reset level of the floating diffusion capacitor of the first tap during a third time period. In step 624, method 600 includes resetting the floating diffusion capacitor of the second tap during a third time period. Steps 618 - 624 are performed during the third time period and thus can be performed simultaneously or in any order.

[0042] In step 626, method 600 includes performing a fourth integration on the photodetector during a fourth time period. The fourth integration includes: in step 626A, accumulating a fourth charge on the photodetector; and in step 626B, directing the fourth charge to the floating diffusion capacitor of the first tap using the transfer gate of the first tap. In step 628, method 600 includes reading out the charge stored on the floating diffusion capacitor of the fourth tap during the fourth time period. The charge can be read out using the readout circuitry of the fourth tap. In step 630, method 600 includes reading the reset level of the floating diffusion capacitor of the second tap during the fourth time period. In step 632, method 600 includes resetting the floating diffusion capacitor of the third tap during the fourth time period. Steps 626 - 632 are performed during the fourth time period and thus can be performed simultaneously or in any order.

[0043] Multi - tap pixels can be implemented in various applications. In addition to data links in data centers, the multi - tap pixels described herein can also be implemented in any other type of computing device. In some implementations, multi - tap pixels are implemented in an optical glass storage readout system. The optical glass storage system can store data in a three - dimensional voxel grid. To read out the stored data, one or more voxels are illuminated, and the transmitted or reflected light (depending on the system) from the voxels can be detected and analyzed to determine the content of the voxels. Various coding schemes can be used to store and read the data in the voxels. Example coding schemes include amplitude - based coding and birefringence - based coding. In some embodiments, the optical glass memory includes voxels at different depths, and wavelength - based depth focusing techniques or other focusing techniques can be used to read. For example, the refractive index of some optical materials depends on the wavelength of the incident light. Thus, through appropriate design and use of optical materials, an optical system can be implemented to focus light at different depths within the optical material using light of different wavelengths. In this way, the readout system can include a light source capable of outputting light of different wavelengths. During a read operation, light of different wavelengths is sequentially turned on, focusing the light on the voxels at different depths without any mechanical movement. The downstream photoelectric sensor sequentially acquires and stores the data from the voxels.

[0044] A photoelectric sensor including multi - tap pixels can be used to rapidly and continuously acquire multiple optical signals, each optical signal from a different voxel. Each tap can store the optical signal from the voxel. Additional taps are capable of acquiring additional optical signals. After reading a predetermined number of voxels or after the taps of the pixel are full, the readout system can be repositioned to read a different voxel region. During the repositioning process, the readout of the taps can be performed using the readout dead time that exists during the more typical operation of the multi - tap pixel.

[0045] Figure 7A schematic diagram is shown, schematically illustrating an example optical glass storage and read system 700 that utilizes multi-tap pixels. The read system 700 includes a light source 702 for irradiating an optical glass memory 704. Various types of light sources can be utilized, such as a laser light source. In the depicted example, the optical glass memory 704 includes a three-dimensional voxel grid 706, where voxels 706 are shown at a first depth 708 and a second depth 710. These two depths 708 and 710 are for illustration only, and the optical glass memory 704 can include voxels having more than two depth levels. The read system 700 operates using a wavelength-based depth focusing scheme to read voxels 706 at different depths within the optical glass memory 704. Thus, the light source 702 can include one or more light sources capable of outputting light of different wavelengths. The read system 700 also includes an optional homogenizer 712 for providing uniform illumination and a microlens array 714 for focusing the light onto the voxels 706.

[0046] Depending on the encoding of the optical glass storage system 704, different read schemes can be implemented. Example encoding schemes include amplitude-based encoding and birefringence-based encoding. The depicted example read system 700 utilizes a birefringence-based encoding scheme. Thus, the read system 700 includes a polarizer 716 for polarizing the light output by the light source 702. In the depicted example, a transmission system is implemented, and a photoelectric sensor array 718 is disposed on the side of the optical glass memory 740 opposite to the light source 702. In other embodiments, a reflection system is implemented, and the photoelectric sensor and the light source 702 are located on the same side. The light transmitted through the voxels 706 is modified by the voxels 706 and is directed to an analyzer 720, and the data is also transmitted to the photoelectric sensor array 718. In the depicted example, the analyzer 720 is implemented to read the angle and / or delay of the received light. The photoelectric sensor array 718 includes a plurality of multi-tap pixels for simultaneously reading multiple voxel positions and storing the transmitted data. The photoelectric sensor array 718 can be implemented in various ways. Example embodiments include one-dimensional and two-dimensional photoelectric sensor arrays.

[0047] During a read operation, multiple voxels 706 are irradiated by the light source 702. Under the wavelength-based depth focusing scheme, different wavelengths of light can be used to irradiate voxels 706 at different depths. For example, in the depicted system, light of wavelength λ 1 (represented by a solid line) is used to irradiate a plurality of first voxels 722 at the first depth 708, and light of wavelength λ 2 (represented by a dashed line) is used to irradiate a plurality of second voxels 724 at the second depth 710. Different wavelengths of light can be used to irradiate other depth levels. The light source 702 first outputs light of wavelength λ 1light to illuminate a plurality of first voxels 722 at a first depth 708. Information from the plurality of first voxels 722 is analyzed and stored in a corresponding number of first taps of a plurality of multi-tap pixels in the photoelectric sensor array 718. Then, the light source 702 is switched to an output light having a wavelength of λ 2 to illuminate a plurality of second voxels 724 at a second depth 710. Information from the plurality of second voxels 724 is analyzed and stored in a corresponding number of second taps of a plurality of multi-tap pixels in the photoelectric sensor array 718. Other groups of voxels can be illuminated with light of different wavelengths, and the information retrieved from these voxels is stored in other taps of the plurality of multi-tap pixels. After the light source 702 and the photoelectric sensor array 718 have performed a predetermined number of groups of illumination and integration respectively, the reading system 700 is repositioned using a scanning system to read the voxels 706 at different positions. During the repositioning process, the taps of the plurality of multi-tap pixels can be read out.

[0048] Figure 8 FIG. shows a flowchart of an example method 800 for reading an optical glass storage system using multi-tap pixels. These steps describe an iterative loop process until a predetermined number of voxel arrays are read and the read operation is completed. In step 802, method 800 includes illuminating a first voxel array in the optical glass storage system using a light source. The first voxel array can be illuminated with light of a first wavelength output by the light source. One or more light sources can be implemented. In some embodiments, the light source is a laser source. In other embodiments, the light source is capable of quickly switching between output lights of different wavelengths.

[0049] In step 804, method 800 includes performing a plurality of first integrations on a plurality of first taps of a plurality of multi-tap pixels in response to light received from the illuminated first voxel array. The plurality of first taps includes the first tap from each multi-tap pixel. The first integration includes: in step 804A, accumulating a plurality of first charges on the photodetectors of the plurality of multi-tap pixels; in step 804B, using the transfer gates of the plurality of first taps to direct the first charges to the floating diffusion capacitors of the plurality of first taps respectively.

[0050] In step 806, method 800 includes illuminating a second voxel array in the optical glass system using a light source. The second voxel array can be illuminated with light of a second wavelength output by the light source.

[0051] In step 808, method 800 includes performing a plurality of second integrations on a plurality of second taps of a plurality of multi-tap pixels in response to light received from the illuminated second voxel array. The plurality of second taps include second taps from each multi-tap pixel. The second integration includes: in step 808A, accumulating a plurality of second charges on the photodetectors of the plurality of multi-tap pixels; in step 808B, using the transfer gates of the plurality of second taps to direct the second charges respectively to the floating diffusion capacitors of the plurality of second taps.

[0052] In step 810, method 800 includes using a repositioning system to reposition the reading system such that the light source is positioned to output light directed at a third voxel array and a fourth voxel array. The repositioning system can be implemented in various ways. For example, various mechanical devices can be used to reposition the optical glass storage system, the light source, and / or the photoelectric sensor individually or in some combination.

[0053] In step 812, method 800 includes reading out the charges stored on the floating diffusion capacitors of the plurality of first and second taps. The reading out of the charges is performed within the same time period during which the reading system is repositioned. In step 814, method 800 includes resetting the floating diffusion capacitors of the plurality of first and second taps. In step 816, method 800 includes reading the reset levels of the floating diffusion capacitors of the plurality of first and second taps. Similar to step 812, steps 814 and 816 can be performed within the same time period as the repositioning process of the reading system.

[0054] The multi-tap pixels described herein can be implemented in various applications through novel operating techniques, which can improve the efficiency of the systems implementing them in terms of power and cost. For example, the data link and the optical glass storage reading system described above provide two example applications that utilize these operating techniques to reduce or eliminate the downtime of such pixels. The reduction in downtime enables them to operate at higher bandwidths, while the nature of these pixels enables them to operate at lower power, thus enabling new implementations with an efficiency several orders of magnitude lower than typical applications. In some embodiments, the methods and processes described herein can be bound to the computing system of one or more computing devices. Specifically, such methods and processes can be implemented as computer applications or services, application programming interfaces (APIs), libraries, and / or other computer program products.

[0055] Figure 9A non - limiting embodiment of a computing system 900 is schematically shown, which can execute one or more of the above - described methods and processes. For example, the computing system 900 can be implemented as a controller that includes executable instructions for controlling a multi - tap pixel to execute any of the methods and processes described in the above sections. The computing system 900 is shown in a simplified form. The computing system 900 can take the form of one or more personal computers, server computers, tablet computers, home entertainment computers, network computing devices, gaming devices, mobile computing devices, mobile communication devices (e.g., smart phones), and / or other computing devices.

[0056] The computing system 900 includes a logic machine 902 and a storage machine 904. The computing system 900 can optionally include a display subsystem 906, an input subsystem 908, a communication subsystem 910, and / or Figure 9 other components not shown in.

[0057] The logic machine 902 includes one or more physical devices configured to execute instructions. For example, the logic machine 902 can be configured to execute instructions that are part of one or more applications, services, programs, routines, libraries, objects, components, data structures, or other logical constructs. These instructions can be implemented to perform tasks, implement data types, transform the state of one or more components, achieve technical effects, or otherwise reach an intended result.

[0058] The logic machine 902 can include one or more processors configured to execute software instructions. Additionally or alternatively, the logic machine 902 can include one or more hardware or firmware logic machines configured to execute hardware or firmware instructions. The processors of the logic machine 902 can be single - core or multi - core, and the instructions executed thereon can be configured for sequential, parallel, and / or distributed processing. The various components of the logic machine 902 can optionally be distributed among two or more separate devices, which can be remotely located and / or configured for coordinated processing. Aspects of the logic machine 902 can be virtualized and executed by remotely accessible networked computing devices configured in a cloud - computing configuration.

[0059] The storage machine 904 includes one or more physical devices configured to hold instructions executable by the logic machine 902 to implement the methods and processes described herein. When implementing such methods and processes, the state of the storage machine 904 can be transformed, for example, to hold different data.

[0060] The storage machine 904 may include removable and / or built-in devices. The storage machine 904 may include optical memories (e.g., CD, DVD, HD-DVD, Blu-ray Disc, etc.), semiconductor memories (e.g., RAM, EPROM, EEPROM, etc.), and / or magnetic memories (e.g., hard disk drive, floppy disk drive, tape drive, MRAM, etc.), among others. The storage machine 904 may include volatile, non-volatile, dynamic, static, read / write, read-only, random access, sequential access, location-addressable, file-addressable, and / or content-addressable devices.

[0061] It should be understood that the storage machine 904 includes one or more physical devices. However, aspects of the instructions described herein may alternatively be propagated via a communication medium (e.g., electromagnetic signals, optical signals, etc.) that cannot be held by a physical device for a finite duration.

[0062] Aspects of the logic machine 902 and the storage machine 904 may be integrated into one or more hardware logic components. These hardware logic components may include, for example, field programmable gate arrays (FPGA), program- and application-specific integrated circuits (PASIC / ASIC), program- and application-specific standard products (PSSP / ASSP), system-on-a-chip (SOC), and complex programmable logic devices (CPLD).

[0063] The terms "module", "program", and "engine" may be used to describe an aspect of the computing system 900 implemented to perform a specific function. In some cases, a module, program, or engine may be instantiated via the logic machine 902 that executes instructions held by the storage machine 904. It will be understood that different modules, programs, and / or engines may be instantiated from the same application, service, code block, object, library, routine, API, function, etc. Similarly, the same module, program, and / or engine may be instantiated by different applications, services, code blocks, objects, routines, APIs, functions, etc. The terms "module", "program", and "engine" may include single or multiple sets of executable files, data files, libraries, drivers, scripts, database records, etc.

[0064] It should be understood that the "service" used herein refers to an application program that can be executed across multiple user sessions. A service is available for use by one or more system components, programs, and / or other services. In some embodiments, a service may run on one or more server computing devices.

[0065] When the display subsystem 906 is included, it can be used to present a visual representation of the data maintained by the storage machine 904. This visual representation can take the form of a graphical user interface (GUI). When the methods and processes described herein change the data maintained by the storage machine, thus transforming the state of the storage machine 904, the state of the display subsystem 906 can also be transformed accordingly to visually present the changes in the underlying data. The display subsystem 906 can include one or more display devices employing almost any type of technology. Such display devices can be combined with the logic machine 902 and / or the storage machine 904 in a shared enclosure, or such display devices can be peripheral display devices.

[0066] When the input subsystem 908 is included, it can include or interface with one or more user input devices such as a keyboard, a mouse, a touch screen, or a game controller. In some embodiments, the input subsystem 908 can include or interface with selected natural user input (NUI) components. Such components can be integrated or peripheral, and the conversion and / or processing of input actions can be performed on-board or off-board. Example NUI components can include a microphone for voice and / or sound recognition; infrared, color, stereo, and / or depth cameras for machine vision and / or gesture recognition; head trackers, eye trackers, accelerometers, and / or gyroscopes for motion detection and / or intent recognition; and electric field sensing components for evaluating brain activity.

[0067] When the communication subsystem 910 is included, it can be configured to communicatively couple the computing system 900 with one or more other computing devices. The communication subsystem 910 can include wired and / or wireless communication devices compatible with one or more different communication protocols. As a non-limiting example, the communication subsystem 910 can be configured to communicate via a wireless telephone network, a wired or wireless local area network, or a wide area network. In some embodiments, the communication subsystem 910 can allow the computing system 900 to send and receive messages to and from other devices via a network such as the Internet.

[0068] On the other hand, an optical data receiver including pixels is provided. Each pixel includes a photodetector and a plurality of taps. Each tap includes a floating diffusion capacitor, a transfer gate for controlling the charge flow between the photodetector and the floating diffusion capacitor, and a readout circuitry. The optical data receiver further includes a controller including executable instructions for controlling the pixel to perform a first integration on the photodetector during a first time period and read out the charge stored on the floating diffusion capacitor of the first tap among the plurality of taps using the readout circuitry of the first tap. The controller further includes executable instructions for controlling the pixel to perform a second integration on the photodetector during a second time period and read out the charge stored on the floating diffusion capacitor of the second tap among the plurality of taps using the readout circuitry of the second tap. In this aspect, additionally or alternatively, performing the first integration includes accumulating charge on the photodetector and transferring the accumulated charge to the floating diffusion capacitor of the second tap. In this aspect, additionally or alternatively, the controller further includes executable instructions for controlling the pixel to reset the floating diffusion capacitor of the first tap after reading out the charge and read the reset floating diffusion capacitor of the first tap during the first time period; and to reset the floating diffusion capacitor of the second tap after reading out the charge and read the reset floating diffusion capacitor of the second tap during the second time period. In this aspect, additionally or alternatively, the controller further includes executable instructions for controlling the pixel to perform a third integration on the photodetector during a third time period and read out the charge stored on the floating diffusion capacitor of the third tap among the plurality of taps using the readout circuitry of the third tap; and to perform a fourth integration on the photodetector during a fourth time period and read out the charge stored on the floating diffusion capacitor of the fourth tap among the plurality of taps using the readout circuitry of the fourth tap. In this aspect, additionally or alternatively, performing the first integration includes accumulating a first charge on the photodetector and transferring the accumulated first charge to the floating diffusion capacitor of the second tap. Performing the second integration includes accumulating a second charge on the photodetector and transferring the accumulated second charge to the floating diffusion capacitor of the third tap. Performing the third integration includes accumulating a third charge on the photodetector and transferring the accumulated third charge to the floating diffusion capacitor of the fourth tap. Performing the fourth integration includes accumulating a fourth charge on the photodetector and transferring the accumulated fourth charge to the floating diffusion capacitor of the first tap. In this aspect, additionally or alternatively, the controller further includes executable instructions for controlling the pixel to reset the floating diffusion capacitor of the fourth tap and read the reset floating diffusion capacitor of the third tap during the first time period. The controller further includes executable instructions for controlling the pixel to reset the floating diffusion capacitor of the first tap and read the reset floating diffusion capacitor of the fourth tap during the second time period. The controller further includes executable instructions for controlling the pixel to reset the floating diffusion capacitor of the second tap and read the reset floating diffusion capacitor of the first tap during the third time period.The controller further includes executable instructions for controlling the pixel to reset the floating diffusion capacitor of the third tap and read the reset floating diffusion capacitor of the second tap during a fourth time period. In this regard, additionally or alternatively, the optical data receiver further includes a stacked structure having a sensor layer and a circuit layer. In this regard, additionally or alternatively, the optical data receiver further includes a complementary metal oxide semiconductor image sensor.

[0069] On the other hand, a network data transceiver is provided, which includes a plurality of pixels, each pixel including a photodetector and a plurality of taps. Each tap includes a floating diffusion capacitor, a transfer gate for controlling the charge flow between the photodetector and the floating diffusion capacitor, and a readout circuit system. The network data transceiver further includes a controller, which includes executable instructions for controlling the pixels in the plurality of pixels to perform a first integration on the photodetector within a first time period, and reading out the charge stored on the floating diffusion capacitor of the first tap among the plurality of taps using the readout circuit system of the first tap; performing a second integration on the photodetector within a second time period, and reading out the charge stored on the floating diffusion capacitor of the second tap among the plurality of taps using the readout circuit system of the second tap. In this regard, additionally or alternatively, the network data transceiver further includes a vertical cavity surface emitting laser array. In this regard, additionally or alternatively, performing the first integration includes accumulating charge on the photodetector and transferring the accumulated charge to the floating diffusion capacitor of the second tap. In this regard, additionally or alternatively, the controller further includes executable instructions for controlling the pixels in the plurality of pixels to reset the floating diffusion capacitor of the first tap after reading out the charge within the first time period, and reading the reset floating diffusion capacitor of the first tap; resetting the floating diffusion capacitor of the second tap after reading out the charge within the second time period, and reading the reset floating diffusion capacitor of the second tap. In this regard, additionally or alternatively, the controller further includes executable instructions for controlling the pixels in the plurality of pixels to perform a third integration on the photodetector within a third time period, and reading out the charge stored on the floating diffusion capacitor of the third tap among the plurality of taps using the readout circuit system of the third tap; performing a fourth integration on the photodetector within a fourth time period, and reading out the charge stored on the floating diffusion capacitor of the fourth tap among the plurality of taps using the readout circuit system of the fourth tap. In this regard, additionally or alternatively, performing the first integration includes accumulating a first charge on the photodetector and transferring the accumulated first charge to the floating diffusion capacitor of the second tap. Performing the second integration includes accumulating a second charge on the photodetector and transferring the accumulated second charge to the floating diffusion capacitor of the third tap. Performing the third integration includes accumulating a third charge on the photodetector and transferring the accumulated third charge to the floating diffusion capacitor of the fourth tap. Performing the fourth integration includes accumulating a fourth charge on the photodetector and transferring the accumulated fourth charge to the floating diffusion capacitor of the first tap. In this regard, additionally or alternatively, the controller further includes executable instructions for controlling the pixels in the plurality of pixels to reset the floating diffusion capacitor of the fourth tap within the first time period, reset the floating diffusion capacitor of the first tap within the second time period, reset the floating diffusion capacitor of the second tap within the third time period, and reset the floating diffusion capacitor of the third tap within the fourth time period.In this regard, additionally or alternatively, a plurality of pixels include a stacked structure having a sensor layer and a circuit layer.

[0070] On the other hand, an optical glass storage reading system is provided, which includes a repositioning system for repositioning the optical glass storage reading system and a reading head. The reading head includes a light source for irradiating the optical glass storage system, a microlens array for focusing the light from the light source onto a voxel array of the optical glass storage system, and a photoelectric sensor array. The photoelectric sensor array includes a plurality of pixels for receiving light from the optical glass storage system, and each pixel includes a photodetector and a plurality of taps. Each tap includes a floating diffusion capacitor, a transfer gate for controlling the charge flow between the photodetector and the floating diffusion capacitor, and a readout circuit system. The photoelectric sensor array further includes a controller, and the controller includes executable instructions for controlling each pixel to accumulate a first charge on the photodetector during a first time period and transfer the accumulated first charge to the floating diffusion capacitor of the first tap among the plurality of taps; accumulate a second charge on the photodetector during a second time period and transfer the accumulated second charge to the floating diffusion capacitor of the second tap among the plurality of taps. The controller further includes executable instructions for controlling each pixel to read out the first and second charges stored on the floating diffusion capacitors of the first and second taps during a third time period, reset the floating diffusion capacitors of the first and second taps, and read the reset floating diffusion capacitors of the first and second taps. In this regard, additionally or alternatively, the third time period occurs during the activation of the repositioning system. In this regard, additionally or alternatively, the reading head further includes a polarizer for filtering the light from the light source and an analyzer for analyzing the delay of the light from the optical glass storage system. In this regard, additionally or alternatively, the controller further includes executable instructions for controlling each pixel to accumulate a third charge on the photodetector during a fourth time period before the third time period and transfer the accumulated third charge to the floating diffusion capacitor of the third tap among the plurality of taps; and accumulate a fourth charge on the photodetector during a fifth time period before the third time period and transfer the accumulated fourth charge to the floating diffusion capacitor of the fourth tap among the plurality of taps. The controller further includes executable instructions for controlling each pixel to read out the charges stored on the floating diffusion capacitors of the third and fourth taps during the third time period.

[0071] It should be understood that the configurations and / or methods described herein are exemplary in nature only, and these specific embodiments or examples should not be considered restrictive because there are various variations. The specific routines or methods described herein may represent one or more of any number of processing strategies. Therefore, the various operations shown and / or described may be performed in the order shown and / or described, in other orders, in parallel, or omitted. Similarly, the order of the above processes may also be changed.

[0072] The subject matter of the present disclosure includes all novel and non-obvious combinations and sub-combinations of various processes, systems, and configurations, as well as other features, functions, acts, and / or properties disclosed herein, and any and all equivalents thereof.

Claims

1. An optical data receiver, comprising: Pixels, comprising: A photodetector; and A plurality of taps, each tap comprising: A floating diffusion capacitor; A transfer gate for controlling the charge flow between the photodetector and the floating diffusion capacitor; and A readout circuitry; and A controller, comprising executable instructions for controlling the pixel to: During a first time period: Perform a first integration on the photodetector; and Read out the charge stored on the floating diffusion capacitor of the first tap among the plurality of taps using the readout circuitry of the first tap; and During a second time period; Perform a second integration on the photodetector; Read out the charge stored on the floating diffusion capacitor of the second tap among the plurality of taps using the readout circuitry of the second tap.

2. The optical data receiver according to claim 1, wherein performing the first integration comprises: Accumulating charge on the photodetector; and Transferring the accumulated charge to the floating diffusion capacitor of the second tap.

3. The optical data receiver according to claim 2, wherein the controller further comprises executable instructions for controlling the pixel to: During the first time period: After reading out the charge, reset the floating diffusion capacitor of the first tap; and read the reset floating diffusion capacitor of the first tap; During the second time period; After reading out the charge, reset the floating diffusion capacitor of the second tap; and read the reset floating diffusion capacitor of the second tap.

4. The optical data receiver according to claim 1, wherein the controller further comprises executable instructions for controlling the pixel to: During a third time period: Perform a third integration on the photodetector; and Read out the charge stored on the floating diffusion capacitor of the third tap among the plurality of taps using the readout circuitry of the third tap ； and During a fourth time period: Perform a fourth integration on the photodetector; Read out the charge stored on the floating diffusion capacitor of the fourth tap among the plurality of taps using the readout circuitry of the fourth tap.

5. The optical data receiver according to claim 4, wherein: Performing the first integration comprises: Accumulating a first charge on the photodetector; and Transferring the accumulated first charge to the floating diffusion capacitor of the second tap; Performing the second integration comprises: Accumulating a second charge on the photodetector; and Transferring the accumulated second charge to the floating diffusion capacitor of the third tap; Performing the third integration comprises: Accumulating a third charge on the photodetector; and Transferring the accumulated third charge to the floating diffusion capacitor of the fourth tap; and performing the fourth integration comprises: Accumulating a fourth charge on the photodetector; and Transferring the accumulated fourth charge to the floating diffusion capacitor of the first tap.

6. The optical data receiver according to claim 5, wherein the controller further comprises executable instructions for controlling the pixels to: During the first time period: Reset the floating diffusion capacitor of the fourth tap ； And Read the reset floating diffusion capacitor of the third tap; During the second time period: Reset the floating diffusion capacitor of the first tap; And Read the reset floating diffusion capacitor of the fourth tap; During the third time period: Reset the floating diffusion capacitor of the second tap; And Read the reset floating diffusion capacitor of the first tap; And During the fourth time period: Reset the floating diffusion capacitor of the third tap; And Read the reset floating diffusion capacitor of the second tap.

7. The optical data receiver according to claim 1, further comprising a stacked structure having a sensor layer and a circuit layer.

8. The optical data receiver according to claim 1, further comprising a complementary metal oxide semiconductor image sensor.

9. A network data transceiver, Comprising: A plurality of pixels, each pixel comprising: A photodetector; and A plurality of taps, each tap comprising: A floating diffusion capacitor; A transfer gate for controlling the charge flow between the photodetector and the floating diffusion capacitor; and A readout circuit system; and A controller comprising executable instructions for controlling the pixels in the plurality of pixels to: During a first time period: Perform a first integration on the photodetector; Read out the charge stored on the floating diffusion capacitor of the first tap among the plurality of taps using the readout circuit system of the first tap; During a second time period; Perform a second integration on the photodetector; Read out the charge stored on the floating diffusion capacitor of the second tap among the plurality of taps using the readout circuit system of the second tap.

10. The network data transceiver according to claim 9, further comprising a vertical cavity surface emitting laser array.

11. The network data transceiver according to claim 9, wherein performing the first integration Comprises: Accumulating charge on the photodetector; And Transferring the accumulated charge to the floating diffusion capacitor of the second tap.

12. The network data transceiver according to claim 9, wherein the controller further comprises executable instructions for controlling the pixels in the plurality of pixels to: During the first time period: After reading out the charge, reset the floating diffusion capacitor of the first tap ； And Read the reset floating diffusion capacitor of the first tap; During the second time period; After reading out the charge, reset the floating diffusion capacitor of the second tap; And Read the reset floating diffusion capacitor of the second tap.

13. The network data transceiver according to claim 9, wherein the controller further comprises executable instructions for controlling the pixels in the plurality of pixels to: During a third time period: Perform a third integration on the photodetector; The readout circuit system using the third tap reads the charge stored on the floating diffusion capacitor of the third tap among the multiple taps. ； And In the fourth time period: Perform a fourth integration on the photodetector; The readout circuit system using the fourth tap reads the charge stored on the floating diffusion capacitor of the fourth tap among the multiple taps.

14. The network data transceiver according to claim 9, wherein: Performing the first integration includes: Accumulating a first charge on the photodetector; and Transferring the accumulated first charge to the floating diffusion capacitor of the second tap; Performing the second integration includes: Accumulating a second charge on the photodetector; and Transferring the accumulated second charge to the floating diffusion capacitor of the third tap; Performing the third integration includes: Accumulating a third charge on the photodetector; and Transferring the accumulated third charge to the floating diffusion capacitor of the fourth tap; and performing the fourth integration includes: Accumulating a fourth charge on the photodetector; and Transferring the accumulated fourth charge to the floating diffusion capacitor of the first tap.

15. The network data transceiver according to claim 9, wherein the controller further includes executable instructions for controlling the pixels among the multiple pixels to: In the first time period, reset the floating diffusion capacitor of the fourth tap; In the second time period, reset the floating diffusion capacitor of the first tap; In the third time period, reset the floating diffusion capacitor of the second tap; And In the fourth time period, reset the floating diffusion capacitor of the third tap.

16. The network data transceiver according to claim 9, wherein the multiple pixels include a stacked structure having a sensor layer and a circuit layer.

17. An optical glass storage and read system, comprising: A repositioning system for repositioning the optical glass storage and read system; And A read head, comprising: A light source for irradiating the optical glass storage system; A microlens array for focusing light from the light source onto a voxel array of the optical glass storage system; An optoelectronic sensor array, comprising: Multiple pixels for receiving light from the optical glass storage system, each pixel comprising: A photodetector; and Multiple taps, each tap comprising: A floating diffusion capacitor; A transfer gate for controlling the charge flow between the photodetector and the floating diffusion capacitor; and A readout circuit system; and A controller, including executable instructions for controlling each pixel to: In the first time period: Accumulating a first charge on the photodetector; and Transferring the accumulated first charge to the floating diffusion capacitor of the first tap among the multiple taps; In the second time period; Accumulating a second charge on the photodetector; and Transferring the accumulated second charge to the floating diffusion capacitor of the second tap among the multiple taps; and In the third time period; Read out the first charge and the second charge stored on the floating diffusion capacitors of the first tap and the second tap; Reset the floating diffusion capacitors of the first tap and the second tap; and Read the reset floating diffusion capacitors of the first tap and the second tap.

18. The optical glass storage system according to claim 17, wherein the third time period occurs during the activation period of the repositioning system.

19. The optical glass storage system according to claim 17, wherein the read head further comprises: a polarizer for filtering light from the light source; and an analyzer for analyzing the delay of the light from the optical glass storage system.

20. The optical glass storage system according to claim 17, wherein the controller further comprises executable instructions for controlling each pixel to: During a fourth time period occurring before the third time period: Accumulate a third charge on the photodetector ； and Transfer the accumulated third charge to the floating diffusion capacitor of the third tap among the plurality of taps; During a fifth time period occurring before the third time period; Accumulate a fourth charge on the photodetector; and Transfer the accumulated fourth charge to the floating diffusion capacitor of the fourth tap among the plurality of taps; and During the third time period; Read out the charge stored on the floating diffusion capacitors of the third tap and the fourth tap.

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