Instruction processing method and device, SPI host and interface circuit
By designing an instruction-dependent cache architecture in the SPI driver module of the SPI host, combining instructions and optimizing cache usage, the problem of low efficiency of SPI slaves by the SPI host read and write SPI slaves is solved, and more efficient read and write operations and longer device service life is achieved.
Patent Information
- Application Number
- CN202311735452.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-15
- Publication Date
- 2025-06-17
AI Technical Summary
In the prior art, the SPI host is inefficient when reading and writing SPI slaves due to the size limitation of the FIFO and the communication across the clock domain, especially when determining that the FIFO is empty and full, the read and write efficiency affects the read and write efficiency.
By designing an instruction-dependent cache architecture in the SPI driver module, the instructions are merged according to the dependencies between the front and rear instructions, the instruction overhead is reduced, and the number of read and write times to the SPI slave is reduced through cache optimization.
It improves the read and write efficiency of SPI slaves by SPI masters, reduces instruction overhead and wait time, and extends the service life of SPI slaves.
Smart Images
Figure CN120162085A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular, to an instruction processing method, apparatus, SPI host, and interface circuit. Background Art
[0002] In the design of an SPI host, the SPI host usually uses an external SPI slave to store processed image data and code data that needs to be read and written after power-on. Among them, SPI (Serial Peripheral Interface) is a full-duplex synchronous serial communication interface. The SPI slave can be an SPI Flash, and the SPI Flash is a non-volatile storage medium based on the SPI interface in the current market. The control unit is a module in the SPI host, and the control unit communicates with the SPI slave through an SPI driver module (i.e., SPI Master) outside the control unit. Specifically, the control unit mainly completes read, write, and erase operations by sending instructions, addresses, data, etc. to the SPI slave according to the specified SPI timing through the SPI Master. During the communication process, since the frequency at which the control unit sends instructions to the SPI Master through the Advanced Peripheral Bus (APB) is usually more than twice the frequency at which the SPI Master sends to the SPI slave, in a cross-clock domain, addresses and data are generally buffered in a First Input First Output (FIFO) manner. The FIFO design of the SPI Master directly affects the efficiency of reading and writing the SPI slave.
[0003] In the traditional design method, the size of the FIFO limits the read and write efficiency, and the SPI Master needs to judge the empty and full status of the FIFO during the read and write process, and the above read and write process is suspended after the FIFO is full until the FIFO is half full before restarting the read and write process. Even if the SPI Master can work at a high frequency, the waiting generated during the read and write process for judging the empty and full status of the FIFO also affects the efficiency of reading and writing the SPI slave. Summary of the Invention
[0004] This application provides an instruction processing method, apparatus, SPI host, and interface circuit to solve the problem of low efficiency in reading and writing the SPI slave existing in the prior art.
[0005] According to a first aspect of this application, there is provided an instruction processing method, which is applied to an SPI driver module on an SPI host, and the method includes:
[0006] Obtain a first instruction and a second instruction; wherein, the first instruction is an instruction carrying first configuration data sent by a control unit, and the second instruction is an instruction carrying second configuration data stored locally, and the control unit is externally connected to the SPI driving module and is located on an SPI host;
[0007] Determine the dependency relationship between the first instruction and the second instruction according to the first configuration data and the second configuration data;
[0008] When the dependency relationship is a specified type of dependency relationship, merge the first instruction and the second instruction into a single instruction, and send the single instruction to an SPI slave external to the SPI host.
[0009] Optionally, the first configuration data includes at least one of a first instruction type, a first address, and a first instruction length; the second configuration data includes at least one of a second instruction type, a second address, and a second instruction length;
[0010] Then, the determining the dependency relationship between the first instruction and the second instruction according to the first configuration data and the second configuration data includes:
[0011] When both the first instruction type and the second instruction type are read data instructions, and the first address is the sum of the second address and the second instruction length, determine that the dependency relationship between the first instruction and the second instruction is a specified type of dependency relationship;
[0012] Or,
[0013] When both the first instruction type and the second instruction type are write data instructions, and the first address is the sum of the second address and the second instruction length, determine that the dependency relationship between the first instruction and the second instruction is a specified type of dependency relationship.
[0014] Optionally, the merging the first instruction and the second instruction into a single instruction and sending the single instruction to an SPI slave external to the SPI host includes:
[0015] When both the first instruction type and the second instruction type are write data instructions, merge the first configuration data and the second configuration information to obtain merged configuration data, and merge the data to be written carried in the first instruction and the data to be written carried in the second instruction to obtain merged data;
[0016] According to the merged configuration data, after caching the merged data, send it to an SPI slave external to the SPI host.
[0017] Optionally, determining the dependency relationship between the first instruction and the second instruction according to the first configuration data and the second configuration data includes:
[0018] When the first instruction type is a read data instruction, the second instruction type is an erase data instruction or a write data instruction, the first address is between the second address and the third address, and the length of the first instruction does not exceed the length of the second instruction, determining that the dependency relationship between the first instruction and the second instruction is a non-specified type of dependency relationship; wherein, the third address is the result of adding the second address and the length of the second instruction;
[0019] Or,
[0020] When the first instruction type is a read data instruction, the second instruction type is an erase data instruction or a write data instruction, the first address is between the second address and the third address, and the length of the first instruction exceeds the length of the second instruction, determining that the dependency relationship between the first instruction and the second instruction is a mixed dependency relationship; wherein, the mixed dependency relationship includes a non-specified type of dependency relationship and a non-dependency relationship.
[0021] Optionally, after determining the dependency relationship between the first instruction and the second instruction, the method further includes:
[0022] When the dependency relationship is the non-specified type of dependency relationship and the length of the first instruction does not exceed the length of the second instruction, reading the data corresponding to the first instruction from the local cache;
[0023] When the dependency relationship is the mixed dependency relationship and the length of the first instruction exceeds the length of the second instruction, reading the data that does not exceed the length of the second instruction from the local cache, and reading the data that exceeds the length of the second instruction from the SPI slave outside the SPI host.
[0024] Optionally, when sending the single instruction to the SPI slave outside the SPI host, the method further includes:
[0025] Sending the check code corresponding to the merged data to the SPI slave, so that the SPI slave can determine whether there is packet loss in the transmission process of the merged data according to the check code.
[0026] According to a second aspect of the present application, there is provided an SPI host, including an SPI driver module and a control unit for executing the instruction processing method according to any one of the first aspects above.
[0027] According to a third aspect of the present application, there is provided an instruction processing apparatus, including: an SPI driver module applied to an SPI host, and the apparatus includes:
[0028] An acquisition module, configured to acquire a first instruction and a second instruction; wherein, the first instruction is an instruction carrying first configuration data sent by a control unit, and the second instruction is an instruction carrying second configuration data stored locally, and the control unit is externally connected to the SPI driver module and is located on the SPI host;
[0029] A determination module, configured to determine a dependency relationship between the first instruction and the second instruction according to the first configuration data and the second configuration data;
[0030] A combined sending module, configured to, when the dependency relationship is a specified type of dependency relationship, combine the first instruction and the second instruction into a single instruction, and send the single instruction to an SPI slave outside the SPI host.
[0031] According to a fourth aspect of the present application, there is provided an interface circuit, including the instruction processing apparatus described in the third aspect.
[0032] An instruction processing method provided by the present application, which is applied to an SPI driver module on an SPI host, and the method includes: acquiring a first instruction and a second instruction; wherein, the first instruction is an instruction carrying first configuration data sent by a control unit, and the second instruction is an instruction carrying second configuration data stored locally, and the control unit is externally connected to the SPI driver module and is located on the SPI host; determining a dependency relationship between the first instruction and the second instruction according to the first configuration data and the second configuration data; when the dependency relationship is a specified type of dependency relationship, combining the first instruction and the second instruction into a single instruction, and sending the single instruction to an SPI slave outside the SPI host.
[0033] By combining the first instruction and the second instruction into a single instruction, the present application reduces the instruction overhead of the SPI driver module on the SPI host, thereby improving the efficiency of reading and writing the SPI slave.
[0034] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become easily understood through the following description. Description of the Drawings
[0035] The drawings here are incorporated into the description and form a part of this description, showing embodiments consistent with the present application, and are used together with the description to explain the principles of the present application.
[0036] Figure 1Schematic structural diagram of an SPI host provided by an embodiment of the present application;
[0037] Figure 2 Schematic structural diagram of another SPI host provided by an embodiment of the present application;
[0038] Figure 3 Schematic flowchart of an instruction processing method provided by an embodiment of the present application;
[0039] Figure 4 Schematic flowchart of a write instruction processing method provided by an embodiment of the present application;
[0040] Figure 5 Schematic flowchart of a read instruction processing method provided by an embodiment of the present application;
[0041] Figure 6 Schematic structural diagram of an instruction processing device provided by an embodiment of the present application.
[0042] Through the above-mentioned drawings, specific embodiments of the present application have been shown, and more detailed descriptions will be given later. These drawings and textual descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed implementation manners
[0043] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application.
[0044] In the traditional design method, the size of the FIFO limits the read and write efficiency, and the SPI Master needs to judge the empty and full states of the FIFO during the read and write processes. When the FIFO is full, the above-mentioned read and write processes are suspended until the FIFO is half full before the read and write processing resumes. Even though the SPI Master can operate at high frequencies, the waiting generated during the read and write processes due to the operation of judging the empty and full states of the FIFO also affects the efficiency of reading and writing the SPI slave. However, there is a problem of low efficiency in reading and writing the SPI slave.
[0045] To solve the above technical problems, the overall inventive concept of the present application is how to provide an instruction processing method applied to the semiconductor field, which reduces the instruction overhead of the SPI driver module by merging the first instruction and the second instruction into a single instruction, thereby improving the efficiency of reading and writing the SPI slave.
[0046] The technical solution of the present application and how the technical solution of the present application solves the above technical problems will be described in detail below with specific embodiments. The following several specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below with reference to the accompanying drawings.
[0047] Embodiment 1:
[0048] In order to solve the read / write waiting problem caused by the judgment process when using FIFO in the prior art, and also to avoid frequent read / write operations on the Flash outside the SPI host, in this embodiment, the FIFO is replaced with a cache Cache design. According to the dependency relationship of the previous and subsequent read / write erase instructions, a read / write erase mechanism of an instruction-dependent cache (including instruction execution strategies corresponding to different dependency relationships) is designed. Even if the previous instruction has not finished operating in the SPI driver module, the SPI Master can receive the next instruction (i.e., an instruction relative to the previous instruction), and at the same time, according to the dependency relationship before and after the instruction, the instruction and address overhead required for the next instruction can be saved.
[0049] Figure 1 It is a schematic structural diagram of an SPI host provided by an embodiment of the present application. As Figure 1 shown, the SPI host 100 includes: a control unit 1 and an SPI driver module 2. Among them, the SPI host 100 can adopt an Image Signal Processor (ISP) chip, or can also adopt other types of chips. The present application does not make a specific limitation on the chip type adopted by the SPI host 100. The control unit 1 can refer to a Microcontroller Unit (MCU), or can also refer to other types of control units. The present application also does not make a specific limitation on this. The SPI driver module 2 adopts an instruction-dependent cache architecture. The instruction-dependent cache architecture provides multiple dependency relationships and instruction execution strategies corresponding to the dependency relationships. The SPI driver module 2, also known as the SPI Master, can perform read / write erase operations according to the instruction execution strategies corresponding to the dependency relationships. The specific description is shown in the following Embodiments 2 and 3 and will not be repeated here. Among them, the dependency relationships include specified type dependency relationships, non-instruction type dependency relationships, and no dependency relationships, and the instruction execution strategy corresponding to the specified type dependency relationship is to merge instructions.
[0050] As Figure 1 shown, in this embodiment, the communication between the SPI host 100 and the SPI slave is realized through the communication between the SPI driver module 2 and the SPI receiving module. The SPI slave can refer to an SPI Flash.
[0051] In this embodiment, the SPI driver module 2 communicating with the SPI slave makes different decisions based on the dependency relationship between the front and rear instructions. Based on this, by adopting the SPI driver module with the above-mentioned instruction-dependent cache architecture in the embodiments of the present application, the first instruction and the second instruction can be merged into a single instruction, which reduces the instruction overhead of the SPI driver module and thus improves the efficiency of reading and writing the SPI slave.
[0052] In a possible implementation, as Figure 2 shown, the SPI driver module 2 includes: an instruction register 21, an address register 22, a configuration register 23, an instruction judgment unit 24, an address judgment unit 25, an instruction control unit 26, a cache 27, and an SPI driver unit 28. Among them, the cache 27 can be a Static Random-Access Memory (SRAM).
[0053] When the control unit 1 sends an instruction to the SPI Flash through the SPI driver module 2, the instruction (i.e., read instruction, write instruction, or erase instruction), address, read / write length, and data are configured in advance; among them, the instruction, address, and read / write length are configured through the corresponding registers, and the data is sent to the SPI Flash after being buffered by the storage unit (i.e., the above-mentioned cache 27). In order to confirm the dependency relationship between the front and rear instructions, this embodiment retains the instruction, address, and read / write length stored in the previous instruction register, and judges them with the current instruction (i.e., the next instruction relative to the previous instruction, or this instruction).
[0054] Specifically, the previous instruction is stored in the instruction register 21, the address of the previous instruction is stored in the address register 22, and the configuration data such as the instruction length of the previous instruction is stored in the configuration register 23; the instruction judgment unit 24 is used to judge the current instruction type and whether the current instruction and the previous instruction are both read instructions or both write instructions; the address judgment unit 25 is used to judge whether the current instruction address is equal to the sum of the previous instruction address and the previous instruction length.
[0055] In this embodiment, the judgment of instructions and the judgment of addresses are not limited to between two instructions, and can also be between three instructions, four instructions, etc. For example, instructions A, B, and C arranged in sequence are all write instructions, and the instruction judgment result is that all three instructions are write instructions; the address judgment result is that the addresses of the three instructions are arranged in sequence; at this time, the instruction control unit can be provided with a corresponding instruction execution strategy to merge these three instructions into a single instruction.
[0056] The instruction control unit 26 receives the instruction judgment result uploaded by the instruction judgment unit 24 and the address judgment result uploaded by the address judgment unit 25, determines the dependency relationship between two instructions according to these two judgment results, and then according to the instruction execution strategy corresponding to the dependency relationship, sends the instructions to the SPI Flash through the cache 27 and the SPI driver unit 28.
[0057] That is to say, the previous instruction, its address, and the configured read / write length are all stored in the corresponding registers for comparison with the relevant configurations of the next instruction. After passing through the instruction judgment unit 24 and the address judgment unit 25, the instruction control unit determines the dependency relationship between the two instructions, and then performs corresponding cache or instruction merging operations; finally, all instructions, addresses, data, etc. will be sent to the SPI Flash by the SPI driver unit 28 according to the SPI timing. It should be noted that the size of the cache area and the content of each instruction execution strategy can be designed according to the characteristics of the stored data.
[0058] In addition, when the data corresponding to the current read instruction does not exceed the data corresponding to the previous write instruction, in this embodiment, the data corresponding to the current read instruction can be directly obtained from the cache 27 without reading from the SPI Flash, further reducing the instruction overhead of the SPI driver module.
[0059] Based on the above embodiments, the technical solution of the present application will be described in more detail below in combination with several specific embodiments.
[0060] Embodiment 2:
[0061] Figure 3 It is a flowchart of an instruction processing method provided by an embodiment of the present application. As Figure 3 shown, the method of this embodiment is applied to the SPI driver module on the SPI host and includes the following steps:
[0062] S10. Obtain a first instruction and a second instruction; wherein, the first instruction is an instruction carrying first configuration data sent by the control unit, and the second instruction is an instruction carrying second configuration data stored locally. The control unit is externally connected to the SPI driver module and is located on the SPI host.
[0063] It should be understood that any one of the first configuration data and the second configuration data includes, but is not limited to: instruction type, address, instruction length, etc. The instruction type includes, but is not limited to: read instruction, write instruction, erase instruction, etc., and the address can be the address of the starting position. The first instruction can be understood as the current instruction or the next instruction; the second instruction can be understood as the previous instruction. That is to say, the first instruction is later than the second instruction in terms of timing.
[0064] S20. Determine the dependency relationship between the first instruction and the second instruction according to the first configuration data and the second configuration data.
[0065] In this embodiment, the following several dependency relationships are preset for two adjacent instructions: the dependency relationship of a specified type, the dependency relationship of a non-specified type, no dependency relationship, and a mixed dependency relationship. The specific description of this step is given below and will not be elaborated here.
[0066] S30. When the dependency relationship is the dependency relationship of a specified type, merge the first instruction and the second instruction into a single instruction, and send the single instruction to the SPI slave outside the SPI host.
[0067] In the embodiments of the present application, different instruction execution policies are set for different types of dependency relationships. Specifically, for the dependency relationship of a specified type, the corresponding instruction execution policy is to merge instructions; for the dependency relationship of a non-specified type, the corresponding instruction execution policy is to process instructions based on a cache; for no dependency relationship, the corresponding instruction execution policy is to execute instructions sequentially.
[0068] In the embodiments of the present application, by merging the first instruction and the second instruction into a single instruction, the instruction overhead of the SPI driver module is reduced, thereby improving the efficiency of reading and writing the SPI slave.
[0069] Based on the above steps S10 to S30, this embodiment describes this solution in detail:
[0070] As shown in Table 1, in this embodiment, the following several dependency relationships are preset for two adjacent instructions: the dependency relationship of a specified type, the dependency relationship of a non-specified type, no dependency relationship, and a mixed dependency relationship.
[0071] Table 1 Dependency Relationship and Instruction Execution Policy
[0072]
[0073] In a possible implementation, the first configuration data includes at least one of a first instruction type, a first address, and a first instruction length; the second configuration data includes at least one of a second instruction type, a second address, and a second instruction length.
[0074] Since the first instruction type and the second instruction type both include but are not limited to: read instruction, write instruction, erase instruction, etc., there are the following 9 types of instruction type relationships: Read After Read (RAR), Write After Write (WAW), Write After Read (WAR), Write After Erase (WAE), Erase After Read (EAR), Read After Write (RAW), Read After Erase (RAE), Erase After Write (EAW), and Erase After Erase (EAE).
[0075] Among them, the two instruction type relationships of Read After Read and Write After Write can correspond to the dependency relationships of the instruction types in the following first and second; they can also correspond to the non-dependency relationships in the following fifth and sixth.
[0076] The three instruction type relationships of Write After Read, Write After Erase, and Erase After Read correspond to the non-specified type dependency relationships in the following third and ninth.
[0077] The four instruction type relationships of Read After Write, Erase After Write, Read After Erase, and Erase After Erase can correspond to the non-dependency relationships in the following seventh and eighth.
[0078] Embodiments of the present application will describe this in detail: Step S20, determining the dependency relationship between the first instruction and the second instruction according to the first configuration data and the second configuration data, including but not limited to any one of the following:
[0079] First, when both the first instruction type and the second instruction type are read data instructions, and the first address is the sum of the second address and the second instruction length, determine that the dependency relationship between the first instruction and the second instruction is a specified type of dependency relationship.
[0080] After determining that the dependency relationship between the first instruction and the second instruction is a specified type of dependency relationship, this embodiment can execute the instruction execution strategy of the merge read instruction (both the merge read instruction and the following merge write instruction belong to merge instructions), and this strategy has the following advantages:
[0081] For read instructions, the overhead for each instruction is 8-bit instruction and 24-bit address. Special read instructions also have 8-bit placeholder data. Each time read instructions are merged, at least 32-bit overhead can be saved. In addition, by using a cache with a larger storage space and superimposing the operation of merging read instructions, the problem of the maximum read length limit for read instructions that occurs when using a FIFO can be solved. When the read length is determined to be reading a large amount of data, this embodiment can also pre-extract the data to be written to the SPI slave from the cache later, reducing the number of times of reading data from the SPI slave subsequently.
[0082] Second, when both the first instruction type and the second instruction type are write data instructions, and the first address is the sum of the second address and the second instruction length, determine that the dependency relationship between the first instruction and the second instruction is a specified type of dependency relationship.
[0083] After determining that the dependency relationship between the first instruction and the second instruction is a specified type of dependency relationship, this embodiment can execute an instruction execution strategy for merging write instructions, and this strategy has the following advantages:
[0084] For write instructions, 8-bit write enable instructions, 8-bit instructions, and 24-bit addresses are required before each instruction. Each time write instructions are merged, at least 32-bit overhead can be saved. After a write instruction is completed, it is usually necessary to wait for the status bit of the Flash to be idle before writing again. Merging write instructions can not only reduce 32-bit overhead, but also reduce the waiting idle time between the first instruction and the second instruction. In the prior art, when using a FIFO, the next instruction must wait until the previous write instruction is completely finished. In contrast, in this embodiment under an instruction-dependent cache architecture, the data of the next instruction that satisfies the specified type of dependency relationship can be entered into the cache behind the data of the previous instruction.
[0085] In summary, for the specified type of dependency relationship, which involves the two instruction type relationships of read-after-read and write-after-write, the instruction execution strategy is to merge instructions. The operation of merging instructions can reduce the overhead when the SPI driver module sends instructions to the SPI slave, and at the same time reduce the time for the first instruction to wait for the SPI slave to become idle after the second instruction ends.
[0086] In a possible implementation manner, in step S30, merging the first instruction and the second instruction into a single instruction and sending the single instruction to the SPI slave outside the SPI host includes:
[0087] S301. When both the first instruction type and the second instruction type are write data instructions, merge the first configuration data and the second configuration information to obtain merged configuration data, and merge the data to be written carried in the first instruction and the data to be written carried in the second instruction to obtain merged data.
[0088] S302. After caching the merged data according to the merged configuration data, send it to the SPI slave outside the SPI host.
[0089] This embodiment provides a specific merging method. The operation of this merging instruction can reduce the overhead when the SPI driver module sends instructions to the SPI slave, and at the same time reduce the time for the SPI slave to resume idle after the first instruction waits for the second instruction to end.
[0090] In a possible implementation, step S20. Determine the dependency relationship between the first instruction and the second instruction according to the first configuration data and the second configuration data, and includes but is not limited to any of the following:
[0091] Third. When the first instruction type is a read data instruction, the second instruction type is an erase data instruction or a write data instruction, the first address is between the second address and the third address, and the length of the first instruction does not exceed the length of the second instruction, determine that the dependency relationship between the first instruction and the second instruction is a non-specified type of dependency relationship; where the third address is the sum of the second address and the length of the second instruction.
[0092] Among them, for the instruction type relationship of read after erase, the corresponding instruction execution strategy in this embodiment is: judge whether to read the data at the same address after erasing. If so, it can be considered that the address has been completely erased, and the data is output by counting and outputting a high level. That is to say, directly output a high level according to the read length count after the erase instruction is executed, which can also be regarded as an operation of reading all 1s in the data of the SPI slave.
[0093] For the instruction type relationship of read after write, the corresponding instruction execution strategy in this embodiment is: when the next instruction is a read instruction after the previous write instruction ends, first judge whether the address range is stored in the cache. If all the data to be read is in the cache, the data written by the previous instruction can be directly read from the cache. If a part of it is in the SPI slave, first output the data in the cache, and at the same time send the instruction to the SPI slave to obtain the other part of the data that does not exist in the cache.
[0094] In summary, after determining that the dependency relationship between the first instruction and the second instruction is a non-specified type of dependency relationship, the process of processing instructions based on the cache in this embodiment is as follows:
[0095] For non-specified types of dependencies, which involve the relationships between write-after-read and erase-after-read instruction types, the instruction execution strategy corresponding to the former is to directly read the data carried in the previous write instruction from the cache, and the instruction execution strategy corresponding to the latter is to implement counting in the cache and output data all of which are 1 to the micro control unit. Neither of the two instruction execution strategies executed by the SPI driver module performs a read operation on the SPI slave. The read operation of reading data from the cache has the advantage of faster reading speed.
[0096] Fourthly, when the first instruction type is a read data instruction, the second instruction type is an erase data instruction or a write data instruction, the first address is between the second address and the third address, and the length of the first instruction exceeds the length of the second instruction, it is determined that the dependency relationship between the first instruction and the second instruction is a mixed dependency relationship; among them, the mixed dependency relationship includes non-specified type dependency relationships and no-dependency relationships.
[0097] This application provides the diversity of dependency relationships, providing technical support for further improving the efficiency of reading and writing the SPI slave.
[0098] In a possible implementation, after determining the dependency relationship between the first instruction and the second instruction, the method further includes the following step S40 or step S50:
[0099] S40. When the dependency relationship is a non-specified type of dependency relationship and the length of the first instruction does not exceed the length of the second instruction, read the data corresponding to the first instruction from the local cache.
[0100] S50. When the dependency relationship is a mixed dependency relationship and the length of the first instruction exceeds the length of the second instruction, read the data of the part that does not exceed the length of the second instruction from the local cache, and read the data of the part that exceeds the length of the second instruction from the SPI slave outside the SPI host.
[0101] For the mixed dependency relationship, in this embodiment, part of the data is read from the cache according to the instruction execution strategy corresponding to the non-specified type of dependency relationship; another part of the data is read from the SPI slave according to the instruction execution strategy corresponding to the no-dependency relationship.
[0102] The embodiments of this application can use a cache with a larger storage space to extract the data to be written to the SPI slave subsequently from the cache, reduce the number of times of reading data from the SPI slave subsequently, and extend the service life of the SPI slave.
[0103] In a possible implementation, when sending a single instruction to the SPI slave of the SPI host, the method further includes:
[0104] S60. Send the checksum corresponding to the merged data to the SPI slave, so that the SPI slave can determine whether there is packet loss in the transmission process of the merged data according to the checksum.
[0105] In this embodiment, considering whether the data after erasing and writing by the SPI slave is correct, a data verification unit can be introduced into the SPI driver module to verify the quality of data communication.
[0106] Optionally, step S20. Determine the dependency relationship between the first instruction and the second instruction according to the first configuration data and the second configuration data, and further includes but is not limited to any of the following:
[0107] Fifth. When the first instruction type and the second instruction type are both read data instructions, and the first address is not the sum of the second address and the second instruction length, determine that the dependency relationship between the first instruction and the second instruction is no dependency relationship.
[0108] Sixth. When the first instruction type and the second instruction type are both write data instructions, and the first address is not the sum of the second address and the second instruction length, determine that the dependency relationship between the first instruction and the second instruction is no dependency relationship.
[0109] When the previous instruction and the next instruction are both write instructions but do not meet the specified type of dependency relationship, the data of the next instruction can also use the cache as a buffer area. After the previous write instruction ends, the SPI driver module sends another write instruction, which also reduces the number of write operations to the SPI slave, thereby extending the service life of the SPI slave.
[0110] Optionally, step S20. Determine the dependency relationship between the first instruction and the second instruction according to the first configuration data and the second configuration data, and further includes but is not limited to any of the following:
[0111] Seventh. When the first instruction type is a write data instruction and the second instruction type is an erase data instruction or a read data instruction, determine that the dependency relationship between the first instruction and the second instruction is no dependency relationship;
[0112] Eighth. When the first instruction type is an erase data instruction and the second instruction type is an erase data instruction or a read data instruction, determine that the dependency relationship between the first instruction and the second instruction is no dependency relationship.
[0113] Among them, no dependency means that there is no dependency between the front and rear instructions, and no special operation needs to be performed on the first instruction. Therefore, read-after-write, read-after-erase, and write-after-erase cannot generate dependencies between the front and rear, so these instruction type relationships all correspond to no dependencies. Since the erase instruction of the SPI slave has a fixed erase range: 32KB, 64KB, the entire sector (this sector refers to the area on the disk of the SPI master) or the entire SPI master, and there are different 8-bit erase instructions for each erase range, the write-after-erase instruction cannot form a front-to-back dependency relationship, so the write-after-erase is also classified as having no dependency.
[0114] In addition, this embodiment can also provide: Ninth, when the first instruction type is an erase data instruction and the second instruction type is a write data instruction, it is determined that the dependency relationship between the first instruction and the second instruction is a non-specified type of dependency relationship.
[0115] For the non-specified type of dependency relationship, the instruction type relationship of write-after-erase involved therein corresponds to an instruction execution strategy of determining whether an erase operation is performed on the same address after the previous write instruction. If so, the content of the same address stored in the cache is cleared, which can maintain the consistency between the cache and the content stored in the SPI slave.
[0116] In this embodiment, read-after-write, write-after-erase, etc. are all typical cache operations, that is, the cache is directly operated after the write instruction.
[0117] Embodiment 3:
[0118] In this embodiment, the following analysis is performed on the specified type of dependency relationship:
[0119] (1) If the front and rear instructions are both write instructions and the addresses of the front and rear instructions are consecutive, then this embodiment can merge the two front and rear write instructions, thereby reducing the overhead of instructions, addresses, and the waiting time after the SPI driver module sends an instruction.
[0120] (2) If the front and rear instructions are both read instructions and the addresses of the front and rear instructions are consecutive, then this embodiment can merge the two front and rear read instructions, thereby reducing the overhead of instructions, addresses, and the waiting time after the SPI driver module sends an instruction.
[0121] This embodiment combines Figure 4 The following analysis is performed on the first case:
[0122] Figure 4 It is a schematic flow diagram of the write instruction processing method provided by the embodiment of the present application. As Figure 4 shown, the method of this embodiment includes the following steps:
[0123] S41. Obtain a write instruction.
[0124] S42. Determine whether the previous instruction is a write instruction. If not, execute step S43; if so, execute step S44.
[0125] S43. Determine that the dependency relationship between the write instruction and the previous instruction is no dependency relationship. After executing step S43, execute step S46.
[0126] S44. Determine whether the address of the write instruction is equal to the sum of the address of the previous instruction and the write length of the previous instruction. If not, execute step S43; if so, execute step S45.
[0127] S45. Merge the write instruction and the previous instruction into a single instruction.
[0128] S46. Write the data to be written into the cache and then start storing it in the Flash.
[0129] According to the above process, when a write instruction is received, first determine whether the previous instruction is a write instruction. When the previous instruction is also a write instruction, then continue to determine whether the address of the new instruction is after the end address of the previous write instruction. If both conditions are met, this instruction and the previous instruction can be merged, and the data is stored in the cache waiting to be stored in the Flash together. If any one of the conditions is not met, it is considered an instruction without dependency. The data first enters the cache for buffering, and after the previous instruction is completed, the SPI driver unit 28 starts to execute this instruction.
[0130] For the instruction type relationship of write-after-write, in this embodiment, each time a write instruction is sent to the SPI slave, a 2-byte write enable instruction needs to be sent first, and then a 2-byte write instruction, 3 bytes, and write data (the length of the data is set customarily) are sent. When a new write instruction comes after the previous write instruction ends and the address offset range is the same, if the previous write instruction does not exceed the maximum writable data volume, this embodiment can merge the next read instruction with the previous read instruction. At the same time, the write data is stored in the cache, and the address position is placed after the previous write data waiting to be written into the Flash. Even if the address is not consecutive after determination, the cache can also be used as a buffer for the next write instruction, enabling the SPI driver module to receive the next instruction before the previous write instruction ends.
[0131] This embodiment combines Figure 5 Analyze the second case as follows:
[0132] Figure 5 is a schematic flow diagram of the read instruction processing method provided by the embodiment of the present application. As Figure 5 shown, the method of this embodiment includes the following steps:
[0133] S51. Obtain the read instruction.
[0134] S52. Determine whether the previous instruction is a read instruction. If so, execute step S53; if not, execute step S55.
[0135] S53. Determine whether the address of the read instruction is equal to the sum of the address of the previous instruction and the write length of the previous instruction. If so, execute step S54; if not, execute step S59.
[0136] S54. Determine that the dependency relationship between the read instruction and the previous instruction is a dependency relationship of instruction types, and read data from the cache.
[0137] S55. Determine whether the address of the read instruction is within the operation range of the previous instruction. If so, execute step S56; if not, execute step S59.
[0138] S56. Determine whether the read length exceeds the operation length of the previous instruction. If not, execute step S57; if so, execute step S58.
[0139] S57. Determine that the dependency relationship between the read instruction and the previous instruction is a non-specified type of dependency relationship, and read data from the cache.
[0140] S58. Determine that the dependency relationship between the non-exceeding part and the previous instruction is a non-specified type of dependency relationship, and read the data of the non-exceeding part from the cache; determine that the dependency relationship between the exceeding part and the previous instruction is a non-dependency relationship, and for the data of the exceeding part, execute step S59.
[0141] S59. Send an instruction to read data from the Flash.
[0142] According to the above process, when a read instruction arrives, in this embodiment, first determine whether the previous instruction is a read instruction. When the previous instruction is also a read instruction, then continue to determine whether the address of the new instruction (i.e., this instruction) is after the end address of the previous read instruction. If so, this embodiment combines this instruction and the previous read instruction; if not, this embodiment determines that there is no dependency relationship between the two instructions. When the previous instruction is not a read instruction, then determine whether the current address is within the operation range of the previous instruction (i.e., the address range written or erased by the previous instruction in the SPI slave). If not, determine that there is no dependency relationship between the two instructions, and execute these two instructions successively. And when executing this instruction, send an instruction to read data from the Flash.
[0143] If it is within the operation range, then further determine whether the read length of the current read instruction exceeds the end address of the previous instruction. The non-exceeding part is determined to be the non-instruction type of dependency relationship corresponding to read after erase or read after write, and the exceeding part is considered to have no dependency relationship. For the part with no dependency relationship, this embodiment directly sends an instruction to read data from the SPI slave.
[0144] When the prior art uses a FIFO, the read data length of a single read instruction is limited by the FIFO depth. When the FIFO is full, the data read back from the Flash cannot wait for the FIFO to return to half full again. Therefore, the data read back will be lost when the FIFO is full, and only the maximum read length can be set for each read instruction. When exceeding this length, a new read instruction must be sent again. For example, when the FIFO depth is 16 words, one instruction can only read 32 bytes. To avoid this situation, in this embodiment, the FIFO is replaced with a cache having a larger storage space, and then by determining whether there is a dependency relationship of a specified type between the previous and subsequent instructions, if so, the read instructions are merged to further reduce the overhead of 8-bit instructions and 24-bit addresses.
[0145] Embodiment 4:
[0146] Figure 6 It is a schematic structural diagram of an instruction processing device provided by an embodiment of the present application. The device of this embodiment can be in the form of software and / or hardware. As Figure 6 shown, the instruction processing device provided by this embodiment includes: an acquisition module 61, a determination module 62, and a combined transmission module 63. Among them:
[0147] The acquisition module 61 is used to acquire a first instruction and a second instruction; wherein, the first instruction is an instruction carrying first configuration data sent by a control unit, and the second instruction is an instruction carrying second configuration data stored locally. The control unit is externally connected to an SPI driver module and is located on an SPI host.
[0148] The determination module 62 is used to determine the dependency relationship between the first instruction and the second instruction according to the first configuration data and the second configuration data.
[0149] The combined transmission module 63 is used to, when the dependency relationship is a specified type of dependency relationship, combine the first instruction and the second instruction into a single instruction, and send the single instruction to an SPI slave outside the SPI host.
[0150] In a possible implementation manner, the first configuration data includes at least one of a first instruction type, a first address, and a first instruction length; the second configuration data includes at least one of a second instruction type, a second address, and a second instruction length; then the determination module 62 is further used for:
[0151] When both the first instruction type and the second instruction type are read data instructions, and the first address is the sum of the second address and the second instruction length, it is determined that the dependency relationship between the first instruction and the second instruction is a specified type of dependency relationship.
[0152] Alternatively, when both the first instruction type and the second instruction type are write data instructions, and the first address is the result of adding the second address and the second instruction length, determine that the dependency relationship between the first instruction and the second instruction is a specified type of dependency relationship.
[0153] In a possible implementation, the merging and sending module 63 is further configured to:
[0154] When both the first instruction type and the second instruction type are write data instructions, merge the first configuration data and the second configuration information to obtain merged configuration data, and merge the data to be written carried in the first instruction and the data to be written carried in the second instruction to obtain merged data.
[0155] According to the merged configuration data, after caching the merged data, send it to the SPI slave outside the SPI host.
[0156] In a possible implementation, the decision-making module 62 is further configured to:
[0157] When the first instruction type is a read data instruction, the second instruction type is an erase data instruction or a write data instruction, the first address is between the second address and the third address, and the first instruction length does not exceed the second instruction length, determine that the dependency relationship between the first instruction and the second instruction is a non-specified type of dependency relationship; where the third address is the result of adding the second address and the second instruction length.
[0158] Alternatively, when the first instruction type is a read data instruction, the second instruction type is an erase data instruction or a write data instruction, the first address is between the second address and the third address, and the first instruction length exceeds the second instruction length, determine that the dependency relationship between the first instruction and the second instruction is a mixed dependency relationship; where the mixed dependency relationship includes a non-specified type of dependency relationship and a non-dependency relationship.
[0159] In a possible implementation, after determining the dependency relationship between the first instruction and the second instruction, the instruction processing device is further configured to:
[0160] In the case where the dependency relationship is a non-specified type of dependency relationship and the first instruction length does not exceed the second instruction length, read the data corresponding to the first instruction from the local cache.
[0161] In the case where the dependency relationship is a mixed dependency relationship and the first instruction length exceeds the second instruction length, read the data of the part that does not exceed the second instruction length from the local cache, and read the data of the part that exceeds the second instruction length from the SPI slave outside the SPI host.
[0162] In a possible implementation, the instruction processing device is further configured to:
[0163] Send the check code corresponding to the merged data to the SPI slave, so that the SPI slave can determine whether there is packet loss during the transmission of the merged data according to the check code.
[0164] The instruction processing device provided in this embodiment can be used to execute the instruction processing method provided in any of the above method embodiments. The implementation principles and technical effects are similar and will not be elaborated here.
[0165] An embodiment of the present application provides an SPI master, including an SPI driver module and a control unit for executing the above method embodiments.
[0166] This embodiment also provides an interface circuit, including the instruction processing device in the above embodiment.
[0167] It should be understood that various forms of processes shown above can be used, steps can be reordered, added or deleted. For example, the steps recorded in the disclosure of the present application can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in the present application can be achieved. There is no limitation here.
[0168] The above specific implementation manners do not constitute a limitation to the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the principles of the present application shall be included within the protection scope of the present application.
Claims
1. An instruction processing method, characterized in that, An SPI driver module applied to an SPI host, the method includes: Obtain a first instruction and a second instruction; wherein, the first instruction is an instruction carrying first configuration data sent by a control unit, and the second instruction is an instruction carrying second configuration data stored locally. The control unit is externally connected to the SPI driver module and is located on the SPI host; Determine the dependency relationship between the first instruction and the second instruction according to the first configuration data and the second configuration data; When the dependency relationship is a specified type of dependency relationship, merge the first instruction and the second instruction into a single instruction, and send the single instruction to an SPI slave outside the SPI host.
2. The method according to claim 1, characterized in that, The first configuration data includes at least one of a first instruction type, a first address, and a first instruction length; the second configuration data includes at least one of a second instruction type, a second address, and a second instruction length; Then, determining the dependency relationship between the first instruction and the second instruction according to the first configuration data and the second configuration data includes: When both the first instruction type and the second instruction type are read data instructions, and the first address is the sum of the second address and the second instruction length, determine that the dependency relationship between the first instruction and the second instruction is a specified type of dependency relationship; Or, When both the first instruction type and the second instruction type are write data instructions, and the first address is the sum of the second address and the second instruction length, determine that the dependency relationship between the first instruction and the second instruction is a specified type of dependency relationship.
3. The method according to claim 2, characterized in that, Merging the first instruction and the second instruction into a single instruction and sending the single instruction to an SPI slave outside the SPI host includes: When both the first instruction type and the second instruction type are write data instructions, merge the first configuration data and the second configuration information to obtain merged configuration data, and merge the data to be written carried in the first instruction and the data to be written carried in the second instruction to obtain merged data; According to the merged configuration data, send the merged data to an SPI slave outside the SPI host after caching.
4. The method according to claim 2, characterized in that, Determining the dependency relationship between the first instruction and the second instruction according to the first configuration data and the second configuration data includes: When the first instruction type is a read data instruction, the second instruction type is an erase data instruction or a write data instruction, the first address is between the second address and the third address, and the first instruction length does not exceed the second instruction length, determine that the dependency relationship between the first instruction and the second instruction is a non-specified type of dependency relationship; wherein, the third address is the sum of the second address and the second instruction length; Or, When the first instruction type is a read data instruction, the second instruction type is an erase data instruction or a write data instruction, the first address is located between the second address and the third address, and the length of the first instruction exceeds the length of the second instruction, determine that the dependency relationship between the first instruction and the second instruction is a mixed dependency relationship; wherein, the mixed dependency relationship includes a non-specified type of dependency relationship and a non-dependency relationship.
5. The method according to claim 4, characterized in that, After determining the dependency relationship between the first instruction and the second instruction, the method further includes: When the dependency relationship is the non-specified type of dependency relationship and the length of the first instruction does not exceed the length of the second instruction, read the data corresponding to the first instruction from the local cache. When the dependency relationship is the mixed dependency relationship and the length of the first instruction exceeds the length of the second instruction, read the data that does not exceed the length of the second instruction from the local cache, and read the data that exceeds the length of the second instruction from the SPI slave outside the SPI host.
6. The method according to claim 3, characterized in that, When sending the single instruction to the SPI slave outside the SPI host, the method further includes: Send the check code corresponding to the merged data to the SPI slave, so that the SPI slave can determine whether there is a packet loss in the transmission process of the merged data according to the check code.
7. An SPI host, characterized in that, Includes an SPI driver module and a control unit for executing the instruction processing method according to any one of the above claims 1 to 6.
8. An instruction processing device, characterized in that, Includes: An SPI driver module applied to the SPI host, the device includes: An acquisition module for acquiring a first instruction and a second instruction; wherein, the first instruction is an instruction carrying first configuration data sent by the control unit, the second instruction is an instruction carrying second configuration data stored locally, and the control unit is externally connected to the SPI driver module and is located on the SPI host. A judgment module for determining the dependency relationship between the first instruction and the second instruction according to the first configuration data and the second configuration data. A merge and send module for merging the first instruction and the second instruction into a single instruction and sending the single instruction to the SPI slave outside the SPI host when the dependency relationship is a specified type of dependency relationship.
9. An interface circuit, characterized in that, Includes the instruction processing device according to claim 8.