Data transmission method, apparatus and storage medium

Abstract

This disclosure relates to the field of data transmission technology, proposing a data transmission method, apparatus, and storage medium. The method can be used in a GPU's copy engine. The method includes: in response to a target data block in target data satisfying preset conditions, writing the target data block from a source address to a destination address based on a descriptor corresponding to the target data, wherein the target data consists of multiple data blocks; in response to the target data block being written from the source address to the destination address, writing a first preset value to a position associated with the target data block in the first fence information of the descriptor, wherein the first preset value indicates that the target data block can be processed by the hardware unit where the destination address is located or forwarded to the target hardware unit. According to embodiments of this application, a pipeline can be formed between the CE and the hardware unit, or between multiple CEs, greatly improving data processing efficiency. Furthermore, multiple data blocks can be transmitted using only one descriptor each time target data is transmitted, improving CE performance.

Description

Technical Field

[0001] This disclosure relates to the field of data processing technology, and in particular to a data transmission method, apparatus and storage medium. Background Technology

[0002] In computer systems, the copy engine (CE) is a key component for handling data copying operations. As a direct memory access (DMA) controller within the graphics processing unit (GPU), the CE copies data from the memory of one device or the current device to the memory of another device, and then transfers the data to the GPU of the target device for further processing. However, in current technologies, when the CE needs to transfer a large amount of data, the GPU of the target device must wait for the CE to complete the transfer before it can begin processing, resulting in low data processing efficiency. Summary of the Invention

[0003] In view of this, the present disclosure provides a data transmission method, apparatus and storage medium.

[0004] According to one aspect of this disclosure, a data transfer method is provided. This method can be used in the copy engine of a graphics processing unit (GPU), and includes:

[0005] In response to the target data block in the target data meeting the preset conditions, the target data block is written from the source address to the destination address based on the descriptor corresponding to the target data. The target data consists of multiple data blocks. The preset conditions include that the previous data block of the target data block has been written to the destination address or that the target data block is the first data block in the target data.

[0006] In response to the target data block being written from the source address to the destination address, a first preset value is written to the location associated with the target data block in the first fence information of the descriptor. The first preset value indicates that the target data block can be processed by the hardware unit where the destination address is located or forwarded to the target hardware unit. The first fence is a storage space of a preset size.

[0007] In one possible implementation, in response to the second fence information of the descriptor, the position associated with the target data block is written to a second preset value, determining that the target data block meets the preset conditions, and the second fence is a storage space of a preset size.

[0008] In one possible implementation, the descriptor may also include one or more of the following parameters: source address information, destination address information, size of the target data, and size of each data block in the target data.

[0009] In one possible implementation, being forwarded to the target hardware unit includes forwarding from the hardware unit where the destination address is located to the target hardware unit via other hardware units besides the hardware unit where the destination address is located, or forwarding directly from the hardware unit where the destination address is located to the target hardware unit.

[0010] In one possible implementation, the method further includes:

[0011] In response to the first preset value being written to the location associated with the target data block in the first fence information in the descriptor, the first preset value is written to the location associated with the target data block in the first fence corresponding to the destination address.

[0012] In one possible implementation, the method further includes:

[0013] In response to the fact that the target data has been processed by the hardware unit where the destination address is located or has been forwarded to other hardware units, a second preset value is written to the position associated with the next data block of the target data block in the second fence information of the descriptor, wherein the same destination address is written to each data block in the target data.

[0014] In one possible implementation, in response to the location associated with the next data block of the target data block in the second fence corresponding to the destination address being written with a second preset value, it is determined that the target data block has been processed by the hardware unit where the destination address is located or has been forwarded to other hardware units.

[0015] In one possible implementation, the size of each data block in the target data is related to the time it takes for the hardware unit at the destination address to process the data block, so that the time for transmitting each data block matches the time it takes for the hardware unit at the destination address to process each data block.

[0016] In one possible implementation, the hardware unit includes a graphics processing unit (GPU).

[0017] According to another aspect of this disclosure, a data transmission apparatus is provided. This apparatus can be used in the copying engine of a graphics processing unit (GPU), and the apparatus includes:

[0018] The first writing module is used to write the target data block from the source address to the destination address based on the descriptor corresponding to the target data in response to the target data block meeting the preset conditions. The target data consists of multiple data blocks. The preset conditions include that the previous data block of the target data block has been written to the destination address or that the target data block is the first data block in the target data.

[0019] The second writing module is used to write a first preset value to the location associated with the target data block in the first fence information of the descriptor in response to the target data block having been written from the source address to the destination address. The first preset value indicates that the target data block can be processed by the hardware unit where the destination address is located or forwarded to the target hardware unit. The first fence is a storage space of a preset size.

[0020] In one possible implementation, in response to the second fence information of the descriptor, the position associated with the target data block is written to a second preset value, determining that the target data block meets the preset conditions, and the second fence is a storage space of a preset size.

[0021] In one possible implementation, the descriptor may also include one or more of the following parameters: source address information, destination address information, size of the target data, and size of each data block in the target data.

[0022] In one possible implementation, being forwarded to the target hardware unit includes forwarding from the hardware unit where the destination address is located to the target hardware unit via other hardware units besides the hardware unit where the destination address is located, or forwarding directly from the hardware unit where the destination address is located to the target hardware unit.

[0023] In one possible implementation, the device further includes:

[0024] The third writing module is used to write the first preset value to the location associated with the target data block in the first fence information corresponding to the destination address in response to the first preset value being written to the location associated with the target data block in the first fence information in the descriptor.

[0025] In one possible implementation, the device further includes:

[0026] The fourth writing module is used to write a second preset value to the position associated with the next data block of the target data block in the second fence information of the descriptor in response to the target data being processed by the hardware unit where the destination address is located or being forwarded to other hardware units, wherein each data block in the target data is written with the same destination address.

[0027] In one possible implementation, in response to the location associated with the next data block of the target data block in the second fence corresponding to the destination address being written with a second preset value, it is determined that the target data block has been processed by the hardware unit where the destination address is located or has been forwarded to other hardware units.

[0028] In one possible implementation, the size of each data block in the target data is related to the time it takes for the hardware unit at the destination address to process the data block, so that the time for transmitting each data block matches the time it takes for the hardware unit at the destination address to process each data block.

[0029] In one possible implementation, the hardware unit includes a graphics processing unit (GPU).

[0030] According to another aspect of this disclosure, a data transmission apparatus is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the method described above.

[0031] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the above-described method.

[0032] According to another aspect of this disclosure, a computer program product is provided, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described method.

[0033] According to the embodiments of this application, in response to a target data block in the target data satisfying a preset condition, the target data block is written from the source address to the destination address based on the descriptor corresponding to the target data. The preset condition includes that the previous data block of the target data block has been written to the destination address or that the target data block is the first data block in the target data. In response to the target data block being written from the source address to the destination address, a first preset value is written to the position associated with the target data block in the first fence information of the descriptor. The first preset value indicates that the target data block can be processed by the hardware unit where the destination address is located or forwarded to the target hardware unit. The first fence is a storage space of a preset size, which allows the target data block to perform subsequent operations without waiting for all data blocks in the target data to be written to the destination address. This makes the target data block available for processing by the hardware unit where the destination address is located or forwarded to the target hardware unit, thereby enabling a pipeline to be formed between the CE and the hardware unit or between multiple CEs, greatly improving the efficiency of data processing. Moreover, multiple data blocks can be transmitted using only one descriptor each time the target data is transmitted, improving the performance of the CE.

[0034] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0035] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0036] Figure 1 A schematic diagram illustrating an application scenario of an embodiment of this application is shown.

[0037] Figure 2 A flowchart illustrating a data transmission method according to an embodiment of this application is shown.

[0038] Figure 3 A schematic diagram showing the structure of a descriptor according to an embodiment of this application is provided.

[0039] Figure 4 A schematic diagram of a first fence and a second fence according to an embodiment of this application is shown.

[0040] Figure 5 A structural diagram of a data transmission apparatus according to an embodiment of this application is shown.

[0041] Figure 6 This is a block diagram illustrating an apparatus 1900 for data transmission according to an exemplary embodiment. Detailed Implementation

[0042] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0043] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0044] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0045] In computer systems, the copy engine (CE) is a key component for handling data copying operations. As a direct memory access (DMA) controller within the graphics processing unit (GPU), the CE copies data from the memory of one device or the current device to the memory of another device, and then transfers the data to the GPU of the target device for further processing. However, in current technologies, when the CE needs to transfer a large amount of data, the GPU of the target device must wait for the CE to complete the transfer before it can begin processing, resulting in low data processing efficiency.

[0046] In view of this, this application provides a data transmission method, apparatus, and storage medium. The method of this application can be used on a GPU's CE (Chip Execution Environment), which can divide target data into multiple data blocks to achieve fragmented data transmission. In this application, in response to a target data block in the target data satisfying a preset condition, based on the descriptor corresponding to the target data, the target data block is written from the source address to the destination address. The preset condition includes that the previous data block of the target data block has been written to the destination address or that the target data block is the first data block in the target data. In response to the target data block being written from the source address to the destination address, a first preset value is written to the position associated with the target data block in the first fence information of the descriptor. The first preset value indicates that the target data block can be used by the target data block. The hardware unit where the address is located processes or forwards the data to the target hardware unit. The first fence is a storage space of a preset size, which allows the target data block to be processed or forwarded to the target hardware unit without waiting for all data blocks in the target data to be written to the destination address. After the target data block is written to the destination address, subsequent operations can be performed. This makes the target data block available for processing by the hardware unit where the destination address is located or for forwarding to the target hardware unit. This allows a pipeline to be formed between the CE and the hardware unit or between multiple CEs, which greatly improves the efficiency of data processing. Moreover, multiple data blocks can be transmitted using only one descriptor each time the target data is transmitted, which improves the performance of the CE.

[0047] Figure 1 A schematic diagram illustrating an application scenario of an embodiment of this application is shown. For example... Figure 1 As shown, this application can be applied to scenarios where the CE moves data from the memory of device 1 to the memory of device 2, and moves data from the memory of device 2 to the video memory of device 2. The CE can be on device 2, and by moving data from the memory of device 1 to the video memory of device 2, the hardware unit (such as a GPU) on device 2 can process the data.

[0048] In this application scenario, the data is moved twice. The method described in this embodiment can be used to segment the data into multiple data blocks. These data blocks are first moved sequentially from the memory of device 1 to the memory of device 2. Whenever a data block is moved from the memory of device 1 to the memory of device 2, based on the method described in this embodiment, the data block can be moved from the memory of device 2 to the video memory of device 2 without waiting for other data blocks to complete their movement. Whenever a data block is moved from the memory of device 2 to the video memory of device 2, based on the method described in this embodiment, the GPU on device 2 can process the data block without waiting for other data blocks to complete their movement. Thus, a pipeline processing is formed for each data block, greatly improving the efficiency of data processing.

[0049] It should be noted that the above application scenario uses two data moves as an example. However, it is also possible to move the data only once (such as moving the data only from the memory of device 2 to the video memory of device 2), or to move the data more than once. This application does not impose any restrictions on this.

[0050] Devices 1 and 2 mentioned above can be terminal devices or servers. The terminal device can be any one or more of the following: mobile phone, foldable electronic device, tablet computer, desktop computer, laptop computer, handheld computer, notebook computer, ultra-mobile personal computer (UMPC), netbook, cellular phone, personal digital assistant (PDA), and in-vehicle device. This application does not impose special limitations on the specific type of terminal device; it can have wired or wireless communication capabilities.

[0051] Servers can be located locally or in the cloud, and can be physical devices or virtual devices such as virtual machines and containers. They possess wireless communication capabilities, which can be configured within the server's chip (system) or other components. Wireless communication capabilities can be implemented through mobile communication technologies such as 2G / 3G / 4G / 5G, as well as Wi-Fi, Bluetooth, frequency modulation (FM), data radio, and satellite communication. Wired connections can also be used to communicate and interact with other devices.

[0052] The data transmission method of the embodiments of this application will be described below.

[0053] Figure 2 A flowchart illustrating a data transfer method according to an embodiment of this application is shown. This method can be used in the GPU's copy engine CE, such as... Figure 2 As shown, the method may include:

[0054] Step S201: In response to the target data block in the target data meeting the preset conditions, the target data block is written from the source address to the destination address based on the descriptor corresponding to the target data.

[0055] The target data consists of multiple data blocks, which can be divided into multiple data blocks of the same size. Preset conditions may include that the previous data block of the target data block has been written to the destination address or that the target data block is the first data block in the target data.

[0056] The descriptor corresponding to the target data can be filled in by the driver, which is used to move the target data from the source address (which can be called SrcAddress) to the destination address (which can be called DstAddress). The source address and the destination address can be the memory address and the video memory address on the same device, respectively. For example, the source address is the memory address of device 2 mentioned above, and the destination address is the video memory address on device 2 mentioned above. Alternatively, the source address and the destination address can be the memory address / video memory address on different devices, respectively. For example, the source address is the memory address of device 1 mentioned above, and the destination address is the memory address of device 2 mentioned above.

[0057] Figure 3 A schematic diagram illustrating the structure of a descriptor according to an embodiment of this application is shown. For example... Figure 3 As shown, the parameters of the descriptor may include: first fence (which may be called SignalFence) information and second fence (which may be called WaitFence) information. The descriptor may also include one or more of the following parameters: source address information, destination address information, size of the target data (which may be called DataSize), and size of each data block in the target data (which may be called SegmentSize).

[0058] The first and second fence information can each represent two arrays, the length of which can be equal to the total number of data blocks in the target data (i.e., (DataSize + SegmentSize - 1) / SegmentSize). Each position in the array can be associated with a data block in the target data. The second fence information can be used to indicate whether a data block can begin to be written from the source address to the destination address, and the first fence information can be used to indicate whether a data block has already been written from the source address to the destination address. When a specific position in the array corresponding to the second fence information is written with a second preset value (e.g., 1), it indicates that the data block corresponding to that position can begin transmission, i.e., it can begin to be written from the source address to the destination address. When a specific position in the array corresponding to the first fence information is written with a first preset value (the first preset value can be the same as the second preset value, e.g., 1), it indicates that the data block corresponding to that position can be processed by the hardware unit where the destination address is located.

[0059] A second preset value can be written to the location associated with the target data block in the second fence information of the descriptor, indicating that the target data block meets the preset conditions. The driver can write this second preset value to the descriptor, which indicates that the target data block can begin to be written from the source address to the destination address.

[0060] The second fence information can be associated with a second fence, which can be set in the memory or video memory where the destination address is located. This second fence is a storage space of a preset size, and its size can be associated with the target data; it can be a storage space in video memory or main memory. See also... Figure 4 This illustrates a schematic diagram of a first fence and a second fence according to an embodiment of this application. Figure 4 As shown, the second fence can be seen in the figure as second fence 1 (WaitFence1) and second fence 0 (WaitFence0), which are associated with data block 1 (data1) and data block 0 (data0) representing data blocks, respectively.

[0061] The second fence can include storage spaces associated with each data block. In response to a second preset value being written to the location associated with the target data block in the second fence information of the descriptor, the second preset value can be written to the location associated with the target data block in the second fence corresponding to the destination address. Thus, the value of the second fence in the actual storage space can be synchronized with the second fence information in the descriptor.

[0062] In step S202, in response to the target data block being written from the source address to the destination address, a first preset value is written to the location associated with the target data block in the first fence information of the descriptor.

[0063] The location associated with the target data block in the first fence information can be the location associated with the target data block in the array corresponding to the first fence information. The first preset value can indicate that the target data block can be processed by the hardware unit where the destination address is located or forwarded to the target hardware unit.

[0064] The first fence information can be associated with a first fence, which can be set in the memory or video memory where the destination address is located. This first fence is a storage space of a preset size, and its size can be associated with the target data. It can be a storage space in video memory or main memory. See the example of the first fence for details. Figure 4 The first fence 1 (SignalFence1) and the first fence 0 (SignalFence0) are associated with data block 1 (data1) and data block 0 (data0), respectively.

[0065] In response to the first preset value being written to the location associated with the target data block in the first fence information of the descriptor, the first preset value can be written to the location associated with the target data block in the first fence corresponding to the destination address. This allows the value of the first fence in the actual storage space to be synchronized with the first fence information in the descriptor.

[0066] The aforementioned hardware unit may include a graphics processing unit (GPU). The hardware unit where the destination address is located may be the GPU in the device where the destination address is located. After it obtains the location associated with the target data block in the first fence and writes the first preset value, it can access the target data block to process the target data block. This processing may include performing image rendering, image post-processing, or computational tasks such as deep learning inference.

[0067] The size of each data block in the target data can be related to the processing time of the data block by the hardware unit at the destination address, so that the transmission time of each data block matches the processing time of the data block by the hardware unit at the destination address. For example, by using a preset data block size, the transmission time of each data block can be made as close as possible to the processing time of the data block by the hardware unit at the destination address, thereby allowing the transmission of data blocks and the processing of data blocks by the hardware unit to form a pipeline.

[0068] After the target data block is written to the destination address, the hardware unit at the destination address may choose not to process the target data block, but instead forward it to a target hardware unit other than the one at the destination address, allowing the target hardware unit to process the target data block. In this case, the first preset value can indicate that the target data block is available for forwarding to the target hardware unit. Forwarding to the target hardware unit can include forwarding from the hardware unit at the destination address via other hardware units besides the one at the destination address, or forwarding directly from the hardware unit at the destination address to the target hardware unit.

[0069] At this time, the device driver corresponding to the hardware unit where the destination address is located can fill in the descriptor and perform data transmission according to the methods in steps S201-S202 above. After the SignalFence corresponding to the destination address is written to the first preset value, the WaitFence corresponding to the address of the forwarded hardware unit can be written to the second preset value, so that the target data block can be written into the memory / video memory of the forwarded hardware unit.

[0070] The aforementioned forwarding can be done once or multiple times. That is, the target data block can be processed by the target hardware unit after one forwarding, or it can be forwarded multiple times among multiple hardware units before being processed by the target hardware unit that wrote it in the last forwarding. The aforementioned process of transmitting data across hardware units (i.e., across chips) can be implemented using chip interconnect technologies such as high-speed serial bus (peripheral component interconnect express, PCIe) or C2C (chip to chip). Therefore, by utilizing the first fence and the second fence in this application, it is beneficial to realize pipeline management between the CEs of multiple chips and improve processing efficiency.

[0071] According to the embodiments of this application, in response to a target data block in the target data satisfying a preset condition, the target data block is written from the source address to the destination address based on the descriptor corresponding to the target data. The preset condition includes that the previous data block of the target data block has been written to the destination address or that the target data block is the first data block in the target data. In response to the target data block being written from the source address to the destination address, a first preset value is written to the position associated with the target data block in the first fence information of the descriptor. The first preset value indicates that the target data block can be processed by the hardware unit where the destination address is located or forwarded to the target hardware unit. The first fence is a storage space of a preset size, which allows the target data block to perform subsequent operations without waiting for all data blocks in the target data to be written to the destination address. This makes the target data block available for processing by the hardware unit where the destination address is located or forwarded to the target hardware unit, thereby enabling a pipeline to be formed between the CE and the hardware unit or between multiple CEs, greatly improving the efficiency of data processing. Moreover, multiple data blocks can be transmitted using only one descriptor each time the target data is transmitted, improving the performance of the CE.

[0072] The method may also include:

[0073] In response to the fact that the target data has been processed by the hardware unit where the destination address is located or has been forwarded to other hardware units, a second preset value is written to the position in the second fence information of the descriptor associated with the next data block of the target data block.

[0074] In response to the second preset value being written to the location associated with the next data block of the target data block in the second fence information of the descriptor, the second preset value can be written to the location associated with the next data block of the target data block in the second fence corresponding to the destination address.

[0075] When the position associated with the next data block of the target data block in the second fence corresponding to the destination address is written to the second preset value, it can be determined that the target data block has been processed by the hardware unit where the destination address is located or has been forwarded to other hardware units. Before writing the next data block of the target data block from the source address to the destination address, the positions associated with all data blocks preceding this data block in the second fence information of the descriptor have been written to the second preset value, and the positions associated with all data blocks preceding this data block in the first fence information of the descriptor have been written to the first preset value. This ensures that each data block in the target data is transmitted in sequence.

[0076] In this approach, each data block within the target data can be written to the same destination address. This saves storage space while enabling pipelined control using the second fence information, thereby improving processing efficiency.

[0077] Figure 5This diagram illustrates a structural diagram of a data transmission apparatus according to an embodiment of the present application. This apparatus can be used in the copy engine of a graphics processing unit (GPU), such as... Figure 5 As shown, the device includes:

[0078] The first writing module 501 is used to write the target data block from the source address to the destination address based on the descriptor corresponding to the target data in response to the target data block meeting the preset conditions. The target data consists of multiple data blocks. The preset conditions include that the previous data block of the target data block has been written to the destination address or that the target data block is the first data block in the target data.

[0079] The second writing module 502 is used to write a first preset value to the location associated with the target data block in the first fence information of the descriptor in response to the target data block being written from the source address to the destination address. The first preset value indicates that the target data block can be processed by the hardware unit where the destination address is located or forwarded to the target hardware unit. The first fence is a storage space of a preset size.

[0080] In one possible implementation, in response to the second fence information of the descriptor, the position associated with the target data block is written to a second preset value, determining that the target data block meets the preset conditions, and the second fence is a storage space of a preset size.

[0081] In one possible implementation, the descriptor may also include one or more of the following parameters: source address information, destination address information, size of the target data, and size of each data block in the target data.

[0082] In one possible implementation, being forwarded to the target hardware unit includes forwarding from the hardware unit where the destination address is located to the target hardware unit via other hardware units besides the hardware unit where the destination address is located, or forwarding directly from the hardware unit where the destination address is located to the target hardware unit.

[0083] In one possible implementation, the device further includes:

[0084] The third writing module is used to write the first preset value to the location associated with the target data block in the first fence information corresponding to the destination address in response to the first preset value being written to the location associated with the target data block in the first fence information in the descriptor.

[0085] In one possible implementation, the device further includes:

[0086] The fourth writing module is used to write a second preset value to the position associated with the next data block of the target data block in the second fence information of the descriptor in response to the target data being processed by the hardware unit where the destination address is located or being forwarded to other hardware units, wherein each data block in the target data is written with the same destination address.

[0087] In one possible implementation, in response to the location associated with the next data block of the target data block in the second fence corresponding to the destination address being written with a second preset value, it is determined that the target data block has been processed by the hardware unit where the destination address is located or has been forwarded to other hardware units.

[0088] In one possible implementation, the size of each data block in the target data is related to the time it takes for the hardware unit at the destination address to process the data block, so that the time for transmitting each data block matches the time it takes for the hardware unit at the destination address to process each data block.

[0089] In one possible implementation, the hardware unit includes a graphics processing unit (GPU).

[0090] According to the embodiments of this application, in response to a target data block in the target data satisfying a preset condition, the target data block is written from the source address to the destination address based on the descriptor corresponding to the target data. The preset condition includes that the previous data block of the target data block has been written to the destination address or that the target data block is the first data block in the target data. In response to the target data block being written from the source address to the destination address, a first preset value is written to the position associated with the target data block in the first fence information of the descriptor. The first preset value indicates that the target data block can be processed by the hardware unit where the destination address is located or forwarded to the target hardware unit. The first fence is a storage space of a preset size, which allows the target data block to perform subsequent operations without waiting for all data blocks in the target data to be written to the destination address. This makes the target data block available for processing by the hardware unit where the destination address is located or forwarded to the target hardware unit, thereby enabling a pipeline to be formed between the CE and the hardware unit or between multiple CEs, greatly improving the efficiency of data processing. Moreover, multiple data blocks can be transmitted using only one descriptor each time the target data is transmitted, improving the performance of the CE.

[0091] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0092] This disclosure also provides a data transmission apparatus, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0093] This disclosure also provides a non-volatile computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described method.

[0094] This disclosure also provides a computer program product, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above method.

[0095] Figure 6 This is a block diagram illustrating an apparatus 1900 for data transmission according to an exemplary embodiment. For example, apparatus 1900 may be provided as a server or terminal device. (Refer to...) Figure 6 The apparatus 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0096] Device 1900 may also include a power supply component 1926 configured to perform power management of device 1900, a wired or wireless network interface 1950 configured to connect device 1900 to a network, and an input / output interface 1958 (I / O interface). Device 1900 can operate on an operating system, such as Windows Server, stored in memory 1932. TM macOS X TM Unix TM Linux TM FreeBSD TM Or similar.

[0097] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of the device 1900 to perform the above-described method.

[0098] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0099] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0100] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0101] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0102] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0103] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0104] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0105] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0106] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A data transmission method, characterized in that, The method is used for the copy engine of a graphics processing unit (GPU), and the method includes: In response to a target data block in the target data satisfying a preset condition, the target data block is written from the source address to the destination address based on a descriptor corresponding to the target data. The target data consists of multiple data blocks. The preset condition includes that the previous data block of the target data block has been written to the destination address or that the target data block is the first data block in the target data. In response to the target data block being written from the source address to the destination address, a first preset value is written to the position associated with the target data block in the first fence information of the descriptor. The first preset value indicates that the target data block can be processed by the hardware unit where the destination address is located or forwarded to the target hardware unit. The first fence is a storage space of a preset size in the memory or video memory where the destination address is located. In response to the fact that the target data block has been processed by the hardware unit where the destination address is located or has been forwarded to other hardware units, a second preset value is written to the position associated with the next data block of the target data block in the second fence information of the descriptor. The second preset value indicates that the next data block of the target data block can start transmission. In this case, each data block in the target data is written to the same destination address. The second fence is a storage space of a preset size in the memory or video memory where the destination address is located. The first fence information and the second fence information represent two arrays respectively. The length of the array is equal to the total number of data blocks in the target data. The value of the first fence is synchronized with the first fence information in the descriptor, and the value of the second fence is synchronized with the second fence information in the descriptor.

2. The method according to claim 1, characterized in that, In response to the second fence information of the descriptor being written with a second preset value, it is determined that the target data block meets the preset condition.

3. The method according to claim 2, characterized in that, The descriptor also includes one or more of the following parameters: source address information, destination address information, size of the target data, and size of each data block in the target data.

4. The method according to claim 1, characterized in that, The forwarding to the target hardware unit includes forwarding from the hardware unit where the destination address is located to the target hardware unit via other hardware units besides the hardware unit where the destination address is located, or forwarding directly from the hardware unit where the destination address is located to the target hardware unit.

5. The method according to claim 1 or 2, characterized in that, The method further includes: In response to the first preset value being written to the location associated with the target data block in the first fence information of the descriptor, the first preset value is written to the location associated with the target data block in the first fence corresponding to the destination address.

6. The method according to claim 1, characterized in that, In response to the second preset value being written to the position of the next data block associated with the target data block in the second fence corresponding to the destination address, it is determined that the target data block has been processed by the hardware unit where the destination address is located or has been forwarded to other hardware units.

7. The method according to claim 1, characterized in that, The size of each data block in the target data is related to the time it takes for the hardware unit at the destination address to process the data block, so that the time for transmitting each data block matches the time it takes for the hardware unit at the destination address to process each data block.

8. The method according to claim 1, characterized in that, The hardware unit includes a graphics processing unit (GPU).

9. A data transmission device, characterized in that, The apparatus is used for a copying engine of a graphics processing unit (GPU), and the apparatus includes: The first writing module is used to write the target data block from the source address to the destination address based on a descriptor corresponding to the target data in response to the target data block meeting the preset conditions. The target data consists of multiple data blocks. The preset conditions include the previous data block of the target data block having been written to the destination address or the target data block being the first data block in the target data. The second writing module is used to write a first preset value to the position associated with the target data block in the first fence information of the descriptor in response to the target data block being written from the source address to the destination address. The first preset value indicates that the target data block can be processed by the hardware unit where the destination address is located or forwarded to the target hardware unit. The first fence is a storage space of a preset size in the memory or video memory where the destination address is located. The fourth write module is used to write a second preset value to the position associated with the next data block of the target data block in the second fence information of the descriptor in response to the target data block being processed by the hardware unit where the destination address is located or being forwarded to other hardware units. The second preset value indicates that the next data block of the target data block can start transmission. Each data block in the target data is written to the same destination address. The second fence is a storage space of a preset size in the memory or video memory where the destination address is located. The first fence information and the second fence information represent two arrays respectively. The length of the array is equal to the total number of data blocks in the target data. The value of the first fence is synchronized with the first fence information in the descriptor, and the value of the second fence is synchronized with the second fence information in the descriptor.

10. A data transmission apparatus, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 8.

11. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

12. A computer program product comprising a computer program, or a non-volatile computer-readable storage medium carrying a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

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