A controller circuit for solving ADC conversion data loss
By adding read and write timing and dual-port RAM memory controller circuit structure to the ADC controller, the problem of ADC conversion data is solved, timely storage and efficient management of data is realized, the demand for DMA is reduced, and system resources are saved.
Patent Information
- Application Number
- CN202510644999.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-20
- Publication Date
- 2025-08-08
- Estimated Expiration
- 2045-05-20
AI Technical Summary
In the prior art, the ADC conversion data is easily lost or overwritten, especially when the ADC conversion speed is fast and the system reading speed is slow, the real-time and completeness of the data cannot be guaranteed.
The controller circuit structure includes RAM memory, ADC controller, SRAM controller and host. By adding read and write timing to the ADC controller, data storage is completed in three clock cycles using dual-port RAM memory to prevent data loss.
Data storage is completed within three clock cycles, preventing new data from being lost or old data being overwritten, reducing the need for DMA, saving space and improving performance.
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Figure CN120164500B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a controller circuit, in particular to a controller circuit for solving the problem of ADC conversion data loss, and belongs to the technical field of semiconductor integrated circuits. Background Art
[0002] The data sampled and converted by the ADC is usually stored in a specific data register of the ADC. This specific register may be one or more.
[0003] For the ADC controller, one data register can be used to store the data converted by all channels. This method requires fewer registers. However, when the ADC conversion speed is fast, the system reads the ADC register slowly, and new data may be lost or old data may be overwritten. It cannot be guaranteed that the latest data is read from the ADC data register each time.
[0004] ADC controllers can also use multiple data registers, one for each channel, to store conversion data. However, for ADCs with a large number of channels or higher conversion accuracy, this trades off performance advantages in terms of area. Even in designs where area requirements are less stringent, maintaining data up-to-date is still necessary when continuously converting a single channel or when the ADC conversion speed is faster than the system reading the ADC.
[0005] In addition, if the content in the ADC data register is processed by the CPU at this time, an interrupt or query method is usually used to read the ADC conversion data.
[0006] There are three methods for the system to read ADC conversion data:
[0007] 1) CPU query: such as Figure 8 As shown in the figure, the CPU continuously queries the flag bit of the ADC data register. Once the flag bit is found, the ADC data register is read. This method continuously occupies CPU resources, slowing down the CPU processing. Furthermore, the ADC is constantly converting data, which can lead to delayed data processing, loss of new conversion data, or overwriting of old conversion data. This method typically requires dozens of CPU clock cycles or more.
[0008] 2) CPU interrupts: When interrupts are nested, non-ADC data is processed first, and the ADC data register is read last. Although this method can avoid excessive CPU resource usage, it takes a long time for the CPU to process ADC data, causing new ADC converted data to overflow or overwriting previously unread converted data. Furthermore, this method typically requires dozens of CPU clock cycles or more.
[0009] like Figure 10 As shown in the timing diagram of using the CPU to process ADC data, when interrupts are not nested and the CPU processes the ADC data immediately upon entering the interrupt, although some irrelevant clock cycle overhead before reading the ADC data register is avoided, the time to enter the interrupt will be longer in some slower frequency systems. When the ADC conversion speed is faster than the CPU processing speed, new data may still overflow or overwrite old data, and the clock cycles required for this method are usually more than a dozen CPU clock cycles.
[0010] 3) DMA controller: such as Figure 9 As shown, if the DMA controller and ADC controller are in different clock domains, cross-clock domain processing will take two DMA clock cycles, and reading ADC data will take at least two cycles. If the ADC controller and DMA controller are located on two separate chips, communication between the two chips will take a long time when the chips are sealed together. Whether it is a single-die chip or a multi-die chip, there is always the problem of the ADC data register not storing the latest conversion data.
[0011] Moreover, the DMA controller has a large area overhead and may not be used in some chips.
[0012] Regardless of the design of the ADC controller or the method of reading the ADC data register, the problem of new ADC conversion data overflowing or old ADC conversion data being overwritten may be encountered. Summary of the Invention
[0013] The technical problem to be solved by the present invention is to provide a controller circuit for solving the problem of ADC conversion data loss, thereby preventing the ADC conversion data from being lost.
[0014] In order to solve the above technical problems, the technical solution adopted by the present invention is:
[0015] A controller circuit for resolving ADC conversion data loss comprises a RAM memory, an ADC controller, an ADC, an SRAM controller, and at least one host. The ADC controller comprises a set of RAM write interfaces and a set of data registers. The ADC controller is connected to the ADC for temporarily storing conversion data generated by the ADC in the data registers. The ADC controller is connected to the RAM memory via the set of RAM write interfaces for writing conversion data generated by the ADC temporarily stored in the data registers into the RAM memory. The SRAM controller is connected to the RAM memory for reading conversion data generated by the ADC in the RAM memory. The ADC controller and the SRAM controller are connected to the at least one host for interacting with the host.
[0016] Furthermore, the RAM memory adopts a dual-port RAM memory, which includes a first group of interfaces and a second group of interfaces. The dual-port RAM memory is connected to the SRAM controller via the first group of interfaces, and the dual-port RAM memory is connected to the ADC controller via the second group of interfaces.
[0017] Furthermore, a set of transmission signals of the RAM write interface of the ADC controller includes a read / write clock signal clk, a RAM chip select signal cs for read / write data, a write enable signal we for read / write data, an address addr of a read / write data register, and an input signal data_in for conversion data.
[0018] Furthermore, the timing sequence of the transmission signal of a set of RAM write interfaces of the ADC controller is:
[0019] The starting point of the first clock cycle after the ADC converts the data is the starting point of the current timing clock cycle;
[0020] First clock cycle: ADC sends EOC flag and conversion data to ADC controller;
[0021] Second clock cycle: The ADC controller collects the EOC flag on the rising edge of the second clock cycle and sets the write enable signal we in the RAM read / write interface and the RAM chip select signal cs for reading and writing data; the ADC controller stores the ADC conversion data into the ADC controller's data register through the EOC flag; the ADC controller generates an EOC interrupt for use by the interrupt service routine;
[0022] The third clock cycle: The ADC controller writes the ADC conversion data in the data register into the RAM memory according to the address addr of the read / write data register and through the input signal data_in of the conversion data.
[0023] Furthermore, the ADC controller further includes an address configuration register, and the address addr of the read and write data register is configured in advance by the address configuration register or a portion of RAM memory space is separately allocated for use by the ADC controller. The address addr of the read and write data register is configured to be incremented or not incremented by the address configuration register.
[0024] Furthermore, when there is only one host, the ADC controller and the SRAM controller are connected to the host and interact with the host. The ADC controller acts as a slave. When the ADC conversion data is needed, the SRAM controller reads the conversion data in the RAM memory. At this time, the RAM memory uses a dual-port RAM memory.
[0025] Furthermore, when there are multiple hosts, the multiple hosts, ADC controllers and SRAM controllers are connected to the host arbitration system for interaction. The ADC controller acts as a slave and when it needs to use ADC conversion data, the SRAM controller reads the conversion data in the RAM memory.
[0026] Furthermore, when there are multiple hosts, the ADC controller serves as one of the hosts, and the multiple hosts, ADC controller, SRAM controller, ADC and AHB MUX interface module are connected to the host arbitration system for interaction. The AHB MUX interface module is connected to the RAM memory. When the ADC conversion data is needed, the SRAM controller reads the conversion data in the RAM memory, or other hosts except the ADC controller read the conversion data in the RAM memory.
[0027] Compared with the prior art, the present invention has the following advantages and effects:
[0028] 1. By adding read and write timing to the ADC controller, the present invention can complete ADC data storage within three ADC controller clock cycles. In the first clock cycle, the ADC sends the EOC (end of sequence) flag and converted data to the ADC controller; in the second clock cycle, a write enable is sent to RAM interface 2; and in the third clock cycle, the converted data is written to SRAM via RAM interface 2 for storage, preventing ADC conversion data loss. Because an ADC conversion cycle requires at least one sampling period + Tresolution, the data storage period in the present invention is much shorter than the next data conversion, preventing new data from being lost or old data from being overwritten.
[0029] 2. The ADC data storage structure of the present invention can reduce the ADC's demand for DMA, allowing the DMA to release channels to process requests from other slave devices;
[0030] 3. The ADC data storage structure of the present invention can save more area and improve its performance with a smaller area overhead in a system with low DMA requirements;
[0031] 4. The ADC data storage structure of the present invention can reduce the utilization rate of ADC to DMA even in a system with a large DMA demand, so that DMA can release more clock cycles to process requests from other slaves. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 This is a schematic diagram of embodiment 1 of a controller circuit for resolving ADC conversion data loss according to the present invention.
[0033] Figure 2This is a schematic diagram of embodiment 2 of a controller circuit for resolving ADC conversion data loss according to the present invention.
[0034] Figure 3 This is a schematic diagram of embodiment 3 of a controller circuit for resolving ADC conversion data loss according to the present invention.
[0035] Figure 4 This is a schematic diagram of embodiment 4 of a controller circuit for resolving ADC conversion data loss according to the present invention.
[0036] Figure 5 It is a timing diagram of the ADC controller of the present invention.
[0037] Figure 6 It is a schematic diagram of the dual-port RAM memory of the present invention.
[0038] Figure 7 It is a read and write timing diagram of the dual-port RAM memory of the present invention.
[0039] Figure 8 This is a circuit diagram of using a CPU to process ADC data in the prior art.
[0040] Figure 9 FIG. 1 is a circuit diagram of using DMA to process ADC data in the prior art.
[0041] Figure 10 This is a timing diagram of using a CPU to process ADC data in the prior art. DETAILED DESCRIPTION
[0042] In order to elaborate on the technical solutions adopted by the present invention to achieve the predetermined technical purpose, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.
[0043] Example 1. Figure 1As shown, a controller circuit for solving the problem of ADC conversion data loss includes a RAM memory, an ADC controller, an ADC, an SRAM controller and a host. The ADC controller includes a set of RAM write interfaces and a set of data registers. The ADC controller is connected to the ADC for temporarily storing the conversion data generated by the ADC in the data registers. The ADC controller is connected to the RAM memory through a set of RAM write interfaces for writing the conversion data generated by the ADC temporarily stored in the data registers to the RAM memory. The SRAM controller is connected to the RAM memory for reading the ADC conversion data in the RAM memory. The ADC controller and the SRAM controller are connected to the host to interact with the host.
[0044] Among them, the RAM memory reuses the system RAM, and the system RAM adopts a dual-port RAM memory, such as Figure 6 As shown, the dual-port RAM memory includes a first group of interfaces and a second group of interfaces. The dual-port RAM memory is connected to the SRAM controller via the first group of interfaces, and the dual-port RAM memory is connected to the ADC controller via the second group of interfaces. Figure 7 Shown is the read and write timing diagram of the dual-port RAM.
[0045] The transmission signals of a set of RAM write interfaces of the ADC controller include the read / write clock signal clk, the RAM chip select signal cs for read / write data, the write enable signal we for read / write data, the address addr of the read / write data register, and the input signal data_in for conversion data.
[0046] like Figure 5 As shown in the figure, the timing of the transmission signal of a set of RAM write interfaces of the ADC controller is:
[0047] The starting point of the first clock cycle after the ADC converts the data is the starting point of the current timing clock cycle;
[0048] First clock cycle: ADC sends EOC flag and conversion data to ADC controller;
[0049] Second clock cycle: The ADC controller collects the EOC flag on the rising edge of the second clock cycle and sets the write enable signal we in the RAM read / write interface and the RAM chip select signal cs for reading and writing data; the ADC controller stores the ADC conversion data into the ADC controller's data register through the EOC flag; the ADC controller generates an EOC interrupt for use by the interrupt service routine;
[0050] The third clock cycle: The ADC controller writes the ADC conversion data in the data register into the RAM memory according to the address addr of the read / write data register and through the input signal data_in of the conversion data.
[0051] The ADC controller acts as a slave and when it needs to use the ADC conversion data, the SRAM controller reads the conversion data in the RAM memory.
[0052] The ADC controller also includes an address configuration register. The address addr for reading and writing data registers is pre-configured by the address configuration register or by allocating a separate portion of RAM memory space for the ADC controller. The address addr for reading and writing data registers can be configured to increment or not increment using the address configuration register. The address addr and addrb for the two interfaces of the dual-port RAM can be determined by the system, with the size of each portion determined by the system.
[0053] Example 2. Figure 2 As shown, a controller circuit for solving the problem of ADC conversion data loss includes a RAM memory, an ADC controller, an ADC, an SRAM controller, multiple hosts, and a host arbitration system. The ADC controller includes a set of RAM write interfaces and a set of data registers. The ADC controller is connected to the ADC for temporarily storing the conversion data generated by the ADC in the data registers. The ADC controller is connected to the RAM memory through a set of RAM write interfaces for writing the conversion data generated by the ADC temporarily stored in the data registers to the RAM memory. The SRAM controller is connected to the RAM memory for reading the ADC conversion data in the RAM memory. Multiple hosts, the ADC controller, and the SRAM controller are connected to the host arbitration system for interaction.
[0054] Among them, the RAM memory reuses the system RAM, and the system RAM adopts a dual-port RAM memory, such as Figure 6 As shown, the dual-port RAM memory includes a first group of interfaces and a second group of interfaces. The dual-port RAM memory is connected to the SRAM controller via the first group of interfaces, and the dual-port RAM memory is connected to the ADC controller via the second group of interfaces.
[0055] The transmission signals of a set of RAM write interfaces of the ADC controller include the read / write clock signal clk, the RAM chip select signal cs for read / write data, the write enable signal we for read / write data, the address addr of the read / write data register, and the input signal data_in for conversion data.
[0056] like Figure 5 As shown in the figure, the timing of the transmission signal of a set of RAM write interfaces of the ADC controller is:
[0057] The starting point of the first clock cycle after the ADC converts the data is the starting point of the current timing clock cycle;
[0058] First clock cycle: ADC sends EOC flag and conversion data to ADC controller;
[0059] Second clock cycle: The ADC controller collects the EOC flag on the rising edge of the second clock cycle and sets the write enable signal we in the RAM read / write interface and the RAM chip select signal cs for reading and writing data; the ADC controller stores the ADC conversion data into the ADC controller's data register through the EOC flag; the ADC controller generates an EOC interrupt for use by the interrupt service routine;
[0060] The third clock cycle: The ADC controller writes the ADC conversion data in the data register into the RAM memory according to the address addr of the read / write data register and through the input signal data_in of the conversion data.
[0061] The ADC controller acts as a slave and when it needs to use the ADC conversion data, the SRAM controller reads the conversion data in the RAM memory.
[0062] The ADC controller also includes an address configuration register. The address addr of the read and write data register is configured in advance by the address configuration register or a portion of RAM memory space is separately allocated for use by the ADC controller. The address addr of the read and write data register is configured to be incremented or not incremented by the address configuration register.
[0063] Example 3. Figure 3 As shown, a controller circuit for solving the problem of ADC conversion data loss includes a RAM memory, an ADC controller, an ADC, an SRAM controller and multiple hosts. The ADC controller includes a set of RAM write interfaces and a set of data registers. The ADC controller is connected to the ADC for temporarily storing the conversion data generated by the ADC in the data registers. The ADC controller is connected to the RAM memory through a set of RAM write interfaces for writing the conversion data generated by the ADC temporarily stored in the data registers to the RAM memory. The SRAM controller is connected to the RAM memory for reading the ADC conversion data in the RAM memory. The multiple hosts, the ADC controller and the SRAM controller are connected to the host arbitration system for interaction.
[0064] The RAM memory is separate from the system RAM, meaning a small amount of storage space is allocated specifically for the ADC controller. This SRAM is a single-port SRAM with a fixed base address (addr) for the interface signal. The system must have at least one SRAM for storing private ADC conversion data. The system RAM is connected to the SRAM controller, and the RAM memory is connected to the ADC controller.
[0065] In this embodiment, a group of RAM write interfaces of the ADC controller also needs to have a read function. At this time, the transmission signals of a group of RAM read and write interfaces of the ADC controller include a read and write clock signal clk, a RAM chip select signal cs for read and write data, a write enable signal we for read and write data, an address addr of the read and write data register, an input signal data_in for converted data, and a data output signal data_out.
[0066] like Figure 5 As shown in the figure, the timing of the transmission signal of a set of RAM write interfaces of the ADC controller is:
[0067] The starting point of the first clock cycle after the ADC converts the data is the starting point of the current timing clock cycle;
[0068] First clock cycle: ADC sends EOC flag and conversion data to ADC controller;
[0069] Second clock cycle: The ADC controller collects the EOC flag on the rising edge of the second clock cycle and sets the write enable signal we in the RAM read / write interface and the RAM chip select signal cs for reading and writing data; the ADC controller stores the ADC conversion data into the ADC controller's data register through the EOC flag; the ADC controller generates an EOC interrupt for use by the interrupt service routine;
[0070] The third clock cycle: The ADC controller writes the ADC conversion data in the data register into the RAM memory according to the address addr of the read / write data register and through the input signal data_in of the conversion data.
[0071] The ADC controller acts as a slave and reads the converted data in the RAM memory when the ADC conversion data needs to be used.
[0072] Example 4. Figure 4As shown, a controller circuit for resolving ADC conversion data loss includes a RAM memory, an ADC controller, an ADC, an SRAM controller, multiple hosts, and an AHB MUX interface module. The AHB MUX interface module includes a set of RAM read / write interfaces, and the ADC controller includes a set of data registers. The multiple hosts, the ADC controller, the SRAM controller, the ADC, and the AHBMUX interface module are connected to a host arbitration system for interaction. The SRAM controller is connected to the AHB MUX interface module, and the AHB MUX interface module is connected to the RAM memory via a set of RAM read / write interfaces. The conversion data generated by the ADC is temporarily stored in the data registers of the ADC controller via the host arbitration system. The ADC controller is connected to the RAM memory via a set of RAM read / write interfaces of the host arbitration system and the AHB MUX interface module, and is used to write the ADC conversion data temporarily stored in the data registers to the RAM memory.
[0073] The RAM memory reuses the system RAM, and the system RAM at this time is a single-port RAM. The interface signal of the SRAM needs to process the read and write signals from the ADC controller and the read and write signals from the SRAM controller.
[0074] The transmission signals of a set of RAM read and write interfaces of the AHB MUX interface module include the read and write clock signal clk, the RAM chip select signal cs for read and write data, the write enable signal we for read and write data, the address addr of the read and write data register, the input signal data_in for converted data, and the data output signal data_out.
[0075] like Figure 5 As shown in the figure, the timing of the transmission signal of a set of RAM write interfaces of the ADC controller is:
[0076] The starting point of the first clock cycle after the ADC converts the data is the starting point of the current timing clock cycle;
[0077] First clock cycle: ADC sends EOC flag and conversion data to ADC controller;
[0078] Second clock cycle: The ADC controller collects the EOC flag on the rising edge of the second clock cycle and sets the write enable signal we in the RAM read / write interface and the RAM chip select signal cs for reading and writing data; the ADC controller stores the ADC conversion data into the ADC controller's data register through the EOC flag; the ADC controller generates an EOC interrupt for use by the interrupt service routine;
[0079] The third clock cycle: The ADC controller writes the ADC conversion data in the data register into the RAM memory according to the address addr of the read / write data register and through the input signal data_in of the conversion data.
[0080] The ADC controller serves as one of the hosts, and multiple hosts, ADC controllers, and SRAM controllers are connected to the host arbitration system for interaction. When the ADC conversion data is needed, the SRAM controller reads the conversion data in the RAM memory, or other hosts except the ADC controller read the conversion data in the RAM memory.
[0081] By adding the read and write timing of the RAM interface to the ADC controller, the present invention can complete the ADC data storage within three ADC controller clock cycles. In the first clock cycle, the ADC sends the EOC (end of sequence) flag and the converted data to the ADC controller; in the second clock cycle, the write enable is sent to the RAM interface 2; in the third clock cycle, the converted data is written to the SRAM through the RAM interface 2 to prevent the loss of the ADC converted data. Figure 5 As shown, since one ADC conversion cycle requires at least one sampling cycle + Tresolution, the data storage cycle of the present invention is much shorter than the next data conversion, which can prevent new data from being lost or old data from being overwritten. The ADC data storage structure of the present invention can reduce the ADC's demand for DMA, allowing the DMA to free up channels to process requests from other slave devices. In systems with low DMA demand, the ADC data storage structure of the present invention can save more area and improve its performance with a smaller area overhead. Even in systems with high DMA demand, the ADC data storage structure of the present invention can reduce the ADC's utilization of DMA, allowing the DMA to free up more clock cycles to process requests from other slave devices.
[0082] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.
Claims
1. A controller circuit for resolving ADC conversion data loss, characterized by: The device comprises a RAM memory, an ADC controller, an ADC, an SRAM controller, and at least one host. The ADC controller comprises a set of RAM write interfaces and a set of data registers. The ADC controller is connected to the ADC and is used to temporarily store conversion data generated by the ADC in the data registers. The ADC controller is connected to the RAM memory via a set of RAM write interfaces and is used to write conversion data generated by the ADC temporarily stored in the data registers into the RAM memory. The SRAM controller is connected to the RAM memory and is used to read conversion data generated by the ADC in the RAM memory. The ADC controller and the SRAM controller are connected to at least one host and interact with the host. The transmission signals of a set of RAM write interfaces of the ADC controller include a read / write clock signal clk, a RAM chip select signal cs for read / write data, a write enable signal we for read / write data, an address addr for a read / write data register, and an input signal data_in for conversion data; The timing sequence of the transmission signal of a set of RAM write interfaces of the ADC controller is: The starting point of the first clock cycle after the ADC converts the data is the starting point of the current timing clock cycle; First clock cycle: ADC sends EOC flag and conversion data to ADC controller; Second clock cycle: The ADC controller collects the EOC flag on the rising edge of the second clock cycle and sets the write enable signal we in the RAM read / write interface and the RAM chip select signal cs for reading and writing data; the ADC controller stores the ADC conversion data into the ADC controller's data register through the EOC flag; the ADC controller generates an EOC interrupt for use by the interrupt service routine; The third clock cycle: The ADC controller writes the ADC conversion data in the data register into the RAM memory according to the address addr of the read / write data register and through the input signal data_in of the conversion data.
2. The controller circuit for resolving ADC conversion data loss according to claim 1, characterized in that: The RAM memory is a dual-port RAM memory, which includes a first group of interfaces and a second group of interfaces. The dual-port RAM memory is connected to the SRAM controller via the first group of interfaces, and is connected to the ADC controller via the second group of interfaces.
3. The controller circuit for resolving ADC conversion data loss according to claim 1, wherein: The ADC controller further includes an address configuration register. The address addr of the read / write data register is configured in advance by the address configuration register or a portion of RAM memory space is separately allocated for use by the ADC controller. The address addr of the read / write data register is configured to be incremented or not incremented by the address configuration register.
4. The controller circuit for resolving ADC conversion data loss according to claim 1, characterized in that: When there is only one host, the ADC controller and the SRAM controller are connected to the host and interact with the host. The ADC controller acts as a slave. When the ADC conversion data is needed, the SRAM controller reads the conversion data in the RAM memory. At this time, the RAM memory uses a dual-port RAM memory.
5. The controller circuit for resolving ADC conversion data loss according to claim 1, characterized in that: When there are multiple hosts, the multiple hosts, ADC controllers and SRAM controllers are connected to the host arbitration system to interact. The ADC controller acts as a slave and when it needs to use the ADC conversion data, the SRAM controller reads the conversion data in the RAM memory.
6. The controller circuit for resolving ADC conversion data loss according to claim 5, characterized in that: When there are multiple hosts, the ADC controller serves as one of the hosts. Multiple hosts, the ADC controller, the SRAM controller, the ADC, and the AHB MUX interface module are connected to the host arbitration system for interaction. The AHB MUX interface module is connected to the RAM memory. When the ADC conversion data is needed, the SRAM controller reads the conversion data in the RAM memory, or other hosts except the ADC controller read the conversion data in the RAM memory.
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