Method for improving copper hole filling under condition of high aspect ratio
By forming a barrier layer and a copper grain layer on the semiconductor element, copper plating and chemical mechanical grinding treatment are carried out to expose and fill defects and voids, the problem that semiconductor elements with relatively large depth and width are easily prone to defects and voids during copper plating, and the stability and yield of the component are improved.
Patent Information
- Application Number
- CN202311742907.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-15
- Publication Date
- 2025-06-17
AI Technical Summary
When dealing with semiconductor components with relatively large depth and width, defects and copper voids are easily generated, resulting in low stability and yield of semiconductor components.
By providing the copper-plated semiconductor element with trench obtained by the post-etching process, a barrier layer and a primary copper grain layer are formed in sequence, and a primary copper plating treatment and chemical mechanical grinding are performed to expose defects and voids; then a secondary copper grain layer is formed on the surface, and a secondary copper plating treatment is performed to fill the defects and voids.
It reduces the risk of defects and copper voids, and improves the stability and yield of copper-filled semiconductor components.
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Figure CN120164848A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor integrated circuits, and more particularly, to a method for improving copper filling in high aspect ratio situations. Background Art
[0002] In existing semiconductor copper plating process technologies, a trench formation region corresponding to a copper interconnect of a semiconductor element forming a metal hard mask layer is usually formed by a photolithography and etching process to form a trench, and a barrier layer, a copper seed layer, and a copper layer are sequentially formed on the surface of the semiconductor element; then chemical mechanical polishing of copper is performed. However, when using the existing technology to process semiconductor elements with a relatively large aspect ratio, defects and voids are likely to occur in the upper and middle parts of the trench, which will cause the resistance of the semiconductor element to be too high, and further reduce the stability and yield rate of the semiconductor element product. Summary of the Invention
[0003] The purpose of the present disclosure is to provide a method for improving copper filling in high aspect ratio situations to solve the problems of low stability and low yield rate of semiconductors caused by the easy generation of defects and copper voids when the existing technology processes semiconductor elements with a relatively large aspect ratio.
[0004] To achieve the above purpose, the present disclosure provides a method for improving copper filling in high aspect ratio situations, the method comprising:
[0005] S1. Provide a copper-plated semiconductor element with trenches obtained by a post-etching process; the aspect ratio of the trenches of the copper-plated semiconductor element is 7 or more;
[0006] S2. Sequentially form a barrier layer and a primary copper grain layer on the surface of the copper-plated semiconductor element, and form a first copper plating layer on the surface of the primary copper grain layer by a primary copper plating process;
[0007] S3. Perform chemical mechanical polishing on the semiconductor element obtained in S2 to obtain a semiconductor element to be filled with holes;
[0008] S4. Form a secondary copper grain layer on the surface of the semiconductor element to be filled with holes, and form a second copper plating layer on the surface of the secondary copper grain layer by a secondary copper plating process;
[0009] S5. Perform chemical mechanical polishing on the semiconductor element obtained in S4 to obtain a semiconductor element with copper-filled holes.
[0010] Optionally, the post-etching process includes one or more of a photolithography process, a wet etching process, and a dry etching process.
[0011] Optionally, the barrier layer, the primary copper grain layer, and the secondary copper grain layer are respectively formed by a physical vapor deposition process.
[0012] Optionally, the physical vapor deposition includes vacuum sputtering deposition and / or ion plating deposition; the reaction temperature of the physical vapor deposition is 25 to 300 °C.
[0013] Optionally, the material of the barrier layer is TaN and / or Ta; the coating precursor used to form the barrier layer by the physical vapor deposition includes a target and an optional deposition gas phase; the target is Ta metal, and the deposition gas phase is nitrogen.
[0014] Optionally, the targets used to form the primary copper grain layer and the secondary copper grain layer by the physical vapor deposition are copper metal and / or copper-manganese alloy respectively.
[0015] Optionally, the thicknesses of the primary copper grain layer and the secondary copper grain layer are 200 to 800 angstroms respectively.
[0016] Optionally, step S1 includes:
[0017] S11. Provide a bottom semiconductor substrate with a flat surface;
[0018] S12. Sequentially form a bottom metal diffusion barrier layer, a silicon dioxide layer, a low-K dielectric layer, a top metal diffusion barrier layer, an anti-reflection coating, and a metal hard mask layer on the surface of the bottom semiconductor substrate;
[0019] S13. Process the semiconductor element obtained in S12 by the post-etching process to form the trench, and obtain the semiconductor element to be copper-plated.
[0020] Optionally, step S3 further includes polishing the semiconductor element obtained in S2 by the chemical mechanical polishing, and stopping the polishing process when polishing to the low-K dielectric layer to obtain the semiconductor element to be hole-filled.
[0021] Optionally, step S5 further includes polishing the semiconductor element obtained in S4 by the chemical mechanical polishing, and stopping the polishing process when polishing to the low-K dielectric layer to obtain the copper-filled hole semiconductor element.
[0022] Through the above technical solution, after the semiconductor element to be copper-plated is subjected to the first copper plating treatment and then chemical mechanical polishing to obtain the semiconductor element to be hole-filled, the defects and copper voids generated during copper plating can be exposed; then, the semiconductor element to be hole-filled is subjected to the second copper plating treatment, which can fill the exposed defects and copper voids under the action of the second copper plating treatment, reduce the risk of generating defects and copper voids, and further improve the stability and yield rate of the obtained copper-filled hole semiconductor element.
[0023] Other features and advantages of the present disclosure will be described in detail in the following detailed description section. Description of the Drawings
[0024] The drawings are used to provide a further understanding of the present disclosure and form a part of the specification. Together with the following detailed description, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the drawings:
[0025] Figure 1 is a flowchart of a method for improving copper filling in high aspect ratio holes in the present disclosure.
[0026] Figure 2 is a schematic diagram of a semiconductor element to be copper-plated in the present disclosure.
[0027] Figure 3 is a schematic diagram of a semiconductor element obtained after S2 in the present disclosure.
[0028] Figure 4 is a schematic diagram of a semiconductor element with holes to be filled obtained after S3 in the present disclosure.
[0029] Figure 5 is a schematic diagram of a semiconductor element with copper-filled holes in the present disclosure.
[0030] Description of the Reference Numerals
[0031] 1. Bottom semiconductor substrate; 2. Bottom metal diffusion barrier layer; 3. Silicon dioxide layer; 4. Low-k dielectric layer; 5. Top metal diffusion barrier layer; 6. Anti-reflection coating; 7. Metal hard mask layer; 8. Copper void; 9. Copper plating layer; 10. Barrier layer. Detailed Description of the Embodiments
[0032] The following provides a detailed description of the specific embodiments of the present disclosure in conjunction with the drawings. It should be understood that the specific embodiments described herein are only for the purpose of illustrating and explaining the present disclosure and are not used to limit the present disclosure.
[0033] In the present disclosure, unless otherwise stated, the orientation terms such as "upper, lower" generally refer to the upper and lower of the device in its normal use state. For example, referring to Figure 1 the drawing direction of, "inner, outer" refers to the inside and outside relative to the contour of the device. In addition, the terms "first, second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first, second" may explicitly or implicitly include one or more of such features. In the description of the present disclosure, "a plurality" means two or more unless otherwise specifically defined.
[0034] As Figure 1As shown, the present disclosure provides a method for improving copper filling in high aspect ratio situations, the method comprising:
[0035] S1. Providing a copper-plated semiconductor element to be processed with grooves obtained by a post-etching process; the aspect ratio of the grooves of the copper-plated semiconductor element to be processed is 7 or more;
[0036] S2. Sequentially forming a barrier layer and a primary copper grain layer on the surface of the copper-plated semiconductor element to be processed, and forming a first copper plating layer on the surface of the primary copper grain layer through primary copper plating treatment;
[0037] S3. Chemically mechanically polishing the semiconductor element obtained in S2 to obtain a semiconductor element to be filled with holes;
[0038] S4. Forming a secondary copper grain layer on the surface of the semiconductor element to be filled with holes, and forming a second copper plating layer on the surface of the secondary copper grain layer through secondary copper plating treatment;
[0039] S5. Chemically mechanically polishing the semiconductor element obtained in S4 to obtain a semiconductor element with copper-filled holes.
[0040] Through the above technical solution, after the copper-plated semiconductor element to be processed undergoes primary copper plating treatment, chemical mechanical polishing is performed to obtain a semiconductor element to be filled with holes, which can expose the defects and copper voids generated in the copper plating layer; then, secondary copper plating treatment is performed on the semiconductor element to be filled with holes, which can fill the exposed defects and copper voids under the action of secondary copper plating treatment, reduce the risk of generating defects and copper voids, and further improve the stability and yield rate of the obtained semiconductor element with copper-filled holes.
[0041] In one embodiment, as Figure 2 shown, the copper-plated semiconductor element to be processed described in step S1 includes a bottom semiconductor substrate 1 with a flat surface and a sidewall structure provided above the bottom semiconductor substrate 1, wherein a through-hole structure and a groove structure for accommodating copper are formed between the bottom semiconductor substrate 1 and the sidewall structure; the sidewall structure sequentially includes a bottom metal diffusion barrier layer 2, a silicon dioxide layer 3, a low-k dielectric layer 4, a top metal diffusion barrier layer 5, an anti-reflection coating 6, and a metal hard mask layer 7 from bottom to top.
[0042] In one embodiment, the bottom semiconductor substrate 1 used in the present disclosure is a conventional selection in the art, and no special requirements are made in this application. Among them, contact holes (CT) are provided on the surface of the bottom semiconductor substrate 1. Optionally, the through-hole structure or groove structure on the bottom semiconductor substrate 1 is provided above the contact holes (CT) so that the copper plating plated on the through-hole structure or groove structure contacts the contact holes (CT).
[0043] In one embodiment, the materials of the bottom metal diffusion barrier layer 2 and the top metal diffusion barrier layer 5 used in the present disclosure may be nitrogen-doped silicon carbide (NDC), which is generally formed by chemical vapor deposition. In this embodiment, the setting of the bottom metal diffusion barrier layer 2 and the top metal diffusion barrier layer 5 can block or capture metal ions located below or above the metal diffusion barrier layer 2, preventing the metal below or above the metal diffusion barrier layer 2 from diffusing into the low-k dielectric layer 4 and affecting the semiconductor device.
[0044] In one embodiment, the material of the silicon dioxide layer 3 used in the present disclosure is SiO2, which is generally formed by chemical vapor deposition. In this embodiment, in order to eliminate the problems caused by directly disposing the low-k dielectric layer 4 on the metal diffusion barrier layer 2, SiO2 can be disposed between the low-k dielectric layer 4 and the metal diffusion barrier layer 2, which can effectively improve the interface between the low-k dielectric layer 4 and the metal diffusion barrier layer 2.
[0045] In one embodiment, the material of the low-k dielectric layer 4 generally refers to a material with a dielectric constant K lower than 3.0. For example, the material of the low-k dielectric layer 4 is a dielectric material composed of elements such as C, H, O, and Si; the low-k dielectric layer 4 is generally formed by chemical vapor deposition. In this embodiment, due to the increase in the integration density of integrated circuits, the number of conductor connections is also increasing, resulting in the phenomenon of resistance-capacitance delay, which not only affects the speed of the chip but also poses a serious threat to the working reliability. The circuit signal transmission speed depends on the product of the parasitic resistance and the parasitic capacitance. To solve the problem of resistance-capacitance delay, it is necessary to reduce the parasitic resistance and the parasitic capacitance. On the one hand, the technology of using copper interconnects instead of aluminum interconnects reduces the parasitic resistance. On the other hand, the parasitic capacitance is proportional to the dielectric constant of the insulating medium between circuit layers. Therefore, using a low-k material as the insulating medium between different circuit layers can achieve the purpose of reducing the parasitic capacitance.
[0046] In one embodiment, the method for forming the copper-plated semiconductor device described in step S1 includes:
[0047] S11. Providing a bottom semiconductor substrate 1 with a flat surface;
[0048] S12. Sequentially forming a bottom metal diffusion barrier layer 2, a silicon dioxide layer 3, a low-k dielectric layer 4, a top metal diffusion barrier layer 5, an anti-reflection coating 6, and a metal hard mask layer 7 on the surface of the bottom semiconductor substrate 1;
[0049] S13. Processing the semiconductor substrate obtained in S12 using the post-etching process to obtain the copper-plated semiconductor device.
[0050] In one embodiment, the post-etching process described in the present disclosure includes one or more of a photolithography process, a wet etching process, and a dry etching process. In this embodiment, before performing the post-etching process, the metal hard mask layer 7 in the corresponding trench formation region on the semiconductor element obtained in step S12 can be opened by using photolithography, wet etching, and dry etching, and the bottom metal diffusion barrier layer 2, silicon dioxide layer 3, low-k dielectric layer 4, top metal diffusion barrier layer 5, and anti-reflection coating 6 located below the metal hard mask layer 7 can be removed in sequence from top to bottom to form a trench structure for accommodating copper.
[0051] In one embodiment, the dry etching process and the wet etching process described in the present disclosure are conventional selections in the art, and no special requirements are made in this application.
[0052] In one embodiment, the aspect ratio described in the present disclosure refers to the ratio between the etching depth and the average width during the post-etching process. The larger the aspect ratio, the smaller the average width and / or the larger the depth of the through hole or trench formed after etching.
[0053] In one embodiment, the aspect ratio of the semiconductor element to be copper-plated described in the present disclosure is 7 or more.
[0054] As Figure 2 shown, the surface of the semiconductor element obtained after step S2 is, from bottom to top, a barrier layer 10, a primary copper grain layer (not shown in the figure), and a copper plating layer 9. Among them, the copper plating layer 9 fills the entire through hole structure and trench structure and extends upward by a certain height.
[0055] In one embodiment, step S2 further includes forming a barrier layer 10 on the surface of the semiconductor element to be copper-plated by atomic layer deposition or physical vapor deposition. The barrier layer 10 covers the side surfaces and bottom surfaces of each trench structure and through hole structure and extends outside the trench. Among them, the material of the barrier layer 10 used in the present disclosure is TaN and / or Ta.
[0056] In this embodiment, by providing the barrier layer 10 on the semiconductor element to be copper-plated, on the one hand, it can avoid the influence of copper grains and copper plating on the semiconductor element during subsequent processing; on the other hand, it can avoid copper plating ions from entering the sidewall structure and affecting the semiconductor element.
[0057] In one embodiment, step S2 further includes forming a primary copper grain layer on the surface of the barrier layer 10 by physical vapor deposition, and then performing a primary copper plating treatment to obtain a semiconductor element as Figure 3 shown. Among them, the thickness of the primary copper grain layer is 200 - 800 angstroms.
[0058] In this embodiment, before performing the first copper plating process, a very thin layer of copper grains is first deposited on the surface of the barrier layer 10, which can improve the effect of the copper plating process under the action of the copper grains. When the thickness of the first copper grain layer is relatively large, it can reduce the diameter of the trenches or vias on the semiconductor element to be copper-plated, increase the risk of copper voids generated during the copper plating process, and thus reduce the effect of the copper plating process; when the thickness of the first copper grain layer is relatively small, it will not only reduce the growth efficiency of the copper plating layer but also reduce the integrity of the copper plating formation.
[0059] In one embodiment, step S3 further includes performing a chemical mechanical polishing on the semiconductor element obtained in S2, and stopping the polishing process when the low-k dielectric layer is polished to obtain the semiconductor element with holes to be filled.
[0060] In this embodiment, the inventors of the present disclosure found that when the aspect ratio of the semiconductor element is relatively large, during the copper plating process, more or less copper voids 8 will be formed in the upper middle part of the via structure and trench structure. As Figure 4 shown, after performing a polishing process on the semiconductor element obtained in S2, the copper voids 8 in the obtained semiconductor element with holes to be filled can be exposed. At this time, the copper voids 8 are at the top of the via structure and trench structure.
[0061] In one embodiment, in order to reduce the copper voids 8 in the copper plating layer, the semiconductor element with holes to be filled can be subjected to a second copper plating process.
[0062] In one embodiment, in order to enable the copper plating layer to be formed on the entire surface of the semiconductor element with holes to be filled, a very thin second copper grain layer (not shown in the figure) is first formed on the surface of the semiconductor element with holes to be filled by physical vapor deposition process, wherein the thickness of the second copper grain layer is 200 - 800 angstroms.
[0063] In this embodiment, before performing the second copper plating process, a very thin layer of copper grains is first deposited on the entire surface of the semiconductor element with holes to be filled, which can improve the effect of the copper plating process under the action of the copper grains.
[0064] In one embodiment, the first copper plating process and the second copper plating process described in the present disclosure are conventional selections in the art, and no special requirements are made in this application.
[0065] In one embodiment, step S5 further includes performing a chemical mechanical polishing on the semiconductor element obtained in S4, and stopping the polishing process when the low-k dielectric layer is polished to obtain the copper-filled semiconductor element.
[0066] In one embodiment, the barrier layer, the primary copper grain layer, and the secondary copper grain layer are formed by physical vapor deposition. The physical vapor deposition method described in the present disclosure is to form the coating precursor in the form of atoms or ions, and to impact the formed atoms or ions on the substrate to achieve the purpose of plating the coating precursor on the surface of the substrate.
[0067] In one embodiment, when forming the barrier layer 10 by atomic layer deposition, the coating precursor used includes a target material and an optional deposition gas phase; the target material is Ta metal, and the deposition gas phase is nitrogen.
[0068] In one embodiment, when forming the primary copper grain layer and the secondary copper grain layer by physical vapor deposition, the coating precursor used includes a target material, and the target material is copper metal and / or copper-manganese alloy.
[0069] In one embodiment, as Figure 5 shown, the via-filled semiconductor element prepared by the method of the present disclosure can reduce the defects and copper voids generated during the first copper plating process, form a copper plating layer 9 with better integrity, and can reduce the parasitic resistance of the semiconductor element. Therefore, the method of the present disclosure can improve the yield and reliability of the manufactured semiconductor.
[0070] The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings. However, the present disclosure is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.
[0071] In addition, it should be noted that, in the above specific embodiments, the various specific technical features described can be combined in any suitable manner without conflict. To avoid unnecessary repetition, the present disclosure does not separately describe various possible combination methods.
[0072] Furthermore, any combination can be made between various different embodiments of the present disclosure as long as it does not violate the idea of the present disclosure, and it should also be regarded as the content disclosed by the present disclosure.
Claims
1. A method for improving copper filling in high aspect ratio conditions, characterized in that, The method includes: S1. Providing a copper-plated semiconductor element with grooves obtained by a post-etching process; the aspect ratio of the grooves of the copper-plated semiconductor element is 7 or more; S2. Sequentially forming a barrier layer and a primary copper grain layer on the surface of the copper-plated semiconductor element, and forming a first copper plating layer on the surface of the primary copper grain layer through primary copper plating; S3. Chemically mechanically polishing the semiconductor element obtained in S2 to obtain a semiconductor element with holes to be filled; S4. Forming a secondary copper grain layer on the surface of the semiconductor element with holes to be filled, and forming a second copper plating layer on the surface of the secondary copper grain layer through secondary copper plating; S5. Chemically mechanically polishing the semiconductor element obtained in S4 to obtain a copper-filled hole semiconductor element.
2. The method according to claim 1, characterized in that, The post-etching process includes one or several of a photolithography process, a wet etching process, and a dry etching process.
3. The method according to claim 1, characterized in that, The barrier layer, the primary copper grain layer, and the secondary copper grain layer are respectively formed by a physical vapor deposition process.
4. The method according to claim 3, characterized in that, The physical vapor deposition includes vacuum sputtering deposition and / or ion plating deposition; The reaction temperature of the physical vapor deposition is 25 - 300 °C.
5. The method according to claim 3, characterized in that, The material of the barrier layer is TaN and / or Ta; the coating precursor used to form the barrier layer by the physical vapor deposition includes a target and an optional deposition gas phase; the target is Ta metal, and the deposition gas phase is nitrogen.
6. The method according to claim 3, characterized in that, The targets used to form the primary copper grain layer and the secondary copper grain layer by the physical vapor deposition are respectively copper metal and / or copper-manganese alloy.
7. The method according to claim 1, characterized in that, The thicknesses of the primary copper grain layer and the secondary copper grain layer are respectively 200 - 800 angstroms.
8. The method according to claim 1, characterized in that, Step S1 includes: S11. Providing a bottom semiconductor substrate with a flat surface; S12. Sequentially forming a bottom metal diffusion barrier layer, a silicon dioxide layer, a low-K dielectric layer, a top metal diffusion barrier layer, an anti-reflection coating, and a metal hard mask layer on the surface of the bottom semiconductor substrate; S13. Processing the semiconductor element obtained in S12 by the post-etching process to form the grooves, obtaining the copper-plated semiconductor element.
9. The method according to claim 8, characterized in that, Step S3 further includes chemically mechanically polishing the semiconductor element obtained in S2, and stopping the polishing process when polishing to the low-K dielectric layer, obtaining the semiconductor element with holes to be filled.
10. The method according to claim 8, characterized in that, Step S5 further includes chemically mechanically polishing the semiconductor element obtained in S4, and stopping the polishing process when polishing to the low-K dielectric layer, obtaining the copper-filled hole semiconductor element.