Spread spectrum fractional frequency control circuit, fractional frequency phase-locked loop and chip

Abstract

The present invention provides a spread spectrum fractional frequency division control circuit, a fractional frequency division phase-locked loop, and a chip. The spread spectrum fractional frequency division control circuit includes a spread spectrum circuit, a signal modulator, and a frequency division control signal output circuit. The spread spectrum circuit processes a superposition result according to a corresponding spread spectrum mode to obtain a corresponding first frequency division control signal. The spread spectrum circuit processes the superposition result differently in a non-spread spectrum mode and different spread spectrum modes (including a center spread spectrum mode and a downward spread spectrum mode). Therefore, the technical solution of the present invention can support the non-spread spectrum mode and different spread spectrum modes, and can maintain an effective spread spectrum function when the fractional frequency division ratio is close to 0 or close to 1. Therefore, it can achieve a good phase noise suppression effect while achieving high frequency and high resolution, providing a high degree of flexible configuration capability.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a spread spectrum fractional frequency division control circuit, a fractional frequency division phase-locked loop and a chip. Background Art

[0002] High-speed frequency sources are a major source of electromagnetic interference (EMI) in electronic circuits, potentially negatively impacting system performance and stability. To effectively suppress EMI from high-speed digital systems, various methods can be employed, including the use of high-order filters, power supply decoupling, effective clock line layout, ground isolation from power grounds, and clock buffers. If the system clock is provided by a phase-locked loop (PLL), fractional frequency division and spread spectrum can be performed on the clock to spread the EMI of the output clock across a wider spectrum, effectively reducing EMI and improving system reliability and stability.

[0003] Although some existing spread spectrum control circuits can use the phase delay compensation principle to achieve the superposition of fractional frequency division and spread spectrum functions, they still have the problem of phase spurious (that is, the degree of interference from fractional spurious), and cannot achieve good phase noise performance while achieving high frequency and high resolution.

[0004] Although some other existing spread spectrum control circuits can cyclically modulate their spread spectrum fractional frequency dividers used to achieve fractional frequency division and spread spectrum functions through a Σ-△ modulator, thereby reducing the degree of interference of fractional spurious signals in the modulated output, they can only perform center spread spectrum with a small amplitude. When the fractional frequency division ratio is close to 0 or close to 1, the center spread spectrum function will be distorted downward or upward, that is, it loses its spread spectrum function at this time and has a small scope of application.

[0005] Therefore, a new fractional frequency division and spread spectrum control scheme is urgently needed, which can not only realize the superposition of fractional frequency division and spread spectrum functions to reduce the signal spurious problem existing in the existing fractional frequency division technology, but also provide a high degree of flexible configuration capability to maintain an effective spread spectrum function when the fractional frequency division ratio is close to 0 or close to 1, thereby achieving good phase noise suppression effect while achieving high frequency and high resolution. Summary of the Invention

[0006] The object of the present invention is to provide a spread spectrum fractional frequency division control circuit, a fractional phase-locked loop and a chip, which can realize the superposition of fractional frequency division and spread spectrum functions and also provide a high flexible configuration capability.

[0007] To achieve the above object, the present invention provides a spread spectrum fractional frequency division control circuit, which includes:

[0008] a spread spectrum circuit, configured to superimpose an n+1-bit fractional frequency division control signal with a corresponding triangular wave signal in a corresponding spread spectrum mode to obtain a first superposition result, and perform corresponding processing on the first superposition result according to the spread spectrum mode to obtain a corresponding first frequency division control signal, wherein the processing of the first superposition result by the spread spectrum circuit is different in a non-spread spectrum mode and in different spread spectrum modes;

[0009] a signal modulator, coupled to the spread spectrum circuit, and configured to modulate and shape the first frequency-divided control signal; and

[0010] A frequency division control signal output circuit is coupled to the signal modulator and the corresponding fractional frequency divider, and is used to provide a second frequency division control signal to the fractional frequency divider according to the output of the signal modulator, and the fractional frequency divider is used to divide the corresponding clock based on the second frequency division control signal.

[0011] Optionally, an initial value of the first superposition result is equal to MFN[n:0], the first superposition result is incremented by MODSTEP in each clock cycle of the feedback clock fed back by the fractional divider until it reaches a maximum value, and then the first superposition result is decremented by MODSTEP in each clock cycle of the feedback clock until it decrements back to MFN[n:0];

[0012] The maximum value is MFN[n:0]+MODSTEP*MODCNT, MFN[n:0] is the n+1-bit fractional frequency division control signal, MODSTEP is the spread spectrum modulation step configured by the register, and MODCNT is the number of spread spectrum modulation steps configured by the register.

[0013] Optionally, the register configuration value of MODCNT is calculated based on the modulation frequency and reference clock in the spread spectrum mode, and the register configuration value of MODSTEP is calculated based on the modulation depth in the spread spectrum mode, the n+1-bit fractional frequency division control signal and the corresponding integer frequency division control signal.

[0014] Optionally, the spread spectrum circuit subtracts different first subtrahend values from the first superposition result in a non-spread spectrum mode and in different spread spectrum modes to achieve the different processing in the non-spread spectrum mode and in different spread spectrum modes, and the first subtrahend value is configured by a second register or calculated according to the register configuration values of MODSTEP and MODCNT; wherein MODSTEP is the spread spectrum modulation step configured by the register, and MODCNT is the number of spread spectrum modulation steps configured by the register.

[0015] Optionally, the first subtraction value is equal to 0 in non-spread spectrum mode, equal to MODSTEP*MODCNT / 2 in center spread spectrum mode, and equal to MODSTEP*MODCNT in down spread spectrum mode.

[0016] Optionally, the spread spectrum circuit includes:

[0017] a triangular wave generator, configured to generate and output the triangular wave signal corresponding to the n+1-bit fractional frequency division control signal in the corresponding spread spectrum mode;

[0018] a second accumulator, coupled to the triangular wave generator and the n+1-bit fractional frequency control signal, and configured to superimpose an output of the triangular wave generator and the n+1-bit fractional frequency control signal to obtain a first superposition result;

[0019] A subtractor is coupled to the second accumulator and is used to subtract the first subtraction value from the first superposition result output by the second accumulator to obtain the first frequency division control signal.

[0020] Optionally, the spectrum spreading circuit is further configured to expand the number of bits of the processed result by k bits to output the first frequency division control signal of n+k+1 bits, wherein n≥0, k≥2, and n and k are both integers.

[0021] Optionally, n=13, k=2.

[0022] Optionally, the spectrum spreading circuit further includes a first register, in which an additional value of n+k+1 bits is configured. The spectrum spreading circuit is further used to superimpose the first superposition result or the processed result with the additional value, thereby expanding the number of bits of the processed result by k bits.

[0023] Optionally, the spread spectrum fractional frequency division control circuit further includes:

[0024] a signal separation circuit coupled to the spread spectrum circuit and configured to separate the highest k bits and the remaining n+1 bits of the n+k+1-bit first frequency division control signal to obtain a high k-bit signal and a low n+1-bit signal;

[0025] a high-k bit delay circuit coupled to the signal separation circuit and the frequency division control signal output circuit, and configured to delay the high-k bit signal output by the signal separation circuit and then provide the signal to the frequency division control signal output circuit;

[0026] The signal modulator modulates and shapes the low n+1 bit signal output by the signal separation circuit, and the output of the signal modulator is synchronized with the output of the high k bit delay circuit;

[0027] The frequency division control signal output circuit further superimposes the output of the signal modulator and the output of the high-k bit delay circuit.

[0028] Optionally, the high-k bit delay circuit includes a delay chain, the delay chain includes at least two first delay units connected in cascade, and the number of stages of the first delay units matches the modulation time of the signal modulator.

[0029] Optionally, the first delay unit is a k-bit register; and / or the number of stages of the first delay unit is three, and the signal modulator is a third-order SDM modulator using a MASH structure.

[0030] Optionally, the frequency division control signal output circuit is further configured to: superimpose the output of the high-k bit delay circuit, the output of the signal modulator and the corresponding integer frequency division control signal, and then subtract the k-bit second subtrahend value to obtain the second frequency division control signal after integer frequency division superposition.

[0031] Optionally, the frequency division control signal output circuit includes:

[0032] a third accumulator, coupled to the signal modulator and the high-k bit delay circuit, and configured to superimpose an output of the high-k bit delay circuit and an output of the signal modulator;

[0033] A third register, used to configure the second subtrahend value;

[0034] a fourth accumulator, coupled to the third accumulator, the third register, and a corresponding integer frequency division control signal, and configured to add an output of the third accumulator and the integer frequency division control signal and then subtract the second subtrahend value;

[0035] An output register is coupled to the fourth accumulator and is used to synchronize the output of the fourth accumulator with the feedback clock fed back by the fractional frequency divider to output the second frequency division control signal.

[0036] Optionally, the spread spectrum fractional frequency control circuit also includes a pseudo-random sequence generator for generating and outputting a pseudo-random sequence; the spread spectrum circuit also includes a first accumulator, coupled to the n+1-bit fractional frequency control signal and the pseudo-random sequence generator, and used to superimpose the n+1-bit fractional frequency control signal and the pseudo-random sequence to obtain a second superposition result, and superimpose the second superposition result with the triangular wave signal to obtain the first superposition result.

[0037] Optionally, the spread spectrum circuit is further coupled to an enable signal, a spread spectrum mode control signal, and a spread spectrum direction control signal, and provides the following operating modes according to the enable signal, the spread spectrum mode control signal, and the spread spectrum direction control signal:

[0038] (1) Integer division mode only: the enable signal is at the first level;

[0039] (2) Fractional frequency division mode without superimposed spread spectrum: the enable signal is at the second level, and the spread spectrum mode control signal is at the second level;

[0040] (3) Spread spectrum mode: the enable signal is at the second level, the spread spectrum mode control signal is at the first level, and the center spread spectrum is performed when the spread spectrum direction control signal is at the first level, and the downward spread spectrum is performed when the spread spectrum direction control signal is at the second level.

[0041] Optionally, the spread spectrum circuit further divides the spread spectrum mode into the following types according to the n+1-bit fractional frequency division control signal MFN[n:0] and the spread spectrum direction control signal:

[0042] (3-1) Integer frequency division center spread spectrum mode: the spread spectrum direction control signal is at the first level, and MFN[n:0]=0;

[0043] (3-2) Integer frequency division downward spread spectrum mode: the spread spectrum direction control signal is at the second level, and MFN[n:0]=0;

[0044] (3-3) Center spread spectrum mode with superimposed fractional frequency division: the spread spectrum direction control signal is at the first level, and MFN[n:0]≠0;

[0045] (3-4) Downward spread spectrum mode with fractional frequency division: the spread spectrum direction control signal is at the second level, and MFN[n:0]≠0.

[0046] Based on the same inventive concept, the present invention also provides a fractional phase-locked loop, comprising a predivider, a frequency detector, a charge pump, a low-pass filter and a voltage-controlled oscillator connected in sequence, the fractional phase-locked loop also comprising a fractional frequency divider and a spread spectrum fractional frequency division control circuit as described in the present invention, the output end of the fractional frequency divider being coupled to the feedback input end of the frequency detector, one input end of the fractional frequency divider being coupled to the output end of the voltage-controlled oscillator, and the other input end of the fractional frequency divider being coupled to the output end of the spread spectrum fractional frequency division control circuit.

[0047] Based on the same inventive concept, the present invention further provides a chip comprising the phase-locked loop as described in the present invention.

[0048] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects:

[0049] 1. The spread spectrum fractional frequency division control circuit of the present invention includes a spread spectrum circuit, a signal modulator, and a frequency division control signal output circuit. The spread spectrum circuit is capable of superimposing an n+1-bit fractional frequency division control signal with a corresponding triangular wave signal in a corresponding spread spectrum mode, and performing corresponding processing on the superimposed result according to the spread spectrum mode to obtain a corresponding first frequency division control signal. The spread spectrum circuit processes the first superimposed result differently in a non-spread spectrum mode (e.g., the integer-only spread spectrum mode or the fractional frequency division mode without superimposed spread spectrum in the embodiment of the present invention) and in different spread spectrum modes (e.g., the center spread spectrum mode and the downward spread spectrum mode in the embodiment of the present invention). The first frequency division control signal is modulated and shaped by the signal modulator and then output by the frequency division control signal output circuit as a second frequency division control signal, thereby causing the fractional frequency divider to divide the corresponding clock based on the second frequency division control signal. Therefore, the technical solution of the present invention can support non-spread spectrum mode and different spread spectrum modes, and can maintain an effective spread spectrum function when the fractional division ratio is close to 0 or close to 1, thereby achieving high frequency and high resolution while achieving excellent phase noise suppression.

[0050] 2. According to actual needs, the register configuration values of the spread spectrum modulation step length MODSTEP and the spread spectrum modulation step number MODCNT can be calculated and configured through information such as the spread spectrum modulation frequency and modulation amplitude, thereby providing a high degree of flexible configuration capability and a wide range of applications.

[0051] 3. The spread spectrum fractional frequency division control circuit of the present invention can also expand the number of bits of the processing result obtained by its spread spectrum circuit by k bits, thereby avoiding the problem of signal overflow after the fractional frequency division and spread spectrum functions are superimposed. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0053] Figure 1 FIG. 1 is a schematic diagram of a circuit structure of a phase-locked loop according to a first embodiment of the present invention.

[0054] Figure 2 FIG. 1 is a schematic diagram of the structure of a spread spectrum fractional frequency division control circuit according to a first embodiment of the present invention.

[0055] Figure 3 1 is a schematic diagram of an exemplary structure of a spread spectrum circuit in a spread spectrum fractional frequency division control circuit according to the first embodiment of the present invention.

[0056] Figure 4 FIG. 1 is a schematic diagram of center spectrum spreading performed by the spectrum spreading circuit in the spectrum spreading fractional frequency division control circuit according to the first embodiment of the present invention.

[0057] Figure 5 FIG. 1 is a schematic diagram of downward spreading of the spread spectrum circuit in the spread spectrum fractional frequency division control circuit according to the first embodiment of the present invention.

[0058] Figure 6 This is a schematic diagram of an exemplary structure of a signal modulator in a spread spectrum fractional frequency division control circuit according to the first embodiment of the present invention.

[0059] Figure 7 This is a schematic diagram of an exemplary structure of the third delay unit in the signal modulator of the spread spectrum fractional frequency division control circuit of the first embodiment of the present invention.

[0060] Figure 8 This is a schematic diagram of an exemplary structure of a frequency division control signal output circuit in a spread spectrum fractional frequency division control circuit according to the first embodiment of the present invention.

[0061] Figure 9 FIG. 4 is a schematic diagram of the structure of a spread spectrum fractional frequency division control circuit according to a second embodiment of the present invention.

[0062] Figure 10 1 is a schematic diagram of an exemplary structure of a spread spectrum circuit in a spread spectrum fractional frequency division control circuit according to a second embodiment of the present invention.

[0063] Figure 11 This is a schematic diagram of an exemplary structure of a high-k bit delay circuit in a spread spectrum fractional frequency division control circuit according to the second embodiment of the present invention.

[0064] Figure 12 This is a schematic diagram of an exemplary structure of a frequency division control signal output circuit in a spread spectrum fractional frequency division control circuit according to the second embodiment of the present invention.

[0065] Figure 13 1 is a schematic diagram of an exemplary structure of a spread spectrum fractional frequency division control circuit according to the second embodiment of the present invention (n=13, k=2, m=7). DETAILED DESCRIPTION

[0066] In the following description, a large number of specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, some technical features known in the art are not described to avoid confusion with the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. The same reference numerals throughout represent the same elements. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected to" another element, there are no intervening elements. When used herein, the singular forms "a," "an," and "said / the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of certain features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0067] The following is combined with Figure 1 To the attached Figure 13 The technical solution of the present invention is described in detail with reference to specific embodiments.

[0068] First embodiment

[0069] Please refer to Figure 1 An embodiment of the present invention provides a spread spectrum fractional frequency division control circuit 10 and a fractional frequency division phase-locked loop having the spread spectrum fractional frequency division control circuit 10. That is, the spread spectrum fractional frequency division control circuit 10 of this embodiment is provided in the fractional frequency division phase-locked loop.

[0070] In an example, see Figure 1 The fractional-frequency phase-locked loop of this embodiment includes not only a pre-divider (DIVM, also called a "pre-divider") 11, a phase frequency detector (PFD) 12, a charge pump (CHP) 13, a low-pass filter (LPF, also called a "loop filter") 14 and a voltage-controlled oscillator (VCO) 15 connected in sequence, but also includes a fractional frequency divider (DIVN) 16 and a spread spectrum fractional frequency control circuit 10. One input end of the fractional frequency divider (DIVN) 16 is coupled to the output end of the voltage-controlled oscillator 15, and the other input end is coupled to the output end of the spread spectrum fractional frequency control circuit 10.

[0071] Among them, the prescaler 11 is used to divide the external input clock (whose frequency is F clk_in) is divided to generate a reference clock (not shown), whose frequency is the reference frequency F ref , the reference clock is sent to the frequency detector 12.

[0072] The frequency detector 12 is used to detect the reference clock (whose frequency is F) output by the prescaler 11. ref ) and the feedback clock CLK_DIV output by the fractional divider (DIVN) 16 generate charge and discharge signals (not shown) with a phase difference.

[0073] The charge pump 13 is used to generate a corresponding bias current based on the control of the charge and discharge signal output by the phase and frequency detector 12 .

[0074] The low-pass filter 14 is configured to generate a corresponding control voltage (not shown) based on the bias current provided by the charge pump 13 .

[0075] The voltage controlled oscillator 15 is used to generate a corresponding clock (whose frequency is Fvco) based on the control voltage output by the low-pass filter 14 .

[0076] The spread-spectrum fractional frequency division control circuit 10 is configured to enter a corresponding operating mode (e.g., integer-only frequency division mode, fractional frequency division mode without superimposed spread spectrum, center-spread spectrum mode of integer frequency division or downward spread spectrum mode of integer frequency division, center-spread spectrum mode with superimposed fractional frequency division or downward spread spectrum mode with superimposed fractional frequency division, etc.) based on the configuration of corresponding control signals (including the fractional frequency division control signal MFN[n:0], the integer frequency division control signal MFI[m:0], the enable signal PLLFRAEN, the spread-spectrum mode control signal SSCGBYP, and the spread-spectrum direction control signal SPREADCTL, etc.), and dynamically change the second frequency division control signal MFIS[m:0] generated and output by the fractional frequency divider 16 based on these control signals and the feedback clock CLK_DIV output by the fractional frequency divider 16, thereby making the average value of the division ratio of the fractional frequency divider 16 a preset fractional value.

[0077] The fractional divider 16 is used to divide the clock (whose frequency is Fvco) output by the voltage controlled oscillator 15 based on the second frequency division control signal MFIS[m:0] output by the spread spectrum fractional frequency division control circuit 10, and then feedback the feedback clock CLK_DIV, where m and n are both integers, and m can be equal to (n+1) / 2 or any other suitable value. The expected frequency of the feedback clock CLK_DIV is equal to the phase detection frequency F of the phase frequency detector 12. pfd (which is equal to F ref ). The reference clock frequency F ref (i.e. reference frequency) is as follows:

[0078] F ref= F clk_in / DIVM.

[0079] Wherein, DIVM is the frequency division coefficient of the prescaler 11 .

[0080] When the fractional frequency phase-locked loop is started, the frequency of the feedback clock CLK_DIV gradually approaches the frequency of the reference clock F ref Until locked, the feedback clock CLK_DIV is used as a reference clock for fractional division and spread spectrum and is provided to the spread spectrum fractional division control circuit 10 .

[0081] The output of the frequency detector 12 is effectively filtered out by the low-pass filter 14 to remove phase spurious, and then the control voltage of the voltage controlled oscillator 15 is adjusted to make the output frequency F of the voltage controlled oscillator 15 pll_VCO Lock to the desired frequency point.

[0082] In addition, when the output frequency F of the voltage controlled oscillator 15 pll_VCO Just at the phase frequency F of the phase frequency detector 12 pfd (which is equal to F ref ) at the n±(b / A) multiple frequency point, the spurious frequency is closest to the main signal, and the frequency difference between the two is very small (for example, only 1 / M 3 F pfd ), which cannot be filtered out by the low-pass filter 14. At this time, the voltage-controlled oscillator 15 may be subject to the strongest fractional spurious interference. In addition, due to the high operating frequency and short period of the fractional frequency phase-locked loop, it is more likely to become a source of electromagnetic interference.

[0083] In this embodiment, in order to effectively suppress the electromagnetic interference of the fractional-frequency phase-locked loop, the feedback clock CLK_DIV of the fractional frequency divider is spread by the spread spectrum fractional frequency control circuit 10, and the spread spectrum function is superimposed, thereby dynamically changing the division ratio of the fractional frequency divider 16, so that the average value of the division ratio of the fractional frequency divider 16 is a preset fractional value, and avoiding conflicts between the division ratios in the fractional frequency division mode and the spread spectrum mode.

[0084] Please refer to Figure 2 In one example, the spread spectrum fractional frequency division control circuit 10 includes a pseudo-random sequence generator 100, a spread spectrum circuit 101, a signal modulator 104, and a frequency division control signal output circuit 105. In other examples, the spread spectrum fractional frequency division control circuit 10 may omit the pseudo-random sequence generator 100 as needed.

[0085] The pseudo-random sequence generator 100 is used to generate and output a pseudo-random sequence (PRBS). A pseudo-random sequence (PRBS) has a "random" characteristic, and its cycle length can be related to the number of bits in the pseudo-random sequence generator 100 (also known as the "order of the pseudo-random sequence generator 100"). The larger the number of bits, the longer the PRBS cycle length. Within each cycle, the binary digits "0" and "1" in the pseudo-random sequence PRBS code stream output by the pseudo-random sequence generator 100 are randomly distributed, with an equal number of "0" and "1" bits. Its spectral characteristics closely resemble those of white noise. Incorporating the pseudo-random sequence 100 enables the spread spectrum fractional frequency control circuit 10 to more evenly spread the quantization noise across a higher frequency band, improving the signal-to-noise ratio while reducing the impact of quantization error. Optionally, the pseudo-random sequence generator 100 is a 32-bit linear feedback shift register that can generate the pseudo-random sequence PRBS using methods such as an exclusive-OR operation.

[0086] The spread spectrum circuit 101 is coupled to the n+1-bit fractional frequency division control signal MFN[n:0] and the pseudo-random sequence generator 100, and is used to superimpose the n+1-bit fractional frequency division control signal MFN[n:0] and the pseudo-random sequence generator 100 in a corresponding spread spectrum mode to obtain a second superposition result (not shown), further superimpose the second superposition result with the corresponding triangular wave signal TEMP to obtain a first superposition result (not shown), and perform corresponding processing on the first superposition result according to the spread spectrum mode to obtain an n+1-bit first frequency division control signal OUT[(n+k):0], where n≥0, k≥2, and n and k are both integers. In the non-spread spectrum mode, no triangle wave signal TEMP is superimposed on the second superposition result (i.e., in this case, the triangle wave signal TEMP can be considered to be constantly equal to 0). Furthermore, in the non-spread spectrum mode and in different spread spectrum modes (where different spread spectrum modes have different spreading directions, such as a center spread spectrum mode and a downward spread spectrum mode), the spread spectrum circuit 101 can use any appropriate method to process the first superposition result accordingly. Furthermore, the processing performed by the spread spectrum circuit 101 on the first superposition result differs between the non-spread spectrum mode and the different spread spectrum modes. The non-spread spectrum mode and the spread spectrum mode can be determined by an enable signal PLLFRAEN supplied to the spread spectrum circuit 101. For example, when PLLFRAEN = 0 (i.e., the enable signal is at a low level), the spread spectrum circuit 101 operates in the non-spread spectrum mode, which can be either an integer-only frequency division mode (i.e., an integer-only frequency division mode without superimposed spreading) or a fractional-only frequency division mode (i.e., a fractional-only frequency division mode without superimposed spreading). When PLLFRAEN=1 (i.e., the enable signal is at a high level), the spread spectrum circuit 101 operates in a spread spectrum mode, which can be a spread spectrum mode with only integer frequency division (i.e., an integer frequency division mode with superimposed spread spectrum), or a spread spectrum mode with superimposed fractional frequency division (also referred to as a "fractional frequency division mode with superimposed spread spectrum"). The spread spectrum mode with superimposed fractional frequency division can be a spread spectrum mode with an integer part equal to 0 (i.e., the integer frequency division control signal MFI[m:0]=0), or a spread spectrum mode with an integer part not equal to 0 (i.e., MFI[m:0]≠0).

[0087] Optionally, refer to Figure 3 The spread spectrum circuit 101 subtracts different first subtrahend values from the first superposition result in the non-spread spectrum mode and in different spread spectrum modes, thereby implementing different processing in the non-spread spectrum mode and in different spread spectrum modes. The first subtrahend value is configured by the second register 1013 or calculated based on the register configuration values of MODSTEP and MODCNT, where MODSTEP is the spread spectrum modulation step size configured in the register, and MODCNT is the number of spread spectrum modulation steps configured in the register.

[0088] Please refer to Figure 3In one example, in non-spread spectrum mode (for example, the enable signal PLLFRAEN is configured to be 0, and the spread spectrum mode control signal SSCGBYP is configured to be x, where x represents any level state of 0, 1, or other states; or the enable signal PLLFRAEN is configured to be 1 and the spread spectrum mode control signal SSCGBY is configured to be 1), the first subtracted value is equal to 0; in center spread spectrum mode (for example, the enable signal PLLFRAEN is configured to be 1, SSCGBYP is configured to be 0, and the spread spectrum direction control signal SPREADCTL is configured to be 0), the first subtracted value is equal to MODSTEP*MODCNT / 2; in downward spread spectrum mode (for example, the enable signal PLLFRAEN is configured to be 1, SSCGBYP is configured to be 0, and SPREADCTL is configured to be 1), the first subtracted value is equal to MODSTEP*MODCNT.

[0089] In an example, see Figure 3 The spread spectrum circuit 101 includes a first accumulator U1, a triangle wave generator 1011, a second accumulator U2, a second register 1013 and a subtractor U3.

[0090] Among them, one input end of the first accumulator U1 is coupled to the n+1-bit fractional frequency control signal MFN[n:0], and the other input end is coupled to the output end of the pseudo-random sequence generator 100. The first accumulator U1 is used to superimpose the n+1-bit fractional frequency control signal MFN[n:0] and the pseudo-random sequence PRBS output by the pseudo-random sequence generator 100 to obtain a second superposition result (i.e., the fractional frequency control signal of the superimposed pseudo-random sequence), and provide the second superposition result to an input end of the second accumulator U2.

[0091] The triangle wave generator 1011 is coupled to the spread spectrum mode control signal SSCGBY and the feedback clock CLK_DIV output by the fractional divider 16. The triangle wave generator 1011 is configured to generate and output a triangle wave signal TEMP corresponding to the n+1-bit fractional frequency control signal MFN[n:0] based on the feedback clock CLK_DIV in the spread spectrum mode (e.g., when PLLFRAEN=1 and SSCGBY=0 are configured). In the non-spread spectrum mode (e.g., when PLLFRAEN=0 and SSCGBY=x are configured, or when PLLFRAEN=1 and SSCGBY=1 are configured), the triangle wave generator 1011 outputs TEMP=0. In the spread spectrum mode (e.g., when PLLFRAEN=1 and SSCGBY=0 are configured), the triangle wave generator 1011 can use the feedback clock CLK_DIV output by the fractional divider 16 as a reference clock and an initial value of 0 to generate the triangle wave signal TEMP. For details, see [Referring to] Figures 1 to 3 , the specific principles are as follows:

[0092] The initial value of the triangular wave signal TEMP is 0. With the feedback clock CLK_DIV as the reference clock, TEMP increments by one MODSTEP on the rising edge of each clock cycle of the feedback clock CLK_DIV, with the number of increments equal to the number of spread-spectrum modulation steps configured in the register, MODCNT, until TEMP reaches its maximum value of MODSTEP*MODCNT. Then, with the rising edge of each clock cycle of the feedback clock CLK_DIV, TEMP begins to decrement by one MODSTEP until it returns to its initial value of 0. This process of increasing from 0 to the maximum value of MODSTEP*MODCNT and then decreasing to 0 forms one cycle of the triangular wave signal TEMP.

[0093] A first input terminal of the second accumulator U2 is coupled to the output terminal of the triangular wave generator 1011, and a second input terminal is coupled to the output terminal of the first accumulator U1 (i.e., coupled to the second superposition result n+1-bit fractional frequency division control signal MFN[n:0]). The second accumulator U2 is used to superimpose the triangular wave signal TEMP output by the triangular wave generator 1011 and the output of the first accumulator U1 (i.e., the n+1-bit fractional frequency division control signal MFN[n:0] after superimposing the pseudo-random sequence PRBS) to output a first superposition result.

[0094] Based on this, the first superposition result output by the second accumulator U2 in the spread spectrum mode (e.g., center spread spectrum mode or downward spread spectrum mode) is also a triangular wave signal, whose initial value is equal to the n+1-bit fractional frequency division control signal MFN[n:0], and the first superposition result increases by MODSTEP in each clock cycle of the feedback clock CLK_DIV fed back by the fractional frequency divider 16, until it reaches a maximum value of MFN[n:0]+MODSTEP*MODCNT, with the number of increment steps being MODCNT. Thereafter, the first superposition result decreases by MODSTEP in each clock cycle of the feedback clock CLK_DIV until it decreases back to the n+1-bit fractional frequency division control signal MFN[n:0], with the number of decrement steps also being MODCNT. Wherein, MODSTEP is the spread spectrum modulation step size configured by the register, and MODCNT is the number of spread spectrum modulation steps configured by the register.

[0095] That is, when the fractional-frequency phase-locked loop of this embodiment operates in the corresponding spread spectrum mode (for example, configuring PLLFRAEN=1 and SSCGBY=0), the modulation frequency and modulation depth of its spread spectrum are configured by MODSTEP and MODCNT.

[0096] One input terminal of the subtractor U3 is coupled to the output terminal of the second accumulator U2, and another input terminal is coupled to a second register 1013. The second register 1013 may be a register group, coupled to the spread spectrum mode control signal SSCGBY and the spread spectrum direction control signal SPREADCTL. The second register 1013 is used to configure a first subtrahend value required for the current spread spectrum mode. The subtractor U3 is used to subtract the output of the second accumulator U2 from the first subtrahend value configured in the second register 1013 to output a first frequency division control signal OUT[(n+k):0]. The first subtrahend values configured in the second register 1013 in the non-spread spectrum mode and in different spread spectrum modes are different.

[0097] In one example, in non-spread spectrum mode (for example, configuring PLLFRAEN=1 and SSCGBY=1), the first subtrahend value configured by the second register 1013 is equal to 0; in center spread spectrum mode (for example, configuring PLLFRAEN=1, SSCGBY=0 and SPREADCTL=0), the first subtrahend value configured by the second register 1013 is equal to MODSTEP*MODCNT / 2; in downward spread spectrum mode (for example, configuring PLLFRAEN=1, SSCGBY=0 and SPREADCTL=1), the first subtrahend value configured by the second register 1013 is equal to MODSTEP*MODCNT, where MODCNT is the number of spread spectrum modulation steps configured by the register, and MODSTEP is the spread spectrum modulation step size configured by the register.

[0098] Optionally, the register configuration value of MODCNT is based on the modulation frequency f in the current spread spectrum mode. MOD and the reference clock frequency F ref Calculation, the register configuration value of MODSTEP is calculated based on the modulation depth MD in the current spread spectrum mode and the n+1-bit fractional frequency control signal MFN[n:0] and the corresponding m+1-bit integer frequency control signal MFI[m:0], as follows:

[0099] MODCNT=F clk_in / (DIVM*2*fMOD);MODSTEP=MD*LDF*2 n+1 / (100*MODCNT);

[0100] Where m≥0 and is an integer, F clk_in is the frequency of the external input clock of the fractional-frequency phase-locked loop, f MOD is the spread spectrum modulation frequency, DIVM is the division coefficient of the prescaler 11, MD is the percentage of the spread spectrum modulation depth, LDF is the division ratio of the fractional frequency division, and:

[0101] LDF=MFN+MFI / 2 n+1 ;Fref=F clk_in / DIVM.

[0102] Please refer to Figure 2 and Figure 3 The enable signal PLLFRAEN, the spread spectrum mode control signal SSCGBYP, the spread spectrum direction control signal SPREADCT, the n+1-bit fractional frequency control signal MFN[n:0], and the integer frequency control signal MFI[m:0] can be configured through the corresponding configuration registers. The n+1-bit fractional frequency control signal MFN[n:0] can be provided by the n+1-bit fractional frequency configuration register.

[0103] By configuring the enable signal PLLFRAEN, the spread spectrum mode control signal SSCGBYP, the spread spectrum direction control signal SPREADCT, the n+1-bit fractional frequency division control signal MFN[n:0], and the integer frequency division control signal MFI[m:0] (where m≥0 and is an integer), the spread spectrum fractional frequency division control circuit 10 of this embodiment can provide the following operating modes:

[0104] (1) Integer-only mode: MFI[m:0]≠0, MFN[n:0]=0, PLLFRAEN=0 (i.e., PLLFRAEN is at the first level), SSCGBYP=x (x represents 0 or 1 or other states, i.e., SSCGBYP is at the second level or the first level or other levels). Integer-only mode is entered as long as PLLFRAEN is at the first level, regardless of the state of SSCGBYP (i.e., when PLLFRAEN=0, the entire fractional frequency division and spread spectrum link is closed). This mode is a type of non-spread spectrum mode, an integer frequency division mode without superimposed spread spectrum, and TEMP=0 is continuously maintained in this mode (i.e., the triangle wave generator 1011 does not output a triangle wave signal).

[0105] (2) Non-Frequency Modulation Fractional mode (i.e., fractional frequency division mode only): PLLFRAEN=1 (i.e., PLLFRAEN is at the second level) and SSCGBYP=1 (i.e., SSCGBYP is at the second level). This mode is also a non-spread spectrum mode. Its fractional frequency division control signal MFN[n:0]≠0, and the integer part MFI[m:0] can be equal to 0 (in this case, the fractional frequency division mode does not superimpose the integer frequency division function) or not equal to 0 (in this case, the fractional frequency division mode only superimposes the integer frequency division function);

[0106] (3) Spread spectrum mode: When PLLFRAEN=1 (i.e., PLLFRAEN is at the second level), SSCGBYP=0 (i.e., SSCGBYP is at the first level), and the spread spectrum direction control signal SPREADCT=0 (i.e., at the first level), it is center spread spectrum, and when the spread spectrum direction control signal SPREADCT=1 (i.e., at the second level), it is downward spread spectrum. Among them, the spread spectrum mode can be further divided into the following according to the fractional frequency control signal MFN[n:0] and the spread spectrum direction control signal SPREADCT:

[0107] (3-1) Center Spread Spectrum modulation integer mode: PLLFRAEN = 1 (i.e., PLLFRAEN is at the second level), SSCGBYP = 0 (i.e., SSCGBYP is at the first level), SPREADCT = 0 (i.e., SPREADCT is at the first level), and MFN[n:0] = 0.

[0108] (3-2) Down Spread Spectrum modulation integer mode: PLLFRAEN = 1 (i.e., PLLFRAEN is at the second level), SSCGBYP = 0 (i.e., SSCGBYP is at the first level), SPREADCT = 1 (i.e., SPREADCT is at the second level), and MFN[n:0] = 0.

[0109] (3-3) Center Spread Spectrum modulation Fractional mode with superimposed fractional frequency division: PLLFRAEN = 1 (i.e., PLLFRAEN is at the second level), SSCGBYP = 0 (i.e., SSCGBYP is at the first level), SPREADCT = 0 (i.e., SPREADCT is at the first level), and MFN[n:0] ≠ 0.

[0110] (3-4) Down Spread Spectrum modulation Fractional mode with superimposed fractional frequency division: PLLFRAEN = 1 (i.e., PLLFRAEN is at the second level), SSCGBYP = 0 (i.e., SSCGBYP is at the first level), SPREADCT = 1 (i.e., SPREADCT is at the second level), and MFN[n:0] ≠ 0.

[0111] It is worth noting that in the two spread spectrum modes (3-3) and (3-4) with superimposed fractional frequency division, the integer part MFI[m:0] can be equal to 0 (in this case, the spread spectrum mode only superimposes the fractional frequency division function, not the integer frequency division function), or it can be different from 0 (in this case, the spread spectrum mode superimposes the integer frequency division and fractional frequency division functions).

[0112] Please combine Figures 1 to 5 When the spread spectrum fractional frequency control circuit 10 operates in the integer frequency division mode, the clock frequency F output by the voltage controlled oscillator 15 is pll_VCO For: F pll_VCO =(F clk_in / DIVM)*MFI;

[0113] When the spread spectrum fractional frequency control circuit 10 operates in the fractional frequency mode (which can be the above-mentioned (2) mode or (3-3) mode or (3-4) mode), the clock frequency F output to the voltage controlled oscillator 15 is pll_VCO For: F pll_VCO =(F clk_in / DIVM)*[MFI+(MFN+0.5) / 2 n+1 ].

[0114] Among them, F clk_in is the frequency of the external input clock (ie, the input source clock), MFN is the n+1-bit fractional frequency division control signal, DIVM is the division coefficient of the prescaler 11, and MFI is the m+1-bit integer frequency division control signal.

[0115] An input terminal of the signal modulator 104 is coupled to the output terminal of the spread spectrum circuit 101. The signal modulator 104 is used to modulate and shape the n+1-bit first frequency-divided control signal OUT[n:0] output by the spread spectrum circuit 101. The signal modulator 104 can be implemented using any suitable circuit design.

[0116] Optionally, the signal modulator 104 is a third-order SDM modulator (Sigma-Delta Modulator) using a MASH structure, which can also be written as a Σ(Sigma)-Δ(Delta) modulator or a Δ-Σ modulator. The MASH structure includes but is not limited to a MASH1-1 structure, a MASH2-1 structure, and a MASH1-1-1 structure. An SDM modulator improves signal resolution through oversampling and noise shaping techniques. Its basic principles generally include oversampling, feedback loop-based noise shaping, and digital filtering and decimation.

[0117] In an example, see Figure 6The signal modulator 104 adopts a three-stage MASH1-1-1 structure and includes first to third stage accumulators M1~M3, delays 1041~1043, a delay chain 1044, delays 1045~1047, and accumulators U6~U7. Each stage of the accumulator has an accumulation output terminal, a carry output terminal, and two input terminals.

[0118] The accumulated output of the first-stage accumulator M1 is coupled to an input of the second-stage accumulator M2 and an input of the first-stage accumulator M1 via a delay circuit 1041. Another input of the first-stage accumulator M1 is coupled to the n+1-bit first frequency-divided control signal OUT[n:0] output by the spread spectrum circuit 101. The carry output of the first-stage accumulator M1 is coupled to an input of a delay chain 1044. The output of the delay chain 1044 is coupled to an input of the accumulator U7. The delay chain 1044 is also coupled to the feedback clock CLK_DIV. The delay chain 1044 is configured to delay the carry C0 output from the carry output of the first-stage accumulator M1 by, for example, two beats, using the feedback clock CLK_DIV as a reference clock. The output of the delay chain 1044 then outputs the delayed carry C0D2. Delay 1041 is also coupled to the feedback clock CLK_DIV and is configured to delay the output of the accumulation output terminal of the first-stage accumulator M1 using the feedback clock CLK_DIV as a reference clock. The output value of the accumulation output terminal of the first-stage accumulator M1 is the sum of the delayed output value of delay 1041 and OUT[n:0]. If this sum overflows, the first-stage accumulator M1 performs a carry output operation (C0).

[0119] The accumulation output of the second-stage accumulator M2 is coupled to one input of the third-stage accumulator M3 and another input of the second-stage accumulator M2 via a delay 1042. The carry output of the second-stage accumulator M2 is coupled to the input of a delay 1045. The output of the delay 1045 is coupled to one input of the accumulator U6. The delay 1045 is also coupled to the feedback clock CLK_DIV. The delay 1045 is configured to delay the carry C1 output from the carry output of the second-stage accumulator M2, for example, by one beat, using the feedback clock CLK_DIV as a reference clock. The output of the delay 1045 outputs the delayed carry C1D1. The delay 1042 is also coupled to the feedback clock CLK_DIV. The delay 1042 is configured to delay the output of the accumulation output of the second-stage accumulator M2, using the feedback clock CLK_DIV as a reference clock. Among them, the output value of the accumulation output terminal of the second-stage accumulator M2 is the sum of the output value after delay by the delayer 1042 and the output value of the accumulation output terminal of the first-stage accumulator M1. If the sum overflows, the second-stage accumulator M2 performs a carry C1 output operation.

[0120] The accumulation output of the third-stage accumulator M3 is coupled to the input of a delayer 1043, the output of which is coupled to the other input of the third-stage accumulator M3. The carry output of the third-stage accumulator M3 is coupled to the input of a delayer 1046, the output of which is coupled to the other input of the accumulator U6. Delayer 1043 is also coupled to the feedback clock CLK_DIV. Delayer 1043 is configured to delay the output of the accumulation output of the third-stage accumulator M3 using the feedback clock CLK_DIV as a reference clock. The output value of the accumulation output of the third-stage accumulator M3 is the sum of the output value after delay of delayer 1043 and the output value of the accumulation output of the second-stage accumulator M2. If this sum overflows, the third-stage accumulator M3 performs a carry output operation C2.

[0121] Furthermore, delays 1041 - 1043 , delay chain 1044 , and delays 1045 - 1047 may be implemented using any suitable circuit design. For example, delays 1041 - 1043 may be implemented using n+1-bit registers, delay chain 1044 may be implemented using a cascaded 1-bit register 1044 a and a 1-bit register 1044 b, and delay 1045 may be implemented using the 1-bit register 1044 a.

[0122] Please refer to Figure 7 The delayer 1046 and the delayer 1047 are both composed of a register 104a and a subtractor 104b. The register 104a is also coupled to the feedback clock CLK_DIV, and uses the feedback clock CLK_DIV as the reference clock to delay the signal received by the register 104a (it can also be said to be "delayed by one beat"). One input end of the subtractor 104b is coupled to the output end of the register 104a, and the other input end is coupled to the signal received by the register 104a, thereby performing a subtraction operation on the input of the register 104a and the output of the register 104a.

[0123] from Figure 6 As shown in the figure, the signal modulator 104 outputs OUTSD[n:0]=C2-C2D1+C1D1-C2D1+C2D2-C1D2+C0D2. When n=13, the result has 8 different values [-3, -2, -1, 0, 1, 2, 3, 4].

[0124] Please combine Figure 1 and Figure 2The frequency division control signal output circuit 105 is coupled to the signal modulator 104 and the fractional frequency divider (DIVN) 16 in the fractional frequency phase-locked loop (PLL). The frequency division control signal output circuit 105 is used to superimpose the output OUTSD[n:0] of the signal modulator 104 and the corresponding integer frequency division control signal MFI[m:0] to output the second frequency division control signal MFIS[m:0] after integer frequency division superposition to the fractional frequency divider 16. The fractional frequency divider 16 is used to divide the clock (its frequency Fvco) output by the voltage-controlled oscillator 15 based on the second frequency division control signal MFIS[m:0] output by the frequency division control signal output circuit 105.

[0125] In an example, see Figure 8 The frequency division control signal output circuit 105 includes a fourth accumulator U5 and an output register 1052. One input of the fourth accumulator U5 is coupled to the output of the signal modulator 104, and the other input of the fourth accumulator U5 is coupled to the integer frequency division control signal MFI[m:0]. The fourth accumulator U5 is used to superimpose the output OUTSD[n:0] of the signal modulator 104 and the integer frequency division control signal MFI[m:0]. The input of the output register 1052 is coupled to the output of the fourth accumulator U5. The output register 1052 is also coupled to the feedback clock CLK_DIV and is used to synchronize the output of the fourth accumulator U5 with the feedback clock CLK_DIV to output the second frequency division control signal MFIS[m:0] after the integer frequency division is superimposed.

[0126] In the above embodiment, n, k, and m can be any appropriate values. Figures 1 to 8 In one example, n=13, k=2, and m=7. The working principle of the spread spectrum fractional frequency control circuit 10 of this example is as follows:

[0127] First, the triangle wave generator 1011 in the spread spectrum circuit 101 uses 0 as the initial value and the feedback clock CLK_DIV as the reference clock. Within one cycle of the spread spectrum mode with fractional frequency superposition (for example, when PLLFRAEN=1 and SSCGBY=0 is configured), the generator increments by one step size MODSTE on each rising edge of CLK_DIV, with a number of increments MODCNT, gradually increasing to a maximum value MODSTEP*MODCNT. Then, the generator decrements by one step size MODSTEP on each rising edge of CLK_DIV until it returns to 0, thereby generating the triangle wave TEMP[13:0]. Simultaneously, the first accumulator U1 in the spread spectrum circuit 101 superimposes MFN[13:0] with the pseudo-random sequence PRBS output by the pseudo-random sequence generator 100.

[0128] Next, the second accumulator U2 in the spread spectrum circuit 101 superimposes the triangular wave TEMP and MFN[13:0] after superimposing the pseudo-random sequence PRBS to generate a first superposition result, which is a triangular wave signal. The triangular wave signal uses the feedback clock CLK_DIV as the reference clock. In the spread spectrum mode of superimposing fractional frequency (for example, when PLLFRAEN=1 and SSCGBY=0 are configured), the triangular wave signal increases by a step size MODSTE at the rising edge of each cycle of CLK_DIV, and the number of increments is MODCNT. The signal gradually increases to the maximum value MFN[13:0]+MODSTEP*MODCNT, and then decreases by a step size MODSTEP at the rising edge of each cycle of CLK_DIV until it decreases back to MFN[13:0].

[0129] The subtractor U3 in the spread spectrum circuit 101 further subtracts the first subtrahend value configured in the second register 1013. In the center spread spectrum mode, the first subtrahend value configured in the second register 1013 is 1 / 2*MODCNT*MODSTEP. In the downward spread spectrum mode, the first subtrahend value configured in the second register 1013 is MODSTEP*MODCNT.

[0130] Next, the 13-bit first frequency division control signal OUT[13:0] output by the spread spectrum circuit 101 is modulated and shaped by the signal modulator 104 and output as OUTSD[13:0], thereby spreading the quantization noise to a higher frequency band. As a result, the fractional frequency phase-locked loop can filter out high-frequency noise through its low-pass filter.

[0131] Then, the frequency division control signal output circuit 105 adds the output OUTSD[13:0] of the signal modulator 104 to the integer frequency division control signal MFI[7:0], and obtains the second frequency division control signal MFIS[7:0] after the clock synchronization of the output register 1052. The MFIS[7:0] is provided to the fractional frequency divider 16 in the fractional frequency phase-locked loop. The fractional frequency divider 16 performs fractional frequency division on the clock output by the voltage-controlled oscillator 15 based on MFIS[7:0] to obtain the feedback clock CLK_DIV, and finally makes the frequency of the feedback clock CLK_DIV reach the reference frequency F provided by the prescaler 11. ref , to achieve the locking of the fractional frequency phase-locked loop.

[0132] Therefore, the spread spectrum fractional frequency division control circuit and the fractional frequency division phase-locked loop having the spread spectrum fractional frequency division control circuit provided in this embodiment are capable of superimposing an n+1-bit fractional frequency division control signal with a corresponding triangular wave signal in a corresponding spread spectrum mode, and performing corresponding processing on the superposition result according to the spread spectrum mode to obtain a corresponding first frequency division control signal, and the spread spectrum circuit processes the first superposition result differently in a non-spread spectrum mode and in different spread spectrum modes, and the first frequency division control signal is divided after modulation and shaping by a signal modulator. The control signal output circuit outputs a second frequency division control signal, which in turn causes the fractional frequency divider to divide the corresponding clock based on the second frequency division control signal. This allows the device to support non-spread spectrum mode and different spread spectrum modes (including multiple different center spread spectrum modes and downward spread spectrum modes). This prevents downward or upward distortion caused by excessive spread spectrum modulation amplitude when the fractional frequency division ratio approaches 0 or 1. Furthermore, noise shaping technology can be used to effectively reduce spurious signals, enabling the fractional frequency phase-locked loop to achieve high frequency and high resolution while also achieving excellent phase noise performance. Furthermore, the register configuration values for the spread spectrum modulation step length MODSTEP and the number of spread spectrum modulation steps MODCNT can be calculated and configured based on the modulation frequency and modulation amplitude of the spread spectrum according to actual needs, thereby providing a highly flexible configuration capability and a wide range of applications.

[0133] In addition, in an example of this embodiment, please refer to Figure 2 The enable signal PLLFRAEN can be provided to the pseudo-random sequence generator 100, the spread spectrum circuit 101, and the signal modulator 104 in the spread spectrum fractional frequency division control circuit 10 of this embodiment to control the enablement of these circuits. Therefore, when PLLFRAEN=0, the entire fractional frequency division and spread spectrum link in the spread spectrum fractional frequency division control circuit 10 is turned off to reduce its circuit power consumption in the integer division only mode.

[0134] In other examples of this embodiment, on the basis that the spread spectrum fractional frequency division control circuit can use PLLFRAEN, SSCGBYP, SPREADCT, MFN[n:0] and MFI[m:0] to achieve the required operating mode, PLLFRAEN can also be made not to be input into some links of fractional frequency division and spread spectrum in the spread spectrum fractional frequency division control circuit 10, for example, not to be input into at least one of the pseudo-random sequence generator 100 and the spread spectrum circuit 101. Thus, when PLLFRAEN=0, only some links of fractional frequency division and spread spectrum in the spread spectrum fractional frequency division control circuit 10 (which include the signal modulator 104) are turned off.

[0135] Based on the same inventive concept, this embodiment also provides a chip, which includes a fractional-frequency phase-locked loop and an internal circuit as described in this embodiment, wherein the clock input end of the internal circuit is coupled to the output end of the voltage-controlled oscillator of the fractional-frequency phase-locked loop, and the fractional-frequency phase-locked loop provides a clock with low spurious rate for the internal circuit.

[0136] Since the chip integrates the fractional frequency phase-locked loop of the present invention, it can effectively resist the serious problem of external electromagnetic interference.

[0137] Second embodiment

[0138] Please combine Figures 1 to 9 It should be understood that in the above embodiment, the OUTSD[n:0] output by the signal modulator 104 after noise shaping is added to the integer frequency division control signal MFI[m:0], the precision of the fractional frequency division is n+1 bits (bit), and the precision of each accumulator M1 to M3 in the signal modulator 104 is also n+1 bits. When the fractional frequency phase-locked loop operates in the fractional frequency division mode without the spread spectrum function (for example, when PLLFRAEN=1 and SSCGBY=1 are configured), the integer plus fractional division of the fractional frequency phase-locked loop is The frequency coefficient can be recorded as "DIVN~DIVN+1", so when MFN[n:0] is full, it is equivalent to adding 1 to the integer frequency coefficient of the fractional-frequency phase-locked loop; and when the fractional-frequency phase-locked loop operates in the spread spectrum mode with superimposed fractional frequency (for example, configuring PLLFRAEN=1 and SSCGBY=0), the spread spectrum modulation amplitude MODSTEP*MODCNT of the center spread spectrum and the downward spread spectrum will also be a maximum of n+1 bits. In this case, the accumulator M1 in the signal modulator 104 may overflow.

[0139] To avoid the problem of accumulator overflow in the signal modulator 104, this embodiment provides a spread spectrum fractional frequency division control circuit 10 and a fractional frequency division phase-locked loop having the spread spectrum fractional frequency division control circuit 10. Compared with the first embodiment, the spread spectrum fractional frequency division control circuit 10 of this embodiment is further configured to, in the current spread spectrum mode, expand the number of bits of the result of processing the first superposition result by k bits to output a first frequency division control signal OUT[(n+k):0] of n+k+1 bits. The spread spectrum fractional frequency division control circuit 10 separates the high-k bits of the signal OUT[(n+k):(n+1)] in OUT[(n+k):0] from the signal modulator 104, and does not participate in the modulation and shaping of the signal modulator 104. Instead, the signal is added to OUT[(n+k):0] after processing by the signal modulator 104 after a corresponding delay to obtain a corresponding second frequency division control signal. Where n ≥ 0, k ≥ 2, and n and k are both integers.

[0140] Please refer to Figure 1The basic architecture of the fractional-frequency phase-locked loop of this embodiment is the same as that of the first embodiment. It not only includes a pre-divider (DIVM, also known as a "pre-divider") 11, a phase frequency detector (PFD) 12, a charge pump (CHP) 13, a low-pass filter (LPF, also known as a "loop filter") 14, and a voltage-controlled oscillator (VCO) 15, which are connected in sequence, but also includes a fractional frequency divider (DIVN) 16 and a spread-spectrum fractional frequency control circuit 10. One input of the fractional frequency divider (DIVN) 16 is coupled to the output of the voltage-controlled oscillator 15, and the other input is coupled to the output of the spread-spectrum fractional frequency control circuit 10. The connection relationship and function of the various modules in this fractional-frequency phase-locked loop are basically the same as those of the first embodiment. Please refer to the relevant content above and will not be repeated here.

[0141] Therefore, the technical solution of this embodiment spreads the feedback clock CLK_DIV of the fractional divider through the spread spectrum fractional frequency division control circuit 10, and superimposes the spread spectrum function, thereby dynamically changing the division ratio of the fractional divider 16, so that the average value of the division ratio of the fractional divider 16 is a preset fractional value, and avoids the conflict of the division ratios in the fractional frequency division mode and the spread spectrum mode, as well as the data overflow of the accumulator in the signal modulator, so as to effectively suppress the electromagnetic interference of the fractional frequency division phase-locked loop.

[0142] Please refer to Figure 10 In one example of this embodiment, the spread spectrum fractional frequency division control circuit 10 includes a pseudo-random sequence generator 100, a spread spectrum circuit 101, a signal separation circuit 102, a high-k bit delay circuit 103, a signal modulator 104, and a frequency division control signal output circuit 105. In other examples, the pseudo-random sequence generator 100 can be omitted from the spread spectrum fractional frequency division control circuit 10 according to actual needs.

[0143] The pseudo-random sequence generator 100 is configured to generate and output a pseudo-random sequence PRBS. The spread spectrum circuit 101 is coupled to the n+1-bit fractional frequency division control signal MFN[n:0] and the pseudo-random sequence generator 100, and is configured to superimpose the n+1-bit fractional frequency division control signal MFN[n:0] with the corresponding triangular wave signal TEMP in a corresponding spread spectrum mode to obtain a second superposition result, and to extend the number of bits of the second superposition result by k bits to obtain an n+k+1-bit first frequency division control signal OUT[(n+k):0], where n≥0, k≥2, and n and k are both integers.

[0144] Optionally, refer to Figure 10 The spread spectrum circuit 101 includes a first accumulator U1, a triangle wave generator 1011, a first register 1012, a second accumulator U2, a second register 1013 and a subtractor U3.

[0145] In which, one input end of the first accumulator U1 is coupled to the n+1-bit fractional frequency control signal MFN[n:0], and the other input end is coupled to the pseudo-random sequence generator 100. The first accumulator U1 is used to superimpose the n+1-bit fractional frequency control signal MFN[n:0] and the pseudo-random sequence PRBS output by the pseudo-random sequence generator 100 to obtain a second superposition result, and provide the second superposition result to an input end of the second accumulator U2.

[0146] The triangle wave generator 1011 is coupled to the spread spectrum mode control signal SSCGBY and is configured to generate and output a triangle wave signal TEMP corresponding to the n+1-bit fractional frequency control signal MFN[n:0] in the spread spectrum mode (e.g., when PLLFRAEN=1 and SSCGBY=0). In the non-spread spectrum mode (e.g., when PLLFRAEN=1 and SSCGBY=1), the triangle wave generator 1011 outputs 0. The specific principles of generating the triangle wave signal TEMP in the spread spectrum mode (e.g., when PLLFRAEN=1 and SSCGBY=0) are the same as those of the first embodiment and are not further described herein. The initial value of the triangle wave signal TEMP is 0. With the feedback clock CLK_DIV as the reference clock, TEMP increases by one step MODSTEP at the rising edge of each clock cycle of the feedback clock CLK_DIV. The number of increments is MODCNT. The maximum value to which TEMP increases is MODSTEP*MODCNT. After that, it decreases by one step MODSTEP at the rising edge of each clock cycle of the feedback clock CLK_DIV until TEMP decreases back to 0. The register configuration value of MODCNT is based on the modulation frequency f in the current spread spectrum mode. MOD and reference clock F ref Calculation, the register configuration value of MODSTEP is calculated according to the modulation depth MD in the current spread spectrum mode and the n+1-bit fractional frequency division control signal MFN[n:0] and the m+1-bit integer frequency division control signal MFI[m:0]. The calculation formulas of MODCNT and MODSTEP are the same as those in the first embodiment and are not repeated here.

[0147] The first register 1012 is configured with an additional value of n+k+1 bits, which is equal to 2, for example. n+kThe first input terminal of the second accumulator U2 is coupled to the output terminal of the triangular wave generator 1011, the second input terminal is coupled to the output terminal of the first accumulator U1 (i.e., coupled to the n+1-bit fractional frequency control signal MFN[n:0]), and the third input terminal is coupled to the output terminal of the first register 1012. The second accumulator U2 is used to superimpose the output of the triangular wave generator 1011, the additional value configured in the first register 1012, and the output of the first accumulator U1 (i.e., the n+1-bit fractional frequency control signal MFN[n:0] after superimposing the pseudo-random sequence PRBS) to achieve a signal bit number extension of k bits. Here, the function of the first register 1012 is to extend the number of bits of the first superposition result after superimposing MFN[n:0] and TEMP by k bits (i.e., the sum of the spread spectrum and fractional frequency code values is extended by k bits) to prevent data overflow.

[0148] One input terminal of the subtractor U3 is coupled to the output terminal of the second accumulator U2, and the other input terminal is coupled to the second register 1013. The second register 1013 can be a register group, which is coupled to the spread spectrum mode control signal SSCGBY and the spread spectrum direction control signal SPREADCTL. The second register 1013 is used to configure the first subtrahend value required for the current mode (i.e., non-spread spectrum mode, center spread spectrum mode or downward spread spectrum mode). The subtractor U3 is used to subtract the output of the second accumulator U2 from the first subtrahend value configured in the second register 1013 to output the n+k+1-bit first frequency division control signal OUT[(n+k):0]. The first subtrahend value configured in the second register 1013 in the non-spread spectrum mode (for example, PLLFRAEN=0 or 1 is configured, and SSCGBY=1) is equal to 0, the first subtrahend value configured in the center spread spectrum mode (for example, PLLFRAEN=1, SSCGBY=0 and SPREADCTL=0) is equal to MODSTEP*MODCNT / 2, and the first subtrahend value configured in the downward spread spectrum mode (for example, PLLFRAEN=1, SSCGBY=0 and SPREADCTL=1) is equal to MODSTEP*MODCNT, where MODCNT is the number of spread spectrum modulation steps configured in the register, and MODSTEP is the spread spectrum modulation step size configured in the register.

[0149] Thus, in this example, the spread spectrum circuit 101 first expands the number of bits of the first superposition result (i.e., the result of superimposing the second superposition result and the triangle wave information) by k bits, and then performs corresponding processing (i.e., subtracting the corresponding first subtrahend value) on the signal after the bit expansion in the current mode through the subtractor U3. Thus, compared with the first embodiment, the spread spectrum circuit 101 can achieve the effect of expanding the number of bits of the result of processing the first superposition result by k bits. In other embodiments of the present invention, the subtractor U3 and the second register 1013 can also be arranged in the upstream stage of the first register 1012, and a corresponding accumulator can be added to the first register 1012. This can achieve the effect of first subtracting the corresponding first subtrahend value from the first superposition result output by the second accumulator U2 (i.e., performing corresponding processing on the first superposition result), and then expanding the number of bits of the processed result by k bits.

[0150] Furthermore, the spread spectrum circuit 101 can be configured via configuration registers for control signals such as the spread spectrum mode control signal SSCGBYP, the spread spectrum direction control signal SPREADCT, the n+1-bit fractional frequency control signal MFN[n:0], and the integer frequency control signal MFI[m:0]. The n+1-bit fractional frequency control signal MFN[n:0] can be provided by the n+1-bit fractional frequency configuration register.

[0151] By configuring the enable signal PLLFRAEN, the spread spectrum mode control signal SSCGBYP, the spread spectrum direction control signal SPREADCT, the n+1-bit fractional frequency division control signal MFN[n:0], and the integer frequency division control signal MFI[m:0] differently, the spread spectrum fractional frequency division control circuit 10 of this embodiment can provide multiple operating modes, such as integer frequency division only mode, integer frequency division spread spectrum mode (including center spread spectrum or downward spread spectrum), fractional frequency division mode without superimposed spread spectrum, and superimposed fractional frequency division spread spectrum mode (including center spread spectrum or downward spread spectrum). The specific conditions of PLLFRAEN, SSCGBYP, SPREADCT, MFN[n:0], and MFI[m:0] in these modes are the same as those in the first embodiment. Please refer to the relevant contents described in the first embodiment above, and no further details will be given here.

[0152] Please continue to refer to Figure 10The input end of the signal separation circuit 102 is coupled to the output end of the spread spectrum circuit 101 (i.e., the output end of the subtractor U3). The signal separation circuit 102 is configured to buffer or register the n+k+1-bit first frequency division control signal OUT[(n+k):0] output by the spread spectrum circuit 101, and to separate and output the highest k bits and the remaining n+1 bits of the n+k+1-bit first frequency division control signal OUT[(n+k):0] to obtain a high-k bit signal OUT[(n+k):(n+1)] and a low-n+1 bit signal OUT[n:0]. The signal separation circuit 102 can adopt any suitable circuit design, such as a signal decoder or a division and modulo operation circuit, and the present invention is not specifically limited thereto.

[0153] Please refer to Figure 10 The input end of the high-k bit delay circuit 103 is coupled to an output end of the signal separation circuit 102. The high-k bit delay circuit 103 is used to delay the high-k bit signal OUT[(n+k):(n+1)] output by the signal separation circuit 102. The high-k bit delay circuit 103 can adopt any suitable circuit design. Figure 11 The high-k bit delay circuit 103 includes a delay chain including at least two cascaded first delay units 103a, and the number of stages of the first delay units 103a matches the modulation time of the signal modulator 104. In one example, the first delay unit 103a is a k-bit register that can buffer and delay the output of the high-k bit signal OUT[(n+k):(n+1)] output by the signal separation circuit 102.

[0154] Please continue Figure 10 One input terminal of the signal modulator 104 is coupled to the other output terminal of the signal separation circuit 102 , and the signal modulator 104 is used to modulate and shape the lower n+1 bit signal OUT[n:0] output by the signal separation circuit 102 .

[0155] The delay time of the high-k bit delay circuit 103 for the high-k bit signal OUT[(n+k):(n+1)] matches the time consumed by the signal modulator 104 to modulate and shape the low-n+1 bit signal OUT[n:0], thereby synchronizing the delayed high-k bit signal OUTD[(n+k):(n+1)] output by the high-k bit delay circuit 103 and the modulated low-n+1 bit signal OUTD[n:0] output by the signal modulator 104. The signal modulator 104 can be implemented using any suitable circuit design.

[0156] In an example, see Figure 11 and Figure 6The first delay unit 103a in the high-k bit delay circuit 103 has three stages, and the signal modulator 104 is a third-order Σ-Δ modulator using a MASH structure. The MASH structure includes, but is not limited to, a MASH1-1 structure, a MASH2-1 structure, and a MASH1-1-1 structure. The third-order MASH1-1-1 structure can use the same circuit design as the third-order MASH1-1-1 structure in the first embodiment, and will not be described in detail here.

[0157] from Figure 6 As shown in the figure, the signal modulator 104 outputs OUTSD[n:0]=C2-C2D1+C1D1-C2D1+C2D2-C1D2+C0D2. When n=13, the result has 8 different values [-3,-2,-1,0,1,2,3,4]. In this case, please further combine Figure 10 When n=13 and k=2, the signal (not marked) obtained by adding the output OUTD[(n+k):(n+1)] of the high-k bit delay circuit 103 and the output OUTSD[n:0] of the signal modulator 104 in the frequency division control signal output circuit 105 has 11 different values [-3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7].

[0158] Please combine Figure 1 and Figure 10 The frequency division control signal output circuit 105 is coupled to the high-k bit delay circuit 103, the signal modulator 104 and the fractional frequency divider (DIVN) 16 in the fractional frequency phase-locked loop (PLL). The frequency division control signal output circuit 105 is used to superimpose the output OUTD[(n+k):(n+1)] of the high-k bit delay circuit 103, the output OUTSD[n:0] of the signal modulator 104 and the corresponding integer frequency division control signal MFI[m:0] to output the second frequency division control signal MFIS[m:0] after integer frequency division superposition to the fractional frequency divider 16. The fractional frequency divider 16 is used to divide the clock (whose frequency is Fvco) output by the voltage-controlled oscillator 15 based on MFIS[m:0] output by the frequency division control signal output circuit 105.

[0159] In an example, see Figure 12The frequency division control signal output circuit 105 includes a third accumulator U4, a third register 1051, a fourth accumulator U5 and an output register 1052. One input end of the third accumulator U4 is coupled to the output end of the signal modulator 104, and the other input end is coupled to the output end of the high-k bit delay circuit 103. The third accumulator U4 can be the same accumulator as the accumulator U7 in the signal modulator 104, or it can be a different accumulator from the accumulator U7 in the signal modulator 104. The third accumulator U4 is used to superimpose the output OUTD[(n+k):(n+1)] of the high-k bit delay circuit 103 and the output OUTSD[n:0] of the signal modulator 104. The output end of the third register 1051 is coupled to the first input end of the fourth accumulator U5, and is used to configure the second subtrahend value of k bits, which is, for example, equal to 2 k-1 The second input terminal of the fourth accumulator U5 is coupled to the output terminal of the third accumulator U4. The third input terminal of the fourth accumulator U5 is coupled to the integer frequency division control signal MFI[m:0]. The fourth accumulator U5 is used to add the output of the third accumulator U4 and the integer frequency division control signal MFI[m:0] and then subtract the second subtrahend value configured in the third register 1051 (for example, 2 k-1 The input end of the output register 1052 is coupled to the output end of the fourth accumulator U5. The output register 1052 is also coupled to the feedback clock CLK_DIV and is used to synchronize the output of the fourth accumulator U5 with the feedback clock CLK_DIV to output the second frequency division control signal MFIS[m:0] after integer frequency division and superposition.

[0160] In the above embodiment, n, k, and m can be any appropriate values. Figure 1 、 Figures 10 to 13 In one example, n=13, k=2, and m=7. The working principle of the spread spectrum fractional frequency control circuit 10 of this example is as follows:

[0161] First, triangular wave generator 1011 in spread spectrum circuit 101 uses feedback clock CLK_DIV as the reference clock. In spread spectrum mode with fractional division (e.g., PLLFRAEN = 1 and SSCGBY = 0), it increments by one step size MODSTEP on each rising edge of CLK_DIV, with a number of increments MODCNT, gradually increasing to a maximum value. It then decrements by one step size MODSTEP on each rising edge of CLK_DIV until it returns to its initial value (e.g., 0, or other values), thereby generating triangular wave TEMP. Simultaneously, first accumulator U1 in spread spectrum circuit 101 superimposes MFN[13:0] with the pseudo-random sequence PRBS output by pseudo-random sequence generator 100.

[0162] Then, the second accumulator U2 in the spread spectrum circuit 101 superimposes the triangle wave TEMP and the MFN[13:0] superimposed with the pseudo random sequence PRBS, and further adds the additional value 2 provided by the first register 1012. 15 The first subtrahend value provided by the second register 1013 is subtracted from the first subtrahend value. In center spread spectrum mode (e.g., configuration PLLFRAEN=1, SSCGBY=0, SPREADCT=0), the first subtrahend value provided by the second register 1013 is 1 / 2*MODCNT*MODSTEP. In downward spread spectrum mode (e.g., configuration PLLFRAEN=1, SSCGBY=0, SPREADCT=1), the first subtrahend value provided by the second register 1013 is MODSTEP*MODCNT. In non-spread spectrum mode (e.g., configuration PLLFRAEN=1, SSCGBY=1), the first subtrahend value provided by the second register 1013 is 0, and TEMP provided by the triangle wave generator is 0.

[0163] Next, the high-order 2-bit signal OUT[15:14] output by the spread spectrum circuit 101 is transmitted to the high-order 2-bit delay circuit 103 by the signal separation circuit 102 for two beats, and then output as OUTD[15:14]. The low-order 13-bit signal OUT[13:0] output by the spread spectrum circuit 101 is modulated and shaped by the signal modulator 104, and then output as OUTSD[13:0]. This spreads the quantization noise to a higher frequency band, so that the fractional-frequency phase-locked loop can filter out high-frequency noise through its low-pass filter.

[0164] Then, OUTD[15:14] output by the high 2-bit delay circuit 103 and OUTSD[13:0] output by the signal modulator 104 are added at the third accumulator U4 of the frequency division control signal output circuit 105, and the result of the addition has 11 different values [-3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7].

[0165] Afterwards, the fourth accumulator U5 in the frequency division control signal output circuit 105 adds the output of the third accumulator U4 to the integer frequency division control signal MFI[7:0] and then subtracts the second subtrahend value (which is equal to 2) provided by the third register 1051. The result is synchronized with the clock of the output register 1052 to obtain the second frequency division control signal MFIS[7:0]. The MFIS[7:0] is provided to the fractional frequency divider 16 in the fractional frequency phase-locked loop. The fractional frequency divider 16 performs fractional frequency division on the clock output by the voltage-controlled oscillator 15 based on MFIS[7:0] to obtain the feedback clock CLK_DIV, thereby ultimately making the frequency of the feedback clock CLK_DIV reach the reference frequency F provided by the prescaler 11. ref , to achieve the locking of the fractional frequency phase-locked loop.

[0166] In this embodiment, the sum of the spread spectrum and the fractional frequency division code value is extended by k bits by the spread spectrum circuit 101 (ie, the signal obtained by superimposing MFN[n:0] and TEMP is further superimposed to set the first subtraction value 2 provided by the first register 1012). n+k ), and in the frequency division control signal output circuit 105, the second subtrahend value 2 is subtracted from the integer frequency division coefficient. k-1 The signal separation circuit 102 also separates the high-k bits of the signal OUT[(n+k):(n+1)] from the expanded signal, so that the high-k bits do not participate in the modulation shaping of the signal modulator 104. Instead, they are directly added to or subtracted from the signal OUTD[n:0] output by the signal modulator 104 after being delayed by the high-k bits delay circuit 103. Therefore, the spread spectrum fractional frequency division control circuit and the fractional frequency division phase-locked loop having the spread spectrum fractional frequency division control circuit of this embodiment can simultaneously realize the spread spectrum and fractional frequency division functions, allowing the spread spectrum frequency and spread spectrum amplitude to be flexibly configured to avoid the problem of downward or upward distortion caused by the large spread spectrum modulation amplitude when the fractional division ratio is close to 0 or close to 1. Furthermore, the noise shaping technology can be used to effectively reduce spurious signals, so that the fractional frequency division phase-locked loop achieves high frequency and high resolution while achieving good phase noise performance. The accumulator overflow problem can also be avoided, and the application range is wide.

[0167] In addition, in an example of this embodiment, please refer to Figure 9 The enable signal PLLFRAEN can be provided to the pseudo-random sequence generator 100, the spread spectrum circuit 101, the signal separation circuit 102, the high-k bit delay circuit 103, and the signal modulator 104 in the spread spectrum fractional frequency division control circuit 10 of this embodiment to control the enablement of these circuits. Therefore, when PLLFRAEN=0, the entire fractional frequency division and spread spectrum link in the spread spectrum fractional frequency division control circuit 10 is turned off to reduce its circuit power consumption in the integer division only mode.

[0168] In other examples of this embodiment, based on the fact that the spread spectrum fractional frequency division control circuit can use PLLFRAEN, SSCGBYP, SPREADCT, MFN[n:0], and MFI[m:0] to achieve the desired operating mode, PLLFRAEN can also be disabled from being input to a portion of the fractional frequency division and spread spectrum links in the spread spectrum fractional frequency division control circuit 10. Thus, when PLLFRAEN = 0, only the portion of the fractional frequency division and spread spectrum links connected to PLLFRAEN are disabled. This portion of the link can include at least one of the pseudo-random sequence generator 100, the signal separation circuit 102, the high-k bit delay circuit 103, and a portion of the spread spectrum circuit 101 and a portion of the signal modulator 104.

[0169] Based on the same inventive concept, one embodiment of the present invention further provides a chip comprising the fractional-frequency phase-locked loop (PFL) described herein and an internal circuit. The clock input of the internal circuit is coupled to the output of the voltage-controlled oscillator (VCO) of the PFL, and the PFL provides a low-spurious clock to the internal circuit. Because the chip incorporates the PFL, it can effectively resist severe external electromagnetic interference.

[0170] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the technical solution of the present invention.

Claims

1. A spread spectrum fractional frequency division control circuit, characterized in that: include: a spread spectrum circuit, configured to superimpose an n+1-bit fractional frequency division control signal with a corresponding triangular wave signal in a corresponding spread spectrum mode to obtain a first superposition result, and perform corresponding processing on the first superposition result according to the spread spectrum mode to obtain a corresponding first frequency division control signal, wherein the processing of the first superposition result by the spread spectrum circuit is different in a non-spread spectrum mode and in different spread spectrum modes; a signal modulator, coupled to the spread spectrum circuit, and configured to modulate and shape the first frequency-divided control signal; and A frequency division control signal output circuit is coupled to the signal modulator and the corresponding fractional frequency divider, and is used to provide a second frequency division control signal to the fractional frequency divider according to the output of the signal modulator, and the fractional frequency divider is used to divide the corresponding clock based on the second frequency division control signal. The spread spectrum circuit is further coupled to an enable signal, a spread spectrum mode control signal, and a spread spectrum direction control signal, and provides the following operating modes according to the enable signal, the spread spectrum mode control signal, and the spread spectrum direction control signal: (1) Integer division mode only: the enable signal is at the first level; (2) Fractional frequency division mode without superimposed spread spectrum: the enable signal is at the second level, and the spread spectrum mode control signal is at the second level; (3) Spread spectrum mode: the enable signal is at the second level, the spread spectrum mode control signal is at the first level, and the center spread spectrum is performed when the spread spectrum direction control signal is at the first level, and the downward spread spectrum is performed when the spread spectrum direction control signal is at the second level.

2. The spread spectrum fractional frequency control circuit according to claim 1, wherein: The initial value of the first superposition result is equal to MFN[n:0], and the first superposition result increases by MODSTEP in each clock cycle of the feedback clock fed back by the fractional divider to a maximum value, and then the first superposition result decreases by MODSTEP in each clock cycle of the feedback clock until it decreases back to MFN[n:0]; wherein the maximum value is MFN[n:0]+MODSTEP*MODCNT, MFN[n:0] is the n+1-bit fractional division control signal, MODSTEP is the spread spectrum modulation step configured by the register, and MODCNT is the number of spread spectrum modulation steps configured by the register.

3. The spread spectrum fractional frequency control circuit according to claim 2, wherein: The register configuration value of MODCNT is calculated based on the modulation frequency and reference clock in the spread spectrum mode, and the register configuration value of MODSTEP is calculated based on the modulation depth in the spread spectrum mode, the n+1-bit fractional frequency division control signal and the corresponding integer frequency division control signal.

4. The spread spectrum fractional frequency control circuit according to any one of claims 1 to 3, wherein: The spread spectrum circuit subtracts different first subtrahend values from the first superposition result in a non-spread spectrum mode and in different spread spectrum modes to implement the different processing in the non-spread spectrum mode and in different spread spectrum modes, and the first subtrahend value is configured by a second register or calculated based on the register configuration values of MODSTEP and MODCNT; wherein MODSTEP is the spread spectrum modulation step configured in the register, and MODCNT is the number of spread spectrum modulation steps configured in the register.

5. The spread spectrum fractional frequency control circuit according to claim 4, wherein: The first subtraction value is equal to 0 in the non-spread spectrum mode, equal to MODSTEP*MODCNT / 2 in the center spread spectrum mode, and equal to MODSTEP*MODCNT in the down spread spectrum mode.

6. The spread spectrum fractional frequency control circuit according to claim 4, wherein: The spread spectrum circuit comprises: a triangular wave generator, configured to generate and output the triangular wave signal corresponding to the n+1-bit fractional frequency division control signal in the corresponding spread spectrum mode; a second accumulator, coupled to the triangular wave generator and the n+1-bit fractional frequency control signal, and configured to superimpose an output of the triangular wave generator and the n+1-bit fractional frequency control signal to output the first superposition result; A subtractor is coupled to the second accumulator and is used to subtract the first subtraction value from the first superposition result output by the second accumulator to obtain the first frequency division control signal.

7. The spread spectrum fractional frequency control circuit according to any one of claims 1 to 3 and 5 to 6, characterized in that: The spectrum spreading circuit is further configured to expand the number of bits of the processed result by k bits to output the first frequency division control signal of n+k+1 bits, wherein n≥0, k≥2, and both n and k are integers.

8. The spread spectrum fractional frequency control circuit according to claim 7, wherein: n=13, k=2.

9. The spread spectrum fractional frequency control circuit according to claim 7, wherein: The spectrum spreading circuit further includes a first register, in which an additional value of n+k+1 bits is configured. The spectrum spreading circuit is further configured to superimpose the first superposition result or the processed result with the additional value, thereby expanding the number of bits of the processed result by k bits.

10. The spread spectrum fractional frequency control circuit according to claim 7, wherein: The spread spectrum fractional frequency control circuit further includes: a signal separation circuit coupled to the spread spectrum circuit and configured to separate the highest k bits and the remaining n+1 bits of the n+k+1-bit first frequency division control signal to obtain a high k-bit signal and a low n+1-bit signal; a high-k bit delay circuit coupled to the signal separation circuit and the frequency division control signal output circuit, and configured to delay the high-k bit signal output by the signal separation circuit and then provide the signal to the frequency division control signal output circuit; The signal modulator is further configured to modulate and shape the low n + 1 bit signal output by the signal separation circuit, and the output of the signal modulator is synchronized with the output of the high k bit delay circuit; The frequency division control signal output circuit is further configured to superimpose the output of the signal modulator and the output of the high-k bit delay circuit.

11. The spread spectrum fractional frequency control circuit according to claim 10, wherein: The high-k bit delay circuit includes a delay chain, which includes at least two first delay units connected in cascade, and the number of stages of the first delay units matches the modulation time of the signal modulator.

12. The spread spectrum fractional frequency control circuit according to claim 11, wherein: The first delay unit is a k-bit register; and / or the number of stages of the first delay unit is three, and the signal modulator is a third-order SDM modulator using a MASH structure.

13. The spread spectrum fractional frequency control circuit according to claim 10, wherein: The frequency division control signal output circuit is further configured to: superimpose the output of the high-k bit delay circuit, the output of the signal modulator and the corresponding integer frequency division control signal, and then subtract the k-bit second subtrahend value to obtain the second frequency division control signal after integer frequency division superposition.

14. The spread spectrum fractional frequency control circuit according to claim 13, wherein: The frequency division control signal output circuit includes: a third accumulator, coupled to the signal modulator and the high-k bit delay circuit, and configured to superimpose an output of the high-k bit delay circuit and an output of the signal modulator; A third register, used to configure the second subtrahend value; a fourth accumulator, coupled to the third accumulator, the third register, and a corresponding integer frequency division control signal, and configured to add an output of the third accumulator and the integer frequency division control signal and then subtract the second subtrahend value; An output register is coupled to the fourth accumulator and is used to synchronize the output of the fourth accumulator with the feedback clock fed back by the fractional frequency divider to output the second frequency division control signal.

15. The spread spectrum fractional frequency control circuit according to any one of claims 1 to 3, 5 to 6 and 8 to 14, wherein: The spread spectrum fractional frequency control circuit also includes a pseudo-random sequence generator for generating and outputting a pseudo-random sequence; the spread spectrum circuit also includes a first accumulator, coupled to the n+1-bit fractional frequency control signal and the pseudo-random sequence generator, and used to superimpose the n+1-bit fractional frequency control signal and the pseudo-random sequence to obtain a second superposition result, and superimpose the second superposition result with the triangular wave signal to obtain the first superposition result.

16. The spread spectrum fractional frequency control circuit according to claim 1, wherein: The spread spectrum circuit further divides the spread spectrum mode into the following types according to the n+1-bit fractional frequency division control signal MFN[n:0] and the spread spectrum direction control signal: (3-1) Integer frequency division center spread spectrum mode: the spread spectrum direction control signal is at the first level, and MFN[n:0]=0; (3-2) Integer frequency division downward spread spectrum mode: the spread spectrum direction control signal is at the second level, and MFN[n:0]=0; (3-3) Center spread spectrum mode with superimposed fractional frequency division: the spread spectrum direction control signal is at the first level, and MFN[n:0]≠0; (3-4) Downward spread spectrum mode with fractional frequency division: the spread spectrum direction control signal is at the second level, and MFN[n:0]≠0.

17. A fractional frequency phase-locked loop, comprising a prescaler, a phase frequency detector, a charge pump, a low-pass filter and a voltage-controlled oscillator connected in sequence, characterized in that: The fractional-frequency phase-locked loop also includes a fractional frequency divider and a spread spectrum fractional frequency control circuit as described in any one of claims 1-16, the output end of the fractional frequency divider is coupled to the feedback input end of the frequency detector and phase detector, one input end of the fractional frequency divider is coupled to the output end of the voltage-controlled oscillator, and the other input end of the fractional frequency divider is coupled to the output end of the spread spectrum fractional frequency control circuit.

18. A chip, characterized in that: Comprising the fractional frequency phase-locked loop as claimed in claim 17.

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