Dark current suppression method, segmented DAC circuit and dark current suppression verification circuit

Abstract

The invention discloses a dark current suppression method, a segmented DAC circuit and a dark current suppression verification circuit, the dark current suppression method is based on the segmented DAC circuit, and the suppression method comprises the following steps: setting the low level of the segmented DAC circuit as a thermometer decoding type; the high order of the segmented DAC circuit is set to a binary coding type. According to the dark current suppression method, the segmented DAC circuit and the dark current suppression verification circuit, the low level of the segmented DAC circuit is set to be the thermometer decoding type, and the high level of the segmented DAC circuit is set to be the binary decoding type, so that the continuity of analog output is ensured, the dark current is accurately suppressed, the suppression precision is not sensitive to circuit mismatch, imbalance and the like, and the circuit reliability is improved. And higher digital-to-analog conversion precision can be realized with lower matching precision, so that the segmented DAC circuit has the advantages of small area and high calibration precision.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a dark current suppression method, a segmented DAC circuit, and a dark current suppression verification circuit. Background Art

[0002] In some infrared detectors, especially long-wave detectors, the dark current (background current) is usually much larger than the photocurrent. Due to the non-uniformity of the manufacturing process, the magnitude of the dark current usually shows a non-uniform distribution. If the dark current is not effectively processed and directly integrated, the dynamic range of the integrator will be significantly reduced, resulting in a decrease in the signal-to-noise ratio of the system. Therefore, in the actual design of the readout circuit, the suppression of the dark current is crucial.

[0003] Currently, the methods for suppressing dark current mainly include the current memory method and the DAC compensation method. The current memory method is usually divided into a memory mode and a normal operation mode. In the memory mode, the dark current is copied by a current mirror and stored using a capacitor; in the normal operation mode, the stored dark current is taken out to complete the suppression of the dark current. The advantage of this method is that the circuit structure is simple and does not rely on complex timing, but its memory time is short, and the dark current needs to be updated frequently, which has certain limitations.

[0004] The DAC compensation method is also divided into a memory mode and a working mode. In the memory mode, the DAC identifies the dark current and stores the corresponding digital code in an external memory or on-chip SRAM; in the working mode, the digital code is taken out from the memory, and the dark current is compensated by the DAC. The advantage of this method is that the storage only needs to be done once and has a high suppression accuracy, but its disadvantage is that it requires additional circuit resources and involves complex timing control.

[0005] In the DAC compensation method, achieving high-precision suppression usually requires a high-precision DAC (digital-to-analog converter), and high-precision DACs rely on highly matched resistors, capacitors, or current mirrors. However, a high-precision matching circuit will significantly increase the chip area, thus limiting the miniaturization of the readout circuit.

[0006] In the application of dark current suppression in the readout circuit, the differential nonlinearity (DNL) performance of the DAC is crucial. As Figure 1 is the transfer function of a non-ideal DAC, when the digital input value is 128, there is an obvious upward jump in the analog output. This phenomenon is relatively common in DACs using binary decoding. The main reason is the mismatch between the weights of the high bits and the low bits. The corresponding DNL distribution is as Figure 2 shown, and it can be seen that there is a huge DNL at 128.

[0007] If the dark current of a certain pixel is distributed at point B, then no matter whether the output current of the DAC is set to point A or point B, the dark current of this pixel cannot be completely suppressed. A large DNL will lead to incomplete dark current compensation, thereby reducing the dynamic range of the system. The maximum remaining dark current I in the readout circuit res The relationship between and the DNL and the least significant bit (LSB) is as follows:

[0008]

[0009] It can be seen from the above formula that increasing the resolution of the DAC (reducing the LSB) and reducing the DNL can reduce the maximum remaining dark current. For high-resolution ADCs, in order to reduce the DNL, a segmented DAC architecture (such as a segmented current mirror DAC or a segmented capacitor ratio DAC) is usually adopted.

[0010] In traditional designs, binary decoding is usually used for the lower bits, while thermometer decoding is used for the higher bits. This is because jumps in the higher bits often result in a larger DNL, and thermometer decoding can effectively reduce the overall DNL of the DAC. As Figure 3 shown, a typical segmented current-steering DAC applies this segmentation strategy. However, such segmented DACs may have mismatch problems during the transition between segments, resulting in a large local DNL, thus being unable to completely suppress the dark current distributed in this interval. At the same time, due to the jumps in the binary code within the segment, the DNL may also be extremely large. As the resolution of the DAC increases, in order to reduce the DNL of the system, the number of bits of thermometer decoding that needs to be increased, which increases the complexity of the decoding logic and thus increases the layout area of the readout circuit. The improvement of the resolution usually requires higher-precision matching resistors, matching capacitors, or matching current mirrors, which will further increase the layout area.

[0011] The information disclosed in this background section is only intended to enhance the overall understanding of the present invention and should not be regarded as an admission or any form of suggestion that this information constitutes prior art already known to those of ordinary skill in the art. Summary of the Invention

[0012] The object of the present invention is to provide a dark current suppression method, a segmented DAC circuit, and a dark current suppression verification circuit, which can effectively suppress the dark current and are insensitive to circuit mismatch in calibration accuracy, thus having the advantages of small area and high calibration accuracy.

[0013] To achieve the above object, a specific embodiment of the present invention provides a dark current suppression method based on a segmented DAC circuit. The suppression method includes:

[0014] Set the lower bits of the segmented DAC circuit to thermometer decoding type;

[0015] Set the high bits of the segmented DAC circuit to binary decoding type.

[0016] In one or more embodiments of the present invention, the currents of the high bits of the segmented DAC circuit satisfy:

[0017] I N+1 <2 N ·I0

[0018]

[0019] Wherein, I N+1 is the current on the first current source of the high bits of the DAC circuit, N is the number of bits of the low bits of the DAC circuit, I0 is the current on each current source of the low bits of the DAC circuit, I N+j is the current on the current sources starting from the second current source of the high bits of the DAC circuit, and M is the number of bits of the high bits of the DAC circuit.

[0020] The present invention also discloses a segmented DAC circuit based on the above dark current suppression method.

[0021] In one or more embodiments of the present invention, the segmented DAC circuit includes a first current source group, a second current source group and a switch group;

[0022] The first current source group includes a plurality of first current sources forming the low bits of the DAC circuit, and the number of the first current sources is 2 N -1, where N is the number of bits of the low bits of the DAC circuit;

[0023] The second current source group includes a plurality of second current sources forming the high bits of the DAC circuit, and the number of the second current sources is M, where M is the number of bits of the high bits of the DAC circuit;

[0024] The switch group has a plurality of first selection terminals connected to the ground voltage, a plurality of second selection terminals connected to the output terminal, a plurality of first connection terminals connected to the first current source, and a plurality of second connection terminals connected to the second current source. The switch group is used for switching between the first connection terminal being connected to the first selection terminal or the second selection terminal, and the switch group is used for switching between the second connection terminal being connected to the first selection terminal or the second selection terminal.

[0025] The present invention also discloses a dark current suppression verification circuit, including:

[0026] A detection module for detecting and generating dark current;

[0027] An FPGA module for converting digital codes based on a piecewise function to generate multi-segment input digital codes;

[0028] A digital-to-analog conversion compensation module, connected to the FPGA module, for generating a compensation current with multiple downward jumps based on the input digital code;

[0029] An integration module, connected to the detection module and the digital-to-analog conversion compensation module, for performing downward or upward integration based on the difference between the dark current and the supplementary current;

[0030] A comparison module, connected to the integration module and the FPGA module, for comparing the integration result of the integration module with a reference voltage, and the FPGA module calibrates the digital code based on the comparison result of the comparison module.

[0031] In one or more embodiments of the present invention, the detection module includes a current mirror for generating a dark current.

[0032] In one or more embodiments of the present invention, the piecewise function is:

[0033]

[0034] where N is the number of bits of the lower part of the DAC circuit, M is the number of bits of the higher part of the DAC circuit, R is the redundancy, DAC in is the input digital code, and M DAC is the digital code.

[0035] In one or more embodiments of the present invention, the digital-to-analog conversion compensation module includes a digital-to-analog converter and a switching transistor. The input end of the digital-to-analog converter is connected to the output end of the FPGA module to receive the input digital code. The output end of the digital-to-analog converter is connected to the control end of the switching transistor. The first end of the switching transistor is connected to the ground voltage, and the second end of the switching transistor is connected to the detection module and the integration module.

[0036] In one or more embodiments of the present invention, the integration module includes: a first switch, a second switch, a capacitor, a comparator, an output transistor, and a current source;

[0037] The first end of the first switch is connected to the detection module and the digital-to-analog conversion compensation module. The second end of the first switch is connected to the first input end of the comparator. The second input end of the comparator is used to receive a first reference signal. The first end of the capacitor is connected to the first input end of the comparator. The second end of the capacitor is connected to the output end of the comparator. The first end of the second switch is connected to the first end of the capacitor. The second end of the second switch is connected to the second end of the capacitor. The output end of the comparator is connected to the control end of the output transistor. The second end of the output transistor is connected to the ground voltage. The first end of the output transistor is connected to the current source and the comparison module.

[0038] In one or more embodiments of the present invention, the dark current suppression verification circuit further includes a buffer connected between the integration module and the comparison module.

[0039] Compared with the prior art, the dark current suppression method, segmented DAC circuit, and dark current suppression verification circuit of the present invention ensure the continuity of analog output by setting the lower bits of the segmented DAC circuit to thermometer decoding type and the higher bits to binary decoding type, achieving precise dark current suppression. Moreover, the suppression accuracy is insensitive to circuit mismatches, offsets, etc., and can achieve higher digital-to-analog conversion accuracy with lower matching accuracy, enabling the segmented DAC circuit to have the advantages of small area and high calibration accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments described in the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0041] Figure 1 It is a waveform diagram of the transfer function of a traditional non-ideal segmented DAC.

[0042] Figure 2 It is a waveform diagram of the DNL of a traditional non-ideal segmented DAC.

[0043] Figure 3 It is a circuit schematic diagram of a traditional segmented DAC.

[0044] Figure 4 It is a circuit schematic diagram of a segmented DAC circuit in an embodiment.

[0045] Figure 5 It is a waveform diagram of the transfer function of a segmented DAC circuit in an embodiment.

[0046] Figure 6 It is a waveform diagram of the DNL of a segmented DAC circuit in an embodiment.

[0047] Figure 7 It is an output curve diagram of sorting all the analog outputs of a segmented DAC circuit in ascending order in an embodiment.

[0048] Figure 8 It is a circuit schematic diagram of a dark current suppression verification circuit in an embodiment.

[0049] Figure 9 It is a waveform diagram corresponding to the dark current suppression process in an embodiment.

[0050] Figure 10 The waveform diagram of the transfer characteristics of the analog segmented DAC circuit of the dark current suppression verification circuit in an embodiment.

[0051] Figure 11 The output waveform diagram of the integration module in an embodiment.

[0052] Figure 12 After calibration is completed in an embodiment, the digital code of the output of the digital-to-analog converter is further increased, and the integration output waveform diagram of the integration module. Detailed implementation manners

[0053] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0054] "Coupled", "connected", or "linked" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium. For example, a connection through an electrical conduction medium may have parasitic inductance or parasitic capacitance; indirect connection may also include a connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through circuits or components such as switches and follower circuits. In addition, in the invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity, or order between these technical features.

[0055] In the detailed description of the specification, reference is made to the accompanying drawings that form a part of it, in which the same reference numerals always represent the same components, and in which the exemplary embodiments that can be implemented are shown by way of illustration. It should be understood that other embodiments can be utilized without departing from the scope of the present disclosure, and structural or logical changes can be made. Therefore, the following detailed description should not be construed as having a limiting meaning.

[0056] The various operations in the specification can be described as a plurality of discrete actions or operations in the order that is most helpful for understanding the claimed subject matter. However, the described order should not be construed as implying that these operations must be order-related. Specifically, these operations may not be executed in the order presented. The described operations may be executed in an order different from that of the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0057] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0058] Various components and devices may be referred to or shown herein in the singular form (e.g., "transistor", "transistor", "switch", etc.), but this is merely for the convenience of discussion, and any element referred to in the singular form may include a plurality of such elements in accordance with the teachings herein.

[0059] The specification describes the use of the phrases "in one embodiment", "in other embodiments", or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "comprising", "including", "having", etc. used with respect to the embodiments of this disclosure are synonymous.

[0060] A dark current suppression method in an embodiment of the present invention is based on a segmented DAC circuit, and the suppression method includes:

[0061] Set the lower bits of the segmented DAC circuit to thermometer decoding type. Using thermometer decoding for the lower bits can ensure low DNL within a segment and guarantee the continuity of the analog output. At the same time, set the higher bits of the segmented DAC circuit to binary decoding type.

[0062] Traditional segmented DACs generally do not adopt the combination of high - bit binary decoding and low - bit thermometer decoding. The main reason is that a large DNL (differential non - linearity) often occurs when switching from thermometer code to binary code. In the DAC circuit proposed in this application, this problem is circumvented by introducing redundancy, which is hereinafter referred to as the segmented DAC circuit. Specifically, during the conversion from segment to segment, the analog output has a certain overlapping area. To achieve this goal, as Figure 4 shown, the currents of the high - bit binary of the segmented DAC circuit need to satisfy:

[0063] I N+1 <2 N ·I0 (1)

[0064]

[0065] Wherein, I N+1 is the current on the first current source of the high - bit of the segmented DAC circuit, N is the number of bits of the lower - bit of the segmented DAC circuit, I0 is the current on each current source of the lower - bit of the segmented DAC circuit, I N+j is the current on the current sources starting from the second current source of the high - bit of the segmented DAC circuit, and M is the number of bits of the high - bit of the segmented DAC circuit.

[0066] Figure 5 shows the transfer function of an 8-bit segmented DAC circuit, where the lower six bits of the segmented DAC circuit use thermometer decoding and the higher two bits use binary decoding. The two binary codes of the higher bits divide the transfer curve of the segmented DAC circuit into four segments. As Figure 5 shown, there are overlapping regions between segments, resulting in a downward jump in the transfer curve. This jump corresponds to a negative value of DNL, as Figure 6 shown. Apparently, a larger DNL may mean a weakened ability of the DAC circuit in dark current calibration. However, as Figure 7 shown, when all analog outputs are rearranged in ascending order (from smallest to largest), its curve shows that the output is continuous. Therefore, as long as the magnitude of the dark current is within the output range of the segmented DAC circuit, no matter which point the dark current is distributed at, the segmented DAC circuit can accurately suppress the dark current. In contrast, a traditional DAC may exhibit Figure 1 the phenomenon shown, for example, the dark current distributed at point B cannot be completely suppressed. Therefore, for a DAC circuit used for dark current suppression, a negative DNL has no impact on the calibration accuracy, while only a positive DNL will cause a decrease in the dark current suppression accuracy.

[0067] In a segmented DAC circuit, compared with a traditional segmented DAC, its significant advantage is that the calibration accuracy is insensitive to circuit mismatch, which benefits from the design of the lower thermometer code (without non-linearity). Due to the inherent characteristics of the thermometer code, its DNL is:

[0068]

[0069] where σ I is the standard deviation.

[0070] The DNL of binary decoding is:

[0071]

[0072] Due to the use of binary codes in the higher bits and the combination of redundancy, the positive DNL of the segmented DAC circuit is determined by the DNL of its thermometer code, rather than its higher binary code. Although the negative DNL of the segmented DAC circuit is large, it does not affect its ability to calibrate the dark current. Therefore, it can be said that the segmented DAC circuit achieves a higher number of DAC precisions with a lower matching accuracy. Therefore, compared with a traditional segmented DAC, the segmented DAC circuit suppresses the dark current more precisely, and the segmented DAC circuit has the same calibration ability as a full thermometer code DAC, but its control logic and area are significantly reduced compared with a full thermometer code DAC.

[0073] Due to the fact that the lower bits of the segmented DAC circuit adopt thermometer code, the higher bits adopt binary code and are combined with redundancy, the positive DNL of the segmented DAC circuit is determined by the DNL of the thermometer code, rather than by the binary code. Although the negative DNL of the segmented DAC circuit is relatively large, this does not affect its ability to calibrate dark current. Therefore, the segmented DAC circuit is comparable to the full-thermometer-code DAC in terms of calibration ability. In contrast, the positive DNL and negative DNL of the traditional segmented DAC are both limited by the DNL characteristics of the binary code, so it has disadvantages in terms of dark current calibration accuracy.

[0074] In addition, the characteristic that the segmented DAC circuit is insensitive to circuit mismatch can also be understood from another perspective. Within a segment, due to the characteristics of the thermometer code, device mismatch will not cause a drastic upward jump in the analog output, and the upward jump in the analog output is the core reason for the decline in the dark current calibration ability of the DAC. Between segments, due to the existence of downward jumps, device mismatch can only cause the amplitude of the downward jumps to increase or decrease. If the device mismatch increases the downward jump, this change will not reduce the ability of the DAC to suppress dark current. And if the device mismatch weakens the downward jump, as long as the degree of mismatch is not severe enough to reverse the downward jump into an upward jump, the dark current suppression ability of the segmented DAC circuit will not be affected at all.

[0075] According to the above analysis, when all the analog outputs of the segmented DAC circuit are rearranged in ascending order, its analog outputs show continuity. Therefore, as long as the dark current of the pixel is distributed within the output range of the segmented DAC circuit, this segmented DAC circuit can achieve complete suppression of the dark current.

[0076] As Figure 4 shown, based on the above dark current suppression method, the present application also discloses a segmented DAC circuit. In one embodiment, the segmented DAC circuit includes a first current source group, a second current source group, and a switch group. In other embodiments, the segmented DAC circuit can also be other circuit structures.

[0077] The first current source group includes a plurality of first current sources forming the lower bits of the DAC circuit, and the number of the first current sources is 2 N -1, where N is the number of bits of the lower bits of the DAC circuit. The second current source group includes a plurality of second current sources forming the higher bits of the DAC circuit, and the number of the second current sources is M, where M is the number of bits of the higher bits of the DAC circuit.

[0078] Among them, the current generated by each first current source in the lower bits is all I0, and among the second current sources in the higher bits, the currents from the first second current source to the last second current source are in turn: I N+1 、I N+2 …I N+M, and the current magnitudes of the second current sources satisfy the above formulas (1) and (2).

[0079] The switch group has multiple first selection terminals connected to the ground voltage, multiple second selection terminals connected to the output terminal, multiple first connection terminals connected to the first current source, and multiple second connection terminals connected to the second current source. The switch group is used to switch between the first connection terminal being connected to the first selection terminal or the second selection terminal, and the switch group is used to switch between the second connection terminal being connected to the first selection terminal or the second selection terminal. The output terminal finally outputs the current Iout.

[0080] To determine the input digital code of the segmented DAC circuit for accurately calibrating the pixel dark current, a specific algorithm also needs to be designed. As Figure 8 shown, the present application also discloses a dark current suppression verification circuit based on a specific algorithm, including: a detection module, an FPGA module, a digital-to-analog conversion compensation module, an integration module, and a comparison module.

[0081] The detection module is used to detect and generate the dark current.

[0082] The FPGA module is used to convert the digital code M DAC based on a piecewise function to generate multiple segments of input digital code DAC in .

[0083] The digital-to-analog conversion compensation module is connected to the FPGA module. The digital-to-analog conversion compensation module is used to generate a compensation current with multiple downward jumps based on the input digital code DAC in .

[0084] The integration module is connected to the detection module and the digital-to-analog conversion compensation module. The integration module is used to perform downward or upward integration based on the difference between the dark current and the supplementary current.

[0085] The comparison module 10 is connected to the integration module and the FPGA module. The comparison module 10 is used to compare the integration result of the integration module with the reference voltage VREF. The FPGA module calibrates the digital code M DAC based on the comparison result of the comparison module 10.

[0086] The detection module includes a current mirror for generating the dark current. In one embodiment, the detection module includes a first MOS transistor M1 and a second MOS transistor M2. The source electrodes of the first MOS transistor M1 and the second MOS transistor M2 are connected to the power supply voltage. The gate electrode of the first MOS transistor M1 is connected to the gate electrode of the second MOS transistor M2. The gate electrode of the first MOS transistor M1 is connected to the drain electrode of the first MOS transistor M1 to receive the input signal Vin. The drain electrode of the second MOS transistor M2 is used to output the dark current when the input signal Vin is 0.

[0087] The piecewise function is as follows:

[0088]

[0089] where N is the number of bits of the lower part of the DAC circuit, M is the number of bits of the higher part of the DAC circuit, R is the redundancy, DAC in is the input digital code, and M DAC is the digital code.

[0090] The digital-to-analog conversion compensation module includes a digital-to-analog converter 20 and a switching transistor M3. The input end of the digital-to-analog converter 20 is connected to the output end of the FPGA module to receive the input digital code DAC in , the output end of the digital-to-analog converter 20 is connected to the control end of the switching transistor M3, the first end of the switching transistor M3 is connected to the ground voltage, and the second end of the switching transistor M3 is connected to the detection module and the integration module.

[0091] The integration module includes: a first switch SW1, a second switch SW2, a capacitor C, a comparator COMP, an output transistor M4, and a current source. In one embodiment, the current source includes a fifth MOS transistor M5.

[0092] The first end of the first switch SW1 is connected to the detection module and the digital-to-analog conversion compensation module, the second end of the first switch SW1 is connected to the first input end of the comparator COMP, the second input end of the comparator COMP is used to receive a first reference signal Vref1, the first end of the capacitor C is connected to the first input end of the comparator COMP, the second end of the capacitor C is connected to the output end of the comparator COMP, the first end of the second switch SW2 is connected to the first end of the capacitor C, the second end of the second switch SW2 is connected to the second end of the capacitor C, the output end of the comparator COMP is connected to the control end of the output transistor M4, the second end of the output transistor M4 is connected to the ground voltage, the first end of the output transistor M4 is connected to the drain of the fifth MOS transistor M5 of the current source and the positive input end of the comparison module 10, and the negative input end of the comparison module 10 is connected to the reference voltage VREF.

[0093] The opening and closing of the first switch SW1 and the second switch SW2 are controlled by the FPGA module, so as to control the integration time and the reset time by the FPGA.

[0094] The integration module further includes a buffer buffer connected between the integration module and the comparison module 10. The positive input end of the buffer buffer is connected to the source of the output transistor M4 and the drain of the fifth MOS transistor M5, and the output end of the buffer buffer is connected to the positive input end of the comparison module 10 and the negative input end of the buffer buffer.

[0095] First, the digital code M of the digital-to-analog converter 20 is sent through the FPGA module DACSet to 0 and extend the integration time. In this state, any deviation between the dark current generated by the second MOS transistor M2 and the compensation current provided by the switching transistor M3 for suppressing the dark current will be integrated to saturation by the integration module. This reduces the sensitivity of the calibration accuracy of the segmented DAC circuit to current noise, amplifier offset, comparator offset, and comparator noise. If the integration module integrates to saturation, the integration voltage needs to satisfy:

[0096] V int >max{V sat,pos ,V sat,neg}

[0097] where V sat,pos is the maximum voltage for upward integration, and V sat,neg is the maximum voltage for downward integration;

[0098] If the current of the least significant bit LSB of the segmented DAC circuit is I LSB , and the integration capacitor is C, the required integration time is:

[0099]

[0100] After the integration is completed, the output voltage of the integration module either integrates upward to saturation or integrates downward to saturation. The output voltage of the integration module is compared with the reference voltage VREF by the comparison module 10. If the output of the comparison module 10 is the ground voltage GND, the digital code M DAC is incremented by 1 until a jump from the ground voltage GND to the power supply voltage VDD occurs in the comparison module 10. At this time, the digital code M DAC of the segmented DAC circuit is the optimal point for calibrating the dark current.

[0101] Figure 9 shows the relevant process. Assume that the "pixel dark current" in the figure represents the distribution point of the dark current of a certain pixel. Starting from zero, gradually increase the digital code M DAC of the digital-to-analog converter 20. Initially, the compensation current is less than the dark current, and the integration module will integrate the current downward to saturation. In this case, the digital code M DAC continues to rise until the analog output reaches point A. Since the compensation current is still less than the dark current, the integration module continues to integrate the current downward to saturation. Subsequently, the digital code M DAC is incremented by 1, and the output value of the digital-to-analog converter 20 jumps from point A to point B. Instead, the compensation current decreases, and the integration module still integrates the current downward to saturation, and there is no jump in the comparison module 10. Subsequently, the digital code M DACContinue to increase until the compensation current is greater than the dark current. At this time, the integration module will integrate the current upward until saturation, and the output of the comparison module 10 will jump. When the jump occurs, the difference between the dark current and the compensation current is (DNL + LSB) / 2 (less than or equal to the maximum remaining dark current). Therefore, the point where the output of the comparison module 10 jumps is the optimal point for calibrating the dark current. It can be seen from the above process that this calibration algorithm can accurately find the optimal digital code M of the digital-to-analog converter 20 DAC , making the dark current and the compensation current closest, and at the same time avoiding the interference caused by the downward jump in the transfer curve of the digital-to-analog converter 20.

[0102] In one embodiment, the digital-to-analog converter 20 uses a high-precision 14-bit DAC chip AD5648 to simulate the proposed segmented DAC circuit. Specifically, the 14-bit DAC is divided into two segments: the lower 11 bits use thermometer code, and the higher 3 bits use redundant binary code. Since the DNL of commercial DAC chips is excellent enough, the lower 11 bits can be directly regarded as thermometer code. To simulate the redundant binary code of the higher 3 bits, the following piecewise function can be used:

[0103]

[0104] Before the digital code M DAC enters the 14-bit high-precision DAC, it will be converted by this piecewise function and then input into the 14-bit high-precision DAC chip, so as to generate a transfer function similar to that of the segmented DAC circuit, as Figure 10 shown.

[0105] Figure 11 For the verification circuit based on Figure 8 , the output waveform of the integration module during the actual dark current calibration process. It can be observed that when the compensation current is less than the dark current, the integration module integrates downward until it reaches the saturation state; once the compensation current is greater than the dark current, the integration module switches to upward integration and continues to rise to saturation. The output signal of the comparison module 10 will also jump from the zero level (ground voltage) to the high level (power supply voltage), indicating the completion of the calibration process, which corresponds to Figure 10 point A in.

[0106] Figure 12 After the calibration is completed, when further increasing the output digital code of the digital-to-analog converter 20, the integration output of the integration module. At this time, the input digital code is directly transmitted to the digital-to-analog converter 20. It can be seen that this dark current calibration algorithm combined with the redundant DAC can effectively achieve sufficient suppression of the dark current.

[0107] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, in any aspect, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention. Any reference signs in the claims should not be construed as limiting the claims involved.

[0108] In addition, it should be understood that although this specification is described in terms of embodiments, not every embodiment only contains an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A dark current suppression method, characterized in that: Based on the segmented DAC circuit, the suppression method includes: Set the low bit of the segmented DAC circuit to the thermometer decoding type; The high bit of the segmented DAC circuit is set to binary decoding type.

2. The dark current suppression method according to claim 1, characterized in that: The high-order currents of the segmented DAC circuit satisfy: I N+1 <2 N ·I0 Among them, I N+1 is the current on the first current source of the high bit of the DAC circuit, N is the number of bits of the low bit of the DAC circuit, I0 is the current on each current source of the low bit of the DAC circuit, I N+j is the current on the current source starting from the second current source in the high position of the DAC circuit, and M is the number of bits in the high position of the DAC circuit.

3. A segmented DAC circuit, characterized in that: Based on the dark current suppression method as claimed in claim 1 or 2.

4. The segmented DAC circuit according to claim 3, characterized in that: The segmented DAC circuit includes a first current source group, a second current source group and a switch group; The first current source group includes a plurality of first current sources forming the low bits of the DAC circuit, and the number of the first current sources is 2 N -1, where N is the number of low bits of the DAC circuit; The second current source group includes a plurality of second current sources forming high bits of the DAC circuit, the number of the second current sources is M, where M is the number of bits of the high bits of the DAC circuit; The switch group has multiple first selection terminals connected to the ground voltage, multiple second selection terminals connected to the output terminal, multiple first connection terminals connected to the first current source, and multiple second connection terminals connected to the second current source. The switch group is used for switching between the first connection terminal being connected to the first selection terminal or being connected to the second selection terminal, and the switch group is used for switching between the second connection terminal being connected to the first selection terminal or being connected to the second selection terminal.

5. A dark current suppression verification circuit, characterized in that: include: A detection module, used for detecting and generating dark current; An FPGA module, used for converting the digital code to generate multiple segments of input digital code based on the piecewise function; A digital-to-analog conversion compensation module is connected to the FPGA module and is used to generate a compensation current with multiple downward jumps based on an input digital code; An integration module, connected to the detection module and the digital-to-analog conversion compensation module, for performing downward or upward integration based on the difference between the dark current and the supplementary current; The comparison module is connected to the integration module and the FPGA module, and is used to compare the integration result of the integration module with the reference voltage. The FPGA module calibrates the digital code based on the comparison result of the comparison module.

6. The dark current suppression verification circuit according to claim 5, characterized in that: The detection module includes a current mirror for generating a dark current.

7. The dark current suppression verification circuit according to claim 5, characterized in that: The piecewise function is: Among them, N is the number of low-order bits of the DAC circuit, M is the number of high-order bits of the DAC circuit, R is the redundancy, and DAC in To enter a digital code, M DAC For digital code.

8. The dark current suppression verification circuit according to claim 5, characterized in that: The digital-to-analog conversion compensation module includes a digital-to-analog converter and a switch tube. The input end of the digital-to-analog converter is connected to the output end of the FPGA module to receive the input digital code, the output end of the digital-to-analog converter is connected to the control end of the switch tube, the first end of the switch tube is connected to the ground voltage, and the second end of the switch tube is connected to the detection module and the integration module.

9. The dark current suppression verification circuit according to claim 5, characterized in that: The integration module includes: a first switch, a second switch, a capacitor, a comparator, an output tube and a current source; The first end of the first switch is connected to the detection module and the digital-to-analog conversion compensation module, the second end of the first switch is connected to the first input end of the comparator, the second input end of the comparator is used to receive a first reference signal, the first end of the capacitor is connected to the first input end of the comparator, the second end of the capacitor is connected to the output end of the comparator, the first end of the second switch is connected to the first end of the capacitor, the second end of the second switch is connected to the second end of the capacitor, the output end of the comparator is connected to the control end of the output tube, the second end of the output tube is connected to the ground voltage, and the first end of the output tube is connected to the current source and the comparison module.

10. The dark current suppression verification circuit according to claim 5, characterized in that: The dark current suppression verification circuit also includes a buffer connected between the integration module and the comparison module.

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