A shift circuit, an integrated circuit device, and an electronic device

Abstract

This application discloses a shift circuit, an integrated circuit device and an electronic device in the field of computer technology. In this application, the shift circuit can split a piece of shift information of the same data into at least two pieces, and these shift sub-information are asynchronously processed by at least two shift modules, which can improve the data shift efficiency; moreover, since each shift module is interconnected and its output port supports a delay function, the shift logic can be flexibly combined, and the timing problems caused by shifting are also solved.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and particularly to a shift circuit, an integrated circuit device, and an electronic device. Background Art

[0002] In the design of System-on-a-Chip (SoC), bus protocols are widely used. Bus protocols help build an efficient storage and computing architecture. Commonly used bus protocols include Avalon, AXI, AHB, APB, etc. During the connection, conversion, etc. processes based on bus protocols, data shifting often occurs. For example, data needs to be shifted left or right by one byte. If the data bit width is 512 bits, then in the SoC, (512 / 8)×2 - 1 = 127 kinds of shifting situations need to be designed, which will lead to complex combinational logic within the chip and it is difficult to meet the timing requirements of chip design.

[0003] Therefore, how to optimize the data shifting logic and its timing in the SoC is a problem that those skilled in the art need to solve. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a shift circuit, an integrated circuit device, and an electronic device to optimize the data shifting logic and its timing in the SoC.

[0005] In a first aspect, this application provides a shift circuit, including: a data input module, configured to obtain data to be shifted, add a delay to the data to be shifted, and transmit the data after the delay to the connected shift module; a requirement recognition module, configured to recognize the shifting information of the data to be shifted and transmit the shifting information to the splitting module; the splitting module, configured to split the shifting information into at least two shifting sub-information and transmit the at least two shifting sub-information to the shift modules that support the corresponding shifting sub-information respectively; at least two shift modules that are interconnected and whose output ports support the delay function, configured to perform a shifting operation on the data after the received delay according to the received shifting sub-information.

[0006] In a second aspect, this application provides an integrated circuit device, including: the shift circuit according to any one of the foregoing items.

[0007] In a third aspect, this application provides an electronic device, including: the integrated circuit device according to any one of the foregoing items.

[0008] As can be seen from the above solution, the present application provides a shift circuit, including: a data input module, configured to obtain data to be shifted, add a delay to the data to be shifted, and transmit the delayed data to the connected shift module; a requirement recognition module, configured to recognize the shift information of the data to be shifted and transmit the shift information to the splitting module; the splitting module, configured to split the shift information into at least two types of shift sub-information and transmit the at least two types of shift sub-information to the shift modules that support the corresponding shift sub-information respectively; at least two shift modules that are interconnected and whose output ports support the delay function, configured to perform a shift operation on the received delayed data according to the received shift sub-information.

[0009] It can be seen that the beneficial effects of the present application are as follows: The shift circuit splits one shift information of the same data into at least two parts, and these shift sub-informations are asynchronously processed by at least two shift modules, which can improve the data shift efficiency; moreover, since the respective shift modules are interconnected and their output ports support the delay function, the shift logic can be flexibly combined, and the timing problems caused by shifting can also be solved, optimizing the data shift logic and its timing in the SoC.

[0010] Correspondingly, an integrated circuit device and an electronic device provided by the present application also have the above technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0012] Figure 1 It is a schematic diagram of a shift circuit disclosed in the present application;

[0013] Figure 2 It is a schematic diagram of the connection between a data input module and each shift module disclosed in the present application;

[0014] Figure 3 It is a schematic diagram of the connection between shift modules disclosed in the present application;

[0015] Figure 4 It is a schematic diagram of the connection between the second shift modules disclosed in the present application;

[0016] Figure 5 It is a schematic diagram of the second shift circuit disclosed in the present application;

[0017] Figure 6 It is a schematic diagram of the third shift circuit disclosed in the present application;

[0018] Figure 7 Schematic diagram of the information splitting module disclosed in this application;

[0019] Figure 8 Schematic diagram of the shift logic within a shift module disclosed in this application;

[0020] Figure 9 Server structure diagram provided by this application;

[0021] Figure 10 Terminal structure diagram provided by this application. Detailed implementation manners

[0022] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other examples obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application.

[0023] Currently, during the processes of connection, conversion, etc. based on the bus protocol, the situation where data needs to be shifted often occurs. For example, the data needs to be shifted left or right by one byte. If the data bit width is 512 bits, then 127 shift situations need to be designed in the SoC, which is (512 / 8)×2 - 1 = 127. This will result in complex combinational logic within the chip and it is difficult to meet the timing requirements of chip design. For this reason, this application provides a shift solution that can split a piece of shift information of the same data into at least two pieces, and these shift sub-information are asynchronously processed by at least two shift modules, which can improve the data shift efficiency; and, since each shift module is interconnected and its output port supports the delay function, the shift logic can be flexibly combined, and the timing problems caused by shifting can also be solved, optimizing the data shift logic and its timing in the SoC.

[0024] See Figure 1 As shown, an embodiment of this application discloses a shift circuit, including: a data input module, a requirement recognition module, a splitting module, and at least two shift modules that are interconnected and whose output ports support the delay function.

[0025] Among them, the data input module is used to obtain the data to be shifted, add a delay to the data to be shifted, and transmit the delayed data to the connected shift module.

[0026] A demand recognition module, configured to recognize the shift information of the data to be shifted, and transmit the shift information to the splitting module. In one implementation, the demand recognition module is configured to recognize the shift information according to the destination address and the source address of the data to be shifted. Among them, the data to be shifted can also be input to the demand recognition module, so that the demand recognition module recognizes the shift information according to the destination address and the source address of the data to be shifted; of course, the information such as the destination address and the source address of the data to be shifted can also be directly used as the shift demand information and input to the demand recognition module, so that the demand recognition module obtains the shift information accordingly.

[0027] A splitting module, configured to split the shift information into at least two shift sub-informations, and transmit the at least two shift sub-informations to the shift modules that support the corresponding shift sub-informations respectively. In one implementation, the splitting module is configured to determine at least two shift lengths according to the shift information, and split the shift information according to the at least two shift lengths to obtain at least two shift sub-informations. The at least two shift lengths can be: 1 bit, 4 bits, 8 bits (i.e., 1 byte), and double bytes, etc.

[0028] At least two shift modules that are interconnected and whose output ports support the delay function, configured to perform a shift operation on the received data after delay according to the received shift sub-information. Figure 1 Among them, N shift modules are connected in series.

[0029] In this embodiment, the demand recognition and shift information splitting logics are added. In order to avoid causing timing problems, the data input module is not only used to obtain the data to be shifted, but also adds a delay to the data to be shifted and transmits the data after delay to the connected shift module. Specifically, the data input module can be directly connected to each shift module, or can be directly connected to any one of them, and through the connection between the shift modules, the connection from the data input module to each shift module is realized. As Figure 2 shown in A, the data input module is directly connected to each shift module, so there will be redundant connection lines; as Figure 2 shown in B, the shift modules are connected in series, and the data input module is connected to any one of them. In this way, the connection can be completed with fewer connection lines, which is beneficial to simplifying the circuit. It should be noted that in the connection method shown in B, if the data does not need to be shifted after passing through a certain shift module, then the input and output of this shift module are exactly the same, that is: there is no shift processing of the data in this shift module. For example: the data only needs to be shifted left by one byte, but the data needs to pass through the double-word shift module to reach the byte shift module, then there is no shift change of the data after passing through the double-word shift module. Among them, the double-word shift module supports the data to be shifted left or right by two bytes; the byte shift module supports the data to be shifted left or right by one byte.

[0030] To solve the timing problem, in this embodiment, the output ports of each shift module support a delay function. In the specific design, this delay function can be built into the output ports of each shift module or external to the output ports of each shift module. In one implementation, a delay function is provided inside the output ports of each shift module; correspondingly, at least two shift modules are used to: add a delay to the shifted data obtained by their own shift operations using the delay function in the output ports, and output the delayed data. In this design, each shift module is directly serially connected. When the delay function is external to the output ports of each shift module, a delay module is connected to the output ports of each shift module; the delay module is used to: add a delay to the shifted data input from any shift module and output the delayed data. As Figure 3 shown, each shift module is serially connected, but a delay module is connected between each pair and at the output port of the last shift module.

[0031] It should be noted that the shift lengths supported by different shift modules are in an integer multiple relationship, such as 1 bit, 4 bits, 8 bits (i.e., 1 byte), and double bytes, etc.

[0032] When shifting data, in addition to determining the shift length, it is also necessary to determine the shift direction. In this embodiment, a shift sub - information indicates: a shift direction and the length to be shifted in this shift direction. For example, if a shift sub - information is to shift 1 bit to the left, then this shift sub - information will be transmitted by the splitting module to the 1 - bit shift module. Since data is mostly transmitted in the form of a data stream, the shift module also needs to judge the data end signal.

[0033] In one embodiment, the right shift of data can be implemented as follows: Any shift module determines that the shift direction is right shift according to the received shift sub - information and the end signal of the received delayed data is valid, then performs a right shift operation on the received delayed data according to the received shift sub - information and outputs it according to the set bit width. If it is determined that the shift direction is right shift according to the received shift sub - information and the end signal of the currently received delayed data is invalid, the currently received delayed data is cached. After receiving the delayed data again, the delayed data received again is merged with the cached data; a right shift operation is performed on the merged data according to the received shift sub - information and output according to the set bit width. If the end signal of the delayed data received again is valid, the process ends when the cache is empty; otherwise, a right shift operation is performed on the cached data according to the received shift sub - information and output according to the set bit width; if the end signal of the delayed data received again is invalid, after waiting to receive the delayed data again, the delayed data received again is merged with the cached data; a right shift operation is performed on the merged data according to the received shift sub - information and output according to the set bit width. For example: If the set bit width is 4 bits, the delayed data input to the shift module is 0100 and the end signal of this data is valid, then in the case where the current shift sub - information is a right shift of 2 bits, a right shift operation is performed on the received delayed data according to the received shift sub - information, that is: 0100 is shifted to 0001, and the process can end after output. If the end signal of 0100 is invalid, then 0100 needs to be cached first. After receiving the delayed data again, such as receiving 1110 and 1100 later (assuming there are a total of 3 beats of data here, that is, the end signal of 1100 is valid); then 0100 and 1110 are merged in the cache to get 11100100, which is right - shifted by two bits to output 1001, leaving 11; then the remaining 11 is merged with 1100 to get 110011, then 0011 is output here, leaving 11, and then the remaining 11 is output to end the process.

[0034] In one embodiment, the data left shift can be implemented according to the following process: If any shift module determines that the shift direction is left shift according to the received shift sub-information, it will perform a left shift operation on the received data after delay according to the received shift sub-information. After outputting the left-shifted data for one clock cycle according to the set bit width, it will cache the remaining left-shifted data. If the end signal of the received data after delay is valid and the remaining left-shifted data is empty, the process ends. If the end signal of the received data after delay is valid and the remaining left-shifted data is not empty, it will perform a left shift operation on the remaining left-shifted data according to the received shift sub-information and output it according to the set bit width. If the end signal of the received data after delay is invalid, after receiving the data after delay again, it will merge the data after delay received again with the cached data. Then, it will perform a left shift operation on the merged data according to the received shift sub-information, output the left-shifted data for one clock cycle according to the set bit width, and cache the remaining left-shifted data. If the end signal of the data after delay received again is valid, the process ends when the cache is empty; otherwise, it will perform a left shift operation on the cached data according to the received shift sub-information and output it according to the set bit width. If the end signal of the data after delay received again is invalid, it will execute the steps of receiving the data after delay again, merging the data after delay received again with the cached data, performing a left shift operation on the merged data according to the received shift sub-information, outputting the left-shifted data for one clock cycle according to the set bit width, and caching the remaining left-shifted data. The specific process of left shift can refer to the aforementioned right shift and Figure 8 , which will not be elaborated here.

[0035] Please refer to Figure 4 . At least two shift modules include: a double-word shift module and a byte shift module. There is an intermediate delay module connected between the double-word shift module and the byte shift module. The double-word shift module is connected to the data input module, and the output port of the byte shift module is connected to the output delay module. In this design, the delay function is external to the output port of each shift module, and the delay module connected to the output port of the byte shift module also has the function of data output, so it is called the output delay module. The delay module between the double-word shift module and the byte shift module is called the intermediate delay module because it is placed between the two shift modules.

[0036] Correspondingly, at least two shift modules include: a 4-bit shift module and a 1-bit shift module. There is an intermediate delay module connected between the 4-bit shift module and the 1-bit shift module. The 4-bit shift module is connected to the data input module, and the output port of the 1-bit shift module is connected to the output delay module. Among them, the 4-bit shift module supports the data to be shifted left or right by 4 bit positions; the 1-bit shift module supports the data to be shifted left or right by one bit position. For others, please refer to Figure 4If the shift circuit includes a double-word shift module, a byte shift module, a 4-bit shift module, and a 1-bit shift module at the same time, please refer to the specific circuit connection in Figure 5 。

[0037] In this embodiment, the shift circuit splits the shift information of the same data into at least two parts, and these shift sub-information are asynchronously processed by at least two shift modules, which can improve the data shift efficiency; moreover, since each shift module is interconnected and its output port supports the delay function, the shift logic can be flexibly combined, and the timing problems generated by the shift can also be solved, optimizing the data shift logic and its timing in the SoC.

[0038] Please refer to Figure 6 , a shift circuit includes an input interruption module (i.e., data input module), a demand processing module (i.e., demand recognition module), an information splitting module, a double-word shift module, an intermediate interruption module, a byte shift module, and an output interruption module. In this example, the interruption module is the aforementioned delay module.

[0039] Specifically, the demand processing module can calculate the shift information according to relevant demand information such as the destination address and the source address. The shift information may include the double-word movement distance, the double-word movement direction, the byte shift distance, and the byte movement direction, etc.

[0040] The information splitting module can split a piece of shift information into two parts, and the two parts of information change from synchronous to asynchronous and are respectively sent to the double-word shift module and the byte shift module.

[0041] The interruption module is used to optimize the timing. Since a large amount of combinational logic will be generated during the shift process and the timing will be relatively poor, it is necessary to beat-optimize the data and the synchronous handshake signal through registers in the interruption module on the premise of conforming to the handshake protocol (such as adding a fixed delay). This process is called interruption, that is, interrupting the combinational logic.

[0042] The double-word shift module and the byte shift module can shift the input data according to the shift information. Specifically, the last signal (i.e., the end signal) can be used to judge whether the current input is the last beat, and the valid / ready handshake signal, etc., are judged to ensure that both before and after the shift conform to the bus protocol.

[0043] Please refer to Figure 7 , Figure 6The information splitting module may include: an input interface processing module, two FIFOs (First Input First Output, a first-in-first-out buffer), and their respective corresponding output interface processing modules. It can be seen that the information splitting module is connected to several shifting modules, and the corresponding number of FIFOs and output interface processing modules are set therein. The depth of the FIFO is two, which can avoid resource waste. It is preferred to use FIFOs built with registers rather than large RAM resources, which can also avoid resource waste. Specifically, the shifted information is transmitted to the information splitting module through the valid / ready handshake protocol. Then, the input interface processing module writes the shifted information into the two FIFOs respectively. After writing, valid becomes effective. When both FIFOs are full at the same time, a handshake is completed, that is, information output is performed only when both FIFOs are full at the same time. The output interface processing module also completes the conversion between the FIFO interface and the handshake protocol. One FIFO corresponds to a group of shifted sub-information.

[0044] During the specific design, since the input / output interruption module needs to interact with other modules, it is necessary to pipeline both the data and the valid / ready handshake signal, while the intermediate interruption module only needs to pipeline the data.

[0045] Please refer to Figure 8 , and any shifting module follows this process to implement data shifting. When the data and the corresponding shifted information are input into the shifting module, the shifting module first determines the shifting direction, and there are 3 cases.

[0046] When not shifting, the input data is directly output through the corresponding output interface until the output of this packet ends.

[0047] When shifting to the right, first determine whether the current packet has only one beat. When the last corresponding to the first beat is valid, it is considered to have only one beat; if it is invalid, it is considered to have multiple beats. When the current packet has only one beat, the data is directly shifted to the right by the corresponding number of shifts and then output. When the current packet has multiple beats, first cache the current beat data in a register; when new data arrives, it is merged with the cached data, and then shifted to the right by the corresponding number and output until the end-of-packet signal is received; during this process, the input data needs to be merged with the previous cache and output while caching new data to replace the previous cached data; when the end-of-packet signal is received, it is necessary to determine whether all the remaining cached data has been output. If it has been output, the shifting operation of the current packet ends; otherwise, an additional beat is required to shift the remaining cached data to the right by the corresponding number and output, and then the shifting operation of the current packet is considered to end.

[0048] When moving left, first determine whether the current packet has only one beat. If the last bit corresponding to the first beat of the data is valid, it is considered to have only one beat; otherwise, it is considered to have multiple beats. When the current packet has only one beat, directly shift the data to the left by the corresponding number and output it, and cache the data of this beat at the same time. After output, check whether there is any cache. When there is remaining cache, shift the cached data to the left by the corresponding number and output it; otherwise, end. When the current packet has multiple beats, first directly shift the data to the left by the corresponding number and output it, and cache the current data at the same time until the end-of-packet signal is received. When the end-of-packet signal is received, it is necessary to determine whether all the remaining cache has been output. If it has been output, end; otherwise, an additional beat is required to shift the cached data to the left by the corresponding number and output it.

[0049] It should be noted that the cases of double-word shifting include ((data bit width / 32) - 1) × 2 + 1 cases, and the byte shifting includes (3 × 2 + 1 = 7) cases. Since a double word is 32 bit, after completing the double-word shifting, byte shifting can be achieved simultaneously on this basis, thus realizing both double-word shifting and byte shifting. Since each double word is 4 bytes and can be shifted at most 3 times, including the cases of shifting left, shifting right, and not shifting, there are a total of 7 cases. Specifically, when the data bit width / 32 results in a total of n double words, the number of shifting cases is ((n - 1) × 2 + 1). When performing double-word shifting, the shifting unit is 32 bit, that is, a double word; when performing byte shifting, the unit is 8 bit, that is, a byte. When shifting, the mask corresponding to the data (used to indicate which byte is valid) also needs to be shifted. Since one double word corresponds to 4 bytes and one mask corresponds to one byte, when performing byte shifting, the shifting unit of the byte mask is 1 bit, while when performing double-word shifting, the shifting unit of the double-word mask is 4 bits. For example: in double-word shifting, when the data is shifted by 32 bit, the corresponding mask is shifted by 4 bit. When performing byte shifting, when the data is shifted by 8 bit, the corresponding mask is shifted by 1 bit.

[0050] Figure 6 The proposed scheme separates double-word shifting and byte shifting and then combines them, which can reduce the combinational logic in circuit design, optimize the timing, and simultaneously achieve byte-level shifting in any direction. Moreover, the double-word shifting module and the byte shifting module exist independently, so they can be used separately. Thus, logically, there are three shifting cases: only the double-word shifting module, only the byte shifting module, and both the double-word shifting module and the byte shifting module. Figure 6 The shown circuit can be used as three modules according to different situations.

[0051] Next, an integrated circuit device provided by an embodiment of the present application will be introduced. The integrated circuit device described below can be referred to each other with other embodiments described herein.

[0052] An embodiment of the present application discloses an integrated circuit device, including: at least one shift circuit described in any of the foregoing embodiments. The integrated circuit device may be: an FPGA, a GPU, a CPU, a storage device, etc.

[0053] Next, an electronic device provided by an embodiment of the present application will be introduced. An electronic device described below may be referred to each other with other embodiments described herein.

[0054] An embodiment of the present application discloses an electronic device, including: at least one integrated circuit device described in any of the foregoing embodiments.

[0055] In one implementation, the functions implemented by each module in the shift circuit can be realized by a computer program, which can be stored in a memory and executed by a processor. In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: obtaining data to be shifted, adding a delay to the data to be shifted, and transmitting the delayed data to the connected shift module.

[0056] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: identifying the shift information of the data to be shifted, and transmitting the shift information to the splitting module.

[0057] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: splitting the shift information into at least two types of shift sub-information, and transmitting the at least two types of shift sub-information to the shift modules that support the corresponding shift sub-information respectively.

[0058] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: performing a shift operation on the received delayed data according to the received shift sub-information.

[0059] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: identifying the shift information according to the destination address and source address of the data to be shifted.

[0060] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: determining at least two shift lengths according to the shift information, splitting the shift information according to the at least two shift lengths, and obtaining at least two types of shift sub-information.

[0061] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: adding a delay to the shifted data obtained by the self-shift operation by using the delay function in the output port of the self, and outputting the delayed data.

[0062] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: Add a delay to the shifted data input to any shift module by itself, and output the delayed data.

[0063] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: If it is determined according to the received shift sub-information that the shift direction is right shift and the end signal of the received delayed data is valid, then perform a right shift operation on the received delayed data according to the received shift sub-information, and output it according to the set bit width.

[0064] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: If it is determined according to the received shift sub-information that the shift direction is right shift and the end signal of the currently received delayed data is invalid, then cache the currently received delayed data. After receiving the delayed data again, merge the delayed data received again with the cached data; perform a right shift operation on the merged data according to the received shift sub-information, and output it according to the set bit width.

[0065] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: If the end signal of the delayed data received again is valid, end the process when the cache is empty; otherwise, perform a right shift operation on the cached data according to the received shift sub-information, and output it according to the set bit width; if the end signal of the delayed data received again is invalid, execute the steps of merging the delayed data received again with the cached data after receiving the delayed data again; perform a right shift operation on the merged data according to the received shift sub-information, and output it according to the set bit width.

[0066] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: If it is determined according to the received shift sub-information that the shift direction is left shift, then perform a left shift operation on the received delayed data according to the received shift sub-information. After outputting the left-shifted data by one beat according to the set bit width, cache the remaining left-shifted data; if the end signal of the received delayed data is valid and the remaining left-shifted data is empty, end the process; if the end signal of the received delayed data is valid and the remaining left-shifted data is not empty, then perform a left shift operation on the remaining left-shifted data according to the received shift sub-information, and output it according to the set bit width.

[0067] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: If the end signal of the delayed data received is invalid, after receiving the delayed data again, the delayed data received again is merged with the cached data; according to the received shift sub-information, the merged data is shifted left, and after outputting the shifted left data by one beat according to the set bit width, the remaining shifted left data is cached; if the end signal of the delayed data received again is valid, the process ends when the cache is empty; otherwise, according to the received shift sub-information, the cached data is shifted left and output according to the set bit width; if the end signal of the delayed data received again is invalid, after waiting to receive the delayed data again, the delayed data received again is merged with the cached data; according to the received shift sub-information, the merged data is shifted left, and after outputting the shifted left data by one beat according to the set bit width, the remaining shifted left data is cached.

[0068] Further, an embodiment of the present application also provides an electronic device. This electronic device can be either a server as shown in Figure 9 or a terminal as shown in Figure 10 . Figure 9 and Figure 10 are both structural diagrams of electronic devices shown according to an exemplary embodiment, and the content in the figure cannot be considered as any limitation on the scope of use of the present application.

[0069] Figure 9 This is a schematic structural diagram of a server provided by an embodiment of the present application. The server may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. Among them, the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the relevant steps in the shift disclosed in any of the foregoing embodiments.

[0070] In this embodiment, the power supply is used to provide working voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of the present application, and no specific limitation is imposed on it here; the input / output interface is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application needs, and no specific limitation is made here.

[0071] In addition, as a carrier for resource storage, the memory can be a read-only memory, a random access memory, a disk, or an optical disc, etc. The resources stored thereon include an operating system, a computer program, and data, etc., and the storage method can be temporary storage or permanent storage.

[0072] Among them, the operating system is used to manage and control each hardware device and computer program on the server to enable the processor to perform operations and processing on the data in the memory, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the shift method disclosed in any of the foregoing embodiments, the computer program can further include computer programs that can be used to complete other specific tasks. In addition to data such as update information of the application program, the data can also include data such as developer information of the application program.

[0073] Figure 10 The following is a schematic structural diagram of a terminal provided by an embodiment of the present application. The terminal may specifically include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, etc.

[0074] Generally, the terminal in this embodiment includes: a processor and a memory.

[0075] Among them, the processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor can also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor can be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor can also include an AI (Artificial Intelligence) processor, and the AI processor is used to process computing operations related to machine learning.

[0076] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory, as well as non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory is at least used to store the following computer programs. After the computer programs are loaded and executed by the processor, the relevant steps in the shifting method executed by the terminal side disclosed in any of the foregoing embodiments can be implemented. In addition, the resources stored in the memory may also include an operating system and data, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, update information of application programs.

[0077] In some embodiments, the terminal may further include a display screen, an input / output interface, a communication interface, sensors, a power supply, and a communication bus.

[0078] Those skilled in the art can understand that Figure 10 the structure shown in does not constitute a limitation on the terminal, and it may include more or fewer components than those shown in the figure.

[0079] Next, a non-volatile storage medium provided by an embodiment of the present application will be introduced. The non-volatile storage medium described below may be referred to in mutual reference with other embodiments described herein.

[0080] A non-volatile storage medium is used to store computer programs. When the computer programs are executed by a processor, the functions implemented by each module in the foregoing shifting circuit are realized. Among them, the non-volatile storage medium is a computer-readable non-volatile storage medium. As a carrier for storing resources, it may be a read-only memory, a random access memory, a disk, or an optical disc, etc. The resources stored thereon include an operating system, computer programs, and data, etc., and the storage method may be temporary storage or permanent storage.

[0081] Next, a computer program product provided by an embodiment of the present application will be introduced. The computer program product described below may be referred to in mutual reference with other embodiments described herein.

[0082] A computer program product includes computer programs / instructions. When the computer programs / instructions are executed by a processor, the functions implemented by each module in the foregoing shifting circuit are realized.

[0083] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other.

[0084] The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be implemented directly in hardware, in software modules executed by a processor, or in a combination thereof. The software modules may be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of non-volatile storage medium known in the art.

[0085] Specific examples are used in this article to illustrate the principles and implementation manners of the present application. The descriptions of the above embodiments are only used to help understand the method and its core idea of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A shift circuit, characterized in that, Including: A data input module, configured to obtain data to be shifted, add a delay to the data to be shifted, and transmit the data after the delay to a connected shift module; A requirement recognition module, configured to recognize the shift information of the data to be shifted, and transmit the shift information to a split module; The split module is configured to split the shift information into at least two shift sub-information, and transmit the at least two shift sub-information to shift modules that support the corresponding shift sub-information respectively; At least two shift modules that are interconnected and whose output ports support the delay function, configured to perform a shift operation on the data after the received delay according to the received shift sub-information; Wherein, any shift module, if it determines that the shift direction is right shift according to the received shift sub-information and the end signal of the currently received data after the delay is invalid, caches the currently received data after the delay. After receiving the data after the delay again, it merges the data after the delay received again with the cached data; performs a right shift operation on the merged data according to the received shift sub-information, and outputs according to the set bit width; If the end signal of the data after the delay received again is valid, the process ends when the cache is empty. Otherwise, it performs a right shift operation on the cached data according to the received shift sub-information, and outputs according to the set bit width; if the end signal of the data after the delay received again is invalid, it executes the steps of merging the data after the delay received again with the cached data after receiving the data after the delay again; performing a right shift operation on the merged data according to the received shift sub-information, and outputting according to the set bit width.

2. The shift circuit according to claim 1, wherein The requirement recognition module is configured to recognize the shift information according to the destination address and source address of the data to be shifted.

3. The shift circuit according to claim 1, wherein The split module is configured to determine at least two shift lengths according to the shift information, and split the shift information according to the at least two shift lengths to obtain the at least two shift sub-information.

4. The shift circuit according to claim 1, wherein A delay function is provided in the output port of each shift module; correspondingly, the at least two shift modules are configured to: add a delay to the shifted data obtained by their own shift operation by using the delay function in the output port, and output the data after the delay.

5. The shift circuit according to claim 1, characterized in that, The shift lengths supported by different shift modules are in an integer multiple relationship.

6. The shift circuit according to claim 1, wherein The output ports of each shift module are connected to a delay module; the delay module is configured to: add a delay to the shifted data input to itself by any shift module, and output the data after the delay.

7. The shift circuit according to claim 1, wherein Any shift module, if it determines that the shift direction is right shift according to the received shift sub-information and the end signal of the received data after the delay is valid, performs a right shift operation on the received data after the delay according to the received shift sub-information, and outputs according to the set bit width.

8. The shift circuit according to claim 1, wherein An arbitrary shift module is used to determine that the shift direction is a left shift according to the received shift sub-information. Then, it performs a left shift operation on the received data after the delay according to the received shift sub-information. After outputting the data after the left shift for one cycle according to the set bit width, it caches the remaining data after the left shift. If the end signal of the data after the delay received is valid and the remaining data after the left shift is empty, the process ends. If the end signal of the data after the delay received is valid and the remaining data after the left shift is not empty, it performs a left shift operation on the remaining data after the left shift according to the received shift sub-information and outputs it according to the set bit width.

9. The shift circuit according to claim 8, wherein An arbitrary shift module is used to, if the end signal of the data after the delay received is invalid, wait until the data after the delay is received again, and then merge the data after the delay received again with the cached data. It performs a left shift operation on the merged data according to the received shift sub-information, outputs the data after the left shift for one cycle according to the set bit width, and caches the remaining data after the left shift. If the end signal of the data after the delay received again is valid, the process ends when the cache is empty; otherwise, it performs a left shift operation on the cached data according to the received shift sub-information and outputs it according to the set bit width. If the end signal of the data after the delay received again is invalid, it executes the steps of waiting until the data after the delay is received again, merging the data after the delay received again with the cached data, performing a left shift operation on the merged data according to the received shift sub-information, outputting the data after the left shift for one cycle according to the set bit width, and caching the remaining data after the left shift.

10. The shift circuit according to any one of claims 1 to 9, characterized in that, The at least two shift modules include: a double-word shift module and a byte shift module; an intermediate delay module is connected between the double-word shift module and the byte shift module; the double-word shift module is connected to the data input module, and the output port of the byte shift module is connected to the output delay module.

11. The shift circuit according to any one of claims 1 to 9, characterized in that The at least two shift modules include: a 4-bit shift module and a 1-bit shift module; an intermediate delay module is connected between the 4-bit shift module and the 1-bit shift module; the 4-bit shift module is connected to the data input module, and the output port of the 1-bit shift module is connected to the output delay module.

12. An integrated circuit device, characterized in that, Comprising: The shift circuit according to any one of claims 1 to 11.

13. An electronic device, characterized in that, Comprising: The integrated circuit device according to claim 12.

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