Memory and method of manufacturing the same, electronic device

Abstract

Some embodiments of the present application provide a memory and a manufacturing method thereof. In the manufacturing method of the memory provided by some embodiments of the present application, after forming a storage structure on one side of a substrate, a first field effect transistor is directly formed on the side of the storage structure away from the substrate, so that a first electrode of the first field effect transistor is connected with a word line of the storage structure, thereby realizing the electrical connection between the first field effect transistor and the storage structure. Compared with the manufacturing method of the related memory, by forming the storage structure and the first field effect transistor on the same substrate, the manufacturing cost and difficulty of the memory can be reduced, and the manufacturing efficiency and yield of the memory can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular, relates to a memory, a manufacturing method thereof, and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are increased, so that any slight difference in process production can affect the performance of the devices.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. SUMMARY

[0004] The present application aims at the shortcomings of the prior art and provides a memory, a manufacturing method thereof, and an electronic device.

[0005] In a first aspect, some embodiments of the present application provide a manufacturing method of a memory, comprising:

[0006] forming a storage structure on one side of a substrate; the storage structure comprises at least one layer of a storage array, a word line, and a bit line; the storage array comprises at least one storage unit;

[0007] forming at least one first stacked structure away from the substrate on the side of the storage structure; the first stacked structure comprises at least one layer of a first sacrificial structure and at least one layer of a first semiconductor structure stacked;

[0008] forming a first electrode such that the first electrode is connected with the word line and the first semiconductor structure;

[0009] removing part of the first sacrificial structure so that part of the first semiconductor structure is exposed;

[0010] forming a first dielectric structure and a first gate on the exposed surface of the first semiconductor structure in sequence;

[0011] forming a second electrode such that the second electrode is connected with the first semiconductor structure, thereby forming a first field effect transistor.

[0012] Exemplarily, forming at least one first stacked structure comprises: forming a first planar structure covering the storage structure and at least two first stacked structures embedded in the first planar structure, the first stacked structure in the orthographic projection of the substrate at least partially overlaps with the corresponding storage unit in the orthographic projection of the substrate.

[0013] Exemplarily, the bit lines extend along a first direction parallel to the substrate and are connected to a column of memory cells arranged along the first direction in the memory array at the same layer; and the word lines extend along a second direction perpendicular to the substrate and are connected to a group of memory cells stacked along the second direction.

[0014] Exemplarily, at least one first stack structure is formed at a side of the memory structure away from the substrate, comprising:

[0015] At least two first stack structures are formed at the side of the memory structure away from the substrate;

[0016] The first planar structure is formed in a region of the memory structure not covered by the first stack structure, so that a surface of the first planar structure away from the substrate is flush with a surface of the first stack structure away from the substrate.

[0017] Exemplarily, at least two first stack structures are formed at the side of the memory structure away from the substrate, comprising:

[0018] A first combined film layer is formed at the side of the memory structure away from the substrate based on an epitaxial process; the first combined film layer comprises at least two first sacrificial layers and at least one first semiconductor layer, the first semiconductor layer being located between two adjacent first sacrificial layers;

[0019] The first combined film layer is patterned to form at least two first stack structures; the first stack structure comprises the first sacrificial structure formed after the first sacrificial layer is patterned and the first semiconductor structure formed after the first semiconductor layer is patterned.

[0020] Exemplarily, a first electrode is formed so that the first electrode is connected to the word line and the first semiconductor structure, comprising:

[0021] A first via penetrating through the first stack structure and at least one second via penetrating through the first planar structure are formed; the first via exposes a surface of at least part of the word line away from the substrate, and the second via exposes a surface of a shared word line of the memory structure extending along a second direction away from the substrate; the shared word line is connected to a group of second field effect transistors stacked along the second direction, and the bit line and the shared bit line arranged at the same layer are electrically connected through the second field effect transistors arranged at the same layer; the second direction is perpendicular to the substrate;

[0022] The first electrode filling the first via and a first connecting electrode filling the second via are formed, so that the first connecting electrode is connected to the shared word line.

[0023] Exemplarily, removing part of the first sacrificial structure so that part of the first semiconductor structure is exposed, comprises:

[0024] forming at least two third vias penetrating the first planar structure and at least one first trench; part of the first connection electrode is exposed in the first trench;

[0025] etching back the inner sidewall of the third via, removing part of the first sacrificial structure exposed so that part of the outer peripheral wall of the first semiconductor structure is exposed, and so that each of the third vias arranged in a first direction is in communication with the same first trench; the first direction is parallel to the substrate.

[0026] Exemplarily, sequentially forming a first dielectric structure and a first gate on the surface of the first semiconductor structure exposed, comprises:

[0027] forming the first dielectric structure surrounding part of the outer peripheral wall of the first semiconductor structure;

[0028] forming the first gate based on a deposition process and filling the third via and the second connection electrode of the first trench, so that the first gate surrounds the outer peripheral wall of the first dielectric structure; the first gate of each of the first field effect transistors in the same column is electrically connected through the second connection electrode and the first connection electrode.

[0029] Exemplarily, forming a second electrode so that the second electrode is connected with the first semiconductor structure, forming a first field effect transistor, comprises:

[0030] forming a second planar structure covering the first planar structure and the first stack structure;

[0031] forming at least two fourth vias penetrating the second planar structure and at least part of the first stack structure, and at least one fifth via penetrating the second planar structure; the fourth via exposes part of the first semiconductor structure, and the fifth via exposes part of the first connection electrode;

[0032] forming the second electrode in the fourth via, a third connection electrode in the fifth via, and a fourth connection electrode connecting the second electrodes of the first field effect transistors in the same row; the third connection electrode is connected with the first connection electrode; the fourth connection electrode is arranged on the side of the second planar structure away from the substrate and extends in a third direction; the third direction is parallel to the substrate and intersects the first direction.

[0033] Exemplarily, forming a storage structure on one side of the substrate, comprises:

[0034] forming a second combined film layer on one side of the substrate based on an epitaxial process; the second combined film layer comprises a plurality of second semiconductor layers and a plurality of second sacrificial layers alternately stacked;

[0035] patterning the second combined film layer to form at least two second stacked structures, at least one third stacked structure and at least one fourth stacked structure; the second stacked structure and the fourth stacked structure both extend along a third direction, and the third stacked structure extends along the first direction; along the third direction, both sides of the third stacked structure are provided with a column of the second stacked structures connected to the third stacked structure; along the first direction, the fourth stacked structure is connected to one end of the third stacked structure;

[0036] forming at least two stacked memory cells, the word lines connected to the memory cells and at least two stacked and mutually insulated bit lines based on the second stacked structure and the third stacked structure.

[0037] Exemplarily, forming at least two stacked memory cells, the word lines connected to the memory cells and at least two stacked and mutually insulated bit lines based on the second stacked structure and the third stacked structure comprises:

[0038] forming at least two stacked capacitors based on the second stacked structure;

[0039] forming at least two spaced sub-stacked structures based on the third stacked structure, the sub-stacked structure comprising a bit line group, and the bit line group comprising at least two stacked and mutually insulated bit lines;

[0040] forming a shared bit line group based on the fourth stacked structure, the shared bit line group comprising at least two stacked and mutually insulated shared bit lines;

[0041] forming a third field effect transistor and the word lines connected to the third field effect transistor based on the second stacked structure in which the capacitors are formed; along the third direction, one end of the third field effect transistor is connected to the capacitors, and the other end is connected to the bit lines arranged in the same layer;

[0042] forming at least two stacked second field effect transistors and shared word lines connected to the second field effect transistors based on the sub-stacked structure. In a second aspect, some embodiments of the present application provide a memory, comprising:

[0043] a substrate, and a storage structure, a first field effect transistor and a second field effect transistor arranged on the same substrate;

[0044] the storage structure comprises at least one memory array, word lines and bit lines;

[0045] The first field effect transistor is arranged on a side of the memory structure away from the substrate, and a second field effect transistor is used to control selection of a bit line; the first field effect transistor is electrically connected to the word line and the second field effect transistor, respectively.

[0046] The first field effect transistor includes a first gate, a first electrode and a second electrode, and the first electrode of the first field effect transistor is connected to the word line.

[0047] The first gate of the first field effect transistor is electrically connected to the second gate of the second field effect transistor.

[0048] The bit line extends along a first direction parallel to the substrate and is connected to the third field effect transistor of a column of memory cells arranged along the first direction in the memory array on the same layer;

[0049] The word line extends along a second direction perpendicular to the substrate and is connected to the third field effect transistor of a group of memory cells stacked along the second direction.

[0050] The at least two shared bit lines are arranged on a side of the memory structure along the first direction and are insulated from each other.

[0051] The at least two second field effect transistors are stacked, and the at least one shared word line is connected to the second field effect transistors.

[0052] The second field effect transistors and the shared word line are both arranged between the shared bit lines and the memory structure along the first direction.

[0053] The bit lines and the shared bit lines on the same layer are electrically connected through the second field effect transistors on the same layer.

[0054] The word line is electrically connected to the third gate of the third field effect transistor of a group of memory cells stacked along the second direction.

[0055] The second electrodes of a row of first field effect transistors arranged along a third direction are electrically connected to each other through fourth connection electrodes; the third direction is parallel to the substrate and intersects the first direction.

[0056] The first gates of a column of first field effect transistors arranged along the first direction are electrically connected to each other through second connection electrodes.

[0057] The second connection electrodes are electrically connected to the shared word line through the first connection electrodes.

[0058] The technical scheme provided by some embodiments of the present application has the beneficial technical effects of:

[0059] In the manufacturing method of the memory provided by some embodiments of the present application, after the storage structure is formed on one side of the substrate, the first field effect tube is directly formed on the side of the storage structure away from the substrate. Compared with the manufacturing method of the related three-dimensional stacked memory, by forming the storage structure and the first field effect tube on the same substrate, the manufacturing cost and difficulty of the memory can be reduced, and the manufacturing efficiency and yield of the memory can be improved.

[0060] In the memory provided by some embodiments of the present application, by arranging the first field effect tube and the storage structure on the same substrate, the manufacturing cost and difficulty of the memory can be reduced, and the manufacturing efficiency and yield of the memory can be improved; by electrically connecting the first field effect tube with the word line and the second field effect tube, the electrical function of the first field effect tube can be realized, the operation of the word line can be effectively matched with the operation of the bit line, the circuit is simplified, and the working efficiency of the circuit is improved.

[0061] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0062] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the appended drawings.

[0063] Figure 1 A flowchart of a manufacturing method of a memory provided by some embodiments of the present application is shown in FIG. 1;

[0064] Figure 2 A cross-sectional view of a manufacturing method of a memory provided by some embodiments of the present application is shown in FIG. 2, in which a second combined film layer is formed on one side of a substrate;

[0065] Figure 3 A top view of a manufacturing method of a memory provided by some embodiments of the present application is shown in FIG. 3, in which a second stacked structure, a third stacked structure and a fourth stacked structure are formed;

[0066] Figure 4 A top view of a manufacturing method of a memory provided by some embodiments of the present application is shown in FIG. 4, in which a third planar structure is formed;

[0067] Figure 5 A top view of a manufacturing method of a memory provided by some embodiments of the present application is shown in FIG. 5, in which a support structure is formed;

[0068] Figure 6A cross-sectional view of a film structure after forming a sixth via, according to some embodiments of the present application;

[0069] Figure 7 A cross-sectional view of a film structure at AA, according to some embodiments of the present application; Figure 6

[0070] Figure 8 A cross-sectional view of a film structure at BB, according to some embodiments of the present application; Figure 6

[0071] A cross-sectional view of a film structure at AA after etching a portion of the sidewall of the sixth via, according to some embodiments of the present application; Figure 9

[0072] A cross-sectional view of a film structure at BB after forming a first electrode structure, according to some embodiments of the present application; Figure 10

[0073] A cross-sectional view of a film structure at BB after forming a capacitor, according to some embodiments of the present application; Figure 11

[0074] A top view of a film structure after forming a second trench and a third trench, according to some embodiments of the present application; Figure 12

[0075] A cross-sectional view of a film structure at BB, according to some embodiments of the present application; Figure 13 Figure 12 A cross-sectional view of a film structure at CC, according to some embodiments of the present application;

[0076] Figure 14 Figure 12 A cross-sectional view of a film structure at CC after forming a bit line and a shared bit line, according to some embodiments of the present application;

[0077] Figure 15 A top view of a film structure after forming a fourth planar structure, according to some embodiments of the present application;

[0078] Figure 16 A cross-sectional view of a film structure at CC after forming a bit line and a shared bit line, according to some embodiments of the present application;

[0079] Figure 17 A top view of a film structure after forming a fourth planar structure, according to some embodiments of the present application;

[0080] Figure 18 ​​​A method for manufacturing a memory according to some embodiments of the present application includes forming a third field effect transistor and a word line, and a cross-sectional view of a film structure perpendicular to a substrate at a BB after the forming;

[0081] Figure 19 A method for manufacturing a memory according to some embodiments of the present application includes forming a second field effect transistor and a shared word line, and a cross-sectional view of a film structure perpendicular to a substrate at a CC after the forming;

[0082] Figure 20 A method for manufacturing a memory according to some embodiments of the present application includes forming a first stack structure, and a top view of a film structure after the forming;

[0083] Figure 21 A cross-sectional view of the film structure perpendicular to a substrate at a BB is shown in FIG. 8; Figure 20

[0084] Figure 22 A method for manufacturing a memory according to some embodiments of the present application includes forming a first electrode and a first connection electrode, and a top view of a film structure after the forming;

[0085] Figure 23 A cross-sectional view of the film structure perpendicular to a substrate at a BB is shown in FIG. 10; Figure 22

[0086] A cross-sectional view of the film structure perpendicular to a substrate at a CC is shown in FIG. 11; Figure 24 Figure 22

[0087] Figure 25 A method for manufacturing a memory according to some embodiments of the present application includes forming a second connection electrode, and a top view of a film structure after the forming;

[0088] Figure 26 A cross-sectional view of the film structure perpendicular to a substrate at a BB is shown in FIG. 13;

[0089] Figure 27 A cross-sectional view of the film structure perpendicular to a substrate at a BB is shown in FIG. 13; Figure 26

[0090] A method for manufacturing a memory according to some embodiments of the present application includes forming a fourth via and a fifth via, and a top view of a film structure after the forming; Figure 28

[0091] A method for manufacturing a memory according to some embodiments of the present application includes forming a second electrode, a third connection electrode, and a fourth connection electrode, and a top view of a film structure after the forming; Figure 29

[0092] ​​​​Figure 30 For Figure 29 A cross-sectional view of the film layer structure shown at BB is shown.

[0093] Legend of reference signs:

[0094] 100-substrate; 101-second sacrificial layer; 1011-second sacrificial structure; 102-second semiconductor layer; 1021-second semiconductor structure; 103-first protective layer; 1031-first protective structure; 104-second stacked structure; 105-third stacked structure; 1051-initial sub-stacked structure; 1052-sub-stacked structure; 106-fourth stacked structure; 1061-fourth sub-stacked structure; 107-third planar structure; 1071-sixth via hole; 108-supporting structure; 109-capacitor; 1091-first electrode structure; 1092-first dielectric structure; 1093-second electrode structure;

[0095] 110-second trench; 111-third trench; 112-third field effect transistor; 1121-third dielectric structure; 1122-third gate; 113-second field effect transistor; 1131-second dielectric structure; 1132-second gate; 114-fourth planar structure; 115-seventh via hole; 116-eighth via hole; 117-first stacked structure; 1171-first sacrificial structure; 1172-first semiconductor structure; 1173-second protective structure; 118-first planar structure; 119-first electrode;

[0096] 120-first connecting electrode; 121-first field effect transistor; 1211-first dielectric structure; 1212-first gate; 1213-second electrode; 122-second connecting electrode; 123-second planar structure; 124-fourth via hole; 125-fifth via hole; 126-third connecting electrode; 127-fourth connecting electrode;

[0097] 200-storage structure; 201-bit line; 202-shared bit line; 203-word line; 204-shared word line. DETAILED DESCRIPTION

[0098] Embodiments of the present application will be described below in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions of the technical solutions of some embodiments of the present application, and do not limit the technical solutions of some embodiments of the present application.

[0099] It is to be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. It is further understood that the terms "comprise" and "comprising" and the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0100] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0101] The technical solutions of the present application will be described in detail below with specific examples. It should be noted that the following embodiments can be mutually referenced, borrowed or combined. For the same terms, similar features and similar implementation steps in different embodiments, they will not be described repeatedly.

[0102] Some embodiments of the present application provide a memory manufacturing method. A flowchart of the manufacturing method is shown in FIG. 1, which includes steps S101-S106. Figure 1

[0103] S101, forming a storage structure on one side of a substrate; the storage structure includes at least one layer of a storage array, a word line and a bit line; the storage array includes at least one storage unit.

[0104] S102, forming at least one first stacked structure on the side of the storage structure away from the substrate; the first stacked structure includes at least one layer of a first sacrificial structure and at least one layer of a first semiconductor structure stacked.

[0105] S103, forming a first electrode such that the first electrode is connected with the word line and the first semiconductor structure.

[0106] S104, removing part of the first sacrificial structure such that part of the first semiconductor structure is exposed.

[0107] S105, sequentially forming a first dielectric structure and a first gate on the exposed surface of the first semiconductor structure.

[0108] S106, forming a second electrode such that the second electrode is connected with the first semiconductor structure, forming a first field effect transistor.

[0109] ​In the manufacturing method of the memory provided in some embodiments of the present application, after forming the memory structure on one side of the substrate, the first field effect transistor is formed directly on the side of the memory structure away from the substrate, so that the first electrode of the first field effect transistor is connected with the word line of the memory structure, thereby realizing the electrical connection between the first field effect transistor and the memory structure. Compared with the manufacturing method of the related three-dimensional stacked memory, by forming the memory structure and the first field effect transistor on the same substrate, the manufacturing cost and difficulty of the memory can be reduced, and the manufacturing efficiency and yield of the memory can be improved.

[0110] In order to facilitate the reader to intuitively understand the manufacturing method of the memory provided in some embodiments of the present application and the advantages of the manufacturing method, the following will be combined with the accompanying drawings to describe the manufacturing method of the memory provided in some embodiments of the present application. Figures 2-30 The manufacturing method of the memory will be described in detail.

[0111] In practical application, the memory structure can be only one layer of memory array, or can be a plurality of layers of memory array stacks.

[0112] Optionally, in some embodiments of the present application, forming the at least one first stacked structure comprises: forming a first planar structure covering the memory structure and at least two first stacked structures embedded in the first planar structure, the first stacked structure in the orthographic projection of the substrate at least partially overlaps with the corresponding memory cell in the orthographic projection of the substrate.

[0113] Optionally, in some embodiments of the present application, the bit line extends along a first direction parallel to the substrate and is connected with a column of memory cells arranged along the first direction in the memory array at the same layer; the word line extends along a second direction perpendicular to the substrate and is connected with a group of memory cells stacked along the second direction.

[0114] Optionally, in some embodiments of the present application, the orthographic projection of each first stacked structure in the substrate at least partially overlaps with the orthographic projection range of the corresponding memory cell in the substrate.

[0115] Optionally, in some embodiments of this application, the formation of a memory structure on one side of the substrate 100 in step S101 includes: forming a second combined film layer on one side of the substrate 100 based on an epitaxial process; the second combined film layer includes multiple alternating stacked second sacrificial layers 101 and second semiconductor layers 102; patterning the second combined film layer to form at least two second stacked structures, at least one third stacked structure, and at least one fourth stacked structure; both the second and fourth stacked structures extend along a third direction, and the third stacked structure extends along a first direction; along the third direction, a row of second stacked structures connected to the third stacked structure is provided on both sides of the third stacked structure; along the first direction, one end of the fourth stacked structure is connected to the third stacked structure; forming at least two stacked memory cells, word lines connected to the memory cells, and at least two stacked and mutually insulated bit lines based on the second and third stacked structures.

[0116] Optionally, in some embodiments of this application, the above steps involve forming a second combined film layer on one side of the substrate 100 based on an epitaxial process; the second combined film layer includes multiple alternating stacked second sacrificial layers 101 and second semiconductor layers 102, including: forming alternating stacked second sacrificial layers 101 and second semiconductor layers 102 on one side of the substrate 100 based on an epitaxial process.

[0117] Optionally, such as Figure 2 As shown, a first protective layer 103 can be deposited on the side of the uppermost second sacrificial layer 101 away from the substrate 100 to protect the second sacrificial layer 101. The second combined film layer includes stacked second sacrificial layers 101, second semiconductor layers 102, and a first protective layer 103.

[0118] Optionally, such as Figure 2 As shown, the second composite film layer includes four second sacrificial layers 101, three second semiconductor layers 102, and one first protective layer 103.

[0119] Optionally, in some embodiments of this application, the substrate 100 is a silicon substrate, the material of the second sacrificial layer 101 includes SiGe (germanium silicon), the material of the second semiconductor layer 102 includes Si (silicon), and the material of the first protective layer includes silicon nitride. Optionally, the material of the second semiconductor layer 102 includes single-crystal silicon.

[0120] Optionally, in some embodiments of the present application, the patterning the second combined film layer to form the at least two second stacked structures, the at least one third stacked structure and the at least one fourth stacked structure comprises: processing the second combined film layer based on a patterning process including exposure, development and etching to form the at least two second stacked structures 104 extending along the third direction, the at least one third stacked structure 105 extending along the first direction and the at least one fourth stacked structure 106 extending along the third direction.

[0121] Optionally, as shown in FIG. 1C, the third stacked structure 105 is provided with a column of second stacked structures 104 connected to the third stacked structure 105 on each side of the third stacked structure 105; the fourth stacked structure 106 is connected to the third stacked structure 105 at one end of the third stacked structure 105 along the first direction. Figure 3

[0122] Optionally, as shown in FIG. 1C, the third stacked structure 105 is provided with a column of second stacked structures 104 connected to the third stacked structure 105 on each side of the third stacked structure 105; the fourth stacked structure 106 is connected to the third stacked structure 105 at one end of the third stacked structure 105 along the first direction. Figure 3

[0123] Optionally, in some embodiments of the present application, the second stacked structure 104, the third stacked structure 105 and the fourth stacked structure 106 are integrally formed structures, in order to facilitate intuitive understanding of the second stacked structure 104, the third stacked structure 105 and the fourth stacked structure 106, Figure 3

[0124] Optionally, in some embodiments of the present application, after the step of patterning the second combined film layer to form the at least two second stacked structures, the at least one third stacked structure and the at least one fourth stacked structure, there is further comprising: filling the groove between the adjacent two second stacked structures 104 and the groove between the second stacked structure 104 and the fourth stacked structure 106 based on a deposition process to form a third flat structure 107.

[0125] Optionally, as shown in FIG. 1C, the third stacked structure 105 is provided with a column of second stacked structures 104 connected to the third stacked structure 105 on each side of the third stacked structure 105; the fourth stacked structure 106 is connected to the third stacked structure 105 at one end of the third stacked structure 105 along the first direction. Figure 4 ​​​As shown, based on a deposition process, silicon oxide is filled into the trench between the two adjacent second stacked structures 104 and the trench between the second stacked structure 104 and the fourth stacked structure 106, and based on a CMP (Chemical Mechanical Polishing) process, the silicon oxide is processed so that the surfaces of the second stacked structure 104, the third stacked structure 105 and the fourth stacked structure 106 away from the substrate are exposed, forming a third planar structure 107.

[0126] Optionally, the surfaces of the third planar structure 107, the second stacked structure 104, the third stacked structure 105 and the fourth stacked structure 106 away from the substrate are coplanar.

[0127] Optionally, in some embodiments of the present application, after the third planar structure 107 is formed, the method further comprises: based on a patterning process, processing the third planar structure 107 so that each second stacked structure 104 exposes a side away from the third stacked structure 105; and based on a deposition process, forming a support structure 108 connected to the side of the second stacked structure 104 away from the third stacked structure 105.

[0128] Optionally, the etching removes two side surfaces of the third planar structure 107 along the third direction until the side of each second stacked structure 104 away from the third stacked structure 105 is exposed.

[0129] Optionally, as shown, Figure 5 In the subsequent process, the support structure 108 plays a role of supporting the second stacked structure 104, so as to reduce the probability of fracture of the second stacked structure 104.

[0130] Optionally, in some embodiments of the present application, the material of the support structure 108 includes silicon nitride, which has high strength, so as to help guarantee the structural strength of the support structure 108, and further reduce the probability of fracture of the second stacked structure 104 in the subsequent process, thereby helping to improve the yield of the memory.

[0131] Optionally, in some embodiments of the present application, the surfaces of the support structure 108, the third planar structure 107, the second stacked structure 104, the third stacked structure 105 and the fourth stacked structure 106 away from the substrate are coplanar.

[0132] Optionally, in some embodiments of the present application, the step of forming at least two stacked storage units, word lines connected with the storage units, and at least two stacked and mutually insulated bit lines based on the second stacked structure 104 and the third stacked structure 105 comprises: forming at least two stacked capacitors based on the second stacked structure 104; forming at least two sub-stacked structures arranged at intervals based on the third stacked structure 105, the sub-stacked structure comprising a bit line group, the bit line group comprising at least two stacked and mutually insulated bit lines; forming a shared bit line group comprising at least two stacked and mutually insulated shared bit lines based on the fourth stacked structure 106; forming a third field effect transistor and a word line connected with the third field effect transistor based on the second stacked structure 104 in which the capacitors are formed; along the third direction, one end of the third field effect transistor is connected with the capacitor, and the other end is connected with the bit line arranged in the same layer; forming at least two stacked second field effect transistors and shared word lines connected with the second field effect transistors based on the sub-stacked structure.

[0133] Optionally, in some embodiments of the present application, the step of forming at least two stacked and mutually insulated capacitors based on the second stacked structure 104 comprises: forming a photoresist structure covering the support structure 108, the third flat structure 107, the second stacked structure 104, the third stacked structure 105, and the fourth stacked structure 106; forming at least two vias in the photoresist structure, along the third direction, so that part of the third flat structure 107 on both sides of any one of the second stacked structures 104 is exposed; etching the exposed part of the third flat structure 107 as a mask, forming at least two sixth vias 1071 penetrating the third flat structure 107, the sidewall of the sixth via 1071 comprising part of the sidewall of the second stacked structure 104; laterally etching part of the second stacked structure 104 exposed in the sixth via 1071 to remove part of the second sacrificial structure 1011 of the second stacked structure 104 until any two adjacent sixth vias 1071 along the first direction are connected.

[0134] Optionally, in some embodiments of the present application, the exposed part of the third flat structure 107 is etched as a mask based on the photoresist structure in which the via is formed, to form a plurality of sixth vias 1071 penetrating the third flat structure 107, as shown in Figure 6 and Figure 7 Optionally, as shown in Figure 6 and Figure 7 along the first direction, one second stacked structure 104 is arranged between any two adjacent sixth vias 1071, so that both opposite sidewalls of the second stacked structure 104 are exposed.

[0135] Optionally, as shown in Figure 7 along the first direction, both opposite sidewalls of the sixth via 1071 comprise part of the sidewall of the second stacked structure 104.

[0136] Optionally, in some embodiments of the present application, as shown in Figure 7 and Figure 8 The second stack structure 104, the third stack structure 105 and the fourth stack structure 106 each include the second sacrificial structure 1011, the second semiconductor structure 1021 and the first protective structure 1031 which are alternately stacked, wherein the second sacrificial structure 1011 is formed by the second sacrificial layer 101 after being patterned, the second semiconductor structure 1021 is formed by the second semiconductor layer 102 after being patterned, and the first protective structure 1031 is formed by the first protective layer 103 after being patterned.

[0137] Optionally, after the sixth via hole 1071 is formed, the method further includes: laterally etching part of the sidewall of the sixth via hole 1071. Optionally, the method further includes: etching to expose part of the second sacrificial structure 1011 of the part of the second stack structure 104 in the sixth via hole 1071 until any two adjacent sixth via holes 1071 along the first direction are connected, as shown in Figure 9 , part of the outer peripheral wall of the second semiconductor structure 1021 is exposed.

[0138] Optionally, as shown in Figure 7 and Figure 9 Due to the protection of the third planar structure 107, the fourth stack structure 106 can be prevented from being etched, i.e., the third planar structure 107 also plays a role in protecting the fourth stack structure 106. Optionally, the third planar structure 107 also plays a role in protecting the third stack structure 105.

[0139] Optionally, in the step of forming at least two capacitors which are stacked and insulated from each other based on the second stack structure 104, the method further includes: processing the part of the exposed second semiconductor structure 1021 based on a metal silicide process, so that the part of the exposed second semiconductor structure 1021 forms a metal silicide, thereby obtaining a first electrode structure 1091, as shown in Figure 10 .

[0140] Optionally, in the step of forming at least two capacitors 109 based on the second stack structure 104, the method further includes: sequentially forming a first dielectric structure 1092 and a second electrode structure 1093 which surround the exposed outer sidewall of the first electrode structure 1091 based on a deposition process, thereby obtaining the capacitor 109 including the first electrode structure 1091, the first dielectric structure 1092 and the second electrode structure 1093.

[0141] Optionally, as shown in Figure 11 , along the second direction, the plurality of capacitors 109 are stacked on one side of the substrate 100.

[0142] Optionally, in some embodiments of the present application, the material of the second electrode structure 1093 includes polysilicon.

[0143] Optionally, in some embodiments of the present application, the above-mentioned step of forming at least two spaced sub-stacked structures 1052 based on the third stacked structure 105, the sub-stacked structure 1052 comprising a bit line group, the bit line group comprising at least two stacked and mutually insulated bit lines 201; and forming a shared bit line group based on the fourth stacked structure 106, the shared bit line group comprising at least two stacked and mutually insulated shared bit lines 202, comprises the following steps:

[0144] First, the third stacked structure 105 and the third planar structure 107 are patterned to form a second trench 110 penetrating through the third stacked structure 105 and a third trench 111 penetrating through the third planar structure, respectively; the second trench 110 extends along a first direction; the third trench 111 extends along a third direction, and along the first direction, the third trench 111 is arranged at one end of the fourth stacked structure 106, so that the fourth stacked structure 106 is exposed in the third trench 111, as shown in Figure 12 、 Figure 13 and Figure 14 .

[0145] Then, the partial side walls of the second trench 110 and the partial side walls of the third trench 111 are etched laterally to remove the partial second semiconductor structure 1021 of the initial sub-stacked structure 1051 and the partial second semiconductor structure 1021 of the fourth stacked structure 106, respectively.

[0146] Optionally, the partial side walls of the second trench 110 are etched laterally, including: etching the second semiconductor structure 1021 of the initial sub-stacked structure 1051 exposed in the second trench 110 laterally until the partial second semiconductor structure 1021 in the second stacked structure 104 is exposed, so that a first lateral recess is formed between any two adjacent second sacrificial structures 1011. As shown in Figure 13 the dashed line represents the boundary between the second stacked structure 104 and the initial sub-stacked structure 1051, and the dashed line does not exist in the actual product.

[0147] Optionally, the partial side walls of the third trench 111 are etched laterally, including: etching the second semiconductor structure 1021 of the fourth stacked structure 106 exposed in the third trench 111 laterally until the second semiconductor structure 1021 is completely removed, so that a second lateral recess is formed between any two adjacent second sacrificial structures 1011.

[0148] Then, based on a deposition process, conductive material is deposited in the second trench 110 and the third trench 111, so that the first lateral recess and the second lateral recess are both filled with the conductive material, and the conductive material in the second trench 110 and the third trench 111 is removed to form a bit line 201 located in the first lateral recess and a shared bit line 202 located in the second lateral recess, respectively.

[0149] Optionally, as shown in Figure 15 and Figure 16 The sub-lamination structure 1052 includes a plurality of lamination and insulation bit lines 201 extending along the first direction, and the fourth sub-lamination structure 1061 includes a plurality of lamination and insulation shared bit lines 202 extending along the third direction. The bit lines 201 and the shared bit lines 202 are arranged on the same layer, and the second semiconductor structure 1021 is arranged between the bit lines 201 and the shared bit lines 202.

[0150] Optionally, in some embodiments of the present application, the third field effect transistor 112 and the word line 203 connected to the same group of third field effect transistors 112 are formed based on the second lamination structure 104 in which the capacitor 109 is formed in the above-mentioned step; along the third direction, one end of the third field effect transistor 112 is connected to the capacitor 109, and the other end is connected to the bit line 201 arranged on the same layer; at least two lamination second field effect transistors 113 and the shared word line 204 connected to the second field effect transistor 113 are formed based on the sub-lamination structure 1052, which specifically includes the following steps:

[0151] First, based on the deposition process, the dielectric material is deposited in the second groove 110 and the third groove 111, and based on the CMP process, the fourth flat structure 114 is formed which is coplanar with the surface of the second lamination structure 104 in which the capacitor 109 is formed, the sub-lamination structure 1052 and the fourth sub-lamination structure 1061 away from the substrate, as shown in Figure 17 .

[0152] Then, a photoresist structure covering the second lamination structure 104, the sub-lamination structure 1052, the fourth sub-lamination structure 1061 and the fourth flat structure 114 is formed, and the photoresist structure includes a plurality of vias, so that one end of the sub-lamination structure 1052 close to the fourth sub-lamination structure 1061 is exposed, and part of the second lamination structure 104 is exposed.

[0153] Then, taking the photoresist structure as a mask, the second lamination structure 104 and the sub-lamination structure 1052 are etched to form the seventh via 115 penetrating the second lamination structure 104 and the eighth via 116 penetrating the sub-lamination structure 1052, respectively, as shown in Figure 17 .

[0154] Then, the second sacrificial structure 1011 exposed in the seventh via 115 of the second lamination structure 104 is laterally etched until part of the first dielectric structure 1092 of the capacitor 109 is exposed; the second sacrificial structure 1011 exposed in the eighth via 116 of the sub-lamination structure 1052 is laterally etched.

[0155] Next, based on the deposition process, dielectric material and conductive material are sequentially filled into the seventh via 115 and the eighth via 116 to form a third dielectric structure 1121 and a third gate 1122 surrounding a portion of the second semiconductor structure 1021 in the second stacked structure 104, and to form a second dielectric structure 1131 and a second gate 1132 surrounding a portion of the second semiconductor structure 1021 in the sub-stacked structure 1052.

[0156] Optionally, such as Figure 18 As shown, along the second direction, multiple stacked third field-effect transistors 112 belong to the same group of third field-effect transistors 112, and each group of third field-effect transistors 112 is connected to a word line 203, which extends along the second direction. The third field-effect transistor 112 includes a third dielectric structure 1121, a third gate 1122, and a second semiconductor structure 1021 surrounded by the third dielectric structure 1121.

[0157] Optionally, such as Figure 18 As shown, along the third direction, one end of the third field-effect transistor 112 is connected to the capacitor 109, and the other end is connected to the bit line 201 arranged in the same layer, so that the first electrode structure 1091 of the capacitor 109 and part of the bit line 201 serve as the source and drain of the third field-effect transistor 112.

[0158] Optionally, such as Figure 19 As shown, along the second direction, multiple stacked second field-effect transistors 113 belong to the same group of second field-effect transistors 113. Each group of second field-effect transistors 113 is connected to a shared word line 204, which extends along the second direction. The second field-effect transistor 113 includes a second dielectric structure 1131, a second gate 1132, and a second semiconductor structure 1021 surrounded by the second dielectric structure 1131.

[0159] Optionally, such as Figure 19 As shown, one end of the second field-effect transistor 113 is connected to bit line 201, and the other end is connected to shared bit line 202, so that part of bit line 201 and part of shared bit line 202 act as the source and drain of the second field-effect transistor 113. That is, the electrical connection between bit line 201 and shared bit line 202 arranged on the same layer can be realized through the second field-effect transistor 113.

[0160] Optionally, in the embodiments of this application, based on Figures 2 to 19The shown flow obtains a storage structure 200 on one side of the substrate 100, the storage structure 200 including at least two layers of stacked storage arrays, at least two word lines 203 and at least two bit lines 201; the bit lines 201 extend along a first direction parallel to the substrate 100 and are connected to a column of storage cells arranged along the first direction in the storage array on the same layer; the word lines 203 extend along a second direction perpendicular to the substrate and are connected to a group of storage cells stacked along the second direction. Optionally, the storage cell includes a capacitor 109 and a third field effect transistor 112 electrically connected.

[0161] Optionally, in some embodiments of the present application, the step S102 of forming at least one first stacked structure on the side of the storage structure away from the substrate includes: forming at least two first stacked structures 117 on the side of the storage structure 200 away from the substrate 100; and forming a first planar structure 118 in the region of the storage structure 200 not covered by the first stacked structure 117, so that the surface of the first planar structure 118 away from the substrate is flush with the surface of the first stacked structure 117 away from the substrate.

[0162] Optionally, in some embodiments of the present application, the first stacked structure 117 is formed on the side of the storage structure 200 away from the substrate 100 in a number matching that of the word lines 203, and the first field effect transistor for addressing is formed based on the first stacked structure 117.

[0163] Optionally, in some embodiments of the present application, the step of forming at least two first stacked structures 117 on the side of the storage structure 200 away from the substrate 100 includes: forming a first combined film layer on the side of the storage structure 200 away from the substrate 100 based on an epitaxy process; the first combined film layer includes at least two first sacrificial layers and at least one first semiconductor layer, the first semiconductor layer being located between two adjacent first sacrificial layers; and patterning the first combined film layer to form at least two first stacked structures 117; the first stacked structure 117 includes a first sacrificial structure 1171 formed after patterning of the first sacrificial layer and a first semiconductor structure 1172 formed after patterning of the first semiconductor layer.

[0164] Optionally, in some embodiments of the present application, to facilitate the epitaxy process, before forming the first combined film layer, the method further includes: removing at least part of the first protective structure 1031 so that at least part of the second sacrificial structure 1011 on the top layer of the storage structure 200 is exposed.

[0165] Optionally, based on the epitaxy process, the first sacrificial layer and the first semiconductor layer are alternately formed on the side of the exposed second sacrificial structure 1011 of the storage structure 200. Optionally, in some embodiments of the present application, two layers of first sacrificial layers and one layer of first semiconductor layers are formed.

[0166] Optionally, the first set of film layers are processed based on a patterning process to form at least two first stacked structures 117, as shown in FIG. 1C. Figure 20 Optionally, each first stacked structure 117 at least partially overlaps with a corresponding memory cell in a footprint of the substrate 100 in a plan view, so as to facilitate electrical connection between a first field effect transistor formed based on the first stacked structure 117 and the word line 203.

[0167] Optionally, as shown in FIG. 1C, the first stacked structure 117 includes a first sacrificial structure 1171, a first semiconductor structure 1172, the first sacrificial structure 1171, and a second protective structure 1173. Figure 21

[0168] Optionally, in some embodiments of the present application, after the first stacked structure 117 is formed, the method further includes: forming a first planar structure 118 flush with a surface of the first stacked structure 117 away from the substrate based on a deposition process and a CMP process.

[0169] Optionally, in some embodiments of the present application, the first electrode 119 is formed to pass through the first stacked structure 117 in the step S103, so that the first electrode 119 is connected with the word line 203, including: forming a first via passing through the first stacked structure 117 and at least one second via passing through the first planar structure 118; the first via exposes a surface of at least part of the word line 203 away from the substrate, and the second via exposes a surface of the shared word line 204 of the memory structure 200 away from the substrate; the shared word line 204 is connected with a set of second field effect transistors 113 stacked in the second direction, and the bit line 201 and the shared bit line 202 are electrically connected through the second field effect transistors 113 arranged in the same layer; and forming the first electrode 119 filling the first via and a first connecting electrode 120 filling the second via, so that the first connecting electrode 120 is connected with the shared word line 204.

[0170] Optionally, in some embodiments of the present application, the first stacked structure 117 is patterned based on a patterning process to form at least one first via passing through the first stacked structure 117, so that a surface of at least part of the word line 203 away from the substrate is exposed.

[0171] Meanwhile, the first planar structure 118 is patterned based on the same patterning process to form at least one second via passing through the first planar structure 118, so that a surface of the shared word line 204 away from the substrate is exposed.

[0172] Optionally, a conductive material is filled in the first via and the second via based on a deposition process to form the first electrode 119 located in the first via and the first connecting electrode 120 located in the second via, as shown in FIG. 1D. Figure 22 ​​

[0173] Optionally, as shown in Figure 23 the first electrode 119 extends along the second direction, and one end of the first electrode 119 is connected with the word line 203, i.e., the first electrode 119 is electrically connected with the word line 203.

[0174] Optionally, as shown in Figure 24 the first connecting electrode 120 extends along the second direction, and one end of the first connecting electrode 120 is connected with the shared word line 204, i.e., the first connecting electrode 120 is electrically connected with the shared word line 204.

[0175] Optionally, in some embodiments of the present application, the step S104 removing part of the first sacrificial structure 1171 so that part of the first semiconductor structure 1172 is exposed includes: forming at least two third vias and at least one first trench penetrating the first flat structure 118; part of the first connecting electrode 120 is exposed in the first trench; etching the inner sidewall of the third via, removing the exposed part of the first sacrificial structure 1171, so that the outer peripheral wall of part of the first semiconductor structure 1172 is exposed, and a column of third vias arranged along the first direction are all in communication with the same first trench.

[0176] Optionally, the plurality of third vias penetrating the first flat structure 118 are formed based on a patterning process. Optionally, along the first direction, one third via is formed between any two adjacent first stacked structures 117, so that part of the sidewall of the adjacent two first stacked structures 117 is exposed in the third via.

[0177] Optionally, at the same time of forming the third via, the first trench penetrating the first flat structure 118 is formed based on the same patterning process, so that part of the sidewall of the first connecting electrode 120 is exposed in the first trench, and part of the sidewall of the first stacked structure 117 adjacent to the first connecting electrode 120 is exposed in the first trench.

[0178] Optionally, after forming the third via and the first trench based on the same patterning process, it further includes: laterally etching part of the first sacrificial structure 1171 of the first stacked structure 117 exposed in the third via, so that the outer peripheral wall of part of the first semiconductor structure 1172 in the first stacked structure 117 is exposed, as shown in Figure 25 so that a column of third vias arranged along the first direction are all in communication with the same first trench.

[0179] Optionally, as shown in Figure 25 part of the first sacrificial structure 1171 is reserved to avoid exposure of the capacitor 109, preventing the device formed subsequently from being short-circuited with the capacitor 109.

[0180] Optionally, in some embodiments of the present application, the surface exposed by the first semiconductor structure 1172 in step S105 is sequentially formed with the first dielectric structure 1211 and the first gate 1212, including: forming the first dielectric structure 1211 surrounding the outer wall of part of the first semiconductor structure 1172; forming the first gate 1212 and the second connecting electrode 122 filling the third via and the first trench based on a deposition process, so that the first gate 1212 surrounds the outer wall of the first dielectric structure 1211; the first gate 1212 of each first field effect transistor 121 in the same column is electrically connected through the second connecting electrode 122 and the first connecting electrode 120.

[0181] Optionally, based on a deposition process, the first dielectric structure 1211 surrounding the outer wall of part of the first semiconductor structure 1172 is formed; based on a deposition process, the first gate 1212 surrounding the outer wall of the first dielectric structure 1211 is formed, as shown in Figure 27 .

[0182] Optionally, while forming the first gate 1212, based on the same deposition process, the second connecting electrode 122 is formed in each third via and first trench, so that the third via and the first trench are filled with the second connecting electrode 122, as shown in Figure 26 .

[0183] Optionally, as shown in Figure 26 , along the first direction, one second connecting electrode 122 is arranged between any two adjacent first stacked structures 117, so that the first gates 1212 arranged in a column along the first direction are connected through the second connecting electrode 122, and the first gates 1212 in the same column are connected with the first connecting electrode through one second connecting electrode 122.

[0184] Optionally, in some embodiments of this application, forming a second electrode 1213 in step S106, such that the second electrode 1213 is connected to the first semiconductor structure 1172 to form a first field-effect transistor 121, includes: forming a second flat structure 123 covering the first flat structure 118 and the first stacked structure 117; forming at least two fourth vias 124 penetrating the second flat structure 123 and at least a portion of the first stacked structure 117, and at least one fifth via 125 penetrating the second flat structure 123; the fourth via 124 allows a portion of the first semiconductor structure 1172 to pass through. The body structure 1172 is exposed, and the fifth via 125 exposes part of the first connecting electrode 120; a second electrode 1213 is formed in the fourth via 124, a third connecting electrode 126 is formed in the fifth via 125, and a fourth connecting electrode 127 is formed to connect the second electrode 1213 of the first field-effect transistor 121 in the same row; the third connecting electrode 126 is connected to the first connecting electrode 120; the fourth connecting electrode 127 is disposed on the side of the second flat structure away from the substrate 100 and extends in a third direction; the third direction is parallel to the substrate 100 and intersects with the first direction.

[0185] Optionally, forming a second flat structure 123 covering the first flat structure 118 and the first stacked structure 117 includes: forming the second flat structure 123 based on a deposition process and a CMP process. Optionally, the material of the second flat structure 123 includes silicon oxide.

[0186] Optionally, forming at least two fourth vias 124 penetrating the second flat structure 123 and at least part of the first stacked structure 117, and at least one fifth via 125 penetrating the second flat structure 123, includes: processing the second flat structure 123 based on a patterning process to form at least two fourth vias 124 and at least one fifth via 125.

[0187] Optionally, such as Figure 28 As shown, six fourth vias 124 and two fifth vias 125 are formed.

[0188] Optionally, such as Figure 28 As shown, a portion of the first semiconductor structure 1172 of the first stacked structure 117 is exposed on the bottom wall forming the fourth via 124. Optionally, the peripheral wall of the fourth via 124 includes a portion of the first sacrificial structure 1171 of the first stacked structure 117, so that the subsequently formed second electrode 1213 is insulated from the first gate 1212.

[0189] Optionally, such as Figure 28 As shown, part of the first connecting electrode 120 is exposed on the bottom wall forming the fifth via 125.

[0190] Optionally, after forming the fourth via hole 124 and the fifth via hole 125, the method further comprises: based on a deposition process, depositing a conductive material in the fourth via hole 124, in the fifth via hole 125, and on a side of the second planar structure 123 away from the substrate 100 to form a conductive layer; and based on a patterning process, processing the conductive layer to form the second electrode 1213, the third connection electrode 126, and the fourth connection electrode 127, as shown in Figure 29 and Figure 30 .

[0191] Optionally, as shown in Figure 29 , the third connection electrode 126 is located in the fifth via hole 125, the third connection electrode 126 extends along the second direction, and one end of the third connection electrode 126 is connected to the first connection electrode 120.

[0192] Optionally, as shown in Figure 29 , the fourth connection electrode 127 extends along the third direction.

[0193] Optionally, in combination with Figure 29 and Figure 30 , the second electrode 1213 is located in the fourth via hole 124, the second electrode 1213 extends along the second direction, one end of the second electrode 1213 is connected to the first semiconductor structure 1172, and the other end is connected to the fourth connection electrode 127. Along the third direction, the second electrodes 1213 of the first field effect transistors 121 in the same row are connected to the same fourth connection electrode 127.

[0194] Optionally, as shown in Figure 30 , the first field effect transistor 121 comprises: a first dielectric structure 1211, a partial first semiconductor structure 1172 surrounded by the first dielectric structure 1211, a first gate 1212, a second electrode 1213, and a first electrode 119.

[0195] Based on the same inventive concept, some embodiments of the present application provide a memory, referring to Figure 29 and Figure 30 , the memory comprises: a substrate 100, and a storage structure 200 and a first field effect transistor 121 and a second field effect transistor 113 disposed on the same substrate 100; the storage structure 200 comprises at least one layer of storage array, word line 203 and bit line 201; the first field effect transistor 121 is disposed on a side of the storage structure 200 away from the substrate 100, and the second field effect transistor 113 is used to control the selection of the bit line; the first field effect transistor 121 is electrically connected to the word line 203 and the second field effect transistor 113, respectively.

[0196] By arranging the storage structure 200 and the first field effect transistor 121 on the same substrate 100, the manufacturing cost and difficulty of the three-dimensional stacked memory can be reduced, and the manufacturing efficiency and yield of the three-dimensional stacked memory can be improved; by electrically connecting the first field effect transistor with the word line and the second field effect transistor, the electrical function of the first field effect transistor can be realized, the operation of the word line can be effectively matched with the operation of the bit line, the circuit is simplified, and the working efficiency of the circuit is improved.

[0197] The first field effect transistor 121 includes a first gate 1212, a first electrode 119, and a second electrode 1213, and the first electrode 119 of the first field effect transistor 121 is connected with the word line 203; the second electrodes 1213 of a row of first field effect transistors 121 arranged along a third direction parallel to the substrate 100 are electrically connected with each other; the first gates 1212 of a column of first field effect transistors 121 arranged along a first direction are electrically connected with each other; the first direction and the third direction are both parallel to the substrate 100 and intersect with each other; the second electrodes 1213 of a row of first field effect transistors 121 are electrically connected with each other, and the first gates 1212 of a column of first field effect transistors 121 are electrically connected with each other, which can simplify the circuit connection relationship and save space.

[0198] Optionally, the first gate 1212 of the first field effect transistor 121 is electrically connected with the second gate 1132 of the second field effect transistor 113.

[0199] Optionally, in some embodiments of the present application, the bit line 201 extends along a first direction parallel to the substrate 100 and is electrically connected with a column of third field effect transistors 112 of the storage cells in the storage array at the same layer and arranged along the first direction; the word line 203 extends along a second direction perpendicular to the substrate 100 and is electrically connected with a group of third field effect transistors 112 of the storage cells arranged along the second direction.

[0200] In some embodiments of the present application, the memory includes a plurality of layers of storage arrays stacked along a second direction perpendicular to the substrate 100, and each layer of the storage array parallel to the substrate 100 includes a plurality of array-arranged storage cells, each of which includes a third field effect transistor 112 and a capacitor 109 arranged laterally, and the internal structure of the third field effect transistor 112 is arranged laterally and includes a channel region arranged laterally; the lateral direction is parallel to the direction of the substrate 100, for example, the third direction. The (vertical) stacking and (lateral) arrangement of the storage cells containing the lateral third field effect transistor in the embodiments of the present application can greatly improve the unit area density of the storage cells.

[0201] In some embodiments of the present application, the bit lines 201 are arranged laterally and the word lines 203 are arranged vertically, which can be adapted to the high-density arrangement of the stack of memory cells, and can improve the density of the memory cells. Specifically, the word lines 203 are electrically connected to the third gates 1122 of the third field effect transistors 112 of a group of memory cells stacked along the second direction, and the word lines are longitudinal connections in the memory for selecting a row of memory cells; the bit lines 201 are electrically connected to one source / drain of the third field effect transistors 112 of a column of memory cells arranged along the first direction in the same layer of the memory array, and the bit lines are lateral connections in the memory for reading or writing the state of the memory cells. The bit lines are selected by the input address, and intersect with a specific word line at the selected memory cell. The word lines 203 extend along the second direction perpendicular to the substrate 100, occupy a smaller area of the substrate 100, and from the perspective of the top view, the size of the word lines 203 along the third direction does not exceed (or is close to) the size of the third gates 1122 of the third field effect transistors 112 along the third direction, which can improve the density of the memory cells. Moreover, the extension direction of the bit lines 201 is orthogonal to the extension direction of the word lines 203, which can reduce the signal interference between the bit lines 201 and the word lines 203, and improve the stability and reliability of the signals.

[0202] Optionally, in some embodiments of the present application, the word lines 203 are electrically connected to the third gates 1122 of the third field effect transistors 112 of a group of memory cells stacked along the second direction; and the second electrodes 1213 of a row of first field effect transistors 121 arranged along the third direction parallel to the substrate 100 are electrically connected to each other through the fourth connection electrodes 127. The first gates 1212 of a column of first field effect transistors 121 arranged along the first direction are electrically connected to each other through the second connection electrodes 122.

[0203] By electrically connecting the second electrodes 1213 of a row of first field effect transistors 121 to each other and electrically connecting the first gates 1212 of a column of first field effect transistors 121 to each other, the circuit connection relationship can be simplified and the space can be saved.

[0204] Optionally, in some embodiments of the present application, the memory further comprises: at least two shared bit lines 202 stacked and insulated from each other, arranged on one side of the memory structure 200 along the first direction; at least two stacked second field effect transistors 113 and at least one shared word line 204 connected to the second field effect transistors 113.

[0205] Since the at least one shared word line 204 is connected to the at least two stacked second field effect transistors 113, the at least two stacked second field effect transistors 113 connected to the shared word line 204 can be controlled by controlling the shared word line 204.

[0206] Optionally, in some embodiments of the present application, along the first direction, the second field effect transistor 113 and the shared word line 204 are both arranged between the shared bit line 202 and the storage structure 200.

[0207] For example, as shown in FIG. 1, along the first direction, the bit line 201, the second field effect transistor 113 and the shared bit line 202 in the storage structure 200 are arranged in sequence; the bit line 201 is connected with the shared bit line 202 through the second semiconductor structure 1021 of the second field effect transistor 113. Figure 17 and Figure 19 As shown in FIG. 1, along the first direction, the bit line 201, the second field effect transistor 113 and the shared bit line 202 in the storage structure 200 are arranged in sequence; the bit line 201 is connected with the shared bit line 202 through the second semiconductor structure 1021 of the second field effect transistor 113. Along the second direction, the shared word line 204 needs to be electrically connected with the second gate 1132 of the second field effect transistor 113, so the shared word line 204 is arranged between the shared bit line 202 and the storage structure 200, which is actually to make the shared word line 204 and the second gate 1132 as close as possible in the perspective view, so that the orthogonal projection of the shared word line 204 on the substrate 100 at least partially overlaps with the orthogonal projection of the second gate 1132 on the substrate 100, which is beneficial to reduce or eliminate the exclusive area of the shared word line 204 and improve the density of the storage unit.

[0208] Optionally, the orthogonal projection of the shared word line 204 on the substrate 100 is located within the range of the orthogonal projection of the second gate 1132 on the substrate 100. Optionally, the orthogonal projection of the second gate 1132 on the substrate 100 is located within the range of the orthogonal projection of the shared word line 204 on the substrate 100. Optionally, the orthogonal projection of the shared word line 204 on the substrate 100 completely overlaps with the orthogonal projection of the second gate 1132 on the substrate 100.

[0209] Optionally, in some embodiments of the present application, the bit line 201 and the shared bit line 202 arranged in the same layer are electrically connected through the second field effect transistor 113 arranged in the same layer. In this way, part of the bit line 201 and part of the shared bit line 202 act as the source / drain of the second field effect transistor 113, that is, the electrical connection relationship between the bit line 201 and the shared bit line 202 arranged in the same layer can be realized through the second field effect transistor 113.

[0210] Based on the same inventive concept, some embodiments of the present application provide an electronic device, which comprises any of the memories provided in the above embodiments.

[0211] In some embodiments of the present application, the electronic device adopts any of the memories provided in the above embodiments, and the principle and technical effects thereof are described in the above embodiments and will not be described here.

[0212] Optionally, the electronic device comprises a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply.

[0213] It should be noted that the electronic device is not limited to the above-mentioned several kinds, and those skilled in the art can set any one of the memories provided in the above-mentioned various embodiments of the present application in different devices according to actual application requirements, so as to obtain the electronic device provided in some embodiments of the present application.

[0214] Those skilled in the art can understand that the electronic device provided in some embodiments of the present application can be specially designed and manufactured for the required purpose, or can also include known devices in a general-purpose computer. These devices have any one of the memories provided in the above-mentioned various embodiments.

[0215] According to some embodiments of the present application, at least the following beneficial effects can be achieved:

[0216] In the manufacturing method of the memory provided in some embodiments of the present application, after the storage structure is formed on one side of the substrate, the first field effect tube is directly formed on the side of the storage structure away from the substrate. Compared with the manufacturing method of the related three-dimensional stacked memory, by forming the storage structure and the first field effect tube on the same substrate, the manufacturing cost and difficulty of the memory can be reduced, which helps to improve the manufacturing efficiency and yield of the memory.

[0217] In the memory provided in some embodiments of the present application, by arranging the first field effect tube and the storage structure on the same substrate, the manufacturing cost and difficulty of the memory can be reduced, which helps to improve the manufacturing efficiency and yield of the memory; by electrically connecting the first field effect tube with the word line and the second field effect tube, the electrical function of the first field effect tube can be realized, the operation of the word line and the operation of the bit line can be effectively matched, the circuit is simplified, and the working efficiency of the circuit is improved.

[0218] Those skilled in the art can understand that the steps, measures and schemes in the various operations, methods and processes discussed in the present application can be alternated, changed, combined or deleted. Further, other steps, measures and schemes in the various operations, methods and processes discussed in the present application can also be alternated, changed, rearranged, decomposed, combined or deleted. Further, the steps, measures and schemes in the prior art with the various operations, methods and processes disclosed in the present application can also be alternated, changed, rearranged, decomposed, combined or deleted.

[0219] In the description of the present application, the directions or positional relationships indicated by the words "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are based on the exemplary directions or positional relationships shown in the drawings, and are for the purpose of facilitating the description or simplifying the description of the embodiments of the present application, and do not indicate or imply that the devices or components indicated thereby must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0220] The terms "first", "second", "third", etc. are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated thereby. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0221] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integral connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0222] In the description of the present application, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0223] The above only describes some embodiments of the present application. It should be noted that, for those skilled in the art, other similar implementation means based on the technical idea of the present application can be used without departing from the technical concept of the present application, and such implementation means also belong to the protection scope of some embodiments of the present application.

Claims

1. A method of manufacturing a memory, characterized by, Comprising: forming a memory structure on one side of a substrate; the memory structure comprising at least one memory array, word lines and bit lines; the memory array comprising at least one memory cell; forming at least one first stack structure on the side of the memory structure away from the substrate; the first stack structure comprising at least one first sacrificial structure and at least one first semiconductor structure stacked; forming a first electrode such that the first electrode is connected to the word lines and the first semiconductor structure; removing part of the first sacrificial structure such that part of the first semiconductor structure is exposed; forming a first dielectric structure and a first gate on the exposed surface of the first semiconductor structure in sequence; forming a second electrode such that the second electrode is connected to the first semiconductor structure, forming a first field effect transistor.

2. The method of claim 1, wherein forming at least one first stack structure comprises: forming a first planar structure covering the memory structure and at least two first stack structures embedded in the first planar structure, the first stack structure in the orthographic projection of the substrate at least partially overlaps with the orthographic projection of the corresponding memory cell in the substrate.

3. The method of claim 1, wherein The bit lines extend along a first direction parallel to the substrate and are connected to a column of memory cells arranged along the first direction in the same layer of the memory array; the word lines extend along a second direction perpendicular to the substrate and are connected to a group of memory cells stacked along the second direction.

4. The method of claim 2, wherein the step of forming the memory cell further comprises the step of: forming at least one first stack structure on the side of the memory structure away from the substrate comprises: ​ forming at least two first stack structures on the side of the memory structure away from the substrate; forming the first planar structure in the region of the memory structure not covered by the first stack structure such that the surface of the first planar structure away from the substrate is flush with the surface of the first stack structure away from the substrate.

5. The method of claim 4, wherein the step of forming the memory cell further comprises the step of: forming at least two first stack structures on the side of the memory structure away from the substrate comprises: ​ forming a first combined film layer on the side of the memory structure away from the substrate based on an epitaxial process; the first combined film layer comprises at least two first sacrificial layers and at least one first semiconductor layer, the first semiconductor layer is located between two adjacent first sacrificial layers; patterning the first combined film layer to form at least two first stack structures; the first stack structure comprises the first sacrificial structure formed after patterning the first sacrificial layer and the first semiconductor structure formed after patterning the first semiconductor layer.

6. The method of claim 2, wherein the step of forming the memory is performed by a process selected from the group consisting of: ion implantation, plasma doping, and plasma immersion ion implantation. forming a first electrode such that the first electrode is connected to the word lines and the first semiconductor structure comprises: forming a first via through the first stack structure and at least one second via through the first planar structure; the first via exposes at least part of the surface of the word lines away from the substrate, and the second via exposes the surface of the shared word lines of the memory structure extending along the second direction away from the substrate; the shared word lines are connected to a group of second field effect transistors stacked along the second direction, and the bit lines and shared bit lines arranged in the same layer are electrically connected through the second field effect transistors arranged in the same layer; the second direction is perpendicular to the substrate; forming the first electrode filling the first via and the first connection electrode filling the second via, such that the first connection electrode is connected with the shared word line.

7. The method of claim 6, wherein the step of forming the memory is performed by a process selected from the group consisting of: ion implantation, plasma doping, and plasma immersion ion implantation. removing part of the first sacrificial structure, such that part of the first semiconductor structure is exposed, comprising: forming at least two third vias penetrating the first planar structure and at least one first trench; part of the first connection electrode is exposed on the first trench; etching back the inner sidewall of the third via, removing part of the first sacrificial structure exposed, such that part of the outer peripheral wall of the first semiconductor structure is exposed, and such that each column of the third vias arranged along a first direction is in communication with the same first trench; the first direction is parallel to the substrate.

8. The method of claim 7, wherein the step of forming the memory is performed by a method comprising: forming a first dielectric structure and a first gate on the surface of the first semiconductor structure exposed in sequence, comprising: forming the first dielectric structure surrounding part of the outer peripheral wall of the first semiconductor structure; forming the first gate based on a deposition process and a second connection electrode filling the third via and the first trench, such that the first gate surrounds the outer peripheral wall of the first dielectric structure; the first gate of each of the first field effect transistors in the same column is electrically connected through the second connection electrode and the first connection electrode.

9. The method for manufacturing the memory according to claim 7, characterized in that, forming a second electrode, such that the second electrode is connected with the first semiconductor structure, forming a first field effect transistor, comprising: forming a second planar structure covering the first planar structure and the first stack structure; forming at least two fourth vias penetrating the second planar structure and at least part of the first stack structure, and at least one fifth via penetrating the second planar structure; the fourth via exposes part of the first semiconductor structure, and the fifth via exposes part of the first connection electrode; forming the second electrode located in the fourth via, a third connection electrode located in the fifth via, and a fourth connection electrode connecting the second electrodes of the first field effect transistors in the same row; the third connection electrode is connected with the first connection electrode; the fourth connection electrode is arranged on the side of the second planar structure away from the substrate and extends along a third direction; the third direction is parallel to the substrate and intersects the first direction.

10. The method of claim 9, wherein the step of forming the memory is performed by a method comprising: forming a storage structure on one side of the substrate, comprising: forming a second combined film layer on one side of the substrate based on an epitaxial process; the second combined film layer comprises a plurality of layers of alternately stacked second sacrificial layers and second semiconductor layers; patterning the second combined film layer to form at least two second stack structures, at least one third stack structure and at least one fourth stack structure; the second stack structure and the fourth stack structure both extend along a third direction, and the third stack structure extends along a first direction; along the third direction, both sides of the third stack structure are provided with a column of the second stack structures connected with the third stack structure; along the first direction, the fourth stack structure is connected with one end of the third stack structure; Forming at least two stacked storage units, word lines connected with the storage units and at least two stacked and mutually insulated bit lines based on the second and third stacked structures.

11. The method of claim 10, wherein the step of forming the memory is performed by a method comprising: Forming at least two stacked storage units, word lines connected with the storage units and at least two stacked and mutually insulated bit lines based on the second and third stacked structures, comprising: Forming at least two stacked capacitors based on the second stacked structure; Forming at least two spaced sub-stacked structures based on the third stacked structure, the sub-stacked structure comprising a bit line group, the bit line group comprising at least two stacked and mutually insulated bit lines; Forming a shared bit line group comprising at least two stacked and mutually insulated shared bit lines based on the fourth stacked structure; Forming a third field effect transistor and a word line connected with the third field effect transistor based on the second stacked structure in which the capacitors are formed; along the third direction, one end of the third field effect transistor is connected with the capacitor and the other end is connected with the bit line arranged in the same layer; Forming at least two stacked second field effect transistors and a shared word line connected with the second field effect transistors based on the sub-stacked structure.

12. A memory, comprising: Comprising: a substrate, and a storage structure, a first field effect transistor and a second field effect transistor arranged on the same substrate; the storage structure comprising at least one storage array, a word line and a bit line; one storage array comprising at least one storage unit; the first field effect transistor is arranged on the side of the storage structure away from the substrate, and the second field effect transistor is used for controlling the gating of the bit line; the first field effect transistor is electrically connected with the word line and the second field effect transistor respectively.

13. The memory of claim 12, wherein, the first field effect transistor comprises a first gate, a first electrode and a second electrode, and the first electrode of the first field effect transistor is connected with the word line.

14. The memory of claim 13, wherein, the first gate of the first field effect transistor is electrically connected with the second gate of the second field effect transistor.

15. The memory of claim 13, wherein, the bit line extends along a first direction parallel to the substrate and is connected with a column of third field effect transistors of the storage units arranged along the first direction in the storage array in the same layer; the word line extends along a second direction perpendicular to the substrate and is connected with a group of third field effect transistors of the storage units stacked along the second direction.

16. The memory of claim 15, wherein, Further comprising: at least two stacked and mutually insulated shared bit lines arranged on one side of the storage structure along the first direction; at least two stacked second field effect transistors and at least one shared word line connected with the second field effect transistors.

17. The memory of claim 16, wherein, along the first direction, the second field effect transistors and the shared word lines are both arranged between the shared bit lines and the storage structure.

18. The memory of claim 16, wherein, the bit line and the shared bit line arranged in the same layer are electrically connected through the second field effect transistor arranged in the same layer.

19. The memory of claim 16, wherein, the word line is electrically connected with the third gate of the third field effect transistor of the group of storage units stacked along the second direction.

20. The memory of claim 16, wherein, the second electrodes of the first field effect transistors arranged in a row along a third direction are electrically connected with each other through a fourth connecting electrode, and the third direction is parallel to the substrate and intersects the first direction.

21. The memory of claim 16, wherein, The first gate electrodes of a column of first field effect transistors arranged in the first direction are electrically connected to each other by second connection electrodes.

22. The memory of claim 21, wherein, The second connection electrodes are electrically connected to the shared word line via the first connection electrodes.

23. An electronic device, comprising: Comprising: The memory of any one of claims 12 to 22. The memory of any one of claims 12 to 22.

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