Electronic device

Abstract

An electronic device is provided. The electronic device comprises a substrate, a first insulating layer, a semiconductor oxide layer, a second insulating layer and a gate electrode. The first insulating layer is disposed on the substrate. The semiconductor oxide layer is disposed on the first insulating layer and has a first portion and a second portion adjacent to the first portion. The second insulating layer is disposed on the semiconductor oxide layer. The gate electrode is disposed on the substrate and overlaps the first portion of the semiconductor oxide layer. Wherein, in a spectrum measured by time-of-flight secondary ion mass spectrometry, an H-concentration at a first interface between the second insulating layer and the first portion is greater than an H-concentration at a central portion of the first portion.

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly to an improved electronic device. Background Art

[0002] Electronic products including chips, such as displays, smartphones, tablet computers, laptop computers, and televisions, have become indispensable necessities in modern society. With the booming development of such electronic products, consumers have high expectations for the quality, functions, or prices of these electronic products.

[0003] Electronic products often include transistors to perform operations. However, since doping is required in the process of manufacturing transistors, unnecessary diffusion of dopants may occur, reducing the stability of the transistors. Therefore, these electronic products do not meet consumers' expectations in all aspects, and there are still some problems with electronic products. Developing improved electronic devices remains one of the current goals. Summary of the Invention

[0004] In some embodiments, an electronic device is provided. The electronic device includes a substrate, a first insulating layer, an oxide semiconductor layer, a second insulating layer, and a gate electrode. The first insulating layer is disposed on the substrate. The oxide semiconductor layer is disposed on the first insulating layer and has a first portion and a second portion adjacent to the first portion. The second insulating layer is disposed on the oxide semiconductor layer. The gate electrode is disposed on the substrate and overlaps with the first portion of the oxide semiconductor layer. Wherein, in the spectrum measured by time-of-flight secondary ion mass spectrometry (TOF-SIMS), the H - concentration at a first interface between the second insulating layer and the first portion is greater than the H - concentration at a central portion of the first portion.

[0005] The electronic devices of the present disclosure can be applied to various types of electronic devices. To make the features and advantages of the present disclosure more obvious and understandable, various embodiments are specifically described below in conjunction with the accompanying drawings as follows. Brief Description of the Drawings

[0006] Through the following detailed description in conjunction with the accompanying drawings, we can better understand the viewpoints of the embodiments of the present disclosure. It should be noted that, according to industrial standard practices, some features may not be drawn to scale. In fact, for the sake of clear discussion, the sizes of different components may be increased or decreased.

[0007] Figure 1 A cross-sectional schematic diagram showing an electronic device according to some embodiments of the present disclosure.

[0008] Figures 2 to 8Element analysis schematic diagrams of an electronic device according to some embodiments of the present disclosure are shown separately.

[0009]

Symbol Explanation

[0010] 1: Electronic device

[0011] 100: Substrate

[0012] 110, 112: First conductive layer

[0013] 120, 140, 160, 340, 420, 440: Dielectric layer

[0014] 150: Semiconductor layer

[0015] 200: Third insulating layer

[0016] 300: First insulating layer

[0017] 300B, 320B, 334B: Lower part

[0018] 300T, 320T, 334T: Upper part

[0019] 310: Semiconductor oxide layer

[0020] 310a: First part

[0021] 310b: Second part

[0022] 312: Central part

[0023] 320: Second insulating layer

[0024] 330, 332: Second conductive layer

[0025] 334: Gate electrode

[0026] 334C: Middle part

[0027] 400: Fourth insulating layer

[0028] 430, 450: Third conductive layer

[0029] AA: Active region

[0030] D1: First direction

[0031] D2: Second direction

[0032] DIF1: First difference

[0033] DIF2: Second difference

[0034] I-I’: Cross-section

[0035] P1: First position

[0036] P2: Second position

[0037] PA: Peripheral area

[0038] S1: First interface

[0039] S2: Second interface

[0040] T300: First thickness

[0041] T320: Second thickness

[0042] TA, TP: Transistor Detailed implementation manners

[0043] The following provides a detailed description of the electronic devices in the embodiments of the present disclosure. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific components and arrangements described below are only for simply and clearly describing some embodiments of the present disclosure. Of course, these are only for illustration and not for limiting the present disclosure. In addition, similar and / or corresponding component symbols may be used in different embodiments to indicate similar and / or corresponding components to clearly describe the present disclosure. However, the use of these similar and / or corresponding component symbols is only for simply and clearly describing some embodiments of the present disclosure, and does not represent any association between the different embodiments and / or structures discussed.

[0044] It should be understood that in each embodiment, relative terms may be used, for example, "lower" or "bottom" or "higher" or "top", to describe the relative relationship of one component of the drawing to another component. It can be understood that if the device in the drawing is flipped upside down, the component described on the "lower" side will become the component on the "higher" side. The embodiments of the present disclosure can be combined with the attached Figure 1 And it is understood that the drawings of the present disclosure are also regarded as a part of the public description.

[0045] Furthermore, when it is mentioned that a first material layer is on or over a second material layer, it may include the case where the first material layer is in direct contact with the second material layer, or there may be no direct contact between the first material layer and the second material layer, that is, there may be one or more other material layers between the first material layer and the second material layer. However, when the first material layer is directly on the second material layer, it means the case where the first material layer is in direct contact with the second material layer.

[0046] In addition, it should be understood that the ordinal numbers used in the specification and the claims, such as "first", "second", etc., are used to modify components, and they do not themselves intend to imply or represent that the component (or these components) has any previous ordinal number, nor do they represent the order of one component and another component, or the order in the manufacturing method. The use of these ordinal numbers is only to clearly distinguish a component with a certain name from another component with the same name. The claims and the specification may not use the same terms. For example, the first component in the specification may be the second component in the claims.

[0047] In some embodiments of the present disclosure, terms related to joining and connecting, such as "connect", "interconnect", "bond", etc., unless otherwise defined, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact, and other structures are disposed between these two structures. And these terms related to connection and joining may also include the cases where both structures are movable, or both structures are fixed. In addition, the term "electrically connected" or "electrically coupled" includes any direct and indirect means of electrical connection.

[0048] In the text, terms such as "approximate", "about", "substantially" generally mean within 10%, or 5%, or 3%, or 2%, or 1%, or 0.5% of a given value or range. The given quantity is an approximate quantity, that is, the meanings of "approximate", "about", "substantially" may still be implied even without specific mention of "approximate", "about", "substantially". The phrase "in the range from the first numerical value to the second numerical value" or "the first numerical value ~ the second numerical value" means that the range includes the first numerical value, the second numerical value, and other numerical values therebetween. Furthermore, there may be a certain error between any two numerical values or directions for comparison. If the first numerical value is equal to the second numerical value, it implies that there may be an error of about 10%, or 5%, or 3%, or 2%, or 1%, or 0.5% between the first numerical value and the second numerical value. If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees. If the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0049] Throughout the specification and claims of this disclosure, certain terms are used to refer to specific components. Those skilled in the art should understand that electronic device manufacturers may use different names to refer to the same component. This document does not intend to distinguish between components that have the same function but different names. In the following specification and claims, words such as "comprise", "include", "have", etc. are open-ended terms, and thus should be interpreted as meaning "including but not limited to...". Therefore, when the terms "comprise", "include", and / or "have" are used in the description of this disclosure, they specify the existence of the corresponding components, regions, steps, operations, and / or assemblies, but do not exclude the existence of one or more corresponding components, regions, steps, operations, and / or assemblies.

[0050] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art. It is understood that these terms, such as those defined in a commonly used dictionary, should be interpreted as having a meaning consistent with the relevant technology and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0051] In this disclosure, each direction is not limited to the three axes of a rectangular coordinate system such as the X-axis, Y-axis, and Z-axis, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of description, hereinafter, the X-axis direction is the first direction D1, and the Z-axis direction is the second direction D2. In some embodiments, the cross-sectional schematic diagram described herein is a cross-sectional schematic diagram of the XZ plane. In some embodiments, the normal direction of the substrate may be the second direction D2.

[0052] It should be understood that according to the embodiments of this disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an ellipsometer, or other suitable means can be used to measure the relative setting relationship, depth, thickness, width, or height of each component, or the spacing or distance between components. According to some embodiments, a scanning electron microscope can be used to obtain a cross-sectional structure image of the components to be measured, and measure the depth, thickness, width, or height of each component, or the spacing or distance between components.

[0053] It should be understood that, according to some embodiments of the present disclosure, a time of flight secondary ion mass spectrometer (TOF-SIMS) or other suitable mass spectrometry method can be used to quantitatively analyze and / or qualitatively analyze the elements in each component. According to some embodiments, a sample including the component to be measured can be obtained from the electronic device and the elements in the sample can be analyzed. In some embodiments, TOF-SIMS in negative ion mode, TOF-SIMS in positive ion mode, or a combination thereof can be used to analyze the sample. In some embodiments, the concentration of the sample that can be obtained depends on the accuracy of the analysis method used, and different analysis methods may have different minimum analyzable values. When the concentration of an element in the sample is less than the minimum analyzable value, only the presence or absence of the element can be qualitatively analyzed, and the relative content relationship between the element and other elements can be described, but the concentration of the element cannot be quantitatively analyzed. In other words, the sample may substantially not include the element, that is, the concentration of the element is substantially equal to 0, or the sample may substantially include the element, that is, the concentration of the element is substantially greater than 0, but the concentration of the element is lower than the minimum analyzable value.

[0054] It should be understood that hereinafter, the unit of concentration "atoms / c.c." represents the number of atoms included in each cubic centimeter. Hereinafter, when it is described that "the concentration of an element in the first component (or in the first part, or at the first interface) is greater than the concentration of the said element in the second component (or in the second part, or at the second interface)", it means that the concentration of the said element measured at any arbitrary point in the first component (or in the first part, or at the first interface) is greater than the concentration of the said element measured at any arbitrary point in the second component (or in the second part, or at the second interface). For example, the concentration of the said element at the mid-thickness of the first component is greater than the concentration of the said element at the mid-thickness of the second component. For example, the maximum value of the concentration of the said element in the first component is greater than the maximum value of the concentration of the said element in the second component, but the present disclosure is not limited thereto. For example, the concentration of the said element measured at a first point in the first component is greater than the concentration of the said element measured at a second point in the second component, and the concentration of the said element measured at a third point different from the first point in the first component may be less than or equal to the concentration of the said element measured at the second point in the second component. In addition, when it is described that "the concentration of an element in the first component is greater than the concentration of the said element in the second component", it includes the case where the second component substantially does not include the said element, in other words, it includes the case where the concentration of the said element in the first component is greater than the concentration of the said element in the second component and the concentration of the said element in the second component is substantially 0.

[0055] In the present disclosure, the electronic device may include a display module, a backlight module, an antenna module, a sensing module or a splicing module, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display module may be a non-self-luminous display module or a self-luminous display module. The antenna module may be a liquid crystal type antenna module or a non-liquid crystal type antenna module. The sensing module may be a sensing module for sensing capacitance, light, heat or ultrasonic waves, but is not limited thereto. The electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diodes may include light-emitting diodes or photodiodes. The light-emitting diodes may include, for example, organic light emitting diodes (OLEDs), mini light-emitting diodes (mini LEDs), micro light-emitting diodes (micro LEDs) or quantum dot light-emitting diodes (quantum dot LEDs), but are not limited thereto. The splicing module may be, for example, a display splicing module or an antenna splicing module, but is not limited thereto.

[0056] In addition, the outer shape of the electronic device can be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device can have peripheral systems such as a processing system, a driving system, a control system, a light source system, a shelf system, etc. to support the display module or the splicing module.

[0057] It should be understood that, for the sake of clarity, some components of the electronic device may be omitted in the drawings, and only some components are schematically shown. In some embodiments, additional components may be added to the electronic device described below. In other embodiments, some components of the electronic device described below may be replaced or omitted.

[0058] Referring to Figure 1 , which shows a cross-sectional schematic diagram of the electronic device 1 according to some embodiments of the present disclosure. In some embodiments, as Figure 1 shown, the electronic device 1 may include an active region AA and a peripheral region PA adjacent to the active region AA. In some embodiments, the active region AA may include a transistor TA, and the peripheral region PA may include a transistor TP. In some embodiments, the electronic device 1 may include a substrate 100, a first insulating layer 300, a semiconductor oxide layer 310, a second insulating layer 320, and a gate electrode 334. In some embodiments, the first insulating layer 300 may be disposed on the substrate 100, the semiconductor oxide layer 310 may be disposed on the first insulating layer 300, and the second insulating layer 320 may be disposed on the semiconductor oxide layer 310. In some embodiments, the gate electrode 334 may be disposed on the substrate 100. In some embodiments, the gate electrode 334 may be disposed on the second insulating layer 320 to make the electronic device 1 include a top gate transistor TA. In other embodiments, the gate electrode 334 may be disposed between the substrate 100 and the first insulating layer 300 to make the electronic device 1 include a bottom gate transistor TA.

[0059] Hereinafter, the electronic device 1 will be described in detail.

[0060] In some embodiments, as Figure 1 shown, the substrate 100 is provided. In some embodiments, the substrate 100 may include glass, quartz, sapphire, ceramic, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polypropylene (PP), other suitable materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the substrate 100 may include a light-transmissive substrate, a semi-light-transmissive substrate, or an opaque substrate.

[0061] In some embodiments, asFigure 1 As shown, a first conductive layer 110 and a first conductive layer 112 can be formed on a substrate 100. In some embodiments, the first conductive layer 110 can be disposed in a peripheral region PA, and the first conductive layer 112 can be disposed in the peripheral region PA and an active region AA. In some embodiments, the first conductive layer 110 and the first conductive layer 112 can be formed in the same track or different track processes. In some embodiments, the first conductive layer 110 and the first conductive layer 112 can be a zero-th metal layer (M0 layer).

[0062] In some embodiments, the first conductive layer 110 and the first conductive layer 112 can include a conductive material. In some embodiments, the conductive material can include a metal, a metal nitride, a semiconductor material, other suitable conductive materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the conductive material can include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), silver (Ag), magnesium (Mg), their alloys, their compounds, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the conductive material can include a transparent conductive oxide (TCO). For example, the transparent conductive oxide can include indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), antimony tin oxide (ATO), other suitable transparent conductive materials, or a combination thereof, but the present disclosure is not limited thereto.

[0063] In some embodiments, the first conductive layer 110 and the first conductive layer 112 can be formed by a deposition process, an etching process, a patterning process, other suitable processes, or a combination thereof. For example, the deposition process can include a chemical vapor deposition (CVD) process, a sputtering process, an evaporation process, a physical vapor deposition (PVD) process, other suitable deposition processes, or a combination thereof, but the present disclosure is not limited thereto. For example, the etching process can include a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof, but the present disclosure is not limited thereto.

[0064] In some embodiments, as Figure 1 shown, a dielectric layer 120 can be formed on the substrate 100, the first conductive layer 110, and the first conductive layer 112. In some embodiments, the dielectric layer 120 can include an oxide such as silicon oxide, a nitride such as silicon nitride, a oxynitride such as silicon oxynitride, other suitable buffer materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the dielectric layer 120 can be formed by the aforementioned deposition process or other suitable processes. For example, the dielectric layer 120 can include silicon nitride. In some embodiments, as Figure 1 shown, a dielectric layer 140 can be formed on the dielectric layer 120. In some embodiments, the material and formation method of the dielectric layer 140 can be the same as or different from those of the dielectric layer 120. For example, the dielectric layer 140 can include silicon oxide.

[0065] In some embodiments, as Figure 1 shown, a semiconductor layer 150 can be formed on the dielectric layer 140 and in the peripheral region PA. In some embodiments, the semiconductor layer 150 can include amorphous silicon (a-Si), low temperature polysilicon (LTPS), indium gallium zinc oxide (IGZO), metal oxide, other suitable semiconductor materials, or a combination thereof, but the present disclosure is not limited thereto. For example, the semiconductor layer 150 can include low temperature polysilicon (LTPS). In some embodiments, as Figure 1 shown, a dielectric layer 160 can be formed on the dielectric layer 140 and the semiconductor layer 150. In some embodiments, the material and formation method of the dielectric layer 160 can be the same as or different from those of the dielectric layer 120. For example, the dielectric layer 160 can include silicon oxide.

[0066] In some embodiments, as Figure 1As shown, a third insulating layer 200 can be formed on the dielectric layer 160. In some embodiments, the material and formation method of the third insulating layer 200 can be the same as or different from those of the dielectric layer 120. For example, the third insulating layer 200 can include silicon nitride. In some embodiments, the third insulating layer 200 can serve as a barrier layer for water vapor.

[0067] In some embodiments, as Figure 1 shown, a first insulating layer 300 can be formed on the third insulating layer 200. In some embodiments, the material and formation method of the first insulating layer 300 can be the same as or different from those of the dielectric layer 120. For example, the first insulating layer 300 can include silicon oxide. In some embodiments, the first insulating layer 300 can serve as a bottom insulating layer for the transistor TA in the active region AA. In some embodiments, in the normal direction of the substrate 100, the first insulating layer 300 can have a first thickness T300. In some embodiments, the first thickness T300 can be greater than or equal to and less than or equal to For example, the first thickness T300 can be or any value between the foregoing values or a numerical range composed of any values, but the present disclosure is not limited thereto.

[0068] In some embodiments, as Figure 1 shown, a semiconductor oxide layer 310 can be formed on the first insulating layer 300. In some embodiments, the semiconductor oxide layer 310 can include ITO, IGO, AZO, SnO, ZnO, IZO, IGZO, ITZO, ATO, other suitable semiconductor oxide materials, or a combination thereof, but the present disclosure is not limited thereto. For example, the semiconductor oxide layer 310 can include IGZO.

[0069] In some embodiments, as Figure 1As shown, the semiconductor oxide layer 310 may have a first portion 310a and a second portion 310b adjacent to the first portion 310a. In some embodiments, along the first direction D1, the first portion 310a may be disposed between the second portions 310b. In some embodiments, along the normal direction (second direction D2) of the substrate 100, the first portion 310a of the semiconductor oxide layer 310 may correspond to a subsequently formed gate electrode. In some embodiments, the projection range of the subsequently formed gate electrode on the semiconductor oxide layer 310 is the range of the first portion 310a. In other words, a portion of the semiconductor oxide layer 310 on which the gate electrode is disposed may be referred to as the first portion 310a, and the remaining portion of the semiconductor oxide layer 310 on which the gate electrode is not disposed may be referred to as the second portion 310b. In some embodiments, the first portion 310a of the semiconductor oxide layer 310 may serve as the channel region of the transistor TA in the active region AA, and the second portion 310b of the semiconductor oxide layer 310 may serve as the conductive region of the transistor TA. In some embodiments, the second portion 310b may be a doped region, such as an N-type heavily doped region (N + region) doped with an N-type dopant to electrically connect the semiconductor oxide layer 310 to other components, but the present disclosure is not limited thereto.

[0070] In some embodiments, as Figure 1 shown, a second insulating layer 320 may be formed on the first insulating layer 300 and the semiconductor oxide layer 310. In some embodiments, the material and formation method of the second insulating layer 320 may be the same as or different from those of the dielectric layer 120. For example, the second insulating layer 320 may include silicon oxide. In some embodiments, the second insulating layer 320 may serve as a gate insulating layer. In some embodiments, in the normal direction of the substrate 100, the second insulating layer 320 may have a second thickness T320. In some embodiments, the second thickness T320 may be greater than or equal to and less than or equal to For example, the second thickness T320 may be or any value between the foregoing values or a value range composed of any values, but the present disclosure is not limited thereto.

[0071] In some embodiments, the second thickness T320 of the second insulating layer 320 may be less than the first thickness T300 of the first insulating layer 300. In some embodiments, the ratio of the second thickness T320 to the first thickness T300 (second thickness T320 / first thickness T300) may be greater than or equal to 0.3 and less than or equal to 0.7. For example, the ratio of the second thickness T320 to the first thickness T300 may be 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, or any value between the foregoing values or any numerical range composed of any values, but the present disclosure is not limited thereto. For example, the ratio of the second thickness T320 to the first thickness T300 may be in the range of 0.3 to 0.7, in the range of 0.3 to 0.6, in the range of 0.4 to 0.5, or any numerical range composed of any values between the foregoing values, but the present disclosure is not limited thereto.

[0072] In some embodiments, as Figure 1 shown, a second conductive layer 330, a second conductive layer 332, and a gate electrode 334 may be formed on the second insulating layer 320. In some embodiments, the second conductive layer 330 and the second conductive layer 332 may be disposed in the peripheral region PA, and the gate electrode 334 may be disposed in the active region AA. In some embodiments, in the normal direction of the substrate 100, the gate electrode 334 may overlap with a first portion 310a of the semiconductor oxide layer 310, and the gate electrode 334 does not overlap with a second portion 310b of the semiconductor oxide layer 310. In some embodiments, the second conductive layer 330, the second conductive layer 332, and the gate electrode 334 may include the foregoing conductive materials. In some embodiments, the second conductive layer 330, the second conductive layer 332, and the gate electrode 334 may be formed in the same track or different track processes. In some embodiments, the second conductive layer 330, the second conductive layer 332, and the gate electrode 334 may be a first metal layer (M1 layer). In some embodiments, the second conductive layer 330 may serve as a source electrode of the transistor TP in the peripheral region PA, and the second conductive layer 332 may serve as a drain electrode of the transistor TP in the peripheral region PA. In some embodiments, the gate electrode 334 may be a gate electrode of the transistor TA in the active region AA.

[0073] In some embodiments, as Figure 1 shown, a dielectric layer 340 may be formed on the second insulating layer 320, the second conductive layer 330, the second conductive layer 332, and the gate electrode 334. In some embodiments, the material and formation method of the dielectric layer 340 may be the same as or different from those of the dielectric layer 120. For example, the dielectric layer 340 may include silicon oxide. In some embodiments, as Figure 1As shown, a fourth insulating layer 400 can be formed on the dielectric layer 340. In some embodiments, the material and formation method of the fourth insulating layer 400 can be the same as or different from those of the third insulating layer 200. For example, the fourth insulating layer 400 can include silicon nitride. In some embodiments, the fourth insulating layer 400 can serve as a barrier layer for water vapor.

[0074] In some embodiments, as Figure 1 shown, a dielectric layer 420 can be formed on the fourth insulating layer 400. In some embodiments, the material and formation method of the dielectric layer 420 can be the same as or different from those of the dielectric layer 120. For example, the dielectric layer 420 can include silicon oxide. In some embodiments, as Figure 1 shown, a third conductive layer 430 can be formed on the dielectric layer 420. In some embodiments, the material and formation method of the third conductive layer 430 can be the same as or different from those of the first conductive layer 110. In some embodiments, the third conductive layer 430 can serve as the source electrode of the transistor TA in the active region AA. In some embodiments, as Figure 1 shown, a dielectric layer 440 can be formed on the dielectric layer 420 and the third conductive layer 430. In some embodiments, the material and formation method of the dielectric layer 440 can be the same as or different from those of the dielectric layer 120. For example, the dielectric layer 440 can include silicon oxide. In some embodiments, as Figure 1 shown, a third conductive layer 450 can be formed on the dielectric layer 440. In some embodiments, the material and formation method of the third conductive layer 450 can be the same as or different from those of the first conductive layer 110. For example, the third conductive layer 450 can include ITO. In some other embodiments, the third conductive layer 450 can be disposed on the same layer as the third conductive layer 430. For example, the third conductive layer 450 and the third conductive layer 430 can be disposed on the dielectric layer 420. In some embodiments, the third conductive layer 450 can serve as the drain electrode of the transistor TA in the active region AA. In some embodiments, the third conductive layer 430 and the third conductive layer 450 can be the second metal layer (M2 layer).

[0075] In some embodiments, the oxygen (O) concentration in the aforementioned layer including silicon oxide (e.g., the first insulating layer 300, the second insulating layer 320) may be 6E+21 to 9E+21 atoms per cubic centimeter (atoms / c.c.). For example, the oxygen (O) concentration in the layer including silicon oxide may be 6E+21, 7E+21, 8E+21, 9E+21, or any value or range of values between the aforementioned values, but the present disclosure is not limited thereto. In some embodiments, the O concentration in the aforementioned layer including silicon nitride (e.g., the third insulating layer 200, the fourth insulating layer 400) may be 6E+20 to 8E+20 atoms per cubic centimeter (atoms / c.c.). For example, the oxygen (O) concentration in the layer including silicon nitride may be 6E+20, 7E+20, 8E+20, or any value or range of values between the aforementioned values, but the present disclosure is not limited thereto. In some embodiments, the ratio of the O concentration in the layer of silicon oxide to the O concentration in the layer of silicon nitride (O concentration in the layer of silicon oxide / O concentration in the layer of silicon nitride) may be 7 to 15. For example, the ratio of the O concentration in the layer of silicon oxide to the O concentration in the layer of silicon nitride may be 7, 8, 9, 10, 11, 12, 13, 14, 15, or any value or range of values between the aforementioned values, but the present disclosure is not limited thereto. Accordingly, since water vapor is not easily diffused from the low O concentration layer to the high O concentration layer, the third insulating layer 200 and the fourth insulating layer 400 can serve as a water vapor barrier layer to protect the semiconductor oxide layer 310 disposed between the third insulating layer 200 and the fourth insulating layer 400 from being damaged by water vapor. Furthermore, since the density of the silicon nitride layer is higher than that of the silicon oxide layer, the third insulating layer 200 and the fourth insulating layer 400 can physically isolate water vapor to protect the semiconductor oxide layer 310 from being damaged by water vapor.

[0076] Hereinafter, taking the electronic device 1 as an example, the results of elemental analysis are described, but the present disclosure is not limited thereto. For the sake of convenience of description, different components are respectively marked in the following Figures 2 to 8 However, the following Figures 2 to 8 substantially represents the same analysis result.

[0077] Referring to Figures 2 to 8 , which respectively show schematic diagrams of elemental analysis of the electronic device 1 according to some embodiments of the present disclosure. Among them, Figures 2 to 8 respectively represent along as Figure 1Schematic diagram of elemental analysis for TOF-SIMS analysis in negative ion mode on the cross-section I-I' of the electronic device 1 shown. Among them, the minimum analyzable value of the concentration for TOF-SIMS analysis in negative ion mode is in the range of 1.0E+19 atoms per cubic centimeter (atoms / c.c.) to 1.0E+20 atoms per cubic centimeter. Among them, the concentration of hydrogen (H - ) ions refers to the vertical axis coordinate on the left (concentration (atoms / c.c.)), and its concentration is the concentration after quantitative analysis. And O - , Si - , SiN-, ZnO - , GaO - and InO - contents refer to the vertical axis coordinate on the right (intensity (counts)), and the intensity is the count after quantitative analysis. Among them, the horizontal axis coordinate represents the depth (μm) along the direction opposite to the second direction D2. For example, the horizontal axis coordinate represents the direction from the gate electrode 334 towards the third insulating layer 200. In some embodiments, the concentration of hydrogen (H-) ions in TOF-SIMS analysis in negative ion mode is equivalent to the concentration of hydrogen.

[0078] In some embodiments, as Figure 1 and Figure 2 shown, in the spectrum measured by TOF-SIMS, the H - concentration at the first interface S1 between the second insulating layer 320 and the first part 310a of the semiconductor oxide layer 310 is greater than the H - concentration at the central part 312 of the first part 310a of the semiconductor oxide layer 310. In some embodiments, the central part 312 of the first part 310a is defined as corresponding to Figure 2 shown InO - peak position of the intensity. That is, the central part 312 of the first part 310a may correspond to the maximum value of the intensity of InO-. In some embodiments, the first interface S1 may be defined as corresponding to Figure 2 shown InO - 80% of the peak of the intensity and the position where the depth is less than the central part 312. That is, the first interface S1 may correspond to 80% of the maximum value of the intensity of InO - , and the first interface S1 is farther from the substrate than the central part 312, but the present disclosure is not limited thereto.

[0079] In some embodiments, as Figure 1 and Figure 3As shown, in the spectrum measured by TOF-SIMS, the H⁻ concentration at the second interface S2 between the first insulating layer 300 and the first portion 310a of the semiconductor oxide layer 310 is greater than the H⁻ concentration at the central portion 312 of the first portion 310a of the semiconductor oxide layer 310. In some embodiments, the second interface S2 may be defined as corresponding to Figure 3 a position that is 80% of the peak intensity of InO⁻ as shown and has a depth greater than the central portion 312. For example, the second interface S2 may correspond to 80% of the maximum intensity of InO⁻, and the second interface S2 is closer to the substrate than the central portion 312, but the present disclosure is not limited thereto.

[0080] In some embodiments, as Figure 1 and Figure 4 shown, in the spectrum measured by TOF-SIMS, the H⁻ concentration at the first interface S1 is less than the H⁻ concentration at the second interface S2. Accordingly, since the channel region of the transistor TA in the active region AA is formed on the first interface S1, when the H⁻ concentration at the first interface S1 is low, it is possible to prevent the threshold voltage (threshold voltage, V th ) of the transistor TA from shifting towards a negative voltage.

[0081] In some embodiments, as Figure 1 and Figure 5 shown, in some embodiments, with the first thickness T300 of the first insulating layer 300 in the second direction D2, the first insulating layer 300 is divided into an upper portion 300T and a lower portion 300B, and the H⁻ concentration in the upper portion 300T may be less than the H⁻ concentration in the lower portion 300B. In some embodiments, in the spectrum measured by TOF-SIMS, the H⁻ concentration at the bottom surface of the first insulating layer 300 is greater than the H - concentration at the second interface S2 between the first insulating layer 300 and the first portion 310a of the semiconductor oxide layer 310. In some embodiments, the bottom surface of the first insulating layer 300 is defined as the position in the lower portion 300B of the first insulating layer 300 corresponding to the maximum slope of the H - concentration with respect to depth. That is, the bottom surface of the first insulating layer 300 is at the position of the maximum slope in the lower portion 300B of the first insulating layer 300 in the H - concentration curve.

[0082] Specifically, since the semiconductor oxide layer 310 is susceptible to the influence of the H - concentration in adjacent components, it is necessary to adjust the H -Concentration. When the H- concentration in the adjacent component is too high and diffuses into the semiconductor oxide layer 310, it will cause the conductivity of the first part 310a of the semiconductor oxide layer 310 to be too high, resulting in unnecessary conduction in the first part 310a of the semiconductor oxide layer 310, and deteriorating the transistor TA in the active region AA. Once unnecessary conduction occurs in the first part 310a of the semiconductor oxide layer 310 serving as the channel region, the switching of the transistor TA cannot be controlled by the gate electrode 334. Therefore, the present disclosure improves the electrical performance and / or stability of the transistor by controlling the H- concentration in each component. For example, after performing a reliability test under high temperature and high humidity conditions, unnecessary conduction will not occur. Accordingly, the present disclosure adjusts the H- - concentration in the first insulating layer 300 to prevent the H- in the upper part 300T of the first insulating layer 300 near the semiconductor oxide layer 310 from - diffusing into the semiconductor oxide layer 310.

[0083] Furthermore, since the H- in the lower part 300B of the first insulating layer 300 far from the semiconductor oxide layer 310 is not likely to affect the semiconductor oxide layer 310, the speed of initially forming the first insulating layer 300 can be increased, and the process time can be reduced. For example, when initially forming the first insulating layer 300, N2 can be used to catalyze the reaction of SiH4 and N2O to increase the speed of forming the first insulating layer 300. Then, N2 is removed (without using N2 catalysis) before the first insulating layer 300 is completed, and the reaction of SiH4 and N2O is used to reduce the H- concentration in the upper part 300T of the first insulating layer 300 near the semiconductor oxide layer 310.

[0084] In some embodiments, as Figure 1 and Figure 6 shown, in some embodiments, the second insulating layer 320 is divided into an upper part 320T and a lower part 320B by the second thickness T320 of the second insulating layer 320 in the second direction D2. The H- concentration in the upper part 320T can be greater than the H- concentration in the lower part 320B. In the spectrum measured by TOF-SIMS, the H- concentration at the top surface of the second insulating layer 320 is greater than the H- concentration at the first interface S1 between the second insulating layer 320 and the first part 310a of the semiconductor oxide layer 310. In some embodiments, the top surface of the second insulating layer 320 is defined as the position corresponding to the maximum slope of the H- - concentration with respect to the depth in the upper part 320T of the second insulating layer 320. That is, the top surface of the second insulating layer 320 is at the H- -The maximum value of the slope in the upper portion 320T of the second insulating layer 320 in the concentration curve is determined. - concentration, avoiding the H in the lower portion 320B of the second insulating layer 320 near the semiconductor oxide layer 310 - diffused into the semiconductor oxide layer 310 .

[0085] Furthermore, since the H concentration of the upper portion 320T of the second insulating layer 320 may be greater than the H concentration of the lower portion 320B of the second insulating layer 320, - concentration, the second insulating layer 320 can effectively passivate dangling bonds at the first interface S1 between the semiconductor oxide layer 310 and the second insulating layer 320 to avoid defects in the semiconductor oxide layer 310, thereby improving the electrical performance and / or stability of the transistor TA.

[0086] In some embodiments, Figure 1 and Figure 7 As shown, the slope of the H-concentration in the first insulating layer 300 may be smaller than the slope of the H-concentration in the second insulating layer 320. In some embodiments, in the spectrum measured by TOF-SIMS, the H-concentration at the first interface S1 is greater than the H-concentration above the first interface S1. The first difference DIF1 between the H-concentration at the first position P1 at the second interface S2 and the H-concentration below the second interface S2 may be greater than the H-concentration at the second interface S2. The first difference DIF1 is greater than the second difference DIF2. The H- in the first insulating layer 300 and the second insulating layer 320 near the semiconductor oxide layer 310 are prevented from diffusing into the semiconductor oxide layer 310, and the dangling bonds are effectively passivated.

[0087] In some embodiments, Figure 1 and Figure 8As shown, in the spectrum measured by TOF - SIMS, the first insulating layer 300 has an upper portion 300T and a lower portion 300B, and the intensity of SiN⁻ at the lower portion 300B is greater than the intensity of SiN⁻ at the upper portion 300T. In some embodiments, taking the two interfaces defined by the aforementioned bottom surface of the first insulating layer 300 and the second interface S2 as the upper interface and the lower interface of the first insulating layer 300, and with the first thickness T300 of the first insulating layer 300 in the second direction D2, the first insulating layer 300 is divided into the upper portion 300T and the lower portion 300B. In some embodiments, the SiN⁻ at the lower portion 300B may come from SiN generated by using N2 catalysis when initially forming the first insulating layer 300. - bond. Accordingly, the speed of forming the first insulating layer 300 can be increased.

[0088] In some embodiments, such as Figure 1 and Figure 8 shown, in some embodiments, in the spectrum measured by TOF - SIMS, the gate electrode 334 may have an upper portion 334T, a lower portion 334B, and an intermediate portion 334C disposed between the upper portion 334T and the lower portion 334B. In some embodiments, with the thickness of the gate electrode 334 in the second direction D2, the gate electrode 334 is divided into the upper portion 334T, the intermediate portion 334C, and the lower portion 334B. In some embodiments, the H⁻ concentration at the lower portion 334B is greater than the H - concentration at the intermediate portion 334C. In some embodiments, the H⁻ concentration at the upper portion 334T is greater than the H⁻ concentration at the intermediate portion 334C. In some embodiments, the H - concentration at the lower portion 334B is greater than the H - concentration at the upper portion 334T.

[0089] In summary, according to some embodiments of the present disclosure, an electronic device is provided. The electronic device can adjust the parameters (such as material type, H - concentration, SiN - concentration) of components (such as the first insulating layer, the second insulating layer, the gate electrode, the third insulating layer, the fourth insulating layer) adjacent to the semiconductor oxide layer to improve the electrical performance and / or stability of the electronic device. For example, the first insulating layer and the second insulating layer of the present disclosure can prevent the deterioration of the semiconductor oxide layer in the transistor and / or prevent the threshold voltage from shifting towards a negative voltage. For example, the third insulating layer and the fourth insulating layer of the present disclosure can prevent the semiconductor oxide layer from deteriorating due to water vapor.

[0090] The features between the embodiments of the present disclosure can be arbitrarily combined and used as long as they do not violate the inventive spirit or conflict with each other. In addition, the protection scope of the present disclosure is not limited to the processes, machines, manufactures, compositions of matter, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand from the disclosed content of the present disclosure the processes, machines, manufactures, compositions of matter, devices, methods and steps developed currently or in the future. As long as they can implement substantially the same functions or achieve substantially the same results in the embodiments described herein, they can be used according to the present disclosure. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufactures, compositions of matter, devices, methods and steps. The protection scope of the present disclosure shall be determined by the scope defined by the claims. Any embodiment or claim of the present disclosure does not have to achieve all the purposes, advantages and / or features disclosed in the present disclosure.

[0091] The above outlines several embodiments so that those skilled in the art can better understand the viewpoints of the embodiments of the present disclosure. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without departing from the spirit and scope of the present disclosure.

Claims

1. An electronic device, characterized in that, Comprising: A substrate; A first insulating layer disposed on the substrate; A semiconductor oxide layer disposed on the first insulating layer and having a first portion and a second portion adjacent to the first portion; A second insulating layer disposed on the semiconductor oxide layer; and A gate electrode disposed on the substrate and overlapping with the first portion of the semiconductor oxide layer, Among them, in a spectrum measured by time-of-flight secondary ion mass spectrometry (TOF-SIMS), the concentration of H at a first interface between the second insulating layer and the first portion is greater than the concentration of H at a central portion of the first portion. - - ​​ 2. The electronic device according to claim 1, characterized in that, In this spectrum measured by TOF-SIMS, the H at a second interface between the first insulating layer and the first portion - has a higher concentration than the H - at the central portion of the first portion.

3. The electronic device according to claim 2, characterized in that, In this spectrum measured by TOF-SIMS, the H at the first interface - concentration is less than the H at the second interface - concentration.

4. The electronic device according to claim 2, characterized in that, In the spectrum measured by TOF-SIMS, the H at the bottom surface of the first insulating layer - has a higher concentration than the H at the second interface between the first insulating layer and the first portion - in concentration.

5. The electronic device according to claim 4, characterized in that, In this spectrum measured by TOF-SIMS, the H concentration at a top surface of the second insulating layer is greater than the H⁻ concentration at the first interface between the second insulating layer and the first portion. - ​ 6. The electronic device according to claim 2, characterized in that, In this spectrum measured by TOF-SIMS, the difference between the H⁻ concentration at the first interface and the H concentration at a first position above the first interface is greater than the difference between the H - concentration at the second interface and the H⁻ concentration at a second position below the second interface. - ​​ 7. The electronic device according to claim 2, characterized in that, In this spectrum measured by TOF-SIMS, the first insulating layer has an upper part and a lower part, and the intensity of SiN at the lower part - is greater than the intensity of SiN at the upper part - .

8. The electronic device according to claim 1, characterized in that, Further comprising a third insulating layer disposed under the first insulating layer, wherein the first insulating layer comprises silicon oxide and the third insulating layer comprises silicon nitride.

9. The electronic device according to claim 1, characterized in that, Further comprising a fourth insulating layer disposed on the second insulating layer, wherein the second insulating layer comprises silicon oxide and the fourth insulating layer comprises silicon nitride.

10. The electronic device according to claim 1, characterized in that, The first insulating layer has a first thickness, the second insulating layer has a second thickness, and the second thickness is less than the first thickness.

11. The electronic device according to claim 10, characterized in that, A ratio of the second thickness to the first thickness is in a range of 0.3 to 0.

7.

12. The electronic device according to claim 11, characterized in that, The ratio is in a range of 0.3 to 0.

6.

13. The electronic device according to claim 12, characterized in that, The ratio is in a range of 0.4 to 0.

5.

14. The electronic device according to claim 1, characterized in that, In the spectrum measured by TOF-SIMS, the gate electrode has an upper portion, a lower portion, and an intermediate portion disposed between the upper portion and the lower portion, and the H-concentration at the lower portion is greater than the H-concentration at the intermediate portion.

15. The electronic device according to claim 14, characterized in that, In this spectrum measured by TOF-SIMS, the H- concentration at the upper part is greater than the H - concentration at the middle part.

16. The electronic device according to claim 15, characterized in that, In this spectrum measured by TOF-SIMS, the H at the lower part - has a higher concentration than the H at the upper part - in terms of concentration.

17. The electronic device according to claim 1, characterized in that, The gate electrode is disposed on the second insulating layer.

18. The electronic device according to claim 1, wherein The gate electrode is disposed between the substrate and the first insulating layer.

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