Stacked field effect transistor and manufacturing method

Abstract

The embodiment of the invention provides a stacked field effect transistor and a manufacturing method, and the transistor comprises a fin-shaped structure which comprises a first-type active layer, a second-type isolation layer, a first-type isolation layer and a second-type active layer which are sequentially arranged in the stacking direction; the shallow trench isolation layer is filled at the periphery of the fin-shaped structure and corresponds to the first type of isolation layer and the second type of isolation layer; the first type active layer is used for forming a first field effect transistor, and the second type active layer is used for forming a second field effect transistor; the first gate structure layer is formed on the surface of the fin-shaped structure in the first field effect transistor; and the second gate structure layer is formed on the surface of the fin-shaped structure in the second field effect transistor. According to the stacked field effect transistor and the manufacturing method provided by the embodiment of the invention, the two field effect transistors have a relatively good isolation effect and are independently controlled, so that the stability of the stacked field effect transistor can be improved.

Description

Technical Field

[0001] This application relates to semiconductor technology, and particularly to a stacked field-effect transistor and a manufacturing method thereof. Background Art

[0002] Early integrated circuits mainly used planar manufacturing processes because they were relatively simple and cost-effective. As the circuit integration density increased, the size of transistors was required to be smaller and smaller, and their various dimensions were reduced to below the micron level or even the nanometer level. Taking metal-oxide-semiconductor (MOS) devices as an example, when their size is reduced, negative effects such as the threshold voltage decreasing with the reduction of the channel length, the drain-induced barrier lowering, carrier surface scattering, and velocity saturation will occur, and it is difficult to maintain the device performance at the same level as that of large-size devices.

[0003] To reduce the short-channel effect, the industry has adopted special device structures such as fin field-effect transistors (FinFETs) and gate-all-around field-effect transistors (GAAFETs), which can further improve the influence of the short-channel effect on the device. Both FinFETs and GAAFETs are three-dimensional transistor structures, and the three-dimensional transistor manufacturing technology was developed to overcome the problems encountered in the process of reducing the size of traditional planar devices. The FinFET is characterized by a "fin" - like structure, which is similar to a fish fin and has the advantages of better control ability, low leakage current, size scaling ability, and low-voltage operation. With the advancement of the process node, FinFET technology has been widely used at the 22-nanometer, 16-nanometer, and 14-nanometer nodes, and GAA technology has been introduced at the 5nm node, and subsequent technologies will introduce nano-sheet technology.

[0004] The patent document with the publication number CN117133719B proposes a method and structure for multi-layer stacked transistors. By stacking transistors, two or more layers of transistors are integrated in the vertical space to further improve the transistor integration density and continue the miniaturization of the integrated circuit size. After the first transistor is manufactured, the substrate is inverted and etched, and then the second transistor is manufactured on the etched substrate, that is, the back of the first transistor, to realize a stacked transistor structure with a simplified process and improve the integration of the device and the integrated circuit.

[0005] In the solution disclosed in this patent document, the process of the stacked transistor structure is complex and difficult to implement. During the manufacturing process of the first transistor, its source and drain are formed by etching the fin structure and then through epitaxial growth. After that, methods such as spike annealing or laser annealing are used to achieve the redistribution and activation of the in-doped source and drain diffusing into the channel. The typical spike annealing temperature for source and drain region diffusion is 1000 - 1100 °C. The reason for the in-doped source and drain diffusing into the channel is that there is a gate dielectric layer and an isolated low-k dielectric between the gate metal and the epitaxially grown source and drain, that is, there is a certain distance between the source and drain and the gate. It is necessary to use a thermal process to diffuse the dopants in the source and drain to both sides of the gate to ensure performance. After the source and drain of the first transistor are formed, a high-temperature millisecond annealing technology is required to form the metal and silicide structure. The typical high-temperature millisecond annealing temperature for forming silicide is 650 - 850 °C. After the metal and silicide process, high-temperature processes cannot be used, as it will damage the silicide and metal structure.

[0006] In the solution disclosed in this patent document, when inverting the first transistor to form the source and drain of the second transistor, spike annealing is also required to achieve source and drain diffusion and high-temperature millisecond annealing to form a good contact between silicide and metal to ensure the performance of the second transistor. However, the metal and silicide of the first transistor have already been formed, and the impurity diffusion of the source and drain of the first transistor into the channel has been completed. The source and drain annealing of the second transistor will severely affect the channel diffusion of the first transistor and the structure of silicide and metal. Therefore, the structure proposed in this patent document cannot be combined with the existing process, and there are problems of incompatibility and difficulty in implementation. Summary of the Invention

[0007] To solve one of the above technical defects, an embodiment of the present application provides a stacked field-effect transistor and a manufacturing method.

[0008] According to the first aspect of the embodiments of the present application, a stacked field-effect transistor is provided, including:

[0009] A fin structure, including a first-type active layer, a second-type isolation layer, a first-type isolation layer, and a second-type active layer arranged in sequence along the stacking direction; the first type and the second type are opposite conduction types;

[0010] A shallow trench isolation layer, extending along a plane perpendicular to the stacking direction, filled around the fin structure, and corresponding to the first-type isolation layer and the second-type isolation layer in position; the first-type active layer is used to form the first field-effect transistor, the second-type active layer is used to form the second field-effect transistor, and the first field-effect transistor and the second field-effect transistor are isolated by the second-type isolation layer, the first-type isolation layer, and the shallow trench isolation layer;

[0011] The first gate structure layer formed on the surface of the fin structure in the first field-effect transistor;

[0012] The second gate structure layer formed on the surface of the fin structure in the second field-effect transistor.

[0013] According to the second aspect of the embodiments of the present application, a manufacturing method of a stacked field-effect transistor is provided, including:

[0014] A second-type active layer, a first-type isolation layer, a second-type isolation layer, and a first-type active layer are sequentially formed on a substrate; the first type and the second type are opposite conductive types;

[0015] The second-type active layer, the first-type isolation layer, the second-type isolation layer, and the first-type active layer are etched to form a fin structure;

[0016] A shallow trench isolation layer is formed on the periphery of the first-type isolation layer and the second-type isolation layer;

[0017] A first gate structure layer is formed on the surface of the fin structure to obtain a first field-effect transistor on one side of the shallow trench isolation layer;

[0018] The first field-effect transistor is subjected to a wafer flipping process;

[0019] The substrate, a part of the second-type active layer adjacent to the substrate, and the shallow trench isolation layer are removed to the periphery of the first-type isolation layer;

[0020] A second gate structure layer is correspondingly formed on the surface of the fin structure on the other side of the shallow trench isolation layer to obtain a second field-effect transistor on the other side of the shallow trench isolation layer.

[0021] The technical solution provided by the embodiments of the present application adopts a fin structure, including a first-type active layer, a second-type isolation layer, a first-type isolation layer, and a second-type active layer sequentially arranged along the stacking direction; the first type and the second type are opposite conductive types; a shallow trench isolation layer, extending in a plane perpendicular to the stacking direction, filled in the periphery of the fin structure, and the position corresponding to the first-type isolation layer and the second-type isolation layer; the first-type active layer is used to form a first field-effect transistor, the second-type active layer is used to form a second field-effect transistor, and the first field-effect transistor and the second field-effect transistor are isolated by the second-type isolation layer, the first-type isolation layer, and the shallow trench isolation layer; the first gate structure layer formed on the surface of the fin structure in the first field-effect transistor; the second gate structure layer formed on the surface of the fin structure in the second field-effect transistor, which can enable the two field-effect transistors to have a good isolation effect, and the two are independently controlled, and can improve the stability of the stacked field-effect transistor. Description of the Drawings

[0022] The accompanying drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings:

[0023] Figure 1 is a top view of a stacked field-effect transistor provided by an embodiment of the present application;

[0024] Figure 2 is Figure 1 a cross-sectional view taken along the A-A direction in

[0025] Figure 3 is Figure 1 a cross-sectional view taken along the B-B direction in

[0026] Figure 4 is a flowchart of a manufacturing method of a stacked field-effect transistor provided by an embodiment of the present application;

[0027] Figure 5 is a top view of forming an active structure in the manufacturing method of a stacked field-effect transistor provided by an embodiment of the present application;

[0028] Figure 6 is Figure 5 a cross-sectional view taken along the C-C direction in

[0029] Figure 7 is a top view of etching the active structure in the manufacturing method of a stacked field-effect transistor provided by an embodiment of the present application;

[0030] Figure 8 is Figure 7 a cross-sectional view taken along the D-D direction in

[0031] Figure 9 is Figure 7 a cross-sectional view taken along the E-E direction in

[0032] Figure 10 is a top view of forming a shallow trench isolation layer in the manufacturing method of a stacked field-effect transistor provided by an embodiment of the present application;

[0033] Figure 11 is Figure 10 a cross-sectional view taken along the F-F direction in

[0034] Figure 12 is Figure 10 a cross-sectional view taken along the G-G direction in

[0035] Figure 13 is a top view of forming a first transistor gate structure, a source structure, and a drain structure in the manufacturing method of a stacked field-effect transistor provided by an embodiment of the present application;

[0036] Figure 14 is Figure 13 a cross-sectional view along the H-H direction in

[0037] Figure 15 is Figure 13 a cross-sectional view along the I-I direction in

[0038] Figure 16 a cross-sectional view of forming the first transistor insulating layer in the manufacturing method of the stacked field-effect transistor provided by the embodiment of the present application Figure One ;

[0039] Figure 17 a cross-sectional view of forming the first transistor insulating layer in the manufacturing method of the stacked field-effect transistor provided by the embodiment of the present application Figure Two ;

[0040] Figure 18 a cross-sectional view of forming the first transistor electrode lead-out layer in the manufacturing method of the stacked field-effect transistor provided by the embodiment of the present application Figure One ;

[0041] Figure 19 a cross-sectional view of forming the first transistor electrode lead-out layer in the manufacturing method of the stacked field-effect transistor provided by the embodiment of the present application Figure Two ;

[0042] Figure 20 a cross-sectional view of inverting the wafer in the manufacturing method of the stacked field-effect transistor provided by the embodiment of the present application Figure One ;

[0043] Figure 21 a cross-sectional view of inverting the wafer in the manufacturing method of the stacked field-effect transistor provided by the embodiment of the present application Figure Two ;

[0044] Figure 22 a cross-sectional view of removing the substrate and part of the second-type active layer in the manufacturing method of the stacked field-effect transistor provided by the embodiment of the present application Figure One ;

[0045] Figure 23 a cross-sectional view of removing the substrate and part of the second-type active layer in the manufacturing method of the stacked field-effect transistor provided by the embodiment of the present application Figure Two ;

[0046] Figure 24 a cross-sectional view of removing part of the shallow trench isolation layer in the manufacturing method of the stacked field-effect transistor provided by the embodiment of the present application Figure One ;

[0047] Figure 25 a cross-sectional view of removing part of the shallow trench isolation layer in the manufacturing method of the stacked field-effect transistor provided by the embodiment of the present applicationFigure Two ;

[0048] Figure 26 A cross-sectional view of forming a second transistor insulating layer in the manufacturing method of the stacked field-effect transistor provided by the embodiment of the present application Figure One ;

[0049] Figure 27 A cross-sectional view of forming a second transistor insulating layer in the manufacturing method of the stacked field-effect transistor provided by the embodiment of the present application Figure Two .

[0050] Reference numerals:

[0051] 01 - Gate structure; 02 - Source structure; 03 - Drain structure; 04 - Fin structure;

[0052] 10 - Second type isolation layer; 11 - First type active layer;

[0053] 20 - First type isolation layer; 21 - Second type active layer;

[0054] 30 - Shallow trench isolation layer; 31 - Gate structure layer; 32 - Insulating layer;

[0055] 40 - First dielectric layer; 41 - First metal via; 42 Second dielectric layer; 43 - Second metal via; 44 - Third dielectric layer; 45 - Third metal via; 46 - Passivation layer; 47 - Bonding carrier wafer. Detailed implementation manners

[0056] In order to make the technical solutions and advantages in the embodiments of the present application clearer and more understandable, the following further describes the exemplary embodiments of the present application in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than an exhaustive list of all embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0057] This embodiment provides a stacked field-effect transistor, which is a stacked device with a field-effect transistor provided above and below, and the two field-effect transistors are opposite to each other up and down. This device is formed on a wafer, and multiple stacked field-effect transistors are formed on the wafer, and then chips are obtained through processes such as packaging and dicing.

[0058] Figure 1 This is a schematic diagram for showing the basic architecture of the field-effect transistor and is not a structural diagram of an actual device. Figure 1It shows that the stacked field-effect transistor mainly includes three parts: a gate structure 01, a source structure 02, a drain structure 03, and a fin structure 04. The gate structure 01 is located between the source structure 02 and the drain structure 03, and the extending direction of the fin structure 04 is perpendicular to the gate structure 01, the source structure 02, and the drain structure 03.

[0059] The number of fin structures 04 is at least one. When the number of fin structures 04 is more than two, they are arranged at intervals between the source structure 02 and the drain structure 03. In this embodiment Figure 1 only shows the scheme of three fin structures 04.

[0060] As Figure 2 and Figure 3 shown, the stacked field-effect transistor provided in this embodiment includes: a fin structure 04, a shallow trench isolation layer, a gate structure layer, a source structure layer, and a drain structure layer.

[0061] Among them, the fin structure 04 includes a first-type active layer 11, a second-type isolation layer 10, a first-type isolation layer 20, and a second-type active layer 21 arranged in sequence along the stacking direction. The first-type active layer 11 is used to form a first field-effect transistor, and the second-type active layer 21 is used to form a second field-effect transistor. The two field-effect transistors are stacked, and are isolated by the second-type isolation layer 10, the first-type isolation layer 20, and the shallow trench isolation layer.

[0062] The first type and the second type are opposite conduction types. If the first type is P-type, the second type is N-type; if the first type is N-type, the second type is P-type. The example provided in this embodiment is: the first-type active layer 11 is an N+-type active layer, the second-type active layer 21 is a P+-type active layer; the first-type isolation layer 20 is an N-type isolation layer, and the second-type isolation layer 10 is a P-type isolation layer.

[0063] The number of fin structures 04 is at least one, and can be one, two, three, or more than three. The fin structures 04 are arranged at intervals.

[0064] The shallow trench isolation layer 30 extends in a plane perpendicular to the stacking direction, fills the periphery of the fin structure, and its position corresponds to the first-type isolation layer 20 and the second-type isolation layer 10. The shallow trench isolation layer 20, the first-type isolation layer 20, and the second-type isolation layer 10 isolate the first field-effect transistor from the second field-effect transistor.

[0065] On both sides of the shallow trench isolation layer 30, a first field-effect transistor and a second field-effect transistor are fabricated respectively. The two field-effect transistors are stacked up and down, and the stacking direction is Figure 2In the vertical direction. The shallow trench isolation layer 30, the second type isolation layer 10, and the first type isolation layer 20 isolate the two field effect transistors from each other so that their working processes do not affect each other.

[0066] The first gate structure layer is formed on the surface of the fin structure in the first field effect transistor, and the second gate structure layer is formed on the surface of the fin structure in the second field effect transistor.

[0067] Based on the above technical solution, a source region is also provided. The source region includes a first type active layer, a second type isolation layer, a first type isolation layer, and a second type active layer formed together with the fin structure; the shallow trench isolation layer is filled around the source region and corresponds to the first type isolation layer and the second type isolation layer.

[0068] The first source structure layer is formed on the surface of the source region in the first field effect transistor, and the second source structure layer is formed on the surface of the source region in the second field effect transistor.

[0069] Based on the above technical solution, a drain region is also provided. The drain region includes a first type active layer, a second type isolation layer, a first type isolation layer, and a second type active layer formed together with the fin structure; the shallow trench isolation layer is filled around the drain region and corresponds to the first type isolation layer and the second type isolation layer.

[0070] The first drain structure layer is formed on the surface of the drain region in the first field effect transistor; the second drain structure layer is formed on the surface of the drain region in the second field effect transistor.

[0071] The first gate structure layer, the first source structure layer, and the first drain structure layer located on one side of the shallow trench isolation layer 30 are used to form the first field effect transistor, and the second gate structure layer, the second source structure layer, and the second drain structure layer on the other side of the shallow trench isolation layer 30 are used to form the second field effect transistor. The two field effect transistors are stacked vertically and are upside down.

[0072] Specifically, the part of the gate structure layer 31 covering the surface of the fin structure 04 on one side of the shallow trench isolation layer 30 forms the first gate structure 01 of the first field effect transistor; the part covering the surface of the fin structure 04 on the other side of the shallow trench isolation layer 30 forms the second gate structure 01 of the first field effect transistor.

[0073] The part of the source structure layer (not shown in the figure) covering the surface of the source region on one side of the shallow trench isolation layer 30 forms the source structure 02 of the first field effect transistor, and the part covering the surface of the source region on the other side of the shallow trench isolation layer 30 forms the source structure 02 of the second field effect transistor.

[0074] The part of the leakage structure layer (not shown in the figure) covering the surface of the leakage region on one side of the shallow trench isolation layer 30 forms the drain structure 03 of the first field effect transistor, and the part covering the surface of the leakage region on the other side of the shallow trench isolation layer 30 forms the drain structure 03 of the second field effect transistor.

[0075] In one embodiment: along the direction perpendicular to the stacking direction, each field effect transistor is divided into a source region, a drain region, and a fin structure 04. The fin structure 04 serves as the channel region and is formed of the same type of semiconductor material as the source region and the drain region.

[0076] In the solution disclosed in the patent document mentioned in the background art of the present application, the two field effect transistors formed by stacking are an NMOS and a PMOS respectively, and they share an active structure. When there are different on and off combinations of the NMOS and the PMOS, the current signals in the shared active structure will interfere with each other. For example, when the NMOS and the PMOS are both turned on, there will be both NMOS and PMOS current signals in the active structure. The source and drain of the NMOS and the PMOS respectively receive the common signal, which is likely to cause crosstalk and interfere with the logic function recognition and performance of the transistor.

[0077] In the solution provided in this embodiment, the first type of isolation layer 10 and the second type of isolation layer 20 isolate the two field effect transistors (NMOS and PMOS). There is an N-type first type of isolation layer 20 (abbreviated as N-type isolation layer) and a P-type second type of isolation layer 10 (abbreviated as P-type isolation layer) between the two field effect transistors. For the NMOS, the P-type isolation layer isolates the NMOS and the PMOS devices; for the PMOS, the N-type isolation layer and the P-type isolation layer of the NMOS device isolate the PMOS and the NMOS devices, and the channel regions of the two field effect transistors are independently controlled and isolated from each other, improving the stability of the stacked transistor structure.

[0078] The technical solution provided in this embodiment adopts a fin structure, including a first type of active layer, a second type of isolation layer, a first type of isolation layer, and a second type of active layer arranged in sequence along the stacking direction; the first type and the second type are of opposite conductive types; a shallow trench isolation layer extending along a plane perpendicular to the stacking direction and filling the periphery of the fin structure, and the position corresponds to the first type of isolation layer and the second type of isolation layer; the first type of active layer is used to form the first field effect transistor, the second type of active layer is used to form the second field effect transistor, and the first field effect transistor and the second field effect transistor are isolated by the second type of isolation layer, the first type of isolation layer, and the shallow trench isolation layer; a first gate structure layer formed on the surface of the fin structure in the first field effect transistor; a second gate structure layer formed on the surface of the fin structure in the second field effect transistor, which can enable the two field effect transistors to have a good isolation effect, are independently controlled, and can improve the stability of the stacked field effect transistor.

[0079] Furthermore, the source region, drain region, and channel region are formed of the same type of semiconductor material with a high doping concentration. During the subsequent high-temperature annealing process for forming silicide, the dopants in the source region, drain region, and channel region will not diffuse either. Moreover, the two field-effect transistors in the stacked device are turned on through internal doping with a high concentration within the device. The channel region is controlled by the gate structure. When the gate structure is not powered, due to the energy band difference between the gate structure and the channel, the device can be self-depleted.

[0080] In the above solution, a field-effect transistor may include only the fin structure 04 and the source region, or only the fin structure 04 and the drain region, or include the fin structure 04, the source region, and the drain region.

[0081] Correspondingly, when a field-effect transistor includes only the fin structure 04 and the source region, the fin structure 04 and the source region are obtained simultaneously by etching the first-type active layer 11, the second-type isolation layer 10, the first-type isolation layer 20, and the second-type active layer 21.

[0082] When a field-effect transistor includes only the fin structure 04 and the drain region, the fin structure 04 and the drain region are obtained simultaneously by etching the first-type active layer 11, the second-type isolation layer 10, the first-type isolation layer 20, and the second-type active layer 21.

[0083] When a field-effect transistor includes the fin structure 04, the source region, and the drain region at the same time, the fin structure 04, the source region, and the drain region are obtained simultaneously by etching the first-type active layer 11, the second-type isolation layer 10, the first-type isolation layer 20, and the second-type active layer 21.

[0084] In this embodiment, the fin structure 04, the source region, and the drain region of the first field-effect transistor and the fin structure 04, the source region, and the drain region of the second field-effect transistor are obtained simultaneously by etching the first-type active layer 11, the second-type isolation layer 10, the first-type isolation layer 20, and the second-type active layer 21. Subsequently, the corresponding gate structure layer, source structure layer, and drain structure layer can be directly formed on the active structure. During the process of forming the second field-effect transistor, there is no need for additional high-temperature processes such as spike annealing activation for source-drain epitaxy, avoiding the influence of the high-temperature process of the second transistor on the source-drain diffusion and silicide contact of the first transistor in the traditional solution, thereby improving the yield, device quality, and performance. Moreover, it can also achieve an overall low-temperature process, with good feasibility.

[0085] One implementation is that in each field-effect transistor, the source region extends along the first direction; the drain region extends along the first direction.

[0086] For a field-effect transistor having both a source region and a drain region, the source region and the drain region both extend in a first direction, and the source region and the drain region are spaced apart in a second direction. At least two fin structures 04 are spaced apart between the source region and the drain region; both the first direction and the second direction are perpendicular to the stacking direction, and the first direction is perpendicular to the second direction. The first direction is Figure 1 the up-down direction in Figure 1 and the second direction is the left-right direction in

[0087] In each field-effect transistor, at least two fin structures 04 extend in the second direction, and the fin structures 04 are arranged at intervals in the first direction. The ends of at least two fin structures 04 may extend beyond the source region or the drain region, or may terminate at the source region or the drain region.

[0088] One implementation is that the thickness of the shallow trench isolation layer 30 is less than the sum of the thicknesses of the second-type isolation layer 10 and the first-type isolation layer 20, which is equivalent to the shallow trench isolation layer 30 being located within the coverage ranges of the second-type isolation layer 10 and the first-type isolation layer 20, so that both the second-type isolation layer 10 and the first-type isolation layer 20 have partially exposed sides. The channel region formed by the fin structures is completely wrapped by the gate structure layer in the stacking direction, and all channels can be effectively depleted by adjusting the gate work function, enabling the device to operate normally without leakage problems.

[0089] Specifically, on one side of the shallow trench isolation layer 30, the part of the gate structure layer 31 covering the outer surfaces of the first-type isolation layer 20 and the second-type active layer 21 in the fin structure 04 forms the first gate structure of the first field-effect transistor; on the other side of the shallow trench isolation layer 30, the part of the gate structure layer 31 covering the outer surfaces of the second-type isolation layer 10 and the first-type active layer 11 in the fin structure 04 forms the second gate structure of the second field-effect transistor.

[0090] On one side of the shallow trench isolation layer 30, the part of the source structure layer covering the outer surfaces of the first-type isolation layer 20 and the second-type active layer 21 in the source region forms the first source structure 02 of the first field-effect transistor; on the other side of the shallow trench isolation layer 30, the part of the source structure layer covering the outer surfaces of the second-type isolation layer 10 and the first-type active layer 11 in the source region forms the second source structure 02 of the second field-effect transistor.

[0091] On one side of the shallow trench isolation layer 30, the part of the drain structure layer covering the outer surfaces of the first-type isolation layer 20 and the second-type active layer 21 in the drain region forms the first drain structure 03 of the first field-effect transistor; on the other side of the shallow trench isolation layer 30, the part covering the outer surfaces of the second-type isolation layer 10 and the first-type active layer 11 in the drain region forms the second drain structure 03 of the second field-effect transistor.

[0092] In the above solution, the first gate structure layer in the first field effect transistor includes a gate dielectric layer and a gate electrode layer. Among them, the gate dielectric layer coats the outer surfaces of the first type isolation layer 20 and the second type active layer 21 in each fin structure 04. The gate electrode layer coats the outer surface of the gate dielectric layer. The second gate structure layer in the second field effect transistor includes a gate dielectric layer and a gate electrode layer. Among them, the gate dielectric layer coats the outer surfaces of the second type isolation layer 10 and the first type active layer 11 in each fin structure 04. The gate electrode layer coats the outer surface of the gate dielectric layer.

[0093] The material of the gate dielectric layer can be silicon dioxide, hafnium dioxide, or a common silicon dioxide - hafnium dioxide stacked gate dielectric layer structure, or other dielectric combinations with a relatively high dielectric constant. The gate electrode layer can be a metal layer or a polysilicon layer, etc.

[0094] Further, an insulating layer 32 is formed on the two side surfaces of the shallow trench isolation layer 30, and on the surfaces of the first gate structure layer, the first source structure layer, and the first drain structure layer, as well as on the surfaces of the second gate structure layer, the second source structure layer, and the second drain structure layer. The insulating layer 32 can be an oxide layer, such as made of materials like silicon dioxide.

[0095] Electrode lead - out layers are respectively formed on the surface of the insulating layer 32 in the first field effect transistor and on the surface of the insulating layer 32 in the second field effect transistor, for leading out the electrical signals in the transistor. One implementation is that the electrode lead - out layer includes: a first dielectric layer 40, a second dielectric layer 42, and a third dielectric layer 44 formed in sequence on the surface of the insulating layer 32. Among them, a metal is injected into an opening in the first dielectric layer 40 to form a first metal hole 41, a metal is injected into an opening in the second dielectric layer 42 to form a second metal hole 43, and a metal is injected into an opening in the third dielectric layer 44 to form a third metal hole 45. The three metal holes are in electrical contact with the corresponding parts to lead out the electrical signals. For example, the three metal holes are respectively in electrical contact with the gate structure layer 31, the source structure layer, and the drain structure layer to lead out their electrical signals. Or, the number of dielectric layers and metal holes can be more, and more electrical signals can be led out according to the device design.

[0096] A passivation layer 46 is also provided on the surface of the electrode lead - out layer for protecting the transistor.

[0097] As Figure 4 shown, on the basis of the above technical solution, this embodiment also provides a manufacturing method of a stacked field effect transistor, including:

[0098] Step 101: Form a second type active layer, a first type isolation layer, a second type isolation layer, and a first type active layer in sequence on the substrate; the first type and the second type are opposite conductive types.

[0099] A conventional silicon-based substrate 00 is adopted. The substrate 00 can be an N-type substrate or a P-type substrate, and its thickness is about 500 μm.

[0100] By means of epitaxy, a second-type transistor active layer 21, a first-type isolation layer 20, a second-type isolation layer 10, and a first-type active layer 11 are sequentially grown on the substrate.

[0101] In one implementation, the second-type transistor active layer 21 is P-type, with a thickness of 30 nm - 80 nm and a doping concentration of (1e18 - 1e20) / cm-3.

[0102] The first-type isolation layer 20 is N-type and jointly forms an NP-type isolation structure with the P-type second-type isolation layer 10. The first-type isolation layer 20 and the second-type transistor active layer 21 are used to form the active structure of the second transistor.

[0103] The first-type transistor active layer 11 is N-type, with a thickness of 30 nm - 80 nm and a concentration of (1e18 - 1e20) / cm-3. The second-type isolation layer 10 and the first-type transistor active layer 11 are used to fabricate the first-type transistor active structure.

[0104] The above-mentioned second-type active layer 21, first-type isolation layer 20, second-type isolation layer 10, and first-type active layer 11 form the active layer and isolation layer for subsequently manufacturing a stacked transistor. The substrate and the layers formed by epitaxy can be materials such as silicon, silicon germanium, or germanium.

[0105] The growth thicknesses of the first-type isolation layer 20, second-type isolation layer 10, and first-type active layer 11 are determined according to the actual device size. The second-type isolation layer 10 and the first-type active layer 11 can be slightly thicker than the size required by the actual device to reserve a certain margin for etching after flipping the wafer. The structure formed after step 101 is as Figure 5 and Figure 6 shown.

[0106] Step 102: Etch the second-type active layer, first-type isolation layer, second-type isolation layer, and first-type active layer to form a fin structure.

[0107] In one implementation: Etch the second-type active layer, first-type isolation layer, second-type isolation layer, and first-type active layer to simultaneously form a fin structure and a source region, or simultaneously form a fin structure and a drain region, or simultaneously form a source region, a drain region, and a fin structure.

[0108] The regions for fabricating the stacked transistor active structure, namely the source region, drain region, and fin structure, can be defined by means of mask layer lithography and etching, as Figures 7 to 9 shown.

[0109] The number of fin structures to be etched can be customized according to the drive current requirements of the transistor. In this embodiment, three fin structures 04 are adopted.

[0110] The etching position stops within the second type of active layer 21 and ensures that it is below the depth required for the second transistor, forming a mesa structure in the source region and the drain region. Step 103: Form a shallow trench isolation layer around the first type of isolation layer and the second type of isolation layer.

[0111] A shallow trench isolation layer 30 is formed on the mesa structure formed in the above steps. For example, it can be an oxide layer. Specifically, an oxide can be deposited on the mesa structure to form a shallow trench isolation layer 30 with a certain thickness.

[0112] The thickness of the shallow trench isolation layer 30 is adjusted according to the thicknesses of the first type of isolation layer 20 and the second type of isolation layer 10. For example: The upper surface of the shallow trench isolation layer 30 is located within the second type of isolation layer 10, serving the function of isolating adjacent structures, as Figures 10 to 12 shown.

[0113] Step 104: Form a first gate structure layer on the surface of the fin structure to obtain a first field-effect transistor on one side of the shallow trench isolation layer.

[0114] Based on the above solution, the first gate structure layer includes a gate dielectric layer and a gate electrode layer. First, a gate dielectric layer is deposited on the fin structure 04 through a gate process. This step can specifically be: First, deposit a gate dielectric layer on the surfaces of the above-formed active structure and the shallow trench isolation layer 30, and then remove the unnecessary parts through etching, leaving only the gate dielectric layer on the surface of the fin structure.

[0115] The material of the gate dielectric layer can be silicon dioxide, hafnium dioxide, or a common silicon dioxide - hafnium dioxide stacked gate dielectric layer structure, or a combination of other high-k materials.

[0116] A gate electrode layer is formed on the surface of the gate dielectric layer, which can be a metal layer or a polysilicon layer.

[0117] Furthermore, after forming the shallow trench isolation layer, a first source structure layer is also formed on the surface of the source region;

[0118] Or, after forming the shallow trench isolation layer, a first drain structure layer is also formed on the surface of the drain region.

[0119] In this embodiment, a first source structure layer and a first drain structure layer are correspondingly formed on the surfaces of the source region and the drain region. Specifically, a silicide contact process is completed on the surfaces of the source region and the drain region respectively to form a source electrode structure and a drain electrode structure. For example, through an implantation method or other methods, existing technologies can be used to achieve this.

[0120] When the upper surface of the shallow trench isolation layer 30 is located within the second type of isolation layer 10, a part of the side surface of the second type of isolation layer 10 is exposed, and then a gate dielectric layer is formed on the surfaces of the second type of isolation layer 10 and the first type of active layer 11 in the fin structure.

[0121] As Figures 13 to 15 shown, Figure 13 in the structure shown, a gate dielectric layer is also formed on the surface of the shallow trench isolation layer 30 between adjacent fin structures. Alternatively, there may be no gate dielectric layer on the surface of the shallow trench isolation layer 30 between adjacent fin structures. Figure 15 The source structure or the drain structure is not shown in

[0122] Based on the above technical solution, by controlling the deposition of the gate metal work function, such as the thickness of the gate metal, the material nickel, etc., when the gate is not powered, due to the energy band difference between the gate and the channel, the device can be self-depleted.

[0123] Then, an insulating layer 32 is formed on the surfaces of the above gate structure layer, source structure layer, drain structure layer, and shallow trench isolation layer 30, as Figure 16 and Figure 17 shown. Figure 16 and Figure 17 The cross-sectional positions of Figure One are consistent with the previous appendix. The insulating layer 32 may specifically be an oxide layer and is formed by deposition.

[0124] Next, an electrode lead-out layer is formed on the insulating layer 32. As Figure 18 and Figure 19 shown, the following steps are sequentially performed:

[0125] A first dielectric layer 40 is formed on the upper surface of the insulating layer 32, and the first dielectric layer 40 is an insulating layer. Then, using a mask etching process, holes are opened in the first dielectric layer 40, and the opening positions are determined according to the positions of the components that need to lead out electrical signals below, so that these components are exposed. Then, metal is filled into the openings to form first metal vias 41, which are in electrical contact with these components.

[0126] A second dielectric layer 42 is formed on the surface of the first dielectric layer 40, and the second dielectric layer 42 is an insulating layer. Then, using a mask etching process, holes are opened in the second dielectric layer 42, and the opening positions are determined according to the positions of the components that need to lead out electrical signals below, so that these components are exposed. Then, metal is filled into the openings to form second metal vias 43, which are in electrical contact with these components.

[0127] A third dielectric layer 44 is formed on the surface of the second dielectric layer 42, and the third dielectric layer 44 is an insulating layer. Then, using a mask etching process, holes are opened in the third dielectric layer 44, and the opening positions are determined according to the positions of the components that need to lead out electrical signals below, so that these components are exposed. Then, metal is filled into the openings to form third metal vias 45, which are in electrical contact with these components.

[0128] After that, a passivation layer 46 is formed on the third dielectric layer 44 to passivate and protect the first field-effect transistor.

[0129] Then, a bonding carrier wafer 47 is disposed on the passivation layer 46 by bonding. The bonding carrier wafer 47 has a certain strength to provide support for flipping the wafer and subsequent processes. After the second field-effect transistor is formed, the bonding carrier wafer 47 is removed.

[0130] The first field-effect transistor formed through the above components can specifically be a PMOS device.

[0131] Step 105: Flip the first field-effect transistor.

[0132] Flip the above-formed device upside down so that the substrate 00 faces upward, as Figure 20 and Figure 21 shown.

[0133] Step 106: Remove the substrate, a part of the second-type active layer adjacent to the substrate, and remove the peripheral part of the shallow trench isolation layer to the first-type isolation layer.

[0134] Remove the substrate 00 by etching or chemical mechanical polishing (CMP for short), and remove a part of the P+-type second-type active layer 21 adjacent to the substrate 00 to the top of the inverted shallow trench isolation layer 30, exposing the active structure to form the second transistor, that is, the fin structure and the upper surfaces of the source and drain are exposed, as Figure 22 and Figure 23 shown.

[0135] After that, through a process with a relatively high etching rate of selective etching, etch the shallow trench isolation layer 30 into the N-type first-type isolation layer 20, exposing the P+-type second-type active layer 21 of the second transistor and a part of the N-type first-type isolation layer 20, and at the same time exposing the source and drain platforms of the second transistor.

[0136] Repair the topography of the formed platform and the top of the fin structure through a low etching rate, and etch the second-type active layer 21 to the target height to form the active structure of the second transistor, as Figure 24 and Figure 25 shown.

[0137] Step 107: Form a second gate structure layer on the surface of the fin structure on the other side of the shallow trench isolation layer to obtain a second field-effect transistor on the other side of the shallow trench isolation layer.

[0138] Furthermore, a second source structure layer and a second drain structure layer are correspondingly formed on the surfaces of the source region and the drain region on the other side of the shallow trench isolation layer.

[0139] In this step, the gate process of the second transistor and the silicide contact process of the source and drain are completed in the same manner as the first transistor, forming a gate structure layer, a source structure layer, and a drain structure layer. Specifically, the gate structure layer, the source structure layer, and the drain structure layer are formed on the surfaces of the fin structure, the source region, and the drain region corresponding to the first type of isolation layer 20 and the second type of active layer 21.

[0140] After that, an insulating layer 32 is formed, specifically by depositing an oxide layer, to complete the manufacturing process of the active region of the second transistor, as Figure 26 and Figure 27 shown.

[0141] In the above solution, the second field-effect transistor can be an NMOS device. The source, drain, and channel active structures of the second field-effect transistor and the first field-effect transistor are formed by one-step etching, and they are all highly doped and activated semiconductor materials. There is no need for the spike annealing (about 1000 - 1100 °C) for source-drain diffusion and activation in the prior art, which will not affect the channel diffusion and silicide of the first field-effect transistor that has been manufactured, and can well guarantee the manufacturing yield and improve the manufacturability of the stacked transistor structure.

[0142] Then, an electrode lead-out layer and a passivation layer are formed on the insulating layer 32. Specifically, the implementation method of the first field-effect transistor can be referred to. The manufactured device is as Figure 2 and Figure 3 shown.

[0143] The first field-effect transistors in the upper and lower parts and the second field-effect transistors can be interconnected by defining deep through-holes to realize the electrical connection and interconnection of P-type transistors and N-type transistors, constituting a highly integrated integrated circuit, and realizing a self-depleting non-inverting complementary field-effect transistor with the same doping for the stacked source, drain, and channel.

[0144] In the above solution, the source region extends along the first direction. The drain region extends along the first direction. When the active region and the drain region are set simultaneously, the source region and the drain region are spaced along the second direction; at least two fin structures 04 are spaced between the source region and the drain region; both the first direction and the second direction are perpendicular to the stacking direction, and the first direction is perpendicular to the second direction.

[0145] For the stacked field-effect transistor manufactured by the above manufacturing method provided in this embodiment, the structure can refer to the above content. The manufacturing method provided in this embodiment has the same technical effects as the above content.

[0146] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present application.

[0147] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0148] In the present application, unless otherwise clearly defined and limited, the terms "mounted", "connected", "coupled", "fixed", etc. shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or capable of communicating with each other; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0149] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present application.

[0150] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these changes and modifications.

Claims

1. A stacked field effect transistor, characterized in that: include: A fin-shaped structure, comprising a first type active layer, a second type isolation layer, a first type isolation layer and a second type active layer sequentially arranged along a stacking direction; The first type and the second type are of opposite conductivity types; A shallow trench isolation layer extends along a plane perpendicular to the stacking direction, fills the periphery of the fin structure, and is located corresponding to the first type isolation layer and the second type isolation layer; the first type active layer is used to form a first field effect transistor, the second type active layer is used to form a second field effect transistor, and the first field effect transistor and the second field effect transistor are isolated by the second type isolation layer, the first type isolation layer and the shallow trench isolation layer; A first gate structure layer formed on a surface of a fin structure in a first field effect transistor; A second gate structure layer is formed on the surface of the fin structure in the second field effect transistor.

2. The stacked field effect transistor according to claim 1, characterized in that: Also includes: A source region, including a first type active layer, a second type isolation layer, a first type isolation layer and a second type active layer formed together with the fin structure; a shallow trench isolation layer is filled in the periphery of the source region and corresponds to the first type isolation layer and the second type isolation layer; A first source structure layer formed on the surface of the source region in the first field effect transistor; A second source structure layer formed on the surface of the source region in the second field effect transistor; and / or, The drain region includes a first type active layer, a second type isolation layer, a first type isolation layer and a second type active layer formed together with the fin structure; the shallow trench isolation layer is filled in the periphery of the drain region and corresponds to the first type isolation layer and the second type isolation layer; A first drain structure layer formed on the surface of the drain region in the first field effect transistor; A second drain structure layer is formed on the surface of the drain region in the second field effect transistor.

3. The stacked field effect transistor according to claim 2, characterized in that: The fin-shaped structure, the source region, and the drain region are obtained by synchronously etching the first type active layer, the second type isolation layer, and the first type isolation layer and the second type active layer.

4. The stacked field effect transistor according to claim 2, characterized in that: The source region extends along the first direction; the drain region extends along the first direction; The source region and the drain region are arranged at intervals along the second direction; the fin-shaped structure is arranged between the source region and the drain region; The first direction and the second direction are both perpendicular to the stacking direction, and the first direction is perpendicular to the second direction.

5. The stacked field effect transistor according to claim 1, characterized in that: The number of the fin-shaped structures is at least two, and the fin-shaped structures are arranged at intervals.

6. The stacked field effect transistor according to claim 1, characterized in that: The thickness of the shallow trench isolation layer is less than the sum of the thicknesses of the second type isolation layer and the first type isolation layer.

7. The stacked field effect transistor according to claim 1, characterized in that: The first gate structure layer of the first field effect transistor includes: A gate dielectric layer covering the outer surfaces of the first type isolation layer and the second type active layer in the fin structure in the first field effect transistor; A gate layer, covering the outer surface of the gate dielectric layer; The second gate structure layer of the second field effect transistor includes: A gate dielectric layer covering the outer surface of the second type isolation layer and the first type active layer in the fin structure of the second field effect transistor; The gate layer is coated on the outer surface of the gate dielectric layer.

8. The stacked field effect transistor according to claim 2, characterized in that: Also includes: Insulating layers are formed on both side surfaces of the shallow trench isolation layer, and on the surfaces of the first gate structure layer, the first source structure layer and the first drain structure layer, and on the surfaces of the second gate structure layer, the second source structure layer and the second drain structure layer; The electrode lead-out layer is formed on the surface of the insulating layer in the first field effect transistor and the surface of the insulating layer in the second field effect transistor.

9. A method for manufacturing a stacked field effect transistor, characterized in that: include: Sequentially forming a second type active layer, a first type isolation layer, a second type isolation layer, and a first type active layer on the substrate; The first type and the second type are of opposite conductivity types; Etching the second type active layer, the first type isolation layer, the second type isolation layer and the first type active layer to form a fin structure; forming a shallow trench isolation layer around the first type isolation layer and the second type isolation layer; forming a first gate structure layer on the surface of the fin structure to obtain a first field effect transistor on one side of the shallow trench isolation layer; Flipping the first field effect transistor; Removing the substrate, a portion of the second type active layer adjacent to the substrate, and removing the shallow trench isolation layer to the periphery of the first type isolation layer; A second gate structure layer is correspondingly formed on the surface of the fin structure on the other side of the shallow trench isolation layer to obtain a second field effect transistor on the other side of the shallow trench isolation layer.

10. The manufacturing method according to claim 9, characterized in that: While etching the second type active layer, the first type isolation layer, the second type isolation layer and the first type active layer to form a fin structure, a source region is also formed; After forming the shallow trench isolation layer, the method further comprises: forming a first source structure layer on the surface of the source region; and / or, While etching the second type active layer, the first type isolation layer, the second type isolation layer and the first type active layer to form a fin structure, a drain region is also formed; After forming the shallow trench isolation layer, the method further comprises: forming a first drain structure layer on the surface of the drain region.

11. The manufacturing method according to claim 10, characterized in that: The source region extends along the first direction; the drain region extends along the first direction; The source region and the drain region are arranged at intervals along the second direction; the fin-shaped structure is arranged between the source region and the drain region; The first direction and the second direction are both perpendicular to the stacking direction, and the first direction is perpendicular to the second direction.

12. The manufacturing method according to claim 10, characterized in that: After forming the first field effect transistor, the method further includes: forming a bonding carrier on the surface of the first field effect transistor; After forming the second field effect transistor, the method further includes: removing the bonding carrier.

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