Photonic integrated circuit package including substrate having glass core

Abstract

Microelectronic assemblies, related devices and methods are disclosed herein. In some embodiments, a photonic component may include an interposer having a surface, where a material of the interposer includes glass, and the interposer includes a through glass via (TGV); a photonic integrated circuit (PIC) optically coupled to a surface of the interposer by an optical cement or melt bond and electrically coupled to the TGV in the interposer by a hybrid bond interconnect; and an optical component optically coupled to the interposer, where the optical component is optically coupled to the PIC through an optical path through the interposer.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of priority of U.S. Patent Application No. 18 / 059,089, entitled "PHOTONIC INTEGRATED CIRCUIT PACKAGES INCLUDING SUSTRATES WITH GLASS CORES", filed on November 28, 2022, the entire content of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to packaged photonic integrated circuits (PICs) including substrates with glass cores. More specifically, this disclosure relates to techniques, methods, and devices related to PIC architectures that include substrates having glass cores and optical paths passing through the glass cores. Background Art

[0004] When fabricated on a wafer of a semiconductor material such as silicon, an electronic circuit is referred to as an integrated circuit (IC). A wafer having such an IC is typically diced into multiple individual die. A die including a PIC can be packaged into an IC package that contains one or more die and other electronic components such as resistors, capacitors, and inductors. Photonic IC packages can be integrated into an electronic system such as a consumer electronics system. Brief Description of the Drawings

[0005] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. For ease of description, like reference numerals represent like structural elements. Embodiments are illustrated by way of example and not limitation in the figures of the drawings.

[0006] Figure 1A is a schematic cross - sectional view of an example microelectronic component according to some embodiments of the present disclosure.

[0007] Figure 1B is a schematic diagram of an example detail of an active surface of a photonic integrated circuit according to some embodiments of the present disclosure.

[0008] Figure 1C is according to some embodiments of the present disclosure Figure 1A schematic cross - sectional view of an example detail of a conductive interconnect bonding interface of an example microelectronic component.

[0009] Figure 1D is Figure 1A schematic top - view of an example microelectronic component.

[0010] Figure 2A is a schematic cross - sectional view of another example microelectronic component according to some embodiments of the present disclosure.

[0011] Figure 2B Schematic details of an optical bonding interface of a photonic integrated circuit according to some embodiments of the present disclosure.

[0012] Figure 2C Is Figure 2A Schematic top view of an example microelectronic component.

[0013] Figures 3A to 3E Is an example process for manufacturing a Figure 2A Schematic cross-sectional views of different stages of a microelectronic component.

[0014] Figure 4 Is a schematic flowchart listing example operations that may be associated with manufacturing a microelectronic component according to some embodiments of the present disclosure.

[0015] Figure 5 Is a cross-sectional view of a device package including one or more microelectronic components according to any embodiment disclosed herein.

[0016] Figure 6 Is a cross-sectional side view of a device assembly including one or more microelectronic components according to any embodiment disclosed herein.

[0017] Figure 7 Is a block diagram of an example computing device including one or more microelectronic components according to any embodiment disclosed herein. Detailed Description

[0018] For the purpose of illustrating the PIC packages described herein, it is important to understand the phenomena that may come into play during the assembly and packaging of a PIC. The following background information can be considered as a basis that can appropriately explain the present disclosure. Such information is provided solely for purposes of explanation and should not, therefore, be construed in any way as limiting the broad scope of the present disclosure and its potential applications.

[0019] Advances in semiconductor processing and logic design have allowed an increase in the number of logic circuits that can be included in processors and other IC devices. As a result, many processors now have multiple cores monolithically integrated on a single die. Generally, these types of monolithic ICs are also described as planar because they take the form of a flat surface and are typically built on a single silicon wafer made from a single-crystalline silicon ingot. The typical manufacturing process for such monolithic ICs is referred to as a planar process, which allows lithography, etching, thermal diffusion, oxidation, and other such processes to occur on the surface of the wafer such that active circuit elements (e.g., transistors and diodes) are formed on the planar surface of the silicon wafer.

[0020] The current technology allows for the formation of hundreds and thousands of such active circuit elements on a single die, enabling multiple logic circuits to be implemented thereon. In such a monolithic die, the manufacturing process must be optimized equally for all circuits, resulting in a compromise between different circuits. Additionally, due to the limitation that circuits must be placed on a flat surface, some circuits are farther from some other circuits, leading to performance degradation such as longer latency. The manufacturing yield may also be severely affected because if even one circuit fails, the entire die may have to be discarded.

[0021] One solution to overcome such negative impacts of a monolithic die is to break the circuits into smaller dies (e.g., chiplets, tiles) electrically coupled by interconnect bridges. The smaller dies are part of a component of interconnected dies that together form a complete IC in terms of application and / or functionality, such as memory chips, microprocessors, microcontrollers, commodity ICs (e.g., chips for repetitive processing routines, simple tasks, application-specific ICs, etc.), and systems-on-chip (SoCs). In other words, individual dies are connected to create the functionality of a monolithic IC. By using separate dies, each individual die can be optimally designed and manufactured for a specific functionality. For example, a processor core containing logic circuits may be aimed at performance and thus may require a very fast-optimized layout. This has different manufacturing requirements compared to a USB controller, which is built to meet certain Universal Serial Bus (USB) standards rather than processing speed. Thus, by dividing different parts of the overall design into different dies, each die being optimized in terms of design and manufacturing, the overall yield and cost of the combined die solution can be improved.

[0022] The connectivity between these dies can be achieved in many ways. For example, in a 2.5D packaging solution, a silicon interposer and through-silicon vias (TSVs) connect the dies at silicon interconnect speeds with minimal footprint. In another example, a silicon bridge embedded under the edges of two interconnected dies facilitates their electrical coupling. In a three-dimensional (3D) architecture, the dies are stacked on top of each other, thus generally resulting in a smaller footprint. Typically, TSVs and high-pitch solder-based bumps (e.g., C2 interconnects) are used to achieve electrical connectivity and mechanical coupling in such 3D architectures. Bridge and 3D stacking architectures can also be combined to allow a top-packaged chip to communicate with other chips horizontally using a bridge and vertically using through-module vias (TMVs), which are generally larger than TSVs. However, these current interconnect technologies use solder or its equivalent for connectivity, thus having low vertical and horizontal interconnect densities.

[0023] One way to reduce low vertical interconnect density is to use an interposer, which increases vertical interconnect density but suffers from low lateral interconnect density when the substrate wafer of the interposer is passive. In a general sense, an "interposer" is typically used to refer to a silicon substrate wafer that interconnects two dies. By including active circuit elements in the interposer, lateral speed can be improved, but more expensive manufacturing processes are required, especially when using large substrate dies to interconnect smaller dies. Additionally, not all interfaces require fine-pitch connections, which can result in additional manufacturing and handling overhead without the benefits of fine pitch.

[0024] Integrating optical communication into an IC package further increases complexity. Contemporary optical communication and other systems typically employ PICs. Smaller, faster, and less expensive optical components can enable the general-purpose, low-cost, high-capacity optical communication required for the fast and efficient communication technologies demanded by high-capacity Internet data services. In optical communication, information is transmitted via an optical carrier wave, typically in the visible or near-infrared region of the electromagnetic spectrum. A carrier wave with such a high frequency is sometimes referred to as an optical signal, an optical carrier wave, an optical wave signal, or simply light. A typical optical communication network includes several optical fibers, and each optical fiber can include several channels. A channel is a designated frequency band for an electromagnetic signal and is sometimes referred to as a wavelength. Current technological advancements enable the implementation of parts of an optical communication system at the IC (or chip or die) level within a PIC. Packaging such PICs presents many challenges.

[0025] In a general sense, a PIC integrates photon functions for applying information signals onto electromagnetic waves (e.g., electromagnetic waves at optical wavelengths). PICs are applied in fiber-optic communication, medical, security, sensing, and photon-computing systems. A PIC can implement one or more optical and electro-optical devices, such as lasers, photodetectors, waveguides, and modulators, on a single semiconductor chip. Additionally, a PIC can also include electrical circuitry for processing electrical signals corresponding to these optical signals. This integrated PIC has photon processing and electrical signal processing in the same process node, which may limit optimization. In other embodiments, a PIC can be in a separate process node that optimizes PIC performance, and electrical signal processing can be in a different process node that optimizes high-speed electrical performance.

[0026] Encapsulating a PIC is not trivial. Among these challenges, there is a need for parallel close-spacing interconnections that can achieve high-density, high-bandwidth electrical communication between the PIC and other electrical devices while providing optical access to the PIC for optical signals. In fact, enabling optical signals to enter and exit the PIC is a driver of manufacturing cost and complexity. Additionally, coupling an optical fiber cable (sometimes also referred to as an "optical fiber" or simply "fiber") to the PIC such that electromagnetic signals (e.g., optical signals) can be exchanged between the two is challenging. One way to couple the PIC to the optical fiber is through the use of an intermediate optical coupling structure (OCS) (sometimes called an "optical fiber connector", "optical fiber coupler", "fiber assembly unit" (FAU), or "fiber array block") to achieve edge coupling, which has one end optically coupled to the optical fiber and an opposite end positioned adjacent to the PIC and optically coupled to the PIC such that electromagnetic signals can be exchanged between the PIC and the optical fiber via the OCS.

[0027] However, because signals require a transparent medium for propagation, the PIC must typically be exposed within the package to allow the optical fiber to be coupled to the PIC with sufficient stability even in such an edge-coupling assembly. For example, in some package architectures, the PIC has protrusions for coupling to an optical fiber present at the package edge. In another example, the PIC is located within a cavity such that it is exposed and an optical fiber present at the package edge is coupled to the exposed surface. Neither of these architectures can support a small footprint PIC because a significant area of the PIC with functional structures and circuitry is used in coupling to the optical fiber. Their density of electrical interconnection to other ICs within the package is also limited.

[0028] Another approach is to incorporate a thin glass core into a package substrate or couple the glass core (e.g., integrate a glass interposer as a chiplet) to a package substrate or circuit board. As used herein, the terms core and interposer may be used interchangeably. Compared to conventional epoxy cores, glass cores offer several advantages, including higher plated through hole (PTH) density, lower signal loss, and lower total thickness variation (TTV), among others. Additional functionality is achieved by inserting waveguides into the glass core for optical transmission through the core. The PIC requires both electrical and optical connections to the package substrate, which typically have different heights (e.g., different z-height offsets from the top surface of the glass core, where the electrical connection has a larger z-height offset compared to the optical connection with a shorter z-height offset). One way to address the height variation between the electrical and optical connections is to form a dielectric material with a conductive path therein on an inner portion of the top surface of the glass core and expose an outer portion (e.g., the perimeter) of the glass core such that the PIC can be electrically connected through the dielectric material to the conductive path with a larger z-height offset and optically connected to the exposed top surface of the glass core including the waveguides with a lower z-height offset. The dielectric material including the conductive path may also be referred to herein as a redistribution layer (RDL). However, adding the RDL increases the total z-height of the IC package.

[0029] In one aspect of the present disclosure, examples of photon IC package architectures include using high density interconnects to couple the PIC such that the z-height offset between the PIC electrical and optical connections is minimized. As used herein, "high density interconnect" includes interconnects having a pitch of less than 10 microns. As used herein, pitch is measured center-to-center (e.g., from the center of one interconnect to the center of an adjacent interconnect). In some embodiments, the interconnects (such as interconnect 106 described below with reference to Figure 1A may have a pitch between 2 microns and 70 microns.

[0030] Accordingly, microelectronic components, related devices, and methods are disclosed herein. In some embodiments, a photon component may include an interposer having a surface, wherein the material of the interposer includes glass and the interposer includes through glass vias (TGVs); a photon integrated circuit (PIC) optically coupled to the surface of the interposer by an optical adhesive or fusion bonding and electrically coupled to the TGVs in the interposer by interconnects having a pitch between 2 microns and 70 microns between adjacent interconnects; and an optical component optically coupled to the interposer, wherein the optical component is optically coupled to the PIC through an optical path passing through the interposer.

[0031] Each of the structures, components, packages, methods, devices, and systems of the present disclosure can have several innovative aspects, and no single one of these innovative aspects is solely responsible for all of the desired attributes disclosed herein. Details of one or more embodiments of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0032] In the following detailed description, the various aspects of the illustrative embodiments will be described using terms commonly employed by those of ordinary skill in the art to convey the substance of their work to others skilled in the art.

[0033] The terms "circuit" and "circuitry" mean one or more passive and / or active electrical and / or electronic components arranged to cooperate with each other to provide a desired function. The terms also refer to analog circuitry, digital circuitry, hardwired circuitry, programmable circuitry, microcontroller circuitry, and / or any other type of physical hardware electrical and / or electronic components.

[0034] The term "integrated circuit" (IC) means a circuit integrated into a single monolithic semiconductor or similar material.

[0035] In some embodiments, the IC die disclosed herein may include a substantially single-crystalline semiconductor, such as silicon or germanium, as a substrate material (e.g., a substrate, a body), on which an integrated circuit is fabricated using conventional semiconductor processing methods. The semiconductor substrate material may include, for example, N-type or P-type material. The die may include, for example, a crystalline substrate material formed using bulk silicon (or other bulk semiconductor material) or a silicon-on-insulator (SOI) structure. In some other embodiments, the substrate material of one or more of the IC dies may include alternative materials, which may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of Group III-N, III-V, II-VI, or IV group materials. In other embodiments, the substrate material may include a compound semiconductor, for example, having a first sublattice of at least one element in Group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element in Group V of the periodic table (e.g., P, As, Sb). In other embodiments, the substrate material may include an intrinsic IV or III-V semiconductor material or alloy that is not intentionally doped with any electrically active impurities; in alternative embodiments, a nominal impurity dopant level may be present. In other embodiments, the die may include an amorphous material, such as a polymer; for example, the substrate material may include an epoxy resin filled with silica. In other embodiments, the substrate material may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. Generally, the substrate material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, cupric peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. Although some examples of materials for the die are described herein, any material or structure that can be used as a base (e.g., a substrate material) on which the IC circuits and structures described herein can be built falls within the spirit and scope of the present disclosure.

[0036] Unless otherwise described, the IC die described herein includes one or more IC structures (or simply "ICs") that implement (i.e., are configured to perform) certain functionality. In one such instance, the term "memory die" may be used to describe a die that includes one or more ICs that implement memory circuitry (e.g., an IC that implements one or more of a memory device, a memory array, control logic configured to control the memory device and array, etc.). In another such example, the term "compute die" may be used to describe a die that includes one or more ICs that implement logic / compute circuitry (e.g., an IC that implements one or more of I / O functions, arithmetic operations, data pipelining, etc.).

[0037] In another example, the terms "package" and "IC package" are synonymous, and the terms "die", "IC", and "IC die" are also synonymous. Note that the terms "chip", "dielet", "die", "IC", and "IC die" may be used interchangeably herein. The terms "bridge die", "interconnect bridge", and "interconnect die" may be used interchangeably herein.

[0038] Unless otherwise specified, the term "insulate" means "electrically insulate", and the term "conduct" means "electrically conduct". With respect to optical signals and / or devices, components, and elements that operate on or use optical signals, the term "conduct" may also mean "optically conduct".

[0039] The terms "oxide", "carbide", "nitride", etc. refer to compounds that contain oxygen, carbon, nitrogen, etc., respectively.

[0040] The term "high-k dielectric" refers to a material having a dielectric constant higher than that of silicon oxide, while the term "low-k dielectric" refers to a material having a dielectric constant lower than that of silicon oxide.

[0041] The term "insulating material" or "insulator" (also referred to herein as "dielectric material" or "dielectric") refers to a solid material (and / or a liquid material cured after processing as described herein) that substantially does not conduct electricity. They can include, but are not limited to, organic polymers and plastics, as well as inorganic materials such as ionic crystals, porcelain, glass, silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon nitride, and aluminum oxide or combinations thereof. They can include dielectric materials, highly polarizable materials, and / or piezoelectric materials. Dielectric materials can include any suitable dielectric materials commonly used in semiconductor manufacturing, such as silicon and one or more of oxygen, nitrogen, hydrogen, and carbon (e.g., in the form of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride); polyimide materials; or low-k or ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, photoimageable dielectrics, and / or benzocyclobutene-based polymers). Without departing from the scope of the present disclosure, they can be transparent or opaque. Other examples of insulating materials are underfills and molding or molding-like materials used in encapsulation applications, including (e.g.) materials used in organic interposers, encapsulation supports, and other such components.

[0042] In various embodiments, the components associated with an IC can include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, the components associated with an IC can include components monolithically integrated within the IC, components mounted on the IC, or components connected to the IC. The ICs described herein can be analog or digital and can be used in many applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The ICs described herein can be used in a single IC die or as part of a chipset for performing one or more related functions in a computer.

[0043] In various embodiments of the present disclosure, the transistors described herein can be field effect transistors (FETs), such as MOSFETs. In many embodiments, an FET is a four-terminal device. In a silicon-on-insulator or nanoribbon or gate-all-around (GAA) FET, the FET is a three-terminal device including source, drain, and gate terminals, and uses an electric field to control the current flowing through the device. An FET typically includes a channel material, source and drain regions disposed in and / or on the channel material, and a gate stack including gate electrode material (alternatively referred to as "work function" material) disposed over a portion of the channel material ("channel portion") between the source and drain regions, and optionally also including a gate dielectric material between the gate electrode material and the channel material.

[0044] In a general sense, an "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides electrical connectivity between two electrical components, facilitating the transmission of electrical signals between them; an optical interconnect provides an optical connection between two optical components, facilitating the transmission of optical signals between them. As used herein, both electrical and optical interconnects are included in the term "interconnect". The nature of the described interconnects will be understood herein with reference to the signal medium associated therewith. Thus, when used in reference to an electronic device (such as an IC that operates using electrical signals), the term "interconnect" describes any element formed of a conductive material for providing electrical connectivity to one or more elements associated with the IC or / and between various such elements. In such cases, the term "interconnect" may refer to electrical traces (sometimes also referred to as "lines", "wires", "metal lines", or "trenches") and conductive vias (sometimes also referred to as "vias" or "metal vias"). Sometimes, the conductive traces and vias may be referred to as "conductive traces" and "conductive vias" respectively to highlight the fact that these elements include a conductive material such as metal. Similarly, when used in reference to a device that operates on optical signals (such as a PIC), "interconnect" may also describe any element formed of an optically conductive material for providing optical connectivity to one or more elements associated with the PIC. In such cases, the term "interconnect" may refer to optical waveguides, including optical fibers, splitters, optical combiners, optical couplers, and optical vias.

[0045] As used herein, the term "optical element" includes arrangements in the form fabricated in an IC to receive, transform, and / or transmit optical signals as described herein. It may include light conductors such as waveguides, grating couplers, sources of electromagnetic radiation such as lasers, and electro-optic devices such as photodetectors.

[0046] The term "waveguide" refers to any structure for confining and guiding the propagation of light, typically through a substrate material such as silicon or glass, from one location to another. In various examples, waveguides may be formed of silicon, doped silicon, silicon nitride, glass such as silica (e.g., silicon dioxide or SiO2), borosilicate (e.g., 70 wt% to 80 wt% SiO2, 7 wt% to 13 wt% B2O3, 4 wt% to 8 wt% Na2O or K2O, and 2 wt% to 8 wt% Al2O3), etc. Various techniques may be used to form waveguides, including but not limited to in-situ formation of waveguides. For example, in some embodiments, waveguides may be formed in-situ in glass using low-temperature glass-to-glass bonding or by direct laser writing (e.g., laser-written waveguides). In-situ formed waveguides may have lower loss characteristics.

[0047] The term "conductive trace" can be used to describe conductive elements isolated by an insulating material. Within an IC die, such insulating material includes interlayer low-k dielectrics disposed within the IC die. Within a package substrate and a printed circuit board (RGB), such insulating material includes organic materials such as Ajinomoto Build-up Film (ABF), polyimide, or epoxy resin. Such conductive traces are typically disposed in several levels or layers of a metallization stack.

[0048] The term "conductive via" can be used to describe a conductive element that interconnects two or more conductive traces of different levels of a metallization stack. For this purpose, vias can be provided that are substantially perpendicular to the plane of the IC die / chip or support structure on which the IC structure is provided, and the vias can interconnect two conductive traces in adjacent levels or two conductive traces in non-adjacent levels.

[0049] The term "package substrate" can be used to describe any substrate material that facilitates the encapsulation together of any collection of semiconductor dies and / or other electrical components (such as passive electrical components). As used herein, a package substrate can be formed of any material, including but not limited to insulating materials such as resin-impregnated fiberglass (e.g., RGB or printed wiring board (PWB)), glass, ceramic, silicon, silicon carbide, etc. Additionally, as used herein, a package substrate can refer to a substrate that includes build-up layers (e.g., ABF layers).

[0050] The term "metallization stack" can be used to refer to one or more stacked interconnects used to provide connectivity to different circuit components of an IC die / chip and / or a package substrate.

[0051] As used herein, the "pitch" of an interconnect refers to the center-to-center distance between adjacent interconnects.

[0052] The terms "substantially", "close to", "approximate", "near", and "about" generally refer to within + / - 20% of a target value (e.g., within + / - 5% or 10% of the target value) based on the context of a particular value described herein or known in the art.

[0053] Terms indicating the orientation of various elements (e.g., "coplanar", "perpendicular", "orthogonal", "parallel", or any other angle between elements) generally refer to within + / - 5% to + / - 20% of a target value based on the context of a particular value described herein or known in the art.

[0054] The term "connect" refers to a direct connection between things that are connected without any intermediate device (which can be one or more of mechanical, electrical, and / or thermal connections), while the term "couple" refers to a direct connection between things that are connected, or an indirect connection through one or more passive or active intermediate devices.

[0055] The description uses the phrases "in an embodiment" or "in some embodiments", which may each refer to one or more of the same or different embodiments.

[0056] Furthermore, the terms "comprising", "including", "having", etc. used with respect to the embodiments of the present disclosure are synonymous.

[0057] The present disclosure may use perspective-based descriptions such as "above", "below", "top", "bottom", and "side"; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments.

[0058] As used herein, the terms "on", "under", "between", and "over" refer to the relative positioning of one layer or component of a material with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer, or may have one or more intermediate layers. Additionally, a layer disposed between two layers may be in direct contact with one or both of the two layers, or may have one or more intermediate layers. In contrast, a first layer described as "over" a second layer refers to a layer in direct contact with the second layer. Similarly, unless otherwise expressly stated, a feature disposed between two features may be in direct contact with the adjacent features or may have one or more intermediate layers.

[0059] As used herein, the term "disposed" refers to positioning, location, placement, and / or arrangement, rather than any particular method of formation.

[0060] When used in reference to a measurement range, the term "between" includes the endpoints of the measurement range.

[0061] For the purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). As used herein, the symbol "A / B / C" means (A), (B), and / or (C).

[0062] Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, "conductive material" may include one or more conductive materials. In another example, "dielectric material" may include one or more dielectric materials.

[0063] Unless otherwise specified, the use of ordinal adjectives "first", "second", "third", etc. to describe a common object only indicates different instances of like objects being referred to, and is not intended to imply that the objects so described must be in a given sequence in terms of time, space, ranking, or in any other way.

[0064] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which embodiments are shown by way of illustration. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Accordingly, the following detailed description is not limiting.

[0065] The drawings are not necessarily to scale.

[0066] In the drawings, like reference numerals refer to the same or similar elements / materials shown, such that the explanation of an element / material with a given reference numeral provided in the context of one drawing applies to other drawings in which an element / material with the same reference numeral may be shown. Additionally, singular and plural forms of labels may be used with reference numerals to denote single and multiple elements of the same or similar type, kind, or category, respectively.

[0067] Furthermore, in the drawings, some schematic illustrations of example structures of various devices and components described herein may be shown with exact right angles and straight lines, but it is to be understood that when inspecting any structure described herein using, for example, images from suitable characterization tools such as scanning electron microscope (SEM) images, transmission electron microscope (TEM) images, or non-contact profilometers, such schematic illustrations may not reflect real-life process limitations that may cause features to appear not "ideal". In such images of real structures, possible processing and / or surface defects may also be visible, e.g., surface roughness, curvature or profile deviations, pits or scratches, imperfectly straight edges of materials, tapered vias or other openings, unintentional rounding of corners or thickness variations of different material layers, occasional screws, edge or combined dislocations within a crystal region (single or multiple), and / or occasional dislocation defects of individual atoms or atom clusters. There may be other defects not listed here but common in the field of device fabrication and / or packaging.

[0068] Note that in the figures, various components (e.g., interconnects) are shown as aligned (e.g., at corresponding interfaces) merely for ease of illustration; in reality, some or all of them may not be aligned. Additionally, there may be other components within the assemblies, such as bond pads, landing pads, metallization, etc., which are not shown in the figures to prevent clutter. Further, the figures are intended to show the relative arrangement of components within their assemblies, and generally, such assemblies may include other components not shown (e.g., various interface layers or various other components related to optical functionality, electrical connectivity, or thermal mitigation). For example, in some additional embodiments, the assemblies as shown may include more die and other electrical components. Additionally, although some components of the assemblies are shown in the figures as planar rectangles or formed of rectangular solids, this is merely for ease of illustration, and embodiments of these assemblies may be curved, circular, or of other irregular shapes, as dictated by and sometimes inevitable in the manufacturing processes used to fabricate the various components.

[0069] In the figures, a specific number and arrangement of structures and components are presented for illustrative purposes, and any desired number or arrangement of such structures and components may exist in various embodiments.

[0070] Additionally, unless otherwise noted, the structures shown in the figures may take any suitable form or shape depending on material properties, manufacturing processes, and operating conditions.

[0071] For convenience, if there is a set of figures designated by different letters (e.g., Figures 1A - 1D ), then such a set may be referred to herein without the letter (e.g., "Figure 1"). Similarly, if there is a set of reference numerals designated by different numbers or letters (e.g., 104-1, 104-2, etc.), then such a set may be referred to herein without the numbers or letters (e.g., referred to as "104").

[0072] The various operations may be described sequentially as a number of discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations are necessarily order-dependent. In particular, these operations may not be performed in the order presented. The described operations may be performed in a different order than the described embodiments. Various additional operations may be performed, and / or the described operations may be omitted in additional embodiments.

[0073] Figure 1AFIG. 0 is a schematic cross-sectional view of an exemplary microelectronic component 100 in accordance with some embodiments of the present disclosure. The microelectronic component 100 includes a PIC 104, an interposer 103 having through-glass vias (TGVs) 110, and an optical fiber connector 187, where the PIC 104 is electrically coupled to the TGV 110 through an interconnect 106, the pitch between adjacent interconnects 106 is between 2 microns and 70 microns, and the PIC 104 is optically coupled to the optical fiber connector 187 through an optical path 160 passing through the interposer 103. In some embodiments, an example of the interconnect 106 is a hybrid bond, including a metal-metal bond and a dielectric-dielectric bond. As used herein, the terms “microelectronic component,” “photonics package,” “photonics microelectronic component,” and similar variations may be used interchangeably. As used herein, the term “optical path” refers to the path or trajectory by which light travels through an optical medium from one location to another. In some embodiments, the optical path 160 may include one or more waveguides or other structures that guide the optical path.

[0074] The interposer 103 may include a first surface 170-1 (e.g., a bottom surface), an opposite second surface 170-2 (e.g., a top surface), and side surfaces 170-3 that are substantially perpendicular to the first surface 170-1 and the second surface 170-2. In some embodiments, the material of the interposer 103 may include glass. For example, the interposer 103 may include any suitable type of glass known in the art, including but not limited to photoglass, borosilicate glass, soda-lime glass, quartz, or other glass materials. In some embodiments, the glass interposer 103 may include photoimageable glass or other borosilicate-based glasses with oxide additions. In some embodiments, the total thickness (e.g., the z-height) of the interposer 103 may be between 20 microns and 2 millimeters. The TGVs 110 in the interposer 103 may be formed of any suitable conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys. Any suitable process may be used to form the TGVs 110, including, for example, direct laser drilling or a laser-induced deep etching process. In some embodiments, the TGVs 110 disclosed herein may have a pitch between 50 microns and 500 microns. As used herein, the pitch is measured center-to-center (e.g., from the center of a TGV to the center of an adjacent TGV). The TGVs 110 may have any suitable size and shape. In some embodiments, the TGVs 110 may have a circular, rectangular, or other shaped cross-section.

[0075] The PIC 104 may include an active surface 105. A first portion of the active surface 105 of the PIC 104 may be optically coupled to the interposer 103, and a second portion of the active surface 105 may be electrically coupled to the TGV 110 in the interposer 103 through an interconnect 106 (e.g., hybrid bonding). The first portion of the PIC 104 may be physically coupled to the second surface 170-2 of the interposer 103 using any suitable attachment means (e.g., fusion bonding (e.g., as Figure 1A shown) or through an optical adhesive (e.g., optical adhesive 117, as Figure 2A shown)). The fusion bonding (i.e., a dielectric-dielectric bond without a metal-metal bond at the interface) may include a bonding material layer on the bonding surface (e.g., dielectric material 108, as Figure 1Cas shown). In some embodiments, the bonding material may include an inorganic dielectric material, such as silicon and oxygen, nitrogen, and carbon (e.g., in the form of silicon oxide, silicon nitride, or silicon carbide), aluminum and oxygen (e.g., in the form of aluminum oxide), and / or one or more of other forms of inorganic dielectric materials commonly used as interlayer dielectrics (ILDs) in semiconductor devices. In some embodiments, the bonding material may cover the optical elements on the active surface 105 and may serve as a protective layer that maintains the integrity of the optical elements during the manufacturing processes that the PIC 104 may undergo, e.g., the processes are attachment (e.g., by fusion bonding or optical glue), solder reflow, grinding, polishing, underfilling, and molding. The bonding material layer can ensure that, for example, the optical transmission characteristics of the optical elements are not impaired due to contamination by the molding or underfill materials during the manufacturing processes, or the optical functionality is not impaired due to tearing, breaking, or other damaging events during the manufacturing processes. The bonding material layer can also be used to avoid leakage of optical signals from the optical elements including the waveguide 164 during the operation of the PIC 104. For example, when using a silicon oxide material, the bonding material can also be used to provide an oxide-to-oxide bond between the optical elements of the PIC 104 and the interposer 103. In another example, when using a silicon nitride material, the bonding material can be used to provide a nitride-to-nitride bond between the optical elements of the PIC 104 and the interposer 103. The silicon oxide layer in the oxide-to-oxide bond or the silicon nitride layer in the nitride-to-nitride bond can be initially bonded by van der Waals forces and subsequently by high-temperature fusion bonding. The oxide-oxide bond and the nitride-nitride bond can reduce optical signal loss. The optical glue can include any suitable material that allows optical signals to pass through while being used to adhere the PIC 104 and the interposer 103. By way of example and not limitation, the material can include ultraviolet-curable optical adhesives, epoxy resins, silicone resins, modified silanes, and acrylates. The PIC 104 can be optically aligned with the interposer 103 at the bonding interface to minimize optical loss across the optical path 160. In some embodiments, the bonding surface (e.g., the top surface 170-2) of the interposer 103 can be ground and polished to a suitable surface quality so that optical interconnection can be achieved without substantial loss in the optical signal integrity at the bonding interface. In some embodiments, a refractive-index-matching epoxy resin can be used to further reduce optical loss. In some embodiments, optical alignment may not be required because the optical path 160 can be formed after attachment (e.g., in-situ laser-written waveguides).

[0076] A first portion of the active surface 105 of the PIC 104 may include optical elements. In Figure 1B Examples of optical elements above the first portion of the active surface 105 are shown in more detail. Figure 1BIt is a schematic diagram of the surface of the active surface 105 (e.g., see the active surface 105 of PIC 104). Example optical components include an electromagnetic radiation source 166, an electro-optic device 168, and a waveguide 164. In many embodiments, any known method in the art (including semiconductor lithography and deposition methods) can be used to fabricate the optical components on the active surface 105. In some embodiments, the optical components can extend substantially across the entire region (not shown) of the active surface 105. In some embodiments, the optical components can be restricted within a portion of the active surface 105, as shown. In some embodiments, as shown, PIC 104 can be configured to transmit and / or receive optical signals at the active surface 105. For example, PIC 104 can include optical components at the active surface 105, such as grating couplers, which allow PIC 104 to transmit and / or receive light through the active surface 105 (e.g., vertical transmission and reception of light). In some embodiments, PIC 104 can be configured to transmit and / or receive optical signals at a side surface (not shown). In such an example, PIC 104 can include optical components at the active surface 105, such as edge couplers, V-groove arrays, or angled reflectors with grating couplers, which allow PIC 104 to transmit and / or receive light through a side surface that is substantially perpendicular to the active surface 105 (e.g., lateral transmission and reception of light).

[0077] The electromagnetic radiation source 166 can enable the generation of optical signals and can include a laser, for example, if PIC 104 supports wavelengths between approximately 0.8 micrometers and 1.7 micrometers. The electro-optic device 168 can enable the reception, conversion, and transmission of optical signals. In some embodiments, the electro-optic device 168 can be any device or component configured to encode information in / on an electromagnetic signal, such as a modulator, polarizer, phase shifter, and photodetector.

[0078] The waveguide 164 can guide optical signals and also perform coupling, switching, beam splitting, multiplexing, and demultiplexing of optical signals. In some embodiments, the waveguide 164 can include any component configured to feed or emit an electromagnetic signal into a propagation medium such as an optical fiber. In some embodiments, the waveguide 164 can also be configured as an optical multiplexer and / or demultiplexer, for example, to perform wavelength division multiplexing (WDM). In some embodiments, the waveguide 164 can include a demultiplexer such as an arrayed waveguide grating (AWG) demultiplexer, an echelle grating, a single-mode waveguide, or a thin-film filter (TFF) demultiplexer. The waveguide 164 can include any type of planar and non-planar waveguide. In one example, the waveguide 164 can include a silicon photonic waveguide based on a silicon-on-insulator (SOI) platform, which is configured to guide electromagnetic radiation in any wavelength band from about 0.8 micrometers to about 5.0 micrometers. In another example, the waveguide 164 can support wavelengths from about 1.2 micrometers to about 1.7 micrometers in the near-infrared and infrared bands for data communication and telecommunications.

[0079] Although only three such example optical elements are shown in Figure 1B it will be understood that the PIC 104 can include more optical elements of the same or different types, which enable the PIC 104 to be suitably used as a photonic device for receiving, transforming, and transmitting optical and electrical signals.

[0080] Generally, the light provided to the PIC 104 can include any electromagnetic signal (or, in other words, any electromagnetic signal modulated to include information) in which information is encoded. Generally, an electromagnetic signal is a signal associated with optical amplitude, phase, and wavelength, and thus, the description provided herein relates to "optical" signals (or light) and "optical" components. However, as described herein, the photonic microelectronic assembly 100 having the PIC 104 is not limited to operating with electromagnetic signals in the optical spectrum, and the description provided herein with reference to optical signals and / or optical elements equally applies to electromagnetic signals of any suitable wavelength, such as electromagnetic signals in the near-infrared (NIR) and / or infrared (IR) bands and electromagnetic signals in the RF and / or microwave bands.

[0081] The PIC 104 may comprise a semiconductor material, including for example an N-type or P-type material. The PIC 104 may comprise a crystalline substrate formed using, for example, bulk silicon (or other bulk semiconductor material) or a SOI structure (or generally a semiconductor-on-insulator structure). In some embodiments, the PIC 104 may be formed using alternative materials, which may or may not be combined with silicon, including but not limited to lithium niobate, indium phosphide, silicon dioxide, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, aluminum indium arsenide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride or gallium antimonide, or other combinations of group III-N or group IV materials. In some embodiments, the PIC 104 may comprise an amorphous material, such as a polymer. In some embodiments, the PIC 104 may be formed on a printed circuit board (PCB). In some embodiments, the PIC 104 may be heterogeneous, comprising a carrier material (such as glass or silicon carbide) as a substrate having a thin semiconductor layer, above which is the active surface 105. Although several examples of materials for the PIC 104 are described herein, any material or structure that can serve as a basis on which the PIC 104 can be constructed falls within the spirit and scope of the present disclosure.

[0082] The microelectronic component 100 may also include an IC 128. The IC 128 may be electrically coupled to the TGV 110 in the interposer 103 via an interconnect 106. The interconnect 106 may enable an electrical coupling between the PIC 104 and the IC 128. The IC 128 may include any suitable IC functionality. In some embodiments, the IC 128 may include an electro - integrated circuit (EIC) configured to be electrically integrated with the PIC 104 to achieve the intended functionality of the photonic package 100. For example, the EIC may be an application - specific IC (ASIC) that includes one or more switches or driver / receiver circuits used in optical communication systems. In some embodiments, the EIC may include circuitry for communicating between two or more IC die. For example, the EIC may serve as an interconnect bridge that has appropriate circuitry on / within a semiconductor substrate to make connections at silicon interconnect speeds with a small footprint. In some embodiments, the EIC may include active components, including one or more transistors, voltage converters, trans - impedance amplifiers (TIAs), serializer and deserializers (SERDES), clock and data recovery (CDR) components, microcontrollers, etc. In some embodiments, the EIC may include passive circuitry sufficient to enable an interconnect to the PIC 104 and other components in the photonic package 100 without any active components. In some embodiments, the IC 128 may include a processor integrated circuit (XPU) having processing functionality, such as a central processing unit (CPU), a graphics processing unit (GPU), a field - programmable gate array (FPGA), an ASIC, and an accelerator. In various embodiments, the XPU may be or include one or more voltage converters, trans - impedance amplifiers (TIAs), clock and data recovery (CDR) components, microcontrollers, etc. Although Figure 1A the IC 128 is shown as a single IC that may include XPU and / or EIC functionality, in some embodiments, the microelectronic component 100 may include multiple ICs 128 having XPU or EIC functionality coupled via the interconnect 106.

[0083] The microelectronic component 100 may also include a fiber optic connector 187 optically coupled to the interposer 103. The fiber optic connector 187 may also be referred to herein as an "optical component". As Figure 1AAs shown, the fiber optic connector 187 can be physically coupled to the side surface 170-3 (e.g., the lateral surface) of the interposer 103 and optically coupled to the optical path 160 in the interposer 103. In some embodiments, as shown, the fiber optic connector 187 can include a protrusion that physically contacts the second surface 170-2 of the interposer 103 to increase the attachment of the fiber optic connector 187 to the interposer 103. The fiber optic connector 187 can be physically coupled to the interposer 103 using any suitable attachment means (e.g., optical glue or fusion splicing), as described above with reference to the PIC 104.

[0084] The microelectronic component 100 can also include an RDL 148 at the first surface 170-1 of the interposer 103. The RDL 148 can include conductive paths 196 (e.g., including conductive traces, pads / contacts, and / or conductive vias, as shown) through the dielectric material. The RDL 148 can include a set of first conductive contacts 172 on the bottom surface of the RDL 148 and a set of second conductive contacts 174 on the top surface of the RDL 148, where the conductive paths 196 electrically couple individual contacts among the first and second conductive contacts 172, 174. The RDL 148 can be fabricated using any suitable technology, such as RGB technology or redistribution layer technology. In some embodiments, the dielectric material of the RDL 148 can include: oxide materials, such as silicon and oxygen (e.g., in the form of silicon oxide); nitride materials, such as silicon and nitrogen (e.g., in the form of silicon nitride); or organic materials. The RDL 148 can be electrically coupled to the PIC 104 and the IC 128 through the TGV 110 in the interposer 103. In some embodiments, the RDL148 can be omitted (e.g., as Figure 2A shown). In some embodiments, the RDL 148 can be included at both the first surface 170-1 and the second surface 170-2 of the interposer 103 (not shown).

[0085] Figure 1AThe microelectronic component 100 may further include a circuit board 131. In some embodiments, the circuit board 131 may be a package substrate. In particular, the conductive contact portion 172 on the bottom surface of the RDL 148 may be electrically coupled to the conductive contact portion 146 on the top surface of the circuit board 131 through an interconnect 190. The interconnect 190 disclosed herein may take any suitable form. The interconnect 190 may be any suitable interconnect, including solder balls for a ball grid array arrangement, pins in a pin grid array arrangement, or lands in a land grid array arrangement. In some embodiments, a set of interconnects 190 may include solder 136 (e.g., solder bumps or balls that are subjected to thermal reflow to form the interconnect 190). The interconnect 190 including solder may include any suitable solder material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys. In some embodiments, a set of interconnects 190 may include an anisotropic conductive material, such as an anisotropic conductive film or an anisotropic conductive paste. The anisotropic conductive material may include conductive materials dispersed in a non-conductive material. In some embodiments, the anisotropic conductive material may include microscopic conductive particles embedded in an adhesive or a thermosetting adhesive film (e.g., a thermosetting biphenyl-based epoxy resin or an acrylic-based material). In some embodiments, the conductive particles may include polymers and / or one or more metals (e.g., nickel or gold). For example, the conductive particles may include gold coated with nickel or copper coated with silver, which is in turn coated with a polymer. In another example, the conductive particles may include nickel. When the anisotropic conductive material is not compressed, there may be no conductive path from one side of the material to the other side. However, when the anisotropic conductive material is sufficiently compressed (e.g., by conductive contact portions on either side of the anisotropic conductive material), the conductive materials near the compressed region may contact each other to form a conductive path from one side of the film to the other side in the compressed region. In some embodiments, the interconnect 190 disclosed herein may have a pitch between about 50 microns and 300 microns.

[0086] Figure 1AThe microelectronic component 100 may also include an underfill material 127. In some embodiments, the underfill material 127 may extend between the RDL 148 and the circuit board 131 around the associated interconnect 190. The circuit board 131 may be, for example, a motherboard and may have other components attached thereto. As is known in the art, the circuit board may include conductive paths and other conductive contacts for routing power, ground, and signals through the circuit board. In some embodiments, the interconnect 190 may not be coupled to the circuit board 131 but may instead be coupled to another IC package, an interposer, or any other suitable component. The underfill material 127 may be an insulating material, such as a suitable epoxy material. In some embodiments, the underfill material 127 may include a capillary underfill, a non-conductive film (NCF), or a molded underfill. In some embodiments, the underfill material 127 may include an epoxy flux that aids in soldering when forming the interconnect 190 and then polymerizes and encapsulates the interconnect 190. The underfill process may include dispensing the underfill material in a liquid form, allowing the material to flow and fill the space between the RDL 148 and the interposer 103 and the interstitial gaps around the interconnect 190, and subjecting the component to a curing process (such as baking) to cure the material. In some embodiments, the underfill material 127 may be omitted. The underfill material 127 may be selected to have a coefficient of thermal expansion (CTE) that can mitigate or minimize the stress between the RDL 148 and the circuit board 131 caused by non-uniform thermal expansion in the microelectronic component 100. In some embodiments, the CTE of the underfill material 127 may have a value intermediate between the CTE of the RDL 148 (e.g., the CTE of the dielectric material of the RDL 148) and the CTE of the insulating material of the circuit board 131.

[0087] In some embodiments, the microelectronic component 100 may include one or more layers of solder mask (e.g., epoxy liquid, liquid photoimageable polymer, dry film photoimageable polymer, acrylic resin, solvent) that may be disposed in the IC package described herein and may not be labeled or shown to avoid cluttering the drawings. The solder mask may be a liquid or dry film material that includes a photoimageable polymer. In some embodiments, the solder mask may be non-photoimageable.

[0088] Figure 1CIs a schematic cross-sectional view of the details of a particular one of the interconnects 106 in the microelectronic component 100. Note that although only the interconnect 106 is shown, the same structures and descriptions can apply to any other such interconnects including hybrid joints in the microelectronic component 100, where applicable, such as photoimageable dielectric (RID) or liquid metal ink (LMI) interconnects with copper-copper joints. In a general sense, the interconnect 106 can include a metal-metal joint between the bond pad 132 of layer 102-1 and the bond pad 134 of layer 102-2 at the interface 130 between layers 102-1 and 102-2, as well as a dielectric-dielectric joint (e.g., oxide-oxide joint) in the dielectric material 108 of layers 102-1 and 102-2. In some embodiments, layer 102-2 can be included in the PIC 104 or IC 128, and layer 102-1 can be included in the interposer 103. The bond pad 132 of layer 102-1 can be joined to the bond pad 134 of layer 102-2. The dielectric materials 108 in layers 102-1 and 102-2 can be joined to each other. The dielectric material 108 can include inorganic materials such as silicon and one or more of oxygen, nitrogen, and carbon (e.g., in the form of silicon oxide, silicon nitride, or silicon carbide), and / or other forms of inorganic dielectric materials commonly used as interlayer dielectrics (ILDs) in semiconductor devices. The joined metal and dielectric materials form the interconnect 106, including the hybrid joint, thereby providing electrical and mechanical coupling between layers 102-1 and 102-2. In various embodiments, the interconnect 106 can have a linear dimension of less than 5 microns and a pitch of less than 10 microns between adjacent interconnects. In some embodiments, the interconnect 106 can have a pitch between 2 microns and 70 microns (e.g., between 2 microns and 10 microns, between 10 microns and 45 microns, or between 45 microns and 70 microns).

[0089] Figure 1D Is Figure 1A A top view of the microelectronic component. As Figure 1D shown, the microelectronic component 100 can include a plurality of ICs 128 and a plurality of PICs 104 electrically coupled to the interposer 103 through the interconnects 106 (e.g., as Figure 1A shown), as well as a plurality of fiber optic connectors 187, and the plurality of fiber optic connectors 187 are optically coupled to the plurality of PICs 104 through the optical paths 160 in the interposer 103. As Figure 1DAs shown, an individual PIC in PIC 104 can be optically coupled to an individual fiber optic connector in fiber optic connector 187 through an optical path 160 in mediator 103; one or more fiber optic connectors 187 can be optically coupled to an individual PIC 104 through an optical path 160 in mediator 103; and one or more PICs can be optically coupled to other PICs 104 through an optical path 160 in mediator 103. Although Figure 1D microelectronic assembly 100 is shown having three ICs 128, three PICs 104, and four fiber optic connectors 187, microelectronic assembly 100 can have any suitable number and arrangement of ICs 128, PICs 104, and fiber optic connectors 187, as well as any suitable number and arrangement of electrical and optical connections therebetween.

[0090] Figure 2A is a schematic cross-sectional view of another exemplary microelectronic assembly in accordance with some embodiments of the present disclosure. Except for the differences further described, the configuration of the embodiment shown in the figure is similar to Figure 1A that of. The configuration of microelectronic assembly 100 as described herein includes a first PIC 104-1 and a second PIC 104-2, as well as a first fiber optic connector 187-1 and a second fiber optic connector 187-2, wherein the first PIC 104-1 is optically coupled to the first fiber optic connector 187-1 through a first optical path 160-1 passing through mediator 103, the second PIC 104-2 is optically coupled to the second fiber optic connector 187-2 through a second optical path 160-2 passing through mediator 103, and the first PIC 104-1 is optically coupled to the second PIC 104-2 through a third optical path 160-3 passing through mediator 103. As Figure 2B shown, the bonding interface between the first and second PICs 104-1, 104-2 and mediator 103 can include an optical adhesive 117, as referenced above with respect to Figure 1A described. The first and second PICs 104-1, 104-2 can be electrically coupled to IC 128 through interconnects 106, TGVs 110 (not shown), and conductive paths 196 passing through RDL 148. The first PIC 104-1 and the second PIC 104-2 can also be electrically coupled to each other through interconnects 106, TGVs 110 (not shown), and conductive paths 196 passing through RDL 148.

[0091] Figure 2B is Figure 2A a magnified cross-sectional view of a portion of the microelectronic assembly of. As Figure 2B shown, the bonding interface between PIC 104 and mediator 103 can include an optical adhesive 117 at the active surface 105 of PIC 104, as referenced above with respect to Figure 1AThe bonding interface may also include an anti - reflection coating 119 located on the top surface of the interposer 103 to improve light efficiency and reduce light reflection or leakage. In some embodiments, openings 113 may be formed through the optical adhesive 117 to reduce light reflection or loss at the bonding interface. Although Figure 2B a bonding interface including the optical adhesive 117 is shown, the bonding interface between the PIC 140 and the interposer 103 may include a bonding material (e.g., a dielectric material 108 as Figure 1A shown) having openings 113 and / or reflective material 119.

[0092] Figure 2C is Figure 2A a top - view of a microelectronic assembly. As Figure 2C shown, the microelectronic assembly 100 may include a plurality of ICs 128 and a plurality of PICs 104 electrically coupled to the interposer 103 through interconnects 106 (not shown), and a plurality of optical fiber connectors 187, where the plurality of optical fiber connectors 187 are optically coupled to the plurality of PICs 104 through optical paths 160 in the interposer 103. As Figure 2C shown, individual PICs in the PIC 104 may be optically coupled to individual optical fiber connectors in the optical fiber connectors 187 through the optical paths 160 in the interposer 103; one or more optical fiber connectors 187 may be optically coupled to individual PICs 104 through the optical paths 160 in the interposer 103; and one or more PICs may be optically coupled to other PICs 104 through the optical paths 160 in the interposer 103. Although Figure 2C a microelectronic assembly 100 having two ICs 128, eight PICs 104, and eleven optical fiber connectors 187 is shown, the microelectronic assembly 100 may have any suitable number of ICs 128, PICs 104, and optical fiber connectors 187, as well as any suitable number and arrangement of electrical and optical connections therebetween.

[0093] Any suitable techniques may be used to fabricate the microelectronic assembly 100 disclosed herein. For example, Figures 3A to 3E is a side - cross - sectional view of various stages in an exemplary process for fabricating Figure 2A the microelectronic assembly 100 according to various embodiments. Although the operations discussed below with reference to Figures 3A - 3E (and other figures representing manufacturing processes) are shown in a particular order, these operations may be performed in any suitable order. Additionally, additional operations not shown may be performed without departing from the scope of the present disclosure. Further, other operations for fabricating the microelectronic assembly 100 disclosed herein may be modified according to the present disclosure with respect to the various operations Figures 3A to 3E discussed herein.

[0094] Figure 3AShows the assembly after forming the bonding layer 124 on the top surface 170-2 of the interposer 103. The interposer 103 can include a first surface 170-1, a second surface 170-2, and a side surface 170-3. The bonding layer 124 can include bonding pads 132 in the dielectric material 108, as referred to above with reference to Figure 1C described. The bonding layer 124 can include a region 197 of dielectric material without bonding pads 132, where the dielectric material can be subsequently removed, as referred to below with reference to Figure 3B described. In some embodiments, the assembly can include an interposer 103 having a preformed waveguide therein forming an optical path 160. In some embodiments, the interposer 103 can include one or more optical paths or one or more portions of an optical path. In some embodiments, the interposer 103 may not include an optical path or a portion of an optical path, and instead, the optical path can be formed in-situ. The interposer 103 can further include TGVs (e.g., Figure 2A the TGV 110 in) (not shown), which can be preformed or can be formed by creating via openings through the interposer 103 and depositing a conductive material in the via openings.

[0095] Figure 3B Illustrates the assembly after removing the region 197 of dielectric material to expose the second surface 170-2 of the interposer 103 and forming optical paths 160-1, 160-2, 160-3 through the interposer 103. Any suitable technique can be used to remove the dielectric material, including etching, mechanical milling, or laser ablation. The second surface 170-2 of the interposer 103 can be further subjected to grinding and polishing to form an optically smooth surface. The optical paths 160-1, 160-2, 160-3 can be formed using any suitable technique, e.g., by direct laser writing to form the waveguide in-situ.

[0096] Figure 3C Shows the assembly after electrically coupling the IC 128 and the PICs 104-1, 104-2 by forming the interconnects 106 and physically and optically coupling the PICs 104-1, 104-2 (e.g., a first PIC 104-1 and a second PIC 104-2) to the interposer 103. The IC 128 and the PICs 104 can include a bonding layer at the bottom surface, which has bonding pads 134 in the dielectric material 108 (e.g., as Figure 1Cas shown). The bonding pads 132 of the interposer 103 can correspond to the bonding pads 134 of the IC 128 and the PIC 104 for forming a hybrid direct bond (e.g., the interconnect 106). The active surfaces 105 of the PICs 104-1, 104-2 can be physically attached to the active surface 105 of the PIC 104 using any suitable technique (including the optical adhesive 117 as shown, or fusion bonding). The IC 128 and the PIC 104 can be placed using any suitable method, such as automated pick and place. Figure 3C The components of can undergo appropriate bonding processes to form the interconnect 106. For example, the bonding process can include applying suitable pressure and heating to a suitable temperature (e.g., to a moderately high temperature, e.g., between about 50 and 200 degrees Celsius) for a period of time.

[0097] Figure 3D Illustrates the components after forming the RDL 148 at the first surface 170-1 of the interposer 103. The RDL 148 can include a conductive path 196 between the first conductive contact 172 and the second conductive contact 174. The RDL 148 can be fabricated using any suitable technique, such as PCB technology or redistribution layer technology.

[0098] Figure 3E Illustrates the components after physically attaching the fiber optic connectors 187-1, 187-2 to the second surface 170-2 of the interposer 103 and optically aligning them with the corresponding optical paths 160-1, 160-2 and performing a finishing operation. If desired, the fiber optic connectors 187-1, 187-2 can be optically aligned and optically coupled using any suitable technique (such as an optical adhesive or fusion bonding). Example finishing operations include depositing a solder mask (not shown) and depositing solder 136 on the bottom surface of the conductive contact 172 of the RDL 148. If multiple components are fabricated together, the components can be singulated. Figure 3E The components of can themselves be the microelectronic component 100, as shown. Can be performed on Figure 3E The microelectronic component 100 of can undergo further manufacturing operations to form other microelectronic components 100. For example, Figure 3E The solder 136 of the microelectronic component 100 of can be electrically coupled to the circuit board 131 to form an interconnect 190, similar to Figure 2A the microelectronic component 100 of.

[0099] Figure 4is a flow chart of an example method of fabricating an example microelectronic component according to various embodiments. At 402, a bonding layer 124 including bonding pads 132 in a dielectric material 108 may be formed on a surface 170-2 of an interposer 103. In some embodiments, the interposer 103 may include glass. In some embodiments, the interposer 103 may include at least a portion of an optical path 160 and TGVs 110. The bonding layer 124 may include a portion 197 of the dielectric material 108 that does not have bonding pads 132. At 404, the portion 197 of the dielectric material 108 may be removed to expose the surface 170-2 of the interposer 103 and an optical path 160 may be formed. Any suitable process (including grinding) may be used to remove the dielectric material 108. The optical path 160 may be formed by any suitable technique (including direct laser writing). At 406, an IC 128 and a PIC 104 may be electrically coupled to the TGVs 110 in the interposer 103. The IC 128 and the PIC 104 may include a bonding layer at a bottom surface that has bonding pads 134 in the dielectric material 108 (e.g., as Figure 1C shown). The bonding pads 132 of the interposer 103 may correspond to the bonding pads 134 of the IC 128 and the PIC 104 for forming a hybrid direct bond (e.g., an interconnect 106). The PIC 104 may be optically aligned with the optical path 160 as needed and attached to the surface 170-2 of the interposer 103 using any suitable technique (including an optical adhesive or fusion bonding). At 408, an optical fiber connector 187 (e.g., also referred to herein as an optical component) may be optically coupled to the interposer 103 such that the optical fiber connector 187 is optically coupled to the PIC 104 through the optical path 160 that passes through the interposer 103. The optical fiber connector 187 may be optically aligned as needed and physically attached using any suitable technique (including an optical adhesive or fusion bonding). At 410, as needed, a surface finishing operation may be performed and singulation may occur. The surface finishing operation may include, for example, dispensing a solder mask and attaching solder balls.

[0100] The packages disclosed herein (e.g., any microelectronic component 100 or any other embodiment described herein) may be included in any suitable electronic component. Figures 5 - 7 Shows various examples of packages, components, and devices that may be used with or include any IC package disclosed herein.

[0101] Figure 5 is a side cross-sectional view of an example IC package 2200 that may include an IC package according to any embodiment disclosed herein. In some embodiments, the IC package 2200 may be a SiP.

[0102] As shown, the encapsulation substrate 2252 can be formed of an insulator (e.g., ceramic, stacked film, epoxy film with filler particles therein, etc.), and can have conductive paths extending through the insulator between a first side 2272 and a second side 2274 or between different locations on the first side 2272 and / or between different locations on the second side 2274. These conductive paths can be in the form of any interconnect structure including lines and / or vias.

[0103] The encapsulation substrate 2252 can include conductive contacts 2263, which are coupled to the conductive paths 2262 through the encapsulation substrate 2252, thereby allowing the circuitry within the die 2256 and / or the interposer 2257 to be electrically coupled to respective ones of the conductive contacts 2264 (or other devices included in the encapsulation substrate 2252, not shown).

[0104] The IC package 2200 can include an interposer 2257 coupled to the encapsulation substrate 2252 via conductive contacts 2261 of the interposer 2257, first - level interconnects 2265, and conductive contacts 2263 of the encapsulation substrate 2252. The first - level interconnects 2265 shown in the figure are solder bumps, but any suitable first - level interconnects 2265 can be used, such as solder bumps, solder pillars, or bond wires.

[0105] The IC package 2200 can include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254 of the die 2256, first - level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 can be coupled through the interposer 2257 to conductive paths (not shown), thereby allowing the circuitry within the die 2256 to be electrically coupled to respective ones of the conductive contacts 2261 (or other devices included in the interposer 2257, not shown). The first - level interconnects 2258 shown in the figure are solder bumps, but any suitable first - level interconnects 2258 can be used, such as solder bumps, solder pillars, or bond wires. As used herein, a "conductive contact" can refer to a portion of a conductive material (e.g., metal) that serves as an interface between different components; the conductive contact can be recessed into the surface of the component, flush with the surface of the component, or extend away from the surface of the component, and can take any suitable form (e.g., a conductive pad or socket).

[0106] In some embodiments, underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first-level interconnect 2265, and the molding 2268 may be disposed around the die 2256 and the interposer 2257 and contact the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the molding 2268. Example materials that may be used for the underfill material 2266 and the molding 2268 are suitable epoxy resins. The second-level interconnect 2270 may be coupled to the conductive contact 2264. The second-level interconnect 2270 shown in the figure is a solder ball (e.g., for a ball grid array (BGA) arrangement), but any suitable second-level interconnect 2270 may be used (e.g., pins in a pin grid array arrangement or pads in a land grid array arrangement). The second-level interconnect 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and as discussed below with reference to Figure 6 discussed.

[0107] In various embodiments, any die 2256 may be the microelectronic component 100 as described herein. In embodiments where the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The die 2256 may include circuitry for performing any desired functionality. For example, in addition to one or more of the dies 2256 being the microelectronic component 100 as described herein, one or more of the dies 2256 may be logic dies (e.g., silicon-based dies), one or more of the dies 2256 may be memory dies (e.g., HBM), etc. In some embodiments, any die 2256 may be implemented as discussed with reference to any of the previous figures. In some embodiments, at least some of the dies 2256 may not include the implementation as described herein.

[0108] Although the IC package 2200 shown in the figure is a flip-chip package, other package architectures may be used. For example, the IC package 2200 may be a BGA package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer-level chip-scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are shown in the IC package 2200, the IC package 2200 may include any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first side 2272 or the second side 2274 of the package substrate 2252 or on either side of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the art.

[0109] In some embodiments, the interposer 2257 may not be included in the IC package 2200; instead, the die 2256 may be directly coupled to the conductive contact 2263 at the first side 2272 through the first-level interconnect 2265.

[0110] Figure 6 is a cross-sectional side view of an IC device assembly 2300 that can include a component having one or more microelectronic components 100 according to any of the embodiments disclosed herein. The IC device assembly 2300 includes a plurality of components disposed on a circuit board 2302 (which can be, for example, a motherboard). The IC device assembly 2300 includes components disposed on a first side 2340 of the circuit board 2302 and on an opposite second side 2342 of the circuit board 2302; generally, components can be disposed on one or both sides 2340 and 2342. In particular, according to any of the embodiments disclosed herein, any suitable component of the IC device assembly 2300 can include any one of the one or more microelectronic components 100; for example, any IC package discussed below with reference to the IC device assembly 2300 can take the form of any of the embodiments of the IC package 2200 discussed above with reference to Figure 5 discussed.

[0111] In some embodiments, the circuit board 2302 can be a PCB that includes a plurality of metal layers separated from each other by insulator layers and interconnected by conductive vias. Any one or more of the metal layers can be formed in a desired circuit pattern to route electrical signals (optionally in combination with other metal layers) between components coupled to the circuit board 2302. In other embodiments, the circuit board 2302 can be a non-PCB package substrate.

[0112] As shown, in some embodiments, the IC device assembly 2300 can include an on-interposer package structure 2336 coupled to the first side 2340 of the circuit board 2302 by a coupling component 2316. The coupling component 2316 can electrically and mechanically couple the on-interposer package structure 2336 to the circuit board 2302 and can include solder balls (as shown), male and female portions of a socket, an adhesive, underfill material, and / or any other suitable electrical coupling and / or mechanical coupling structure.

[0113] The on-interposer package structure 2336 can include an IC package 2320 coupled to the interposer 2304 by a coupling component 2318. The coupling component 2318 can take any suitable form according to the desired functionality, such as the forms discussed above with reference to the coupling component 2316. In some embodiments, the IC package 2320 can be or include the IC package 2200, for example, as discussed above with reference to Figure 5As described above. In some embodiments, the IC package 2320 may include at least one microelectronic component 100 as described herein. For the sake of not cluttering the drawings, the microelectronic component 100 is not specifically shown in the figures.

[0114] Although a single IC package 2320 is shown in the figure, multiple IC packages may be coupled to the interposer 2304; in fact, additional interposers may be coupled to the interposer 2304. The interposer 2304 may provide an intermediate packaging substrate for bridging the circuit board 2302 and the IC package 2320. Generally, the interposer 2304 may redistribute connections to a wider pitch or rewire connections to different connections. For example, the interposer 2304 may couple the IC package 2320 to the BGA of the coupling component 2316 to couple to the circuit board 2302.

[0115] In the embodiment shown in the figure, the IC package 2320 and the circuit board 2302 are attached to opposite sides of the interposer 2304. In other embodiments, the IC package 2320 and the circuit board 2302 may be attached to the same side of the interposer 2304. In some embodiments, three or more components may be interconnected through the interposer 2304.

[0116] The interposer 2304 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or a polymeric material such as polyimide. In some embodiments, the interposer 2304 may be formed of alternative rigid or flexible materials, which may include the same materials used in semiconductor substrates described above, such as silicon, germanium, and other group III-V and group IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to TSVs 2306. The interposer 2304 may also include embedded devices 2314, including passive and active devices. Such devices may include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2304. The interposer-on-package structure 2336 may take the form of any of the interposer-on-package structures known in the art.

[0117] In some embodiments, the IC device assembly 2300 may include an IC package 2324 coupled to the first surface 2340 of the circuit board 2302 through a coupling component 2322. The coupling component 2322 may take the form of any of the embodiments discussed above with reference to the coupling component 2316, and the IC package 2324 may take the form of any of the embodiments discussed above with reference to the IC package 2320.

[0118] In some embodiments, the IC device assembly 2300 may include a package - on - package structure 2334 coupled to the second surface 2342 of the circuit board 2302 via a coupling member 2328. The package - on - package structure 2334 may include an IC package 2326 and an IC package 2332 coupled together via a coupling member 2330 such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling members 2328 and 2330 may take the form of any embodiment of the coupling member 2316 discussed above, and the IC package 2326 and / or 2332 may take the form of any embodiment of the IC package 2320 discussed above. The package - on - package structure 2334 may be configured according to any package - on - package structure known in the art.

[0119] Figure 7 is a block diagram of an exemplary computing device 2400 that may include one or more components having one or more IC packages according to any embodiment disclosed herein. For example, any suitable component of the computing device 2400 may include a microelectronic component (e.g., 100) according to any embodiment disclosed herein. In another example, any one or more components of the computing device 2400 may include any embodiment of the IC package 2200 (e.g., as Figure 5 shown). In yet another example, any one or more components of the computing device 2400 may include the IC device assembly 2300 (e.g., as Figure 6 shown).

[0120] Multiple components are shown in the figure as being included in the computing device 2400, but any one or more of these components may be omitted or duplicated as suitable for the application. In some embodiments, some or all of the components included in the computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single SoC die.

[0121] Additionally, in various embodiments, the computing device 2400 may not include one or more components shown in the figure, but the computing device 2400 may include interface circuitry for coupling to one or more components. For example, the computing device 2400 may not include a display device 2406, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 2406 may be coupled. In another set of examples, the computing device 2400 may not include an audio input device 2418 or an audio output device 2408, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 2418 or the audio output device 2408 may be coupled.

[0122] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that may be stored in registers and / or memory. The processing device 2402 may include one or more DSPs, ASICs, CPUs, GPUs, cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing device. The computing device 2400 may include a memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard disk drive. In some embodiments, the memory 2404 may include a memory that shares a die with the processing device 2402. This memory may be used as a cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0123] In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, the communication chip 2412 may be configured to manage wireless communications for transferring data to and from the computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may transfer data by using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not include any wires.

[0124] The communication chip 2412 can implement any one of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standard (e.g., IEEE802.16-2005 amendment), LTE project, and any amendments, updates, and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16 compliant broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, which is an acronym for Worldwide Interoperability for Microwave Access, and is a certification mark for products that pass the IEEE 802.16 standard's compliance and interoperability tests. The communication chip 2412 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 2412 can operate according to Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and above. In other embodiments, the communication chip 2412 can operate according to other wireless protocols. The computing device 2400 can include an antenna 2422 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0125] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2412 can include multiple communication chips. For example, a first communication chip 2412 can be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2412 can be dedicated to long-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication chip 2412 can be dedicated to wireless communications, and the second communication chip 2412 can be dedicated to wired communications.

[0126] The computing device 2400 may include a battery / power circuitry 2414. The battery / power circuitry 2414 may include one or more energy storage devices (e.g., a battery or a capacitor) and / or circuitry for coupling components of the computing device 2400 to an energy source (e.g., AC line power) that is separate from the computing device 2400.

[0127] The computing device 2400 may include a display device 2406 (or corresponding interface circuitry, as described above). The display device 2406 may include any visual indicator, such as, for example, a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0128] The computing device 2400 may include an audio output device 2408 (or corresponding interface circuitry, as described above). The audio output device 2408 may include any device that generates an audible indicator, such as, for example, a speaker, headphones, or earbuds.

[0129] The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry, as described above). The audio input device 2418 may include any device that produces a signal representative of sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., an instrument having a Musical Instrument Digital Interface (MIDI) output).

[0130] The computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry, as described above). As is known in the art, the GPS device 2416 may communicate with a satellite-based system and may receive the location of the computing device 2400.

[0131] The computing device 2400 may include other output devices 2410 (or corresponding interface circuitry, as described above). Examples of other output devices 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0132] The computing device 2400 may include other input devices 2420 (or corresponding interface circuitry, as described above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device (such as a mouse), a stylus, a touchpad, a barcode reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0133] The computing device 2400 can have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, smartphone, mobile Internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 can be any other electronic device that processes data.

[0134] The foregoing description of the illustrated embodiments of the present disclosure (including what is described in the abstract) is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. While specific embodiments and examples of the present disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as will be recognized by those skilled in the art.

[0135] Example 1 is a photonics component, comprising: an interposer having a surface, wherein the material of the interposer comprises glass and the interposer comprises through-glass vias (TGVs); a photonic integrated circuit (PIC) optically coupled to the surface of the interposer by an optical adhesive or fusion bonding and electrically coupled to the TGVs in the interposer by hybrid bonding interconnects; and an optical component coupled to the interposer, wherein the optical component is optically coupled to the PIC by an optical path passing through the interposer.

[0136] Example 2 can include the subject matter of Example 1, and can further specify that: the optical component is a fiber optic connector.

[0137] Example 3 can include the subject matter of Example 1 or 2, and can further specify that: the hybrid bonding interconnects have a pitch between adjacent interconnects of 2 microns and 70 microns.

[0138] Example 4A can include the subject matter of any one of Examples 1-3, and can further specify that: the optical path includes a waveguide passing through the interposer.

[0139] Example 4B can include the subject matter of Example 4A, and can further specify that: the waveguide passing through the interposer is a laser-written waveguide.

[0140] Example 5 can include the subject matter of any one of Examples 1-4, and can further specify that: the optical component is coupled to the interposer by an optical adhesive or fusion bonding.

[0141] Example 6 may include the subject matter of any one of Examples 1-5, and may further specify that: the PIC is a first PIC, the hybrid bonding interconnect is a first hybrid bonding interconnect, the optical component is a first optical component, and the optical path is a first optical path, and the photon component may further include: a second PIC optically coupled to the surface of the interposer by optical glue or fusion bonding and electrically coupled to the TGV in the interposer by a second hybrid bonding interconnect; a second optical component coupled to the interposer, wherein the second optical component is optically coupled to the second PIC by a second optical path passing through the interposer.

[0142] Example 7 may include the subject matter of Example 6, and wherein the first PIC is optically coupled to the second PIC by a third optical path passing through the interposer.

[0143] Example 8 may include the subject matter of any one of Examples 1-7, and may further specify that: the hybrid bonding interconnect is a first hybrid bonding interconnect, and the photon component may further include: an IC electrically coupled to the TGV in the interposer by a second hybrid bonding interconnect.

[0144] Example 9 may include the subject matter of Example 8, and may further specify that: the IC includes an electrical integrated circuit or a processor integrated circuit.

[0145] Example 10 may include the subject matter of any one of Examples 1-9, and may further specify that: the surface of the interposer is a second surface, the interposer further includes a first surface opposite to the second surface, and the photon component may further include: a dielectric material on the first surface of the interposer, the dielectric material including a conductive path electrically coupled to the TGV in the interposer; and a circuit board electrically coupled to the conductive path in the dielectric material.

[0146] Example 11 may include the subject matter of any one of Examples 1-5, and may further specify that: the optical component is one of a plurality of optical components, and the PIC is one of a plurality of PICs, and wherein an individual optical component among the plurality of optical components is coupled to an individual PIC among the plurality of PICs by an optical path passing through the interposer.

[0147] Example 12 is a photon component, comprising: a mediator having a first surface, an opposite second surface, and side surfaces substantially perpendicular to the first surface and the second surface, wherein the material of the mediator comprises glass, and the mediator comprises through-glass vias (TGVs); a photonic integrated circuit (PIC) and an integrated circuit (IC) electrically coupled to the TGVs at the second surface of the mediator by interconnections having a pitch between 2 micrometers and 70 micrometers between adjacent interconnections, and the PIC is optically coupled to the second surface of the mediator by an optical adhesive or fusion bonding; and an optical component coupled to the side surface of the mediator, wherein the optical component is optically coupled to the PIC by an optical path passing through the mediator.

[0148] Example 13 may include the subject matter of Example 12 and may further specify that: the optical component is an optical fiber connector.

[0149] Example 14 may include the subject matter of Example 12 or 13 and may further specify that: the optical component is coupled to the side surface of the mediator by an optical adhesive or fusion bonding.

[0150] Example 15 may include the subject matter of any one of Examples 12-14 and may further specify that: the optical path includes a waveguide passing through the mediator.

[0151] Example 16 may include the subject matter of Example 15 and may further specify that: the waveguide passing through the mediator is a laser-written waveguide.

[0152] Example 17 may include the subject matter of any one of Examples 12-16 and may further specify that: the PIC is electrically coupled to the IC through the TGVs.

[0153] Example 18 may include the subject matter of any one of Examples 12-17 and may further specify that: the optical component is a first optical component, and the optical path is a first optical path, and the photon component may further include: a second optical component at the side surface of the mediator, wherein the second optical component is optically coupled to the PIC by a second optical path passing through the mediator.

[0154] Example 19 is a photon component, including: a mediator having a first surface and an opposite second surface, wherein the material of the mediator includes glass, and the mediator includes through-glass vias (TGVs); a plurality of photonic integrated circuits (PICs) optically coupled to the surface of the mediator by optical glue or fusion bonding and electrically coupled to the TGVs in the mediator through interconnections; and a plurality of optical components coupled to the mediator, the plurality of optical components being optically coupled to the plurality of PICs through an optical path passing through the mediator.

[0155] Example 20 may include the subject matter of Example 19 and may further specify that: the plurality of optical components are fiber optic connectors.

[0156] Example 21 may include the subject matter of Example 19 or 20 and may further specify that: the optical path includes a waveguide passing through the mediator.

[0157] Example 22 may include the subject matter of any one of Examples 19-21 and may further specify that: the plurality of optical components are coupled to the mediator by optical glue or fusion bonding.

[0158] Example 23 may include the subject matter of any one of Examples 19-22 and may further specify that: the optical path is a first optical path, and the photon component may further include: a second optical path passing through the mediator, the second optical path optically coupling a corresponding PIC in the plurality of PICs to other corresponding PICs in the plurality of PICs.

[0159] Example 24 may include the subject matter of any one of Examples 19-23 and may further specify that: the interconnection is a first interconnection, and the photon component may further include: an IC electrically coupled to the TGVs in the mediator through a second interconnection.

[0160] Example 25 may include the subject matter of Example 24 and may further specify that: the IC includes an electrical integrated circuit or a processor integrated circuit.

Claims

1. A photon component, comprising: An interposer having a surface, wherein the material of the interposer comprises glass and the interposer includes through-glass vias (TGVs); A photonic integrated circuit (PIC) optically coupled to the surface of the interposer by optical glue or fusion bonding and electrically coupled to the TGVs in the interposer by hybrid bonding interconnections; and An optical component coupled to the interposer, wherein the optical component is optically coupled to the PIC by an optical path passing through the interposer.

2. The photon component according to claim 1, wherein, The optical component is an optical fiber connector.

3. The photon component according to claim 1 or 2, wherein, The hybrid bonding interconnections have a pitch between adjacent interconnections of 2 micrometers and 70 micrometers.

4. The photon component according to any one of claims 1-3, wherein, The optical path includes a waveguide passing through the interposer.

5. The photon component according to any one of claims 1-4, wherein, The optical component is coupled to the interposer by optical glue or fusion bonding.

6. The photon component according to any one of claims 1-5, wherein, The PIC is a first PIC, the hybrid bonding interconnections are first hybrid bonding interconnections, the optical component is a first optical component, and the optical path is a first optical path, and the photonic assembly further comprises: A second PIC optically coupled to the surface of the interposer by optical glue or fusion bonding and electrically coupled to the TGVs in the interposer by second hybrid bonding interconnections; A second optical component coupled to the interposer, wherein the second optical component is optically coupled to the second PIC by a second optical path passing through the interposer.

7. The photon component according to claim 6, and wherein, The first PIC is optically coupled to the second PIC by a third optical path passing through the interposer.

8. The photon component according to any one of claims 1-7, wherein, The hybrid bonding interconnections are first hybrid bonding interconnections, and the photonic assembly further comprises: An IC electrically coupled to the TGVs in the interposer by second hybrid bonding interconnections.

9. The photon component according to claim 8, wherein, The IC includes an electrical integrated circuit or a processor integrated circuit.

10. The photon component according to any one of claims 1-9, wherein, The surface of the interposer is a second surface, the interposer further includes a first surface opposite the second surface, and the photonic assembly further comprises: A dielectric material on the first surface of the interposer, the dielectric material including conductive paths electrically coupled to the TGVs in the interposer; and A circuit board electrically coupled to the conductive paths in the dielectric material.

11. The photon component according to any one of claims 1-5, wherein, The optical component is one of a plurality of optical components, and the PIC is one of a plurality of PICs, and wherein individual optical components of the plurality of optical components are coupled to individual PICs of the plurality of PICs by optical paths passing through the interposer.

12. A photon component, comprising: An interposer having a first surface, an opposite second surface, and side surfaces substantially perpendicular to the first and second surfaces, wherein the material of the interposer comprises glass and the interposer includes through-glass vias (TGVs); A photonic integrated circuit (PIC) and an integrated circuit (IC), the photonic integrated circuit (PIC) and the integrated circuit (IC) being electrically coupled to the TGV through an interconnect with a pitch between adjacent interconnects between 2 micrometers and 70 micrometers at the second surface of the interposer, and the PIC being optically coupled to the second surface of the interposer by optical glue or fusion bonding; and An optical component coupled to the side surface of the interposer, wherein the optical component is optically coupled to the PIC through an optical path passing through the interposer.

13. The photon component according to claim 12, wherein, The optical component is an optical fiber connector.

14. The photon component according to claim 12 or 13, wherein, The optical component is coupled to the side surface of the interposer by optical glue or fusion bonding.

15. The photon component according to any one of claims 12-14, wherein, The optical path includes a waveguide passing through the interposer.

16. The photon component according to claim 15, wherein, The waveguide passing through the interposer is a laser-written waveguide.

17. The photon component according to any one of claims 12 - 16, wherein, The PIC is electrically coupled to the IC through the TGV.

18. The photon component according to any one of claims 12 - 17, wherein, The optical component is a first optical component, and the optical path is a first optical path, and the photonic assembly further includes: A second optical component at the side surface of the interposer, wherein the second optical component is optically coupled to the PIC through a second optical path passing through the interposer.

19. A photon component, comprising: An interposer having a first surface and an opposite second surface, wherein the material of the interposer includes glass and the interposer includes through-glass vias (TGVs); A plurality of photonic integrated circuits (PICs) optically coupled to the surface of the interposer by optical glue or fusion bonding and electrically coupled to the TGVs in the interposer through interconnects; and A plurality of optical components coupled to the interposer, the plurality of optical components being optically coupled to the plurality of PICs through optical paths passing through the interposer.

20. The photon component according to claim 19, wherein, The plurality of optical components are optical fiber connectors.

21. The photon component according to claim 19 or 20, wherein, The optical path includes a waveguide passing through the interposer.

22. The photon component according to any one of claims 19 - 21, wherein, The plurality of optical components are coupled to the interposer by optical glue or fusion bonding.

23. The photon component according to any one of claims 19 - 22, wherein, The optical path is a first optical path, and the photonic assembly further includes: A second optical path passing through the interposer, the second optical path optically coupling a corresponding PIC among the plurality of PICs to other corresponding PICs among the plurality of PICs.

24. The photon component according to any one of claims 19 - 23, wherein, The interconnect is a first interconnect, and the photonic assembly further includes: An IC electrically coupled to the TGV in the interposer through a second interconnect.

25. The photon component according to claim 24, wherein, The IC includes an electrical integrated circuit or a processor integrated circuit.

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