Using least reliable bit energy function to bypass iterations in bit flipping decoders

Abstract

A bit flipping decoder receives a codeword stored in a memory device. The bit flipping decoder determines a plurality of energy function values of the codeword and a least unreliable one of the energy function values of the codeword. The bit flipping decoder increments an iteration count in response to the bit flipping decoder determining that the least unreliable energy function value fails to meet a bit flipping criterion for a current iteration. The incrementation of the iteration count bypasses a comparison of the plurality of energy function values to the bit flipping criterion of the current iteration.

Description

Technical Field

[0001] The present disclosure generally relates to error correction in memory devices, and more specifically, to a bit flip decoder using the least reliable bit energy function value to bypass one or more decoding iterations. Background Art

[0002] A memory subsystem may include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at and retrieve data from the memory devices. Brief Description of the Drawings

[0003] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be regarded as limiting the present disclosure to a particular embodiment, but are for explanation and understanding only.

[0004] Figure 1 Illustrates an example computing system including a memory subsystem in accordance with some embodiments of the present disclosure.

[0005] Figure 2 Is a flowchart of an example method in accordance with some embodiments of the present disclosure for using the least reliable bit energy function value to provide a bit flip to bypass one or more decoding iterations.

[0006] Figure 3 Illustrates a block diagram of an exemplary table including a maximum energy function value and a bit flip threshold for iterations of a bit flip decoder in accordance with some embodiments.

[0007] Figure 4 Is a flowchart of another example method in accordance with some embodiments of the present disclosure for using the least reliable bit energy function value to provide a bit flip to bypass one or more decoding iterations.

[0008] Figure 5 Is a block diagram of an example computer system in which embodiments of the present disclosure may operate. Detailed Description

[0009] Aspects of the present disclosure relate to a bit flip decoder using the least reliable bit energy function value to bypass one or more decoding iterations in a memory subsystem. The memory subsystem can be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices and memory modules are described below in connection with Figure 1 Generally, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data stored at the memory subsystem and may request data retrieved from the memory subsystem.

[0010] The memory device can be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. An example of a non-volatile memory device is a NAND (Negative-AND) memory device. Other examples of non-volatile memory devices are described below in conjunction with Figure 1 this. The dies in the package can be assigned to one or more channels for communication with the memory subsystem controller. Each die can be composed of one or more planes. A plane can be divided into logical units (LUNs). For some types of non-volatile memory devices (such as NAND memory devices), each plane is composed of a group of physical blocks, and a physical block is a group of memory cells for storing data. A cell is an electronic circuit that stores information.

[0011] Depending on the cell type, a cell can store one or more bits of binary information and have various logical states related to the number of bits stored. The logical states can be represented by binary values such as "0" and "1" or combinations of such values. There are various types of cells, such as single-level cells (SLCs), multi-level cells (MLCs), triple-level cells (TLCs), and quad-level cells (QLCs). For example, an SLC can store one bit of information and has two logical states.

[0012] Low-density parity-check (LDPC) codes are often used to implement error correction in a memory subsystem. LDPC codes are a class of high-efficiency linear block codes that include single-parity-check (SPC) codes. LDPC codes have high error correction capabilities and can provide performance close to the Shannon channel capacity. An LDPC decoder uses a "belief propagation" algorithm, which is an iterative exchange of reliability information based on, for example, "confidence". The min-sum algorithm (MSA) (which is a simplified version of the belief propagation algorithm) can be used to decode LDPC codes. A decoder based on the MSA uses a relatively high energy per bit (e.g., picojoules per bit) to decode a codeword and is therefore not very suitable for energy-saving applications such as mobile applications.

[0013] A bit-flip (BF) decoder has been introduced to address this problem. Compared with a decoder based on the MSA, the BF decoder uses less energy per bit at the cost of lower error correction capabilities. In each decoding iteration, the BF decoder evaluates each bit and flips the least reliable bit to correct an error. The least reliable bit is identified by comparing a threshold with the value of the energy function of each bit. The bit-flip threshold can be determined, for example, based on a heuristic process and / or optimized using a machine learning algorithm. Additionally, the bit-flip threshold can vary between decoding iterations. For a given iteration, the comparison of the energy function of each bit with the bit-flip threshold may not result in any bit flips. In other words, although one or more bits may be in error, no bit is eligible to be flipped using the bit-flip threshold for the current iteration. These "no-flip iterations" result in longer decoding times and lower decoder throughput.

[0014] Aspects of the present disclosure address the above and other disadvantages by utilizing the least reliable bit energy function value of a codeword and bypassing one or more iterations of the bit - flip decoding process when the least reliable bit energy function value does not meet a bit - flip threshold. A bit - flip decoder may iterate, for example, at a bit - flip threshold satisfied by the least reliable bit energy function value and cause the decoder to flip one or more bits in the codeword. Thus, the bit - flip decoder can complete the decoding process with improved latency and reduced power consumption.

[0015] Figure 1 An example computing system 100 including a memory subsystem 110 in accordance with some embodiments of the present disclosure is illustrated. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non - volatile memory devices (e.g., memory device 130), or a combination thereof.

[0016] The memory subsystem 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid - state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in - line memory modules (DIMMs), small outline DIMMs (SO - DIMMs), and various types of non - volatile dual in - line memory modules (NVDIMMs).

[0017] The computing system 100 can be, for example, a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, an automobile, or other transportation vehicle), an Internet of Things (IoT) - enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, an industrial device, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0018] The computing system 100 can include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a single memory subsystem 110 is illustrated. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intermediary component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0019] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (such as an NVDIMM controller), and a storage protocol controller (such as a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110 to write data to the memory subsystem 110 and read data from the memory subsystem 110, for example.

[0020] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include (but are not limited to) a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (such as a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 may further utilize the Non-Volatile Memory Express (NVMe) interface to access components (such as the memory device 130). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is described as an example. In general, the host system 120 may access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0021] The memory device 130 / 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (such as the memory device 140) may be (but is not limited to) a Random Access Memory (RAM), such as a Dynamic Random Access Memory (DRAM) and a Synchronous Dynamic Random Access Memory (SDRAM).

[0022] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memories and in-situ write memories, such as three-dimensional cross-point ("3D cross-point") memory devices that are cross-point arrays of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on a change in bulk resistance in combination with a stackable cross-gate format data access array. Thus, compared to many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, in which non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0023] Although non-volatile memory devices such as NAND-type memories (e.g., 2D NAND, 3D NAND) and 3D cross-point arrays of non-volatile memory cells have been described, memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0024] Memory subsystem controller 115 (or simply controller 115) can communicate with memory device 130 to perform operations such as reading data, writing data, or erasing data at memory device 130 and other such operations (e.g., in response to commands scheduled on a command bus by controller 115). Memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic for performing the operations described herein. Memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0025] The memory subsystem controller 115 may include a processing device 117 (processor) configured to execute instructions stored in local memory 119. In the illustrative example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0026] In some embodiments, the local memory 119 may include memory registers for storing memory pointers, fetching data, etc. The local memory 119 may also include a read-only memory (ROM) for storing microcode. Although the example memory subsystem 110 in Figure 1 has been illustrated as including a memory subsystem controller 115, in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem 110).

[0027] Generally, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130 and / or the memory devices 140. The memory subsystem controller 115 may be responsible for other operations such as wear-leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory devices 130. The memory subsystem controller 115 may further include host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory devices 130 and / or the memory devices 140 and convert responses associated with the memory devices 130 and / or the memory devices 140 into information for the host system 120.

[0028] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive an address from the memory subsystem controller 115 and decode the address to access the memory devices 130.

[0029] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device that is an original memory device combined with a local controller (e.g., the local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] The memory subsystem 110 includes an error corrector 113 (e.g., an encoder and / or decoder) that can encode and decode data stored in the memory device. In some embodiments, the controller 115 includes at least a portion of the error corrector 113. For example, the controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, the error corrector 113 is part of the host system 120, an application, or an operating system.

[0031] Encoding data using an error correction code (ECC) allows for the correction of erroneous data bits when the data is retrieved from the memory device. For example, the error corrector 113 may encode data received from the host system 120 and store the data and parity bits as a codeword in the memory device 130. The error corrector 113 may further decode the data stored in the memory device 130 to identify and correct the error bits in the data and then transmit the corrected data to the host system 120. Although illustrated as a single component capable of performing encoding and decoding of data, the error corrector 113 may be / include separate components. In some embodiments, the error corrector 113 encodes data according to a low density parity check (LDPC) code.

[0032] Error corrector 113 uses a BF decoder to decode the codewords stored in memory device 130. For example, error corrector 113 receives the codewords stored in memory device 130. Error corrector 113 performs error correction on the codewords in a set of iterations, such as by using the energy function values of the bits to flip the bits in one or more iterations. The energy function value of a codeword bit is an indication of the reliability of the codeword bit. In some embodiments, the energy function value of a codeword bit is determined based on the number of parity violations per codeword bit and the channel information. The channel information is determined based on the current state of the bit (e.g., after one or more iterations of the BF decoder) and the state of the bit read from the memory device (also referred to as a hard bit). As described below, error corrector 113 implements an enhanced BF decoder that can use the least reliable bit energy function value to perform bit flip decoding to efficiently bypass one or more decoding iterations. More details regarding the operation of error corrector 113 are described below.

[0033] Figure 2 is a flowchart of an example method 200 that uses the least reliable bit energy function value to provide bit flips to bypass one or more decoding iterations in accordance with some embodiments of the present disclosure. Method 200 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 200 is executed by Figure 1 error corrector 113. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Accordingly, not every embodiment requires all of the processes. Other process flows are possible.

[0034] At operation 205, the processing device receives a codeword from the memory device. In some embodiments, the codeword is received from host system 120 during a read operation. The codeword may include a combination of data bits and parity bits. For example, each of the data bits and parity bits is a hard bit generated by reading a memory cell to determine the state of the memory cell (e.g., “0” or “1”). Additionally, each data bit may be verified by multiple parity bits.

[0035] In one embodiment, the processing device optionally receives soft information of a codeword. In addition to the bits of the codeword, the soft information may also include bits received from the memory device. In some embodiments, the memory device may be operable to determine the soft information of a hard read. In other embodiments, the memory device does not generate and does not transmit soft information to the processing device. In some embodiments, the memory device generates soft information for some but not all of the codewords it transmits and transmits the soft information to the processing device. The soft information may indicate the confidence level regarding the hard data bits. For example, the soft information may indicate a high confidence level regarding the hard data bits and the hard data bits may be referred to as strong bits. Alternatively, the soft information may indicate a low confidence level in the hard data bits and the hard data bits are referred to as weak bits.

[0036] In some embodiments, the soft information indicates a specific voltage to which the memory cell is charged (where the memory cell is the memory cell from which the hard data bit is read). In these embodiments, the hard data bit is less reliable (i.e., a weak bit) when its associated soft information indicates that the memory cell is charged to a specific voltage close to the boundary between the two states; and the hard data bit is more reliable (i.e., a strong bit) when its associated soft information indicates that the memory cell is charged to a specific voltage close to the center of the voltage range corresponding to the state (“0” or “1”).

[0037] In some embodiments, for each bit of the hard data bits of a codeword, the soft information includes at most one soft bit. The soft bit of the hard data bit indicates whether the hard data bit is a strong bit or a weak bit. For example, the soft bit may be “0” when its associated hard data bit is weak and “1” when its associated hard data bit is strong. In some embodiments, the number of bits of the soft information of a codeword is strictly less than the number of bits of the codeword. For example, the processing device may receive the indices of the strong bits in the codeword. Alternatively, the processing device may receive the indices of the weak bits in the codeword to reduce the amount of information transmitted from the memory device 130 to the error corrector 113. In some embodiments, for each bit of the hard data bits of a codeword, the soft information includes more than one soft bit. For example, when the soft information includes 2 soft bits, this results in 4 reliability levels for the bits, such as very weak, weak, strong, and very strong.

[0038] At operation 210, the processing device determines an energy function value for a bit of a codeword. The energy function of a codeword bit is an indication of the reliability information of the bit. The error corrector 113 may determine the energy function value of a bit of a codeword based on the number of unsatisfied parity checks of the bit and the channel information of this bit. In some embodiments, a higher number of unsatisfied parity checks of a bit indicates a less reliable bit and results in a higher energy function value for the bit. Similarly, a lower number of unsatisfied parity checks (a higher number of satisfied parity checks) of a bit indicates a more reliable bit and results in a lower energy function value for the bit. The channel information is determined based on the current state of the bit as compared to the state of the bit when the bit was read from the memory device. For example, the channel information of a bit may be defined as the XOR of the current state of the bit (which may have flipped during one or more decoding iterations) and the bit read from the memory device. In this example, the channel information has a value of "1" when there is a mismatch and a value of "0" when the current state of the bit matches the state when the bit was read. A bit is considered more reliable when the current state of the bit is consistent with the state when the bit was read from the memory device. In a non-limiting example, the energy function may be determined according to Equation (1):

[0039] e(bit) = number of parity violations(bit) + channel information(bit) (1)

[0040] The energy function value of a bit is lower when the current state of the bit is consistent with the hard bit received from the memory device as compared to when the current state of the bit is inconsistent with the hard bit. In one embodiment, the error corrector 113 determines the energy function value by retrieving the energy function value of a bit of a codeword from a look-up table based on the number of parity violations of the bit and the channel information of the bit.

[0041] In addition, the error corrector 113 may use soft information to determine the energy function. Continuing with the above example values of "1" as the soft bit value for a strong bit and "0" as the soft bit value for a weak bit, the energy function may, for example, be the number of parity violations plus the channel information minus the soft bit value.

[0042] Similarly, in the above example, a higher e(bit) value indicates a less reliable bit and a lower e(bit) value indicates a more reliable bit. In other embodiments, a high energy function value of a bit indicates a more reliable bit and a low energy function value of a bit indicates a less reliable bit. In this embodiment, the energy function may be determined, for example, by adding the number of satisfied parity checks to the negative of the channel information value. In some embodiments, the error corrector 113 uses scalar values and / or weighted values in addition to parity checks and channel information to determine the energy function value. For example, different rows, columns, or other distinct locations within the memory may be determined to be more or less reliable. Thus, the error corrector 113 may scale or weight the energy function values of bits in these locations.

[0043] In addition to determining the energy function value for each bit, the processing device also flips those bits that satisfy the bit flip criterion of the iterative bit flip decoder. For example, the error corrector 113 evaluates each bit of the codeword by comparing its energy function value with the bit flip criterion of the current iteration to determine whether to flip the bit. When the energy function value of a bit of the codeword does not satisfy the bit flip criterion, the error corrector 113 does not flip the bit. When the energy function value of a bit of the codeword satisfies the bit flip criterion, the error corrector 113 flips the bit. The bit flip criterion may also be referred to herein as bit flip or energy function value threshold. When the energy function value of a bit satisfies the threshold, the error corrector 113 determines to flip the bit. For example, the error corrector 113 may flip the bit when the energy function value of the bit is greater than or equal to the threshold and not flip the bit when the energy function value of the bit is less than the threshold.

[0044] At operation 215, the processing device determines the energy function value of the least reliable bit in the codeword for the initial decoder iteration. For example, when a higher energy function value indicates a less reliable bit, the error corrector 113 determines the maximum value of the energy function values of the codeword. In one embodiment, the error corrector 113 uses the first energy function value as the initial maximum value, compares each determined current energy function value with the maximum value, and updates the maximum value when the current energy function value exceeds the maximum value (e.g., when determining the energy function value in operation 210).

[0045] When the processing device flips a bit in operation 210, the processing device updates the energy function value of the codeword. For example, flipping one or more bits of the codeword may change the number of unsatisfied parity checks and / or the channel information of the codeword. Therefore, the error corrector 113 determines the new energy function value of the bit. In one embodiment, the error corrector 113 only determines the updated energy function values of those bits affected by the flipping of one or more bits and bypasses the determination of the energy function values of the bits whose energy function values will not change. If applicable, the error corrector 113 also determines the updated value of the least reliable energy function value (e.g., the new maximum value).

[0046] In addition, the processing device increments the iteration count to advance to the next iteration. As further described below, the bit flip criterion may be different between iterations. The error corrector 113 may use the current iteration count to look up or otherwise determine the current bit flip criterion. In addition, the error corrector 113 may use the iteration count to determine whether the stop criterion is satisfied.

[0047] At operation 220, at the start of the current decoder iteration (i), the processing device determines whether the least reliable energy function value from the previous decoder iteration (i - 1) satisfies the bit - flip criterion for the current iteration of the bit - flip decoding process. For example, when the maximum value of the energy function values of the codeword from the previous iteration (i - 1) is greater than or equal to the bit - flip criterion, the error corrector 113 determines that at least one bit in the codeword will be flipped in the current iteration. On the other hand, when the maximum value of the energy function values of the codeword from the previous iteration (i - 1) is less than the bit - flip criterion, the error corrector 113 determines that no bits will be flipped in the current iteration. When the least reliable energy function value satisfies the bit - flip criterion, method 200 proceeds to operation 225 to flip one or more bits in the current iteration of the decoding process. When the least reliable energy function value fails to satisfy the bit - flip criterion, the error corrector 113 has determined that no bits will be flipped, bypasses the comparison of the other energy function values of the codeword with the bit - flip criterion, and method 200 proceeds to operation 235.

[0048] At operation 225, when the energy function value of a given bit of the codeword satisfies the bit - flip criterion, the processing device flips one or more bits of the codeword. For example, similar to the description of operation 210, the error corrector 113 may traverse the codeword in a predetermined order and evaluate each bit of the codeword by comparing its energy function value with the bit - flip criterion for the current iteration to determine whether to flip the bit. When the energy function value of a bit of the codeword does not satisfy the bit - flip criterion, the error corrector 113 does not flip the bit. When the energy function value of a bit of the codeword satisfies the bit - flip criterion, the error corrector 113 flips the bit.

[0049] At operation 230, the processing device updates the energy function values of the codeword. For example, flipping one or more bits of the codeword may change the number of unsatisfied parity checks and / or the channel information of the codeword. Thus, the error corrector 113 determines the new energy function values of the bits. In one embodiment, the error corrector 113 only determines the updated energy function values of those bits that are affected by the flipping of one or more bits and bypasses the determination of the energy function values of the bits whose energy function values will not change. If applicable, the error corrector 113 also determines the updated value of the least reliable energy function value (e.g., the new maximum value). Thus, the error corrector 113 tracks the energy values of the least reliable bits for each iteration and uses this energy function in one or more subsequent iterations to decide whether to skip an iteration (bypass the comparison of the other energy function values of the codeword with the bit - flip criterion).

[0050] At operation 235, the processing device increments / increases the iteration count. As further described below, the bit - flip criterion may vary between iterations. The error corrector 113 may use the current iteration count to look up or otherwise determine the current bit - flip criterion. Additionally, the error corrector 113 may use the iteration count to determine whether the stop criterion is satisfied.

[0051] At operation 240, the processing device determines whether a stop criterion is met. The stop criterion may include an indication that no errors are detected in the codeword. In some embodiments, the stop criterion may include a zero syndrome (i.e., 0 unsatisfied parity checks), which indicates that the codeword no longer contains error bits. In some embodiments, the stop criterion may include a maximum number of iterations or a maximum amount of time. For example, error corrector 113 may be operable to perform a maximum number of iterations (e.g., 30 iterations, 40 iterations, 100 iterations, etc.), and when this number of iterations is reached, error corrector 113 outputs the resulting corrected codeword. When the stop criterion is not met, error corrector 113 performs another iteration. For example, when the stop criterion is not met, method 200 returns to operation 220, and error corrector 113 determines whether the least reliable energy function value satisfies the bit flip criterion for the subsequent iteration, which may vary between iterations (described further below). When the stop criterion is met, method 200 proceeds to operation 245.

[0052] At operation 245, the processing device outputs the corrected codeword or a failure indication when the processing device is unable to decode the codeword. For example, error corrector 113 may transmit the corrected codeword or the failure indication to host 120. In one embodiment, the failure indication triggers an upgrade of the decoding process. For example, error corrector 113 may use an MSA decoder to decode the codeword in response to a BF decoder failure.

[0053] Figure 3 Block diagram illustrating exemplary table 300 including least reliable / maximum energy function values and bit flip criteria for iterations of a bit flip decoder according to some embodiments. Although Figure 3 specific examples of iteration count, maximum energy function value, and bit flip criteria are illustrated, the illustrated examples should only be understood as examples. Other mappings of iteration count to bit flip criteria are possible.

[0054] Table 300 includes an iteration count 305 from 0 to N, a maximum energy function value per iteration 310, and a bit flip criterion per iteration 315. As described above, the error corrector 113 determines the energy function value of a bit based on the number of its associated unsatisfied parity checks and the channel information. Using the determined energy function value, the processing device determines the least reliable bit / energy function value 310 (e.g., the maximum energy function value) of the previous iteration (i-1), which will be used in the current iteration (i) to decide whether to bypass the comparison of other energy function values with the bit flip criterion of the current iteration (i). The error corrector 113 can make this determination in the current iteration, as indicated by the iteration count 305, or in the previous iteration. In one embodiment, the error corrector 113 uses Table 300 or another data structure to map the current iteration count 305 to the corresponding bit flip criterion 315. For example, the error corrector 113 can store and maintain a copy of Table 300 in the memory device 130 / 140 and / or the local memory 119.

[0055] Using the example values in Table 300, the maximum energy function value 310 satisfies (e.g., is greater than) the bit flip criterion 315 in iterations 0, 1, and 2. In each of these iterations, the error corrector 113 compares the energy function value of the codeword with the bit flip criterion and thus flips one or more bits. However, when the iteration count 305 reaches iteration 3, the maximum energy function value 310 does not satisfy the bit flip criterion 315 (e.g., 4 is less than 5). As described above, the maximum energy function value 310 of 4 in iteration 3 corresponds to the maximum energy function value calculated in iteration 2 for use in iteration 3. Thus, the error corrector 113 bypasses the comparison of the codeword energy function value (other than the maximum value) with the bit flip criterion and proceeds to the next iteration. Compared to iteration 3, the value of the bit flip criterion 315 decreases in iteration 4. In some embodiments, when the maximum energy function value 310 equals the bit flip criterion 315, it is determined that the bit flip criterion 315 is satisfied. In other embodiments, when the maximum energy function value 310 equals the bit flip criterion 315, it is determined that the bit flip criterion 315 is not satisfied and the iteration continues to bypass the comparison of the energy function value with the bit flip criterion 315 until the maximum energy function value 310 exceeds the bit flip criterion 315, e.g., in iteration 5.

[0056] Figure 4 is a flowchart of another example method 400 that uses the least reliable bit energy function value to provide bit flips to bypass one or more decoding iterations according to some embodiments of the present disclosure. Method 400 can be executed by processing logic, which can include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, the hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 400 is performed by Figure 1The error corrector 113 performs. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, not every embodiment requires all of the processes. Other process flows are possible.

[0057] At operation 405, the processing device receives a codeword from the memory device. As described with reference to operation 205, the codeword may be received from the host system 120 during the execution of a read operation and includes a combination of data bits and parity bits.

[0058] At operation 410, the processing device determines an energy function value for a bit of the codeword. For example, the processing device may use one or more of the number of unsatisfied parities of the bit of the codeword, channel information for this bit, optional soft information, and / or a weight / scalar of the position of the bit within the memory device 130 to determine the energy function value for the bit, as described with reference to operation 210.

[0059] At operation 415, the processing device determines an energy function value for the least reliable bit in the codeword. For example, the processing device determines the maximum value among the energy function values of the codeword, as described with reference to operation 215.

[0060] At operation 420, the processing device determines that the least reliable energy function value fails to satisfy the bit flip criterion for the current iteration of the bit flip decoding process. For example, the error corrector 113 maps the current iteration count to the bit flip criterion, as described with reference to Figure 3 and compares the least reliable energy function value with the bit flip criterion, as described with reference to operation 220 above.

[0061] At operation 425, the processing device increments / increases the iteration count in response to determining that the least reliable energy function value fails to satisfy the bit flip criterion for the current iteration. As described above, the error corrector 113 saves processing power and time by bypassing the comparison of the other energy function values of the codeword with the bit flip criterion and proceeding to the next iteration.

[0062] Figure 5 An example machine of a computer system 500 is illustrated, within which a set of instructions may be executed to cause the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 500 may correspond to a host system (e.g., Figure 1 the host system 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 the memory subsystem 110) or may be used to perform the operations of a controller (e.g., for executing an operating system to perform operations corresponding to Figure 1operation of the error corrector 113). In alternative embodiments, the machine can be connected (e.g., networked) to other machines on a LAN, intranet, extranet, and / or the Internet. The machine can operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0063] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge or any machine capable of executing a set of instructions (sequentially or otherwise) that specify actions to be taken by the machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0064] Example computer system 500 includes a processing device 502, a main memory 504 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0065] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or multiple processors implementing a combination of instruction sets. Processing device 502 can also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 can further include a network interface device 508 to communicate via a network 520.

[0066] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methodologies or functions described herein. The instructions 526 may also reside, at least partially, within the main memory 504 and / or the processing device 502 during execution by the computer system 500, which also constitutes a machine-readable storage medium. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 the memory subsystem 110.

[0067] In one embodiment, the instructions 526 include instructions for implementing functionality corresponding to a bit flip decoder (e.g., implemented by the Figure 1 error corrector 113). Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methodologies of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0068] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0069] However, it should be borne in mind that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the memories or registers or other such information storage systems of the computer system.

[0070] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. For example, a computer system or other data processing system (such as controller 115) may implement computer-implemented methods 200 and 400 in response to its processor executing a computer program (such as a sequence of instructions) contained in a memory or other non-transitory machine-readable storage medium. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to the computer system bus.

[0071] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used in conjunction with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized devices to perform the method. The structure of various such systems will appear as set forth in the claims appended hereto. Additionally, the present disclosure has been described without reference to any particular programming language. It should be understood that various programming languages may be used to implement the teachings of the present disclosure described herein.

[0072] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform a process in accordance with the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (such as a computer). In some embodiments, the machine-readable (such as computer-readable) medium includes a machine (such as a computer) readable storage medium, such as read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, and the like.

[0073] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It should be understood that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure set forth in the appended claims. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A method, comprising: Receive a codeword stored in a memory device; Determine a plurality of energy function values of the codeword; Determine the most unreliable one of the energy function values of the codeword; Determine that the most unreliable energy function value fails to meet a bit - flip criterion for a current iteration of bit - flip decoding of the codeword; And Increment an iteration count in response to determining that the most unreliable energy function value fails to meet the bit - flip criterion, wherein the incrementing of the iteration count bypasses the comparison of the plurality of energy function values with the bit - flip criterion of the current iteration.

2. The method according to claim 1, wherein the bit - flipping criterion for the current iteration is different from the bit - flipping criterion for subsequent iterations and the least reliable energy function value satisfies the bit - flipping criterion for the subsequent iterations.

3. The method according to claim 2, further comprising: Flip a bit in response to determining that the energy function value of the bit of the codeword meets the bit - flip criterion of the subsequent iteration.

4. The method according to claim 1, further comprising: Determine that the most unreliable energy function value also fails to meet a bit - flip criterion for a subsequent iteration of bit - flip decoding of the codeword; And Increment the iteration count again in response to determining that the most unreliable energy function value fails to meet the bit - flip criterion of the subsequent iteration.

5. The method according to claim 1, wherein the least reliable energy function value is determined during a previous iteration of the bit - flipping decoding of the codeword.

6. The method according to claim 1, wherein determining the energy function value of the codeword comprises: retrieving the energy function value of a bit of the codeword from a look - up table using the number of unsatisfied parity checks and channel information, the channel information indicating whether the current state of the bit is the same as the state of the bit read from the memory device.

7. The method according to claim 6, wherein determining the energy function value of the codeword further comprises using soft information associated with the bit of the codeword, wherein the soft bit indicates whether the bit of the codeword is strong or weak.

8. A non - transitory computer - readable storage medium, comprising instructions that, when executed by a processing device, cause the processing device to: receive a codeword stored in a memory device; Determine a plurality of energy function values of the codeword; Determine the most unreliable one of the energy function values of the codeword; Determine that the most unreliable energy function value fails to meet a bit - flip criterion for a current iteration of bit - flip decoding of the codeword; And Increment an iteration count in response to determining that the most unreliable energy function value fails to meet the bit - flip criterion, wherein the incrementing of the iteration count bypasses the comparison of the plurality of energy function values with the bit - flip criterion of the current iteration.

9. The non - transitory computer - readable storage medium according to claim 8, wherein the bit - flipping criterion for the current iteration is different from the bit - flipping criterion for subsequent iterations and the least reliable energy function value satisfies the bit - flipping criterion for the subsequent iterations.

10. The non-transitory computer-readable storage medium according to claim 9, wherein the processing device is further configured to: Flip the bit in response to determining that the energy function value of the bit of the codeword satisfies the bit flip criterion for the subsequent iteration.

11. The non-transitory computer-readable storage medium according to claim 8, wherein the processing device is further configured to: Determine that the least reliable energy function value also fails to satisfy the bit flip criterion for the subsequent iteration of the bit flip decoding of the codeword; and Increment the iteration count again in response to determining that the least reliable energy function value fails to satisfy the bit flip criterion for the subsequent iteration.

12. The non-transitory computer-readable storage medium according to claim 8, wherein the least reliable energy function value is determined during a previous iteration of the bit flip decoding of the codeword.

13. The non-transitory computer-readable storage medium according to claim 8, wherein determining the energy function value of the codeword comprises: Retrieving the energy function value of the bit of the codeword from a look-up table using the number of unsatisfied parity checks and channel information, the channel information indicating whether the current state of the bit is the same as the state of the bit read from the memory device.

14. The non-transitory computer-readable storage medium according to claim 13, wherein determining the energy function value of the codeword further comprises using soft information associated with the bit of the codeword, wherein the soft bit indicates whether the bit of the codeword is strong or weak.

15. A system, comprising: Memory device; And A processing device operably coupled to the memory device to: Receive a codeword stored in the memory device; Determine a plurality of energy function values of the codeword; Determine the most unreliable one of the energy function values of the codeword; Determine that the most unreliable energy function value fails to meet a bit - flip criterion for a current iteration of bit - flip decoding of the codeword, wherein the most unreliable energy function value among the energy function values is determined during a previous iteration of bit - flip decoding of the codeword; and Increment an iteration count in response to determining that the most unreliable energy function value fails to meet the bit - flip criterion, wherein the incrementing of the iteration count bypasses the comparison of the plurality of energy function values with the bit - flip criterion of the current iteration.

16. The system according to claim 15, wherein the bit flip criterion for the current iteration is different from the bit flip criterion for a subsequent iteration and the least reliable energy function value satisfies the bit flip criterion for the subsequent iteration.

17. The system according to claim 16, wherein the processing device is further configured to: Flip the bit in response to determining that the energy function value of the bit of the codeword satisfies the bit flip criterion for the subsequent iteration.

18. The system according to claim 15, wherein the processing device is further configured to: Determine that the least reliable energy function value also fails to satisfy the bit flip criterion for the subsequent iteration of the bit flip decoding of the codeword; and Increment the iteration count again in response to determining that the least reliable energy function value fails to satisfy the bit flip criterion for the subsequent iteration.

19. The system according to claim 15, wherein determining the energy function value of the codeword comprises: Retrieving the energy function value of the bit of the codeword from a look-up table using the number of unsatisfied parity checks and channel information, the channel information indicating whether the current state of the bit is the same as the state of the bit read from the memory device.

20. The system according to claim 19, wherein determining the energy function value of the codeword further comprises using soft information associated with the bit of the codeword, wherein the soft bit indicates whether the bit of the codeword is strong or weak.

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