A method and system for testing the thermal resistance of a semiconductor device package

Abstract

The present invention discloses a method and system for testing the thermal resistance of a semiconductor device package. By applying multi-point pulse current excitation to the package and collecting surface temperature response data, a three-dimensional heat conduction path structure of the package is constructed. Based on this structure, the initial thermal resistance distribution and its non-uniform regions are calculated, and further the thermal resistance separation parameters at each hierarchical interface are extracted to form a hierarchical thermal resistance separation matrix. By performing directional correction on the thermal resistance values of the anisotropic thermal conductive materials, a corrected hierarchical thermal resistance sequence is generated and superimposed on the initial thermal resistance distribution, and finally the total thermal resistance value of the package is calculated. By verifying the matching degree between the total thermal resistance value and the temperature response data, the accuracy of hierarchical thermal resistance separation is ensured, and a detailed thermal resistance distribution map is output, which can accurately and non-destructively separate and quantify the thermal resistance contributions of each hierarchical inside the package. Especially in the face of non-uniform heat flow distribution and anisotropic thermal conductive materials, the accuracy of the measurement results is improved through directional correction.

Description

Technical Field

[0001] The present invention belongs to the field of packaging technology, and particularly relates to a method and system for testing the thermal resistance of semiconductor device packaging. Background Art

[0002] In the field of thermal resistance testing of semiconductor device packaging, existing methods usually rely on direct measurement or estimation based on theoretical models to determine the thermal resistance of each layer of material inside the package. These traditional methods often involve using a heating device to apply a constant or varying amount of heat to the package, and monitoring the temperature change through sensors to calculate the thermal resistance value.

[0003] However, this method has several limitations: firstly, it is difficult to non-destructively separate the specific thermal resistance contributions of different levels (such as chips, solder layers, substrates, etc.) inside the package; secondly, in the case of dealing with uneven heat flow distribution and anisotropic thermal conductivity materials, the existing technology lacks an effective correction mechanism, resulting in a large deviation between the measurement result and the actual situation. Summary of the Invention

[0004] The purpose of the present invention is to provide a method and system for testing the thermal resistance of semiconductor device packaging, which can non-destructively and accurately separate and quantify the thermal resistance contributions of each level inside the package. Especially when facing uneven heat flow distribution and anisotropic thermal conductivity materials, the accuracy of the measurement result is improved through directional correction, so as to solve the problem of how to accurately separate the thermal resistance contributions of different levels inside the package and make effective corrections in the presence of uneven heat flow distribution and anisotropic thermal conductivity materials.

[0005] To achieve the above purpose, the present invention adopts the following technical scheme: A method for testing the thermal resistance of semiconductor device packaging, comprising the following steps:

[0006] Apply multi-point pulsed current excitation to the semiconductor device packaging, collect the surface temperature response data of the packaging, and construct a three-dimensional heat conduction path structure of the packaging according to the temperature response data; Calculate the initial thermal resistance distribution of each level inside the package based on the three-dimensional heat conduction path structure, and determine the uneven area of the initial thermal resistance distribution. For the uneven area, extract the thermal resistance separation parameters at the interfaces of each level to form a hierarchical thermal resistance separation matrix; Perform directional correction on the thermal resistance values corresponding to the anisotropic thermal conductivity materials in the hierarchical thermal resistance separation matrix to generate a corrected hierarchical thermal resistance sequence, and perform weighted superposition of the corrected hierarchical thermal resistance sequence and the initial thermal resistance distribution to calculate the total thermal resistance value of the package; Verify the accuracy of hierarchical thermal resistance separation through the matching degree between the total thermal resistance value and the temperature response data, output the verified thermal resistance values of each level and the total thermal resistance value, and form a thermal resistance distribution map of the package.

[0007] Preferably, applying a multi-point pulsed current excitation to the semiconductor device package and collecting the temperature response data of the package surface includes:

[0008] Select at least three non-collinear positions as current injection points, apply pulsed currents with a preset time interval and amplitude at each injection point, and record the temperature change data of each monitoring point on the package surface;

[0009] Use an infrared camera to monitor the semiconductor device package in real time and record the temperature change conditions of each monitoring point on the package surface under the action of the pulsed current;

[0010] Based on the relationship between the temperature changes of each monitoring point and the pulsed current, calculate the thermal response coefficients corresponding to each injection point, which are used to characterize the heat conduction performance of the package material at different positions;

[0011] Input all the thermal response coefficients into a summary formula to obtain an overall thermal response matrix, and analyze the heat flow distribution inside the package through the overall thermal response matrix.

[0012] Preferably, constructing a three-dimensional heat conduction path structure of the package according to the temperature response data includes:

[0013] Use the temperature change data to determine the temperature distribution of each monitoring point;

[0014] Based on the temperature distribution, define a spatial coordinate system and mark the positions of all monitoring points in the spatial coordinate system;

[0015] For each monitoring point, calculate the heat flow connection strength between it and its surrounding monitoring points to establish a local heat conduction relationship;

[0016] Summarize all the local heat conduction relationships to form an overall three-dimensional heat conduction path structure, and identify the main heat conduction paths and their directions by analyzing the elements in the three-dimensional heat conduction path structure.

[0017] Preferably, calculating the initial thermal resistance distribution of each layer inside the package based on the three-dimensional heat conduction path structure and determining the non-uniform region of the initial thermal resistance distribution includes:

[0018] Extract the heat flow connection strength between each monitoring point and the points directly connected to it from the three-dimensional heat conduction path structure, and calculate the average heat flux density of each monitoring point;

[0019] Use the average heat flux density and the position of the monitoring point to calculate the initial thermal resistance value corresponding to each monitoring point, so as to construct an initial thermal resistance distribution map inside the package;

[0020] In the initial thermal resistance distribution map, define a threshold to identify the non-uniform region, and mark the points that meet the conditions as the non-uniform thermal resistance region;

[0021] For all the identified non-uniform thermal resistance regions, record their position coordinates and corresponding thermal resistance values in the initial thermal resistance distribution map to form a non-uniform thermal resistance report.

[0022] Preferably, for the non-uniform regions, extract the thermal resistance separation parameters at the interfaces of each layer to form a hierarchical thermal resistance separation matrix, including:

[0023] Based on the position coordinates and corresponding thermal resistance values recorded in the non-uniform thermal resistance report, determine the main heat flow paths within each non-uniform region, and select several key points on the main heat flow paths;

[0024] For each key point, calculate the temperature difference between it and the adjacent layer interface, and then calculate the corresponding thermal resistance separation parameter of the layer based on the temperature difference;

[0025] Arrange all the thermal resistance separation parameters in hierarchical order to construct a hierarchical thermal resistance separation matrix;

[0026] By analyzing the non-zero elements in the hierarchical thermal resistance separation matrix, identify the layer interfaces with significant thermal resistance contributions, and record the position information of the layer interfaces and the corresponding thermal resistance separation parameters to form a detailed hierarchical thermal resistance analysis table.

[0027] Preferably, perform a directional correction on the thermal resistance values corresponding to the anisotropic thermal conductive materials in the hierarchical thermal resistance separation matrix to generate a corrected hierarchical thermal resistance sequence, including:

[0028] Identify the elements in the hierarchical thermal resistance separation matrix, and determine the positions of the layer interfaces containing anisotropic thermal conductive materials and their corresponding thermal resistance separation parameters;

[0029] For each layer interface containing anisotropic thermal conductive materials, define a direction correction factor according to the material properties;

[0030] Apply the direction correction factor to correct the hierarchical thermal resistance separation parameters and calculate the corrected thermal resistance values;

[0031] Arrange all the corrected thermal resistance values in hierarchical order to form a corrected hierarchical thermal resistance sequence.

[0032] Preferably, perform a weighted superposition of the corrected hierarchical thermal resistance sequence and the initial thermal resistance distribution to calculate the total thermal resistance of the package, including:

[0033] Based on the initial thermal resistance values of each monitoring point in the initial thermal resistance distribution map and the corrected hierarchical thermal resistance sequence, determine a weight factor for each layer interface;

[0034] Use the weight factor to perform a weighting process on each element in the corrected hierarchical thermal resistance sequence to generate weighted hierarchical thermal resistance values;

[0035] Superimpose the weighted hierarchical thermal resistance values on the initial thermal resistance values at corresponding positions in the initial thermal resistance distribution map, and calculate the total thermal resistance contribution value of each monitoring point;

[0036] Sum up the total thermal resistance contribution values of all monitoring points, and calculate the average thermal resistance value of the entire package.

[0037] Preferably, verify the accuracy of hierarchical thermal resistance separation through the matching degree between the total thermal resistance value and the temperature response data, including:

[0038] Calculate the expected temperature change of each monitoring point based on the temperature change data of each monitoring point;

[0039] Compare the expected temperature change with the actually measured temperature change, and calculate the temperature difference of each monitoring point;

[0040] Calculate the sum of squares of temperature differences based on the temperature differences of all monitoring points;

[0041] Set a predefined threshold. If the sum of squares of temperature differences is less than or equal to the threshold, confirm that the hierarchical thermal resistance separation is accurate.

[0042] Preferably, output the verified hierarchical thermal resistance values and the total thermal resistance value to form a thermal resistance distribution map of the package, including:

[0043] Calculate the finally confirmed thermal resistance value of each layer interface based on the overall average thermal resistance value and the corrected hierarchical thermal resistance sequence;

[0044] Combine the finally thermal resistance values of all layer interfaces with the overall average thermal resistance value to construct a list containing all layer thermal resistance information; [[ID=3]]

[0045] Use the data in the list to mark the thermal resistance values of each layer interface and the overall average thermal resistance value of the package at corresponding positions in the three-dimensional coordinate system, and determine the color depth of each point;

[0046] Output the thermal resistance distribution map, ensuring that the positions of all layer interfaces and their corresponding thermal resistance values are marked on the map, and the thermal resistance sizes of different regions are visually shown by the color depth, and the overall average thermal resistance value of the package is marked on the map.

[0047] On the other hand, the present invention proposes a semiconductor device package thermal resistance test system, including:

[0048] A temperature response data acquisition module for applying multi-point pulse current excitation to the semiconductor device package, collecting the temperature response data on the package surface, and constructing a three-dimensional heat conduction path structure of the package according to the temperature response data;

[0049] The hierarchical thermal resistance separation matrix generation module is used to calculate the initial thermal resistance distribution of each layer inside the package based on the three-dimensional heat conduction path structure, determine the non-uniform region of the initial thermal resistance distribution, extract the thermal resistance separation parameters at the interfaces of each layer for the non-uniform region, and form a hierarchical thermal resistance separation matrix;

[0050] The total thermal resistance value calculation module is used to perform directional correction on the thermal resistance values corresponding to the anisotropic thermal conductive materials in the hierarchical thermal resistance separation matrix, generate a corrected hierarchical thermal resistance sequence, perform weighted superposition of the corrected hierarchical thermal resistance sequence and the initial thermal resistance distribution, and calculate the total thermal resistance value of the package;

[0051] The accuracy verification and result output module is used to verify the accuracy of the hierarchical thermal resistance separation by the matching degree between the total thermal resistance value and the temperature response data, output the verified thermal resistance values of each layer and the total thermal resistance value, and form a thermal resistance distribution map of the package.

[0052] A semiconductor device package thermal resistance testing method and system proposed by the present invention have the following advantages compared with the prior art:

[0053] The present invention constructs a three-dimensional heat conduction path structure of the package by applying multi-point pulse current excitation to the package and collecting surface temperature response data. Based on this structure, the initial thermal resistance distribution and its non-uniform region are calculated, and further the thermal resistance separation parameters at the interfaces of each layer are extracted to form a hierarchical thermal resistance separation matrix. By performing directional correction on the thermal resistance values including anisotropic thermal conductive materials, a corrected hierarchical thermal resistance sequence is generated and superimposed with the initial thermal resistance distribution, and finally the total thermal resistance value of the package is calculated. In addition, by verifying the matching degree between the total thermal resistance value and the temperature response data, the accuracy of the hierarchical thermal resistance separation is ensured, and a detailed thermal resistance distribution map is output, which can accurately separate and quantify the thermal resistance contributions of each layer inside the package non-destructively. Especially in the face of non-uniform heat flow distribution and anisotropic thermal conductive materials, the accuracy of the measurement results is improved through directional correction. This not only helps to deeply understand the heat conduction characteristics inside the package, but also provides reliable data support for optimizing the package design, thereby improving the overall performance and reliability of semiconductor devices. Description of the Drawings

[0054] Figure 1 It is a flowchart of the semiconductor device package thermal resistance testing method of the present invention;

[0055] Figure 2 It is a block diagram of the semiconductor device package thermal resistance testing system of the present invention. Detailed Embodiments

[0056] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. The specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0057] The present invention provides a method for testing the thermal resistance of a semiconductor device package as shown in Figure 1 and includes the following steps:

[0058] Step 1: Apply multi-point pulsed current excitation to the semiconductor device package and collect the temperature response data on the package surface; specifically including:

[0059] Select at least three non-collinear positions on the semiconductor device package as current injection points. The selection of these positions should ensure that the main heat conduction paths of the package can be covered in order to comprehensively evaluate the heat conduction performance inside the package. By applying a pulsed current I_p (p represents the pth injection point) with a preset time interval and amplitude at each injection point, the thermal behavior under actual working conditions can be simulated.

[0060] Use an infrared camera to monitor the semiconductor device package in real time, and record the temperature change ΔT_m of each monitoring point on the package surface under the action of the pulsed current, where m represents the mth monitoring point, ΔT_m=(T_after_m - T_before_m), T_before_m is the temperature before the current is applied, and T_after_m is the temperature after the current is applied; this step indirectly reflects the heat conduction efficiency inside the package by measuring the temperature change. ΔT_m represents the temperature rise caused by the current and reflects the ability of the material to transfer heat.

[0061] Based on the relationship between the temperature change of each monitoring point and the pulsed current, calculate the thermal response coefficient H_p = ΔT_p / I_p corresponding to each injection point, which is used to characterize the heat conduction performance of the package material at different positions; a larger H_p value means poorer heat conduction performance.

[0062] Input all the thermal response coefficients H_p into a summary formula to obtain the overall thermal response matrix H_matrix = ∑_(p = 1)^n H_p, where n is the total number of injection points, and analyze the heat flow distribution inside the package structure through H_matrix.

[0063] Step 2: Construct a three-dimensional heat conduction path structure of the package according to the temperature response data; specifically including:

[0064] Using the temperature change ΔT_m data obtained from Step 1, analyze and determine the temperature distribution of each monitoring point. This step includes sorting and classifying the temperature changes of all monitoring points to understand the temperature differences in different regions.

[0065] Based on the temperature distribution, define a spatial coordinate system and mark the positions P_k(x_k, y_k, z_k) of all monitoring points in the coordinate system, where k represents the k-th monitoring point; the position of each monitoring point is represented by its coordinates on the X, Y, and Z axes.

[0066] For each monitoring point P_k, calculate the heat flow connection strength Q_l = (ΔT_k - ΔT_l) / d_kl between it and the surrounding monitoring points, where d_kl is the distance between the monitoring point P_k and the adjacent monitoring point P_l, so as to establish a local heat conduction relationship; a larger Q_l value means stronger heat conduction ability.

[0067] Summarize all local heat conduction relationships to form the overall three-dimensional heat conduction path structure M = ∑_(l = 1)^mQ_l, where m is the total number of monitoring points adjacent to the monitoring point P_k. By analyzing the elements in M, identify the main heat conduction paths and their directions.

[0068] Step 3: Calculate the initial thermal resistance distribution of each layer inside the package based on the three-dimensional heat conduction path structure and determine the non-uniform region of the initial thermal resistance distribution; specifically including:

[0069] Extract the heat flow connection strength Q_l between each monitoring point P_k and the points directly connected to it from the three-dimensional heat conduction path structure M, and calculate the average heat flux density D_k = ∑_(l = 1)^mQ_l / m of each monitoring point, where m is the number of points directly connected to the monitoring point P_k; this formula represents the average value of the heat flow connection strengths between all adjacent monitoring points around the monitoring point P_k. This value reflects the average heat conduction efficiency at the location of this monitoring point.

[0070] Using the average heat flux density D_k and the position P_k(x_k, y_k, z_k) of the monitoring point, calculate the initial thermal resistance value R_k corresponding to each monitoring point through the formula R_k = ΔT_k / D_k, so as to construct the initial thermal resistance distribution map R_map inside the package; this formula represents the thermal resistance value under unit heat flux density at a given temperature change ΔT_k. A larger R_k value means poorer heat conduction performance.

[0071] In the initial thermal resistance distribution map R_map, a threshold ΔR is defined to identify non-uniform regions. The threshold is determined by the formula ΔR = (max(R_k) - min(R_k)) / n, where n is the total number of monitoring points. Then, all points that satisfy the condition |R_k - avg(R)| > ΔR are marked as non-uniform thermal resistance regions, where avg(R) represents the average value of all R_k. This formula represents the difference between the maximum and minimum values of the thermal resistance distribution divided by the total number of monitoring points, which is used to measure the dispersion degree of the thermal resistance distribution. |R_k - avg(R)| > ΔR is used to screen out the thermal resistance values that deviate significantly from the average value and are identified as non-uniform regions.

[0072] For all identified non-uniform thermal resistance regions, record their position coordinates in the initial thermal resistance distribution map R_map and the corresponding thermal resistance values to form a non-uniform thermal resistance report HRR = {P_k, R_k ||R_k - avg(R)| > ΔR}. The non-uniform thermal resistance report provides detailed information about the abnormal regions, which helps designers to select materials or adjust the structure targeted, thereby improving the overall thermal performance of the package.

[0073] Step 4: For the non-uniform regions, extract the thermal resistance separation parameters at the interfaces of each layer to form a layer thermal resistance separation matrix, which specifically includes:

[0074] Based on the position coordinates P_k and the corresponding thermal resistance values R_k recorded in the non-uniform thermal resistance report HRR, determine the main heat flow paths within each non-uniform region, and select several key points K_j on these paths, where j represents the j-th key point.

[0075] For each key point K_j, calculate the temperature difference ΔT_jk = T_(j + 1) - T_j between it and the adjacent layer interface. This formula represents the temperature difference between adjacent layers, which reflects the temperature change when heat is transferred from one layer to another. Z_j = ΔT_jk / I_p represents the thermal resistance value under unit current intensity, which directly reflects the heat conduction ability of the material at a specific position. Here, T_j is the temperature of the layer where the key point is located, and T_(j + 1) is the temperature of the adjacent layer. Then, calculate the corresponding thermal resistance separation parameter Z_j of this layer according to the formula Z_j = ΔT_jk / I_p.

[0076] Arrange all thermal resistance separation parameters Z_j in hierarchical order to construct a layer thermal resistance separation matrix Z_matrix, where the element Z_(jk) represents the thermal resistance separation parameter between the j-th key point and the k-th layer interface, satisfying Z_matrix(j, k) = Z_j when k = j, otherwise 0. Z_matrix is a diagonal matrix, and its non-zero elements only appear on the main diagonal, indicating the thermal resistance separation parameters between each key point and its corresponding layer interface.

[0077] By analyzing the non-zero elements in the hierarchical thermal resistance separation matrix Z_matrix, the hierarchical interfaces with significant thermal resistance contributions are identified, and the location information of these hierarchical interfaces and the corresponding Z_(jk) values are recorded to form a detailed hierarchical thermal resistance analysis table LHTA = {location, Z_(jk)}, which records all the hierarchical interfaces with significant thermal resistance contributions and their corresponding thermal resistance separation parameters, providing detailed thermal resistance distribution information for further design optimization or material selection adjustment.

[0078] Step Five: Perform directional correction on the thermal resistance values corresponding to the anisotropic thermal conductive materials in the hierarchical thermal resistance separation matrix to generate a corrected hierarchical thermal resistance sequence; specifically including:

[0079] Identify the elements in the hierarchical thermal resistance separation matrix Z_matrix, and determine the location of the hierarchical interfaces containing anisotropic thermal conductive materials and their corresponding thermal resistance separation parameters Z_(jk); by identifying the hierarchical interfaces containing anisotropic thermal conductive materials, subsequent directional correction can be carried out targeted to improve the accuracy of thermal resistance calculation.

[0080] For each hierarchical interface containing anisotropic thermal conductive materials, define a direction correction factor α_l = (λ_a / λ_b) according to its material properties, where λ_a is the thermal conductivity along the main heat flow direction and λ_b is the thermal conductivity perpendicular to the main heat flow direction; this formula represents the ratio of the thermal conductivity along the main heat flow direction to the perpendicular direction. Since the thermal conductivity of anisotropic materials is different in different directions, this ratio is used to correct the deviation in thermal resistance calculation.

[0081] Apply the direction correction factor α_l to correct the hierarchical thermal resistance separation parameter Z_(jk) and calculate the corrected thermal resistance value , which means multiplying the original thermal resistance separation parameter by the direction correction factor to obtain the corrected thermal resistance value. This correction process ensures that the thermal resistance value reflects the true thermal conduction performance of the material.

[0082] Arrange all the corrected thermal resistance values R'_jk in hierarchical order to form a corrected hierarchical thermal resistance sequence R'_seq = {R'_1, R'_2,..., R'_n}. This sequence provides the thermal resistance distribution information after directional correction for further analysis and optimization.

[0083] Step Six: Perform weighted superposition of the corrected hierarchical thermal resistance sequence and the initial thermal resistance distribution to calculate the total thermal resistance of the package; specifically including:

[0084] Based on the initial thermal resistance values \(R_k\) of each monitoring point in the initial thermal resistance distribution map \(R\_map\) and the corrected hierarchical thermal resistance sequence \(R'\_seq = \{R'\_1, R'\_2, \cdots, R'\_n\}\), a weight factor \(W\_l = R'\_l / \sum_{l = 1}^{n}R'\_l\) is determined for each hierarchical interface; where \(n\) is the total number of hierarchical levels. This weight factor reflects the relative importance of the thermal resistance of each level in the overall thermal resistance distribution.

[0085] The elements in the corrected hierarchical thermal resistance sequence \(R'\_seq\) are weighted using the weight factor \(W\_l\) to generate the weighted hierarchical thermal resistance values ; this formula represents the weighted thermal resistance value, which combines the information of the original thermal resistance value and the weight factor, and reflects the actual contribution of the thermal resistance of each level in the overall heat conduction.

[0086] The weighted hierarchical thermal resistance value \(R''\_l\) is superimposed on the initial thermal resistance value \(R_k\) at the corresponding position in the initial thermal resistance distribution map \(R\_map\), and the total thermal resistance contribution value \(T\_total\_k\) of each monitoring point is calculated through the formula \(T\_total\_k = R_k + \sum_{l = 1}^{n}R''\_l\); this formula represents the total thermal resistance contribution value of each monitoring point, which is composed of the initial thermal resistance value and all the weighted hierarchical thermal resistance values. This formula ensures that both the initial thermal resistance distribution and the corrected hierarchical thermal resistance information are fully considered.

[0087] The total thermal resistance contribution values \(T\_total\_k\) of all monitoring points are aggregated, and the average thermal resistance value \(T\_avg = (\sum_{k = 1}^{m}T\_total\_k) / m\) of the overall package is calculated, where \(m\) is the total number of monitoring points, representing the average value of the total thermal resistance contribution values of all monitoring points, which is a comprehensive evaluation of the overall heat conduction performance of the package.

[0088] Step 7: Verify the accuracy of the hierarchical thermal resistance separation through the matching degree between the total thermal resistance value and the temperature response data; specifically including:

[0089] Based on the temperature change \(\Delta T\_m\) data of each monitoring point, calculate the expected temperature change of each monitoring point , where \(I_p\) is the applied current intensity, \(R\_avg\) is the overall average thermal resistance value \(T\_avg\), and \(A_k\) is the surface area of the region where the monitoring point is located; this formula assumes uniform heat conduction inside the package and is used to predict the temperature change that each monitoring point should reach under a given current intensity.

[0090] Compare the expected temperature change \(\Delta T'\_m\) with the actually measured temperature change \(\Delta T\_m\), and calculate the temperature difference \(\delta\_m = \Delta T\_m - \Delta T'\_m\) of each monitoring point; a larger \(\delta\_m\) value may indicate errors or inaccuracies in the hierarchical thermal resistance separation process.

[0091] Based on the temperature difference δ_m at all monitoring points, calculate the sum of squared temperature differences SSE = ∑(m = 1)^q δ_m^2, where q is the total number of monitoring points; a smaller SSE value indicates better consistency between the actual measured values and the expected values.

[0092] Set a predefined threshold ε. If SSE is less than or equal to ε, then confirm that the hierarchical thermal resistance separation is accurate. ε is a predefined threshold used to judge the accuracy of the hierarchical thermal resistance separation.

[0093] Step Eight: Output the verified thermal resistance values of each layer and the total thermal resistance value to form a thermal resistance distribution map of the package; specifically including:

[0094] Based on the overall average thermal resistance value T_avg and the corrected hierarchical thermal resistance sequence R'_seq = {R'_1, R'_2,..., R'_n}, calculate the finally confirmed thermal resistance value of each layer interface , where S_l is the surface area of the l-th layer and J is the applied current intensity; this formula combines the actual measurement results with the theoretical model to ensure the accuracy of the thermal resistance value.

[0095] Combine the finally confirmed thermal resistance values R''_l of all layer interfaces with the overall average thermal resistance value T_avg to construct a list L_R = {R''_1, R''_2,..., R''_n, T_avg} that contains all the thermal resistance information of each layer. It is an ordered list that includes the finally confirmed thermal resistance values of each layer interface inside the package and the overall average thermal resistance value. This list provides comprehensive thermal resistance distribution information for further analysis and visualization.

[0096] Using the data in the list L_R, mark the thermal resistance values R''_l of each layer interface and the overall average thermal resistance value T_avg of the package at the corresponding positions in a three-dimensional coordinate system. Determine the color depth C_k of each point through the formula C_k = R''_k / max(L_R), where max(L_R) represents the maximum value in the list L_R and k represents the k-th marked point; the greater the color depth, the higher the thermal resistance value of that point; conversely, the lower it is.

[0097] Output the thermal resistance distribution map, ensuring that the positions of all layer interfaces and their corresponding thermal resistance values R''_l are marked on the map, and the thermal resistance sizes of different regions are visually shown by the color shades. At the same time, mark the overall average thermal resistance value T_avg of the package on the map. By marking the specific values and color shades, the thermal management characteristics of the package can be intuitively understood.

[0098] On the other hand, the present invention proposes a semiconductor device package thermal resistance test system, as Figure 2 shown, including:

[0099] A temperature response data acquisition module, which is used to apply multi-point pulsed current excitation to a semiconductor device package, collect temperature response data on the package surface, and construct a three-dimensional heat conduction path structure of the package according to the temperature response data;

[0100] A hierarchical thermal resistance separation matrix generation module, which is used to calculate the initial thermal resistance distribution of each layer inside the package based on the three-dimensional heat conduction path structure, determine the non-uniform region of the initial thermal resistance distribution, extract the thermal resistance separation parameters at the interfaces of each layer for the non-uniform region, and form a hierarchical thermal resistance separation matrix;

[0101] A total thermal resistance value calculation module, which is used to perform directional correction on the thermal resistance values corresponding to the anisotropic thermal conductive materials in the hierarchical thermal resistance separation matrix, generate a corrected hierarchical thermal resistance sequence, perform weighted superposition of the corrected hierarchical thermal resistance sequence and the initial thermal resistance distribution, and calculate the total thermal resistance value of the package;

[0102] An accuracy verification and result output module, which is used to verify the accuracy of hierarchical thermal resistance separation by the matching degree between the total thermal resistance value and the temperature response data, output the verified thermal resistance values of each layer and the total thermal resistance value, and form a thermal resistance distribution map of the package.

[0103] In addition, when the above modules are executing, they are also used to implement other steps of the above-mentioned method for testing the thermal resistance of a semiconductor device package, as follows:

[0104] Suppose we need to test the thermal resistance of the package of a high-performance chip. This chip adopts a multi-layer structure (chip + solder layer + substrate), where the solder layer is an anisotropic thermal conductive material (with better thermal conductivity along the Z-axis than the X / Y-axis). The goal is to non-destructively separate the thermal resistance contributions of each layer and optimize the package design through the method of the present invention.

[0105] Multi-point pulsed current excitation and temperature response acquisition:

[0106] Select 3 non-collinear injection points (A, B, C) on the package surface, which are located at the chip edge, center, and substrate interface respectively.

[0107] Apply pulsed current for 5 cycles (I_p = 1A, duration 10ms, interval 1s), and record the temperature changes corresponding to each injection point.

[0108] Use an infrared camera for real-time monitoring to obtain the temperature data of the following monitoring points:

[0109]

[0110] Calculate the thermal response coefficient H_p = ΔT_p / I_p:

[0111] H_A = 2.3 / 1 = 2.3;

[0112] $H_B = 3.1 / 1 = 3.1$;

[0113] $H_C = 1.8 / 1 = 1.8$;

[0114] Construct the overall heat response matrix $H\_matrix = H\_A + H\_B + H\_C = 7.2$.

[0115] Construct a three - dimensional heat conduction path structure:

[0116] Define a spatial coordinate system and mark the positions of 3 monitoring points:

[0117] $A(0,0,0), B(5mm,5mm,0), C(10mm,0,0)$.

[0118] Calculate the heat flow connection strength between adjacent monitoring points $Q\_l=(\\Delta T\_k - \\Delta T\_l) / d\_kl$:

[0119] $Q\_AB=(2.3 - 3.1) / (\\sqrt[(5)^2+(5)^2])=-0.8 / 7.07=-0.113W / mm·℃$;

[0120] $Q\_AC=(2.3 - 1.8) / 10 = 0.05W / mm·℃$;

[0121] $Q\_BC=(3.1 - 1.8) / 5 = 0.26W / mm·℃$;

[0122] Summarize the local heat conduction relationships and find that the main heat conduction path is $B\\to C$ ($Q$ is the largest).

[0123] Initial thermal resistance distribution and identification of non - uniform regions:

[0124] Calculate the average heat flux density $D\_k=\\sum Q\_l / m$ ($m$ is the number of adjacent points):

[0125] $D\_A=(-0.113 + 0.05) / 2=-0.0315W / mm·℃$;

[0126] $D\_B=(-0.113 + 0.26) / 2 = 0.0735W / mm·℃$;

[0127] $D\_C=(0.05 + 0.26) / 2 = 0.155W / mm·℃$;

[0128] Initial thermal resistance $R\_k=\\Delta T\_k / D\_k$:

[0129] $R\_A=2.3 / -0.0315=-73.0℃·mm / W$ (negative value is abnormal, need to check data rationality, assume measurement error here, take absolute value);

[0130] $R_B = 3.1 / 0.0735 = 42.2 \, ^{\circ}C \cdot mm / W$;

[0131] $R_C = 1.8 / 0.155 = 11.6 \, ^{\circ}C \cdot mm / W$;

[0132] Determine the threshold $\Delta R = (\max(R_k) - \min(R_k)) / n = (73.0 - 11.6) / 3 = 20.5 \, ^{\circ}C \cdot mm / W$.

[0133] Mark the non - uniform area: If $avg(R) = (73.0 + 42.2 + 11.6) / 3 = 42.3$, then the points satisfying $|R_k - avg(R)| > \Delta R$ are A and B ($73.0 - 42.3 = 30.7 > 20.5$; $42.2 - 42.3 = 0 < 20.5$).

[0134] The non - uniform thermal resistance report $HRR = \{A(73.0), B(42.2)\}$.

[0135] Hierarchical thermal resistance separation and matrix construction:

[0136] Select key points $K_1(B)$ and $K_2(C)$ on the main heat conduction path $B \to C$.

[0137] Calculate the temperature difference $\Delta T_{jk} = T_{j + 1} - T_j$: Assume the temperature of layer B is $T_B = 3.1 \, ^{\circ}C$ and the temperature of layer C is $T_C = 1.8 \, ^{\circ}C$, then $\Delta T_{jk} = - 1.3 \, ^{\circ}C$.

[0138] Thermal resistance separation parameter (Take the absolute value as 1.3).

[0139] Construct the hierarchical thermal resistance separation matrix $Z_{matrix}$ (diagonal matrix):

[0140] [1.3, 0];

[0141] [0, 1.3].

[0142] Directional correction and generation of hierarchical thermal resistance sequence:

[0143] Identify the solder layer (anisotropic material) at the $B \to C$ interface.

[0144] Define the direction correction factor $\alpha_l = \lambda_a / \lambda_b = 120 \, W / m \cdot K$ (along the Z - axis) / $50 \, W / m \cdot K$ (perpendicular to the Z - axis) $ = 2.4$.

[0145] Correct the thermal resistance value .

[0146] The corrected hierarchical thermal resistance sequence $R'_{seq} = \{3.12, 3.12\}$.

[0147] Weighted Superposition and Total Thermal Resistance Calculation:

[0148] The weight factor \(W_l = R'_l / \sum R'_{seq}=3.12 / (3.12 + 3.12)=0.5\).

[0149] The thermo-resistance value of the weighted layer .

[0150] The total thermal resistance contribution \(T_{total\_k}=R_k+\sum R''_l\):

[0151] \(T_{total\_A}=73.0 + 1.56 = 74.56\);

[0152] \(T_{total\_B}=42.2 + 1.56 = 43.76\);

[0153] \(T_{total\_C}=11.6 + 1.56 = 13.16\);

[0154] The overall average thermal resistance of the package \(T_{avg}=(74.56 + 43.76 + 13.16) / 3 = 43.83\) .

[0155] Accuracy Verification:

[0156] Expected Temperature Change (assuming the surface area \(A_k = 1cm^2\)):

[0157] (much higher than the actual value of \(2.3^{\circ}C\), indicating that the assumption is unreasonable and the model needs to be adjusted).

[0158] After discovering the error, correct the surface area parameter or recalibrate the model. Assume that after correction, \(\Delta T'_m = 2.5^{\circ}C\), \(\delta_m = 2.3 - 2.5=-0.2^{\circ}C\), \(SSE = (-0.2)^2 = 0.04\).

[0159] Set the threshold \(\varepsilon = 0.1\). Since \(SSE\lt\varepsilon\), it is confirmed that the separation is accurate.

[0160] Output of Thermal Resistance Distribution Map:

[0161] The list of final thermal resistance values \(L_R=\{3.12, 3.12, 43.83\}\).

[0162] Mark in the three-dimensional coordinate system:

[0163] The thermal resistance values of the key points \(K_1(B)\) and \(K_2(C)\) are 3.12 and are darker in color (red);

[0164] The thermal resistance values in other areas are lower (blue).

[0165] The overall average thermal resistance of the map annotation \(T_{avg}=43.83\) 。

[0166] Through this embodiment, the thermal resistance at the interface between the solder layer and the substrate (3.12 ) was successfully separated, and significant thermal resistance non-uniformity (74.56 ) was found in the chip edge region (point A). This prompts the designer to optimize the material distribution of the solder layer or increase the heat dissipation structure. The method verification result is accurate (SSE = 0.04 < ε = 0.1), proving its feasibility.

[0167] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for testing the thermal resistance of a semiconductor device package, characterized in that, The steps include: Applying multi-point pulsed current excitation to a semiconductor device package, collecting surface temperature response data of the package, and constructing a three-dimensional heat conduction path structure of the package according to the temperature response data; Calculating the initial thermal resistance distribution of each layer inside the package based on the three-dimensional heat conduction path structure, and determining the non-uniform region of the initial thermal resistance distribution. For the non-uniform region, extracting the thermal resistance separation parameters at the interfaces of each layer to form a layer thermal resistance separation matrix, specifically including: determining the main heat flow paths in each non-uniform region based on the position coordinates and corresponding thermal resistance values recorded in the non-uniform thermal resistance report, and selecting several key points on the main heat flow paths; for each key point, calculating the temperature difference between it and the adjacent layer interface, and then calculating the corresponding thermal resistance separation parameter of the layer according to the temperature difference; arranging all the thermal resistance separation parameters in the layer order to construct a layer thermal resistance separation matrix; by analyzing the non-zero elements in the layer thermal resistance separation matrix, identifying the layer interfaces with significant thermal resistance contributions, and recording the position information of the layer interfaces and the corresponding thermal resistance separation parameters to form a detailed layer thermal resistance analysis table; Performing directional correction on the thermal resistance values corresponding to the anisotropic thermal conductive materials in the layer thermal resistance separation matrix to generate a corrected layer thermal resistance sequence, specifically including: identifying the elements in the layer thermal resistance separation matrix, determining the position of the layer interface containing the anisotropic thermal conductive material and its corresponding thermal resistance separation parameter; for each layer interface containing the anisotropic thermal conductive material, defining a direction correction factor according to the material properties; applying the direction correction factor to correct the layer thermal resistance separation parameter and calculating the corrected thermal resistance value; arranging all the corrected thermal resistance values in the layer order to form a corrected layer thermal resistance sequence; Performing weighted superposition of the corrected layer thermal resistance sequence and the initial thermal resistance distribution to calculate the total thermal resistance of the package; Verifying the accuracy of the layer thermal resistance separation through the matching degree between the total thermal resistance value and the temperature response data, and outputting the verified thermal resistance values of each layer and the total thermal resistance value to form a thermal resistance distribution map of the package.

2. The method for testing the thermal resistance of a semiconductor device package according to claim 1, characterized in that: The applying multi-point pulsed current excitation to a semiconductor device package and collecting surface temperature response data of the package include: Selecting at least three non-collinear positions as current injection points, applying pulsed current with a preset time interval and amplitude at each current injection point, and recording the temperature change data of each monitoring point on the surface of the package; Using an infrared camera to monitor the semiconductor device package in real time and recording the temperature change conditions of each monitoring point on the surface of the package under the action of the pulsed current; Calculating the thermal response coefficient corresponding to each injection point based on the relationship between the temperature change of each monitoring point and the pulsed current, which is used to characterize the heat conduction performance of the package material at different positions; Inputting all the thermal response coefficients into a summary formula to obtain an overall thermal response matrix, and analyzing the heat flow distribution of the internal structure of the package through the overall thermal response matrix.

3. A method for testing the thermal resistance of a semiconductor device package according to claim 2, characterized in that: Constructing a three-dimensional heat conduction path structure of the package according to the temperature response data, including: Using the temperature change data to determine the temperature distribution of each monitoring point; Based on the temperature distribution, define a spatial coordinate system and mark the positions of all monitoring points in the spatial coordinate system; For each monitoring point, calculate the heat flow connection strength between it and the surrounding monitoring points to establish local heat conduction relationships; Summarize all local heat conduction relationships to form an overall three-dimensional heat conduction path structure, and identify the main heat conduction paths and their directions by analyzing the elements in the three-dimensional heat conduction path structure.

4. The method for testing the thermal resistance of a semiconductor device package according to claim 3, wherein: Calculate the initial thermal resistance distribution of each layer inside the package based on the three-dimensional heat conduction path structure, and determine the non-uniform regions of the initial thermal resistance distribution, including: Extract the heat flow connection strength between each monitoring point and the points directly connected to it from the three-dimensional heat conduction path structure, and calculate the average heat flux density of each monitoring point; Use the average heat flux density and the position of the monitoring point to calculate the initial thermal resistance value corresponding to each monitoring point, thereby constructing an initial thermal resistance distribution map inside the package; In the initial thermal resistance distribution map, define a threshold to identify non-uniform regions, and mark the points that meet the conditions as non-uniform thermal resistance regions; For all identified non-uniform thermal resistance regions, record their position coordinates and corresponding thermal resistance values in the initial thermal resistance distribution map to form a non-uniform thermal resistance report.

5. A method for testing the thermal resistance of a semiconductor device package according to claim 4, characterized in that: Perform a weighted superposition of the corrected layer thermal resistance sequence and the initial thermal resistance distribution to calculate the total thermal resistance value of the package, including: Based on the initial thermal resistance values of each monitoring point in the initial thermal resistance distribution map and the corrected layer thermal resistance sequence, determine a weight factor for each layer interface; Use the weight factor to perform weighted processing on each element in the corrected layer thermal resistance sequence to generate weighted layer thermal resistance values; Superimpose the weighted layer thermal resistance values on the initial thermal resistance values at the corresponding positions in the initial thermal resistance distribution map to calculate the total thermal resistance contribution value of each monitoring point; Summarize the total thermal resistance contribution values of all monitoring points to calculate the average thermal resistance value of the overall package.

6. The method for testing the thermal resistance of a semiconductor device package according to claim 5, characterized in that: Verify the accuracy of layer thermal resistance separation through the matching degree between the total thermal resistance value and the temperature response data, including: Calculate the expected temperature change of each monitoring point based on the temperature change data of each monitoring point; Compare the expected temperature change with the actually measured temperature change to calculate the temperature difference of each monitoring point; Calculate the sum of the squares of the temperature differences based on the temperature differences of all monitoring points; Set a predefined threshold. If the sum of the squares of the temperature differences is less than or equal to the threshold, confirm that the layer thermal resistance separation is accurate.

7. A method for testing the thermal resistance of a semiconductor device package according to claim 6, characterized in that: Output the verified thermal resistance values of each layer and the total thermal resistance value to form a thermal resistance distribution map of the package, including: Calculate the finally confirmed thermal resistance value of each layer interface based on the overall average thermal resistance value and the corrected layer thermal resistance sequence; Combine the finally confirmed thermal resistance values of all layer interfaces with the overall average thermal resistance value to construct a list containing all layer thermal resistance information; Use the data in the list to mark the thermal resistance values of each layer interface and the overall average thermal resistance value of the package at the corresponding positions in the three-dimensional coordinate system, and determine the color depth of each point; Output a thermal resistance distribution map, ensuring that the positions of all hierarchical interfaces and their corresponding thermal resistance values are marked on the map, and the thermal resistance magnitudes in different regions are visually shown by the shade of color. At the same time, mark the average thermal resistance value of the entire package on the map.

8. A semiconductor device package thermal resistance test system for implementing the method according to any one of claims 1-7, characterized in that, Including: A temperature response data acquisition module, which is used to apply multi-point pulsed current excitation to the semiconductor device package, collect the temperature response data on the package surface, and construct a three-dimensional heat conduction path structure of the package according to the temperature response data; A hierarchical thermal resistance separation matrix generation module, which is used to calculate the initial thermal resistance distribution of each layer inside the package based on the three-dimensional heat conduction path structure, and determine the non-uniform regions of the initial thermal resistance distribution. For the non-uniform regions, extract the thermal resistance separation parameters at the interfaces of each layer to form a hierarchical thermal resistance separation matrix. Specifically, it includes: determining the main heat flow paths in each non-uniform region based on the position coordinates and corresponding thermal resistance values recorded in the non-uniform thermal resistance report, and selecting several key points on the main heat flow paths; for each key point, calculating the temperature difference between it and the adjacent layer interface, and then calculating the corresponding thermal resistance separation parameter of the layer according to the temperature difference; arranging all the thermal resistance separation parameters in hierarchical order to construct a hierarchical thermal resistance separation matrix; by analyzing the non-zero elements in the hierarchical thermal resistance separation matrix, identifying the hierarchical interfaces with significant thermal resistance contributions, and recording the position information of the hierarchical interfaces and the corresponding thermal resistance separation parameters to form a detailed hierarchical thermal resistance analysis table; A total thermal resistance value calculation module, which is used to perform directional correction on the thermal resistance values corresponding to the anisotropic thermal conductive materials in the hierarchical thermal resistance separation matrix to generate a corrected hierarchical thermal resistance sequence. Specifically, it includes: identifying the elements in the hierarchical thermal resistance separation matrix, determining the positions of the hierarchical interfaces containing anisotropic thermal conductive materials and their corresponding thermal resistance separation parameters; for each hierarchical interface containing anisotropic thermal conductive materials, defining a direction correction factor according to the material properties; applying the direction correction factor to correct the hierarchical thermal resistance separation parameters and calculating the corrected thermal resistance values; arranging all the corrected thermal resistance values in hierarchical order to form a corrected hierarchical thermal resistance sequence; weighting and superimposing the corrected hierarchical thermal resistance sequence and the initial thermal resistance distribution to calculate the total thermal resistance value of the package; An accuracy verification and result output module, which is used to verify the accuracy of the hierarchical thermal resistance separation through the matching degree between the total thermal resistance value and the temperature response data, output the verified thermal resistance values of each layer and the total thermal resistance value, and form a thermal resistance distribution map of the package.

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