Current measurement system and method

Abstract

A current measurement system and a corresponding method are described wherein the current measurement system comprises: a resistor structure having a sense resistor and a calibration resistor wherein a single metal layer of the resistor structure comprises the sense resistor and the calibration resistor; a calibration circuit configured to provide a calibration current through the calibration resistor; and a sense amplifier configured to measure a respective voltage across each of the calibration resistor and the sense resistor.

Description

Technical Field

[0001] Embodiments of the subject matter described herein generally relate to current measurement systems, including current measurement systems having a current sense resistor. Background Art

[0002] Circuits for measuring current are used in a variety of applications. For example, typical current measurement circuits in automotive systems are used to measure the current in each branch of a three-phase motor. The measurement values generated by the current measurement circuit in an automotive system can be used to drive system responses, such as speed and torque. Thus, accurate, precise, and stable current measurement circuits are typically required in automotive applications. This current measurement circuit is typically implemented using a current transducer such as a Hall effect sensor, a Rogowski coil, or a fluxgate sensor. Summary of the Invention

[0003] A brief overview of various exemplary embodiments is presented below. Some simplifications and omissions may be made in the following overview, which is intended to highlight and introduce some aspects of the various exemplary embodiments, but not to limit the scope. A detailed description of the exemplary embodiments sufficient to allow one of ordinary skill in the art to make and use these concepts will follow in a later section.

[0004] In an example embodiment, a current measurement system includes: a resistor structure having a sense resistor and a calibration sensor included in a single metal layer of the resistor structure; a calibration circuit configured to provide a calibration current through a calibration resistor; and a sense amplifier configured to measure a respective voltage across each of the calibration resistor and the sense resistor.

[0005] In one or more embodiments, the sense amplifier includes: a first sense amplifier configured to generate a reference voltage based on the voltage across the calibration resistor; and a second sense amplifier configured to generate a current sense voltage based on the voltage across the sense resistor.

[0006] In one or more embodiments, the current measurement system further includes an analog-to-digital converter (ADC) configured to receive the reference voltage and the current sense voltage and generate at least one digital signal based on the reference voltage and the current sense voltage.

[0007] In one or more embodiments, the at least one digital signal includes a binary representation of the quotient of the reference voltage divided by the current sense voltage.

[0008] In one or more embodiments, the current measurement system further includes: an isolation circuit coupled to the output of the ADC; and a digital-to-analog converter (DAC) configured to receive at least one digital signal from the ADC via the isolation circuit and convert the at least one digital signal into an output voltage. The current through the sense resistor can be determined based on the output voltage.

[0009] In one or more embodiments, the current measurement system further includes a sample-and-hold circuit configured to periodically sample a reference voltage from a first sense amplifier and provide the most recently sampled reference voltage to the ADC.

[0010] In one or more embodiments, the calibration circuit further includes a switch coupled between the output of the calibration circuit and the calibration resistor. The state of the switch is controlled by a clock signal, and the clock signal determines the sampling rate of the sample-and-hold circuit.

[0011] In one or more embodiments, the sense resistor includes a first set of resistor fingers coupled in parallel, and the calibration resistor includes a second set of resistor fingers coupled in series.

[0012] In one or more embodiments, the resistor structure is arranged such that each set of resistor fingers in the second set of resistor fingers of the calibration resistor is disposed between adjacent sets of resistor fingers in the first set of resistor fingers of the sense resistor.

[0013] In an example embodiment, a method includes: providing, by a calibration circuit, a calibration current through a calibration resistor; generating, by a first sense amplifier, a reference voltage based on a voltage across the calibration resistor; and generating, by a second sense amplifier, a current sense voltage based on a voltage across a sense resistor. The calibration resistor and the sense resistor are formed in a single metal layer of a resistor structure.

[0014] In one or more embodiments, the method further includes generating, by an analog-to-digital converter (ADC), at least one digital signal including a binary representation of a quotient of the reference voltage divided by the current sense voltage.

[0015] In one or more embodiments, the method further includes providing, by the ADC via an isolation circuit, the at least one digital signal to a digital-to-analog converter (DAC), and generating, by the DAC, an analog output voltage based on the at least one digital signal. The current through the sense resistor can be determined based on the analog output voltage.

[0016] In one or more embodiments, the method further includes periodically sampling, by a sample-and-hold circuit, the reference voltage at a sampling rate determined by a clock signal, and providing, by the sample-and-hold circuit, the most recently sampled reference voltage to the ADC.

[0017] In one or more embodiments, the method further includes changing, by a calibration circuit, a state of a switch in the calibration circuit based on a clock signal, and a calibration current is provided through the calibration circuit.

[0018] In one or more embodiments, the sense resistor includes a first set of resistive fingers coupled in parallel, and the calibration resistor includes a second set of resistive fingers coupled in series, and the resistor structure is arranged such that each set of resistive fingers in the second set of resistive fingers of the calibration resistor is disposed between adjacent sets of resistive fingers in the first set of resistive fingers of the sense resistor.

[0019] In one or more embodiments, a current measurement system includes: a first resistor arranged in series with a current-carrying conductor; a second resistor coupled to the first resistor, wherein the first resistor and the second resistor are formed from a single metal layer; a calibration circuit configured to provide a calibration current through the second resistor; and a sense amplifier configured to measure respective voltages across the first resistor and the second resistor.

[0020] In one or more embodiments, the sense amplifier includes: a first sense amplifier configured to generate a reference voltage based on the voltage across the second resistor; and a second sense amplifier configured to generate a current sense voltage based on the voltage across the first resistor.

[0021] In one or more embodiments, the current measurement system further includes an analog-to-digital converter (ADC) configured to receive the reference voltage and the current sense voltage and generate at least one digital signal based on the reference voltage and the current sense voltage.

[0022] In one or more embodiments, the current measurement system further includes: an isolation circuit coupled to an output of the ADC; and a digital-to-analog converter (DAC) configured to receive at least one digital signal from the ADC via the isolation circuit and convert the at least one digital signal into an output voltage. The current through the first resistor can be determined based on the output voltage.

[0023] In one or more embodiments, the current measurement system further includes: a sample-and-hold circuit configured to periodically sample the reference voltage from the first sense amplifier and provide the most recently sampled reference voltage to the ADC; and a switch coupled between an output of the calibration circuit and the second resistor. A state of the switch is controlled by a clock signal, and the clock signal determines a sampling rate of the sample-and-hold circuit. Description of the Drawings

[0024] A more complete understanding of the subject matter may be derived by reference to the detailed description and claims, which may be considered in conjunction with the following drawings, in which the same reference numerals refer to similar elements throughout the various figures. The elements in the various figures are shown for simplicity and clarity, and the elements are not necessarily drawn to scale. The various figures, together with the detailed description, are incorporated into and form part of this specification, and are used to further illustrate examples, embodiments, etc., and to explain various principles and advantages according to the present disclosure. In the drawings:

[0025] Figure 1 is a block diagram illustrating an example current measurement system according to one or more embodiments;

[0026] Figure 2 is a top view showing an example resistor structure according to one or more embodiments, wherein the example resistor structure may be used in a current measurement system, such as the current measurement system of technical solution 1;

[0027] Figure 3 is a block diagram illustrating an example current measurement system according to one or more embodiments; and

[0028] Figure 4 is a description of using a current measurement system according to one or more embodiments, such as Figure 1 or 3 is a process flow chart of a method for measuring current by a current measurement system. DETAILED DESCRIPTION

[0029] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. Furthermore, it is not intended to be bound by any expressed or implied theory presented in the previous technical field, background technology or the following detailed description.

[0030] For simplicity and clarity of illustration, the drawings show general construction methods, and descriptions and details of well-known features and techniques may be omitted for brevity. In addition, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements or regions in the various figures may be exaggerated relative to other elements or regions to help improve the understanding of the embodiments described herein.

[0031] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims may be used to distinguish similar elements and are not necessarily used to describe a particular sequential or temporal order. It should be understood that the terms so used may be interchangeable under appropriate circumstances such that the embodiments described herein, for example, can be operated in a sequence other than the sequence shown or otherwise described herein. In addition, the terms "comprise", "include", "have" and any variations thereof are intended to cover non-exclusive inclusion such that a process, method, article or apparatus that comprises a series of elements includes not only those elements but may include other elements not expressly listed or other elements inherent to such process, method, article or apparatus. As used herein, the term "coupled" is defined as being connected directly or indirectly, either electrically or non-electrically. As used herein, the terms "substantially" and "substantially" mean sufficient to achieve the stated purpose in a practical manner and minor deficiencies (if any) are not important for the stated purpose. As used herein, the words "exemplary" and "example" mean "serving as an example, instance or illustration". Any embodiment described herein as exemplary or an example is not necessarily to be construed as preferred or superior to other embodiments. Additionally, certain terms may be used herein for reference only and are thus not intended to be restrictive.

[0032] Unless otherwise stated, directional references such as "top", "bottom", "left", "right", "above", "below", etc. are not intended to require any preferred orientation but are made for illustrative purposes with reference to the orientation of one or more corresponding figures.

[0033] The various embodiments described herein relate to systems and methods for current sensing. For example, a current measurement system may include a resistor structure that includes: a first resistor (sometimes referred to herein as a "sense resistor" or "current sense resistor") having a plurality of parallel resistor fingers for in-line current sensing; and a second resistor (sometimes referred to herein as a "calibration resistor") having a plurality of sets of serially coupled resistor fingers. The voltage across the calibration resistor and the voltage across the sense resistor may each be measured (e.g., by a sense amplifier), and the voltage across the calibration resistor may be used as a reference against which the voltage across the sense resistor may be compared when subsequently determining the magnitude of the current through the sense resistor.

[0034] The calibration resistor and the sense resistor can be formed from the same metal layer and formed on the same substrate such that temperature and manufacturing variations (e.g., variations in critical dimension (CD), metal thickness, resistor finger size, etc.) have the same or substantially the same effect on the resistance of the calibration resistor and the resistance of the sense resistor. The calibration resistor and the sense resistor can also be formed in close proximity to each other. For example, portions of the calibration resistor can be inserted between portions of the sense resistor such that the calibration resistor and the sense resistor are each exposed to similar temperature conditions. In this way, the voltage across the calibration resistor can be used as a reference for the voltage across the sense resistor (e.g., by a multiplying analog-to-digital converter (ADC)) without regard to such temperature and manufacturing variations.

[0035] In one or more embodiments, a first sense amplifier can be used to measure the voltage across the sense resistor of a current measurement system. A calibration circuit of the current measurement system can supply a precision current through the calibration resistor (e.g., directly or by supplying a precision voltage), and a second sense amplifier can be used to measure the voltage across the calibration resistor. A multiplying ADC can receive the output of the first sense amplifier and the output of the second sense amplifier. The output of the second sense amplifier can be used as a reference input to the multiplying ADC. The multiplying ADC can generate a digital signal (e.g., a binary pulse train or multiple parallel binary pulses, where each pulse represents a digital bit) that represents the voltage output by the first sense amplifier, referenced to the voltage output by the second sense amplifier (e.g., the digital signal can represent the quotient of the voltage output by the second sense amplifier divided by the voltage output by the first sense amplifier). The digital signal output by the multiplying ADC can be provided to a digital-to-analog converter (DAC) and / or processing circuitry through an isolation circuit. As used herein, a “multiplying ADC” refers to an ADC that does not require a fixed reference voltage but can receive a reference voltage that can be varied to achieve different gains. The processing circuitry can be configured to determine the magnitude of the current through the sense resistor based on the value represented by the digital signal received from the multiplying ADC.

[0036] In one or more embodiments, a current measurement system may include a sample-and-hold circuit inserted between the output of a second sense amplifier and a reference input of a multiplying ADC, and a calibration circuit may include a switch that selectively connects a precision current or voltage from the calibration circuit to a calibration resistor. The sample-and-hold circuit may periodically sample the output of the second sense amplifier according to a clock signal to update the measured value of the voltage across the calibration resistor. The switch may be switched between an on state (connecting the output of the calibration circuit to the calibration resistor) and an off state (disconnecting the output of the calibration circuit from the calibration resistor) by the same clock signal that is used to trigger the sampling of the sample-and-hold circuit. In this way, compared to other equivalent systems that, for example, continuously measure the voltage across the calibration resistor and continuously supply a precision current through the calibration resistor, the power consumption of the current measurement system can be advantageously reduced.

[0037] Figure 1 A block diagram of a current measurement system 100 is shown, the current measurement system including a resistor structure 102 having a sense resistor 104 and a calibration resistor 106. It should be understood that, unless otherwise specified, herein, "current" refers to electrical current, and "resistance" refers to electrical resistance. The sense resistor 104 may be coupled in series with a bus bar 108, where the current measurement system 100 is configured to measure the current I through the bus bar 108 based at least in part on the voltage across the sense resistor 104. BUS It should be understood that the current measurement system 100 is not limited to use with a bus bar and may alternatively be configured and arranged to measure the current through any suitable current-carrying conductor.

[0038] The voltage across the sense resistor 104 may be determined as the difference between the voltages V BUSN and V BUSP , where V BUSN is the voltage at a node 114 connected between a first end 110 of the bus bar 108 and a first end of the sense resistor 104, and V BUSP is the voltage at a node 116 connected between a second end 112 of the bus bar 108 and a second end of the sense resistor 104. The voltage across the calibration resistor 106 (e.g., V CAL - V BUSN ) may be measured and used as a reference when determining the current I through the bus bar 108. BUSWhen, for calibration purposes (e.g., scaling and temperature compensation), the measured voltage across the sense resistor 104 is compared to the reference. The sense resistor 104 and the calibration resistor 106 can be formed from the same metal layer on the same substrate and be in close proximity to each other such that the sense resistor 104 and the calibration resistor 106 each experience the same or substantially the same temperature variations and manufacturing variations. Because the temperature and manufacturing variations of the sense resistor 104 and the calibration resistor 106 are substantially the same, such variations do not need to be accounted for downstream, which advantageously reduces calibration complexity.

[0039] In addition to the resistor structure 102, the current measurement system 100 can include a calibration circuit 118 coupled to the calibration resistor 106, a sense amplifier 120 coupled to the sense resistor 104 and the calibration resistor 106, a multiplying ADC 122 coupled to the output of the sense amplifier 120, a DAC 126, and an isolation circuit 124 coupled to the output of the multiplying ADC via the isolation circuit 124.

[0040] To measure the current through the bus bar 108, the sense amplifier 120 of the current measurement system 100 can receive a first voltage V at node 114 of the bus bar 108 BUSN (e.g., the voltage at the first end of the sense resistor 104), a second voltage V at node 116 of the bus bar 108 BUSP (e.g., the voltage at the second end of the sense resistor 104), and a calibration voltage V at node 128 CAL . Node 128 can be coupled between the first end of the calibration resistor 106 and the output of the calibration circuit 118, and the calibration circuit 118 provides a calibration current I from the output CAL . In one or more embodiments, the calibration circuit 118 can include a precision voltage source or a precision current source for supplying the calibration current I CAL . In one or more embodiments, a "precision voltage source" can be a voltage source accurate enough such that the associated primary bandgap reference is the only significant error source. In one or more embodiments, a "precision current source" can be a current source such that the associated calibration resistor is the only significant error source. According to various embodiments, the calibration circuit 118 can supply the current I in pulse mode or continuous mode CAL .

[0041] The sense amplifier 120 can generate a reference voltage V based on the amplified (e.g., as a non-limiting example, having a gain between about 20 and about 40) difference between the voltages V CAL and V BUSN (i.e., the voltage across the calibration resistor 106). The sense amplifier 120 can be based on the voltages V REF . The sense amplifier 120 can be based on the voltages V BUSP and VBUSN a difference in amplification (e.g., by way of non-limiting example, having a gain of from about 20 to about 0) therebetween (i.e., the voltage across sense resistor 104) to generate a current sense voltage V SENSE The voltage V at node 114 BUSN can be used as a reference voltage (e.g., an analog ground reference voltage) for calibration circuit 118 and multiplying ADC 122.

[0042] In one or more embodiments, sense amplifier 120 can include at least two auto-zero amplifiers. In one or more embodiments, sense amplifiers 120 can each be configured to provide the same or substantially the same amount of gain.

[0043] Multiplying ADC 122 can receive the reference voltage V REF and the current sense voltage V SENSE from sense amplifier 120. REF Multiplying ADC 122 generates one or more data signals DAT based on the reference voltage V SENSE and the current sense voltage V. Multiplying ADC 122 can provide the data signal DAT to DAC 126 via isolation circuit 124.

[0044] In one or more embodiments, multiplying ADC 122 can transmit DAT as a pulse train representing a binary number across a single serial communication link. In one or more embodiments, the multiplying ADC can transmit DAT as multiple parallel pulses representing a binary number across a parallel communication link. According to one or more embodiments, the binary number represented by DAT can be equal to the quotient of V REF divided by V SENSE . In one or more embodiments, by way of non-limiting example, multiplying ADC 122 can include a multiplying DAC and one or more successive approximation register (SAR) ADCs or delta-sigma ADCs.

[0045] Isolation circuit 124 can provide electrical isolation between the high voltage domain of bus bar 108 and the low voltage domain (i.e., lower than the high voltage domain) of the circuit at the output of DAC 126 and DAC 126. In one or more embodiments, such as in an automotive application where bus bar 108 corresponds to a branch of a three-phase motor, by way of non-limiting example, the high voltage domain can include a voltage between 400V and 800V, and in one or more such embodiments, isolation circuit 124 can be a galvanically isolated communication link (GICL). In one or more other embodiments, such as when bus bar 108 corresponds to the output of a 48V battery, by way of non-limiting example, the high voltage domain can include a voltage between 20V and 70V, and in one or more such embodiments, isolation circuit 124 can include a capacitive isolation circuit.

[0046] The DAC 126 can convert the data signal DAT into an output voltage V OUT The processing circuit (i.e., a computer processing circuit) can receive the output voltage V from the DAC 126 OUT (alternatively, for example, receive V via an ADC OUT in digital representation), and can be configured to generate a current value based on V OUT which represents the current measured at the bus bar 108 using the sense resistor 104. In one or more embodiments, this current value can be stored in a computer-readable memory device coupled to the processing circuit. Although the DAC 126 is shown at the output of the isolation circuit 124 in this example, it should be understood that this is illustrative and non-limiting. For example, in one or more other embodiments, the processing circuit, such as the processing circuit described above, can receive the data signal DAT from the isolation circuit 124 without an intermediate DAC.

[0047] In one or more embodiments, the current measurement system 100 can be included in an automotive system. In one or more such embodiments, the bus bar 108 can be a branch of a three-phase motor, the output of a battery (e.g., a 48V battery), or another suitable current path within the automotive system where current measurement may be required. In one or more such embodiments, the output of the DAC 126 can be provided to a current limiting circuit that is configured to compare the output voltage provided by the DAC 126 with a reference voltage and, upon determining that the output voltage exceeds the reference voltage, reduce the current through the bus bar 108 to a maximum current level or stop (e.g., turn off the source of the current through the bus bar 108).

[0048] Because the calibration resistor 106 and the sense resistor 104 are formed as part of the same resistor structure 102 (e.g., formed as part of the same metal layer and in close proximity to each other), the calibration loop including the calibration resistor 106 and the calibration circuit 118 scales dynamically (i.e., scales V CAL , and thus scales V REF ) with temperature variations that affect the sense resistor 104. For embodiments in which the calibration resistor 106 and the sense resistor 104 are formed from the same metal layer, this calibration loop also compensates for static sheet resistivity and critical dimension (CD) tolerances (each example of manufacturing variability). Because the calibration resistor 106 compensates for temperature and manufacturing variability in this way, the current sensing system including the resistor structure 102 can advantageously omit additional circuitry that would conventionally be required to accommodate such temperature and manufacturing variability.

[0049] As a non-limiting example, Figure 2 a resistor structure 200 is shown, which can beFigure 1 An example embodiment of the resistor structure 102. The resistor structure 200 includes a first set 202 of parallel resistor fingers that together form a first resistor (e.g., Figure 1 the sense resistor 104), and a second set 204 of resistor fingers, where each in the second set 204 is inserted between a corresponding pair of adjacent sets in the first set 202. Herein, each strip of conductive material (e.g., metal) that extends between the contacts 212 and 214 (although not necessarily touching the contacts 212 and 214 in the case of the second set 204) is considered an individual "resistor finger". The second set 204 can be coupled (e.g., connected) in series together to form a second resistor (e.g., Figure 1 the calibration resistor 106).

[0050] The resistor fingers of the first set 202 can be coupled between a first contact 212 and a second contact 214, and the first contact and the second contact can act as the first and second ends of the first resistor formed by the first set 202. For example, the contact 212 can correspond to the first end of the first resistor (e.g., coupled to Figure 1 the node 114), and can be coupled to a first sense amplifier and a second sense amplifier (e.g., the first sense amplifier and the second sense amplifier of the sense amplifier 120). For example, the contact 214 can correspond to the second end of the first resistor (e.g., coupled to Figure 1 the node 116), and can be coupled to the first sense amplifier (e.g., the first sense amplifier of the sense amplifier 120).

[0051] In one or more embodiments, adjacent sets in the second set 204 can be connected in series via wire bondings or interconnects that connect the adjacent sets in the second set 204 at the bond pads 206. The bond pads 208 and 210 of the second set 204 can act as the ends of the second resistor formed by the second set 204. For example, the bond pad 208 can correspond to the first end of the second resistor (e.g., coupled to Figure 1 the node 128), and can be coupled to a calibration circuit (e.g., Figure 1 the calibration circuit 118) and the second sense amplifier (e.g., Figure 1 the second sense amplifier of the sense amplifier 120). For example, the bond pad 210 can correspond to the second end of the second resistor (e.g., coupled to Figure 1 the node 114), and can be coupled to a bus bar (e.g., Figure 1 the bus bar 108) and coupled to the first end of the first resistor.

[0052] In one or more embodiments, the first set 202 may collectively include 40 resistor fingers coupled in series, and the second set 204 may collectively include 40 resistor fingers coupled in series when connected adjacent to the pair of bonding pads 206. Each of the resistor fingers of sets 202 and 204 may have a width of approximately 25 μm. As a non-limiting example, each of the resistor fingers of the first set 202 may have a resistance of approximately 2.5 mΩ. Each of the resistor fingers of the second set 204 may have a resistance of approximately 2 mΩ. Considering 40 2.5 mΩ resistor fingers connected in parallel in the first resistor and 40 2 mΩ resistor fingers connected in series in the second resistor, the first resistor may have a resistance of 100 μΩ, and the second resistor may have a resistance of 80 mΩ. In this document, unless otherwise specified, a quantity referred to as "about" or "approximately" a given value is considered to be within + / - 10% of the given value.

[0053] The resistor fingers of the first set 202 and the second set 204 may each be formed of the same metal layer. In one or more embodiments, as a non-limiting example, the resistor fingers of the first set 202 and the second set 204 may be formed simultaneously via deposition of a metal layer followed by a photolithographic etching process or a lift-off process. As a non-limiting example, the metal layer forming the resistor fingers of the first set 202 and the second set 204 may be copper.

[0054] By forming the first set 202 and the second set 204 from the same metal layer and interspersing the second set 204 among the adjacent sets of the first set 202, the resistor fingers of the first set 202 and the second set 204 may be exposed to the same or substantially the same temperature conditions, such that the resistance variability due to temperature changes may affect the resistor fingers of the first set 202 and the second set 204 in the same or a similar manner. Additionally, by using the same deposition and etching process steps to form the resistor fingers of the first set 202 and the second set 204, it is expected that the resistor fingers of the first set 202 and the second set 204 have the same or similar dimensions (e.g., width, critical dimension (CD), thickness, etc.), such that manufacturing or fabrication process variability affects the resistor fingers of the first set 202 and the second set 204 in the same or a similar manner. In this way, when the resistor structure 200 is implemented in, for example, a current measurement system (e.g., Figure 1 current measurement system 100), the voltage measured across the second resistor may be used as a basis for calibrating the voltage measured across the first resistor, because the respective resistances of the first resistor and the second resistor may be affected by temperature variability and manufacturing non-idealities in the same or a similar manner.

[0055] Figure 3 A block diagram of a current measurement system 300 is shown, which may correspond toFigure 1 An example embodiment of the current measurement system 100. One or more aspects of the current measurement system 300 may be similar to Figure 1 one or more aspects of the current measurement system, where like reference numerals are used herein to denote like elements. For the sake of brevity, the description of such aspects or elements that have been described above may not necessarily be repeated here.

[0056] Since temperature changes are not expected to occur rapidly in some applications, power consumption of the calibration loop of the current measurement system 300 can be advantageously reduced by sampling the voltage across the calibration resistor 106 periodically rather than continuously. In this example, this can be achieved by using a sample-and-hold circuit 308 to sample V REF periodically while preventing current from flowing through the calibration resistor 106 during periods when sampling of V REF is not taking place.

[0057] As shown, the calibration circuit 118 may include an output coupled to node 304. The calibration circuit 118 may be configured to supply a precision voltage V REF2 . This is due to the voltage at node 304. Node 304 may be coupled to node 128 via a resistor 302 and a switch 306, the switch being included in the calibration circuit 118. The resistor 302 may be a precision resistor (e.g., having a tolerance of + / -1%), which may be an external resistor (i.e., not subject to the same temperature conditions as the calibration resistor 106) and / or a trimmed resistor (e.g., trimmed on silicon). In one or more embodiments, by way of non-limiting example, the resistor 302 may have a resistance equal to or approximately equal to 40 Ω (e.g., + / -1%).

[0058] The calibration circuit 118 may receive a clock signal CLK that controls the state of the switch such that the switch 306 toggles between an "off" (high impedance) state and an "on" (low impedance) state. When the switch 306 is in the on state, calibration current I CAL flows from the output of the calibration circuit 118 and through the resistor 302, the switch 306, and the calibration resistor 106. When the switch 306 is in the off state, no current is passed from the calibration circuit 118 through the calibration resistor 106.

[0059] As shown, the sample-and-hold circuit 308 may be coupled to the reference voltage output of the sense amplifier 120 (i.e., providing V REFbetween the output of and the corresponding input of the multiplicative ADC 122. The sample and hold circuit 308 may receive a clock signal CLK, which may be the same clock signal as that for the switch 306 that switches the calibration circuit 118. The sample and hold circuit 308 may be configured to sample the new value of V REF at each rising or falling edge of the configured clock signal CLK. That is, the clock signal CLK may determine the sampling rate of the sample and hold circuit 308. The sample and hold circuit 308 may store the most recently sampled value of V REF and may provide the value as an output to the multiplicative ADC 122.

[0060] The sense amplifier 120 may include a first sense amplifier 310 and a second sense amplifier 312, which are configured to measure the voltages across the calibration resistor 106 and the sense resistor 104, respectively. The first sense amplifier 310 may be configured to generate a reference voltage V REF as the difference between V CAL and V BUSN multiplied by the gain of the first sense amplifier 310. The second sense amplifier 312 may be configured to generate a current sense voltage V SENSE as the difference between V BUSP and V BUSN multiplied by the gain of the second sense amplifier 312.

[0061] In one or more embodiments, the first sense amplifier 310 and the second sense amplifier 312 may each be an auto-zero amplifier. In one or more embodiments, the first sense amplifier 310 and the second sense amplifier 312 may each provide the same or substantially the same gain to their respective outputs. For example, both the first sense amplifier 310 and the second sense amplifier 312 may be configured to provide a gain of about 20 to about 40 to their respective output signals.

[0062] For example, considering a voltage across the calibration resistor 106 of V CAL -V BUSN = 10 mV, the first sense amplifier 310 may provide a gain of 40 to produce a reference voltage V REF of 400 mV. As another example, considering a voltage across the sense resistor 104 of V BUSP -V BUSN = 1 mV, the second amplifier may provide a gain of 40 to produce a current sense voltage V SENSE of 40 mV. Generally, the value of V REF2 and the respective resistances of the resistor 302 and the calibration resistor 106 may be selected (given the respective gains of the sense amplifiers 310 and 312) such that V REFThe expected value of is the same as or higher than V SENSE The expected peak voltage of because the multiplication ADC 122 may require V SENSE Less than V REF .

[0063] In this example, compared with the continuous sampling method, the sampling and holding circuit 308 is used to periodically sample V REF While stopping the supply of I from the calibration circuit 118 outside the sampling period CAL Can advantageously reduce the power consumption of the calibration loop. In various embodiments, as a non-limiting example, when compared with the continuous sampling method, depending on the configuration of the current measurement system 300, the power consumption of the calibration loop can be reduced by about two orders of magnitude or more.

[0064] Figure 4 Illustrates an exemplary process flow for method 400 performed by a current measurement system, such as Figure 1 The current measurement system 100 of or Figure 3 The current measurement system 300 of can generate calibrated current measurement data for a given bus bar or other current-carrying conductor. Refer to Figure 1 The elements of the current measurement system 100 to describe method 400. However, it should be understood that this is illustrative and non-limiting, at least because other suitable current measurement systems can be used to perform method 400 in one or more other embodiments.

[0065] At block 402, a calibration current is provided through the calibration resistor. For example, the calibration circuit 118 can provide a calibration current I through the calibration resistor 106 CAL .

[0066] At block 404, the first voltage across the calibration resistor is measured and amplified using a first sense amplifier to generate a reference voltage. For example, the first sense amplifier of the sense amplifier 120 (e.g., Figure 3 The first sense amplifier 310 of) can measure and amplify V CAL The difference between and V BUSN That is, the voltage across the calibration resistor 106) to generate a reference voltage V REF .

[0067] At block 406, the second voltage across the sense resistor is measured and amplified using a second sense amplifier to generate a current sense voltage. The sense resistor can be coupled in series with a current-carrying conductor (e.g., a bus bar), and the current measurement system will measure the current passing through the current-carrying conductor. For example, the second sense amplifier of the sense amplifier 120 (e.g., Figure 3 The second sense amplifier 312 of) can measure and amplify V BUSP The difference between and VBUSN the difference therebetween (i.e., the voltage across the sense resistor 104) to generate a current sense voltage V SENSE . In one or more embodiments, block 404 and block 406 may be performed simultaneously.

[0068] At block 408, the multiplying ADC generates one or more digital signals based on a reference voltage and the current sense voltage. For example, the multiplying ADC 122 may receive the reference voltage V REF and the current sense voltage V SENSE , and may then generate a digital signal DAT corresponding to the binary representation of the quotient V REF / V SENSE . The current through the sense resistor 104 may be determined based on the digital signal DAT.

[0069] At block 410, the multiplying ADC provides the digital signal to the DAC via an isolation circuit. For example, the multiplying ADC 122 may provide the digital signal DAT to the DAC 126 via the isolation circuit 124.

[0070] At block 412, the DAC may generate a voltage representative of the current through the sense resistor based on the digital signal. For example, the DAC 126 may receive the digital signal from the multiplying ADC 122 via the isolation circuit 124 and may generate an analog output voltage V REF / V SENSE that is equal to or approximately equal to. The processing circuitry coupled to the output of the DAC 126 may receive V OUT or its digital representation, and may determine the current through the sense resistor 104 based on the magnitude of V OUT in view of the known values of the nominal resistances of the sense resistor 104 and the calibration resistor 106, the gain of each of the sense amplifiers 120, and the calibration current I CAL . OUT

[0071] The foregoing description refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless stated otherwise explicitly, “connected” means that one element is directly joined to another element (or directly communicates with another element), and not necessarily joined mechanically. Similarly, unless stated otherwise explicitly, “coupled” means that one element is directly or indirectly joined to another element (or directly or indirectly communicates with another element), and not necessarily joined mechanically. Thus, although the schematic illustrations shown in the figures depict an exemplary arrangement of elements, there may be additional intervening elements, devices, features, or components in one or more embodiments of the subject matter depicted.

[0072] Although the operations of the method are shown and described herein in a particular order, the order of operations of each method may be varied such that particular operations may be performed in reverse order, or such that particular operations may be performed at least partially concurrently with other operations. In another embodiment, instructions or sub-operations of different operations may be implemented in an intermittent and / or alternating manner.

[0073] It should also be noted that at least some of the operations of the methods described herein may be implemented using software instructions stored on a computer-usable storage medium for execution by a computer. By way of example, an embodiment of a computer program product includes a computer-usable storage medium for storing a computer-readable program. A computer-usable storage medium or a computer-readable storage medium may be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device). Examples of permanent computer-usable and computer-readable storage media include semiconductor or solid state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and optical disk. Current examples of optical disks include compact disk read only memory (CD-ROM), compact disk read / write (CD-R / W), and digital video disk (DVD).

[0074] Alternatively, the embodiments described herein may be implemented entirely in hardware or in an implementation including both hardware and software elements. In an embodiment using software, the software may include, but is not limited to, firmware, resident software, microcode, etc.

[0075] Although at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that there are a large number of variations. It should also be understood that one or more of the exemplary embodiments described herein are not intended to limit in any way the scope, applicability, or configuration of the claimed subject matter. Indeed, the foregoing detailed description will provide those skilled in the art with a convenient guide for implementing one or more of the described embodiments. It should be understood that various changes may be made in the function and arrangement of elements without departing from the scope defined by the claims, which scope includes known equivalents and foreseeable equivalents at the time of filing this patent application.

Claims

1. A current measurement system, characterized in that: include: A resistor structure comprising: a sense resistor; and a calibration resistor, wherein a single metal layer of the resistor structure includes the sense resistor and the calibration resistor; a calibration circuit configured to provide a calibration current through the calibration resistor; and A sense amplifier is configured to measure a respective voltage across each of the calibration resistor and the sense resistor.

2. The current measurement system according to claim 1, characterized in that: The sense amplifier comprises: a first sense amplifier configured to generate a reference voltage based on the voltage across the calibration resistor; and A second sense amplifier is configured to generate a current sensing voltage based on the voltage across the sense resistor.

3. The current measurement system according to claim 2, characterized in that: Also included is an analog-to-digital converter ADC, which is configured to: receiving the reference voltage and the current sensing voltage; and At least one digital signal is generated based on the reference voltage and the current sensing voltage.

4. The current measurement system according to claim 3, characterized in that: The at least one digital signal includes a binary representation of a quotient of the reference voltage divided by the current sensing voltage.

5. The current measurement system according to claim 3, characterized in that: Also includes: an isolation circuit coupled to an output of the ADC; as well as A digital-to-analog converter (DAC) is configured to receive the at least one digital signal from the ADC via the isolation circuit and convert the at least one digital signal into an output voltage, wherein a current through the sense resistor is determinable based on the output voltage.

6. The current measurement system according to claim 3, characterized in that: Also includes: A sample-and-hold circuit is configured to periodically sample the reference voltage from the first sense amplifier and provide the most recently sampled reference voltage to the ADC.

7. The current measurement system according to claim 6, characterized in that: The calibration circuit further comprises: A switch is coupled between the output of the calibration circuit and the calibration resistor, wherein a state of the switch is controlled by a clock signal, and wherein the clock signal determines a sampling rate of the sample-and-hold circuit.

8. The current measurement system according to claim 1, characterized in that: The sense resistor includes a first set of resistance fingers coupled in parallel, and the calibration resistor includes a second set of resistance fingers coupled in series.

9. A method, characterized in that include: A calibration current is provided by a calibration circuit through a calibration resistor; generating, by a first sense amplifier, a reference voltage based on a voltage across the calibration resistor; as well as A current sense voltage is generated by a second sense amplifier based on a voltage across a sense resistor, wherein the calibration resistor and the sense resistor are formed in a single metal layer of a resistor structure.

10. A current measurement system, characterized in that: include: a first resistor arranged in series with the current carrying conductor; a second resistor coupled to the first resistor, wherein the first resistor and the second resistor are formed from a single metal layer; a calibration circuit configured to provide a calibration current through the second resistor; as well as A sense amplifier is configured to measure respective voltages across the first resistor and the second resistor.

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