Method and apparatus for monitoring power transistors

Abstract

The invention relates to a method and apparatus for monitoring a power transistor. An example apparatus includes a first transistor (208) implemented using gallium nitride (GaN) (401), the first transistor having a drain configured to receive an input voltage from a power source, a gate configured to receive a voltage from control circuitry, and a source; a second transistor (406) implemented using a GaN (402), the second transistor having a drain coupled to the source of the first transistor, a gate coupled to a current source (416), and a source configured to provide an output voltage based on a voltage (209) at the source of the first transistor; and a third transistor (210) implemented using a GaN (402), the third transistor having a drain coupled to the source of the first transistor and the drain of the second transistor, a gate, and a source configured to be coupled to ground.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 612,972, filed on December 20, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] This specification generally relates to power management circuitry, and more particularly, to methods and devices for monitoring power transistors. Background Art

[0004] Power management circuitry is a critical design component of any electronic device. Generally, power management circuitry refers to the hardware and / or software that converts a first amount of electrical power (e.g., a first voltage and / or current) received from a source into a second amount of electrical power (e.g., a second voltage and / or current) consumable by a load. The power source can include, but is not limited to, a 120-volt alternating current (VAC) or 240 VAC wall outlet, a battery, a generator, power provided by solar cells, etc. Typically, the power management circuitry can also convert the power from a first type (e.g., alternating current (AC)) to a second type (e.g., direct current (DC)) usable by the load. Summary of the Invention

[0005] For a method and device for monitoring a power transistor, an example device includes: a first transistor implemented using gallium nitride (GaN), the first transistor having a drain configured to receive an input voltage from a power source, a gate configured to receive a voltage from a control circuitry, and a source; a second transistor implemented using GaN, the second transistor having a drain coupled to the source of the first transistor, a gate coupled to a current source, and a source configured to provide an output voltage based on the voltage at the source of the first transistor; and a third transistor implemented using GaN, the third transistor having a drain coupled to the source of the first transistor and the drain of the second transistor, a gate, and a source configured to be coupled to ground. Brief Description of the Drawings

[0006] Figure 1 is an example of power delivery that includes a buck regulator circuitry.

[0007] Figure 2 is Figure 1 an example block diagram of the buck regulator circuitry of

[0008] Figure 3 is a diagram showing the characteristics of a GaN power transistor used in the buck regulator circuitry of Figure 2 an example graph of

[0009] Figure 4 is Figure 2 a first exemplary implementation of a monitoring circuit system.

[0010] Figure 5 is an illustrative example of an operation performed by the Figure 4 monitoring circuit system when the low-side power transistor of Figure 2 is turned on.

[0011] Figure 6 is an illustrative example of an operation performed by the Figure 4 monitoring circuit system when the low-side power transistor of Figure 2 is turned off.

[0012] Figure 7 is a flowchart representing example operations that can be run, instantiated, and / or performed using the Figure 2 monitoring circuit system.

[0013] Figure 8 is Figure 2 a second exemplary implementation of a monitoring circuit system.

[0014] Figure 9 is a block diagram of an example processing platform that includes a programmable circuit system structured to run, instantiate, and / or execute example machine-readable instructions and / or perform the Figure 7 example operations to implement the Figure 2 buck regulator circuit system and / or the monitoring circuit system.

[0015] The same reference numerals or other reference indicators are used in the figures to denote (functionally and / or structurally) the same or similar features. DETAILED DESCRIPTION

[0016] The figures are not necessarily drawn to scale. In general, the same reference numerals in the figures and in this specification refer to the same or similar parts. Although the figures show regions with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, the boundaries and / or lines may be unobservable, blended, and / or irregular.

[0017] A power management circuit system can refer to a wide variety of circuit architectures that perform different functions. An example of a power management circuit system is a voltage regulator. A voltage regulator refers to a class of circuit architectures that are designed to provide a constant voltage to a load. An example implementation of a voltage regulator is a buck regulator circuit, which is designed to receive a first DC voltage from a power source and output a lower second DC voltage to the load. The buck regulator circuit can also provide increased current at the second DC voltage compared to the current that can be provided at the first DC voltage. In some instances, the buck regulator is referred to as a buck converter.

[0018] Figure 1 is an example block diagram of a computing environment. Figure 1 includes example power source 102, example AC power circuit system 104, example DC power circuit system 106, example buck regulator circuit system 108, and example load 110. Although example power source 102, example AC power circuit system 104, and example DC power circuit system 106 are shown Figure 1 in the context of a computing environment, these components can be used in any other suitable context. Such contexts can include, but are not limited to, telecommunications / server power, HDTV power, automotive vehicle chargers, high-density power adapters, inverters, and motor drives.

[0019] Example power source 102 provides AC power to Figure 1 the example environment of. Example power source 102 can be implemented by any device that provides AC electrical energy. For example, in Figure 1 the example, example power source 102 is implemented by a 120VAC outlet.

[0020] Example AC power circuit system 104 transforms 120VAC into a different AC signal that can be operated by DC power circuit system 106. Specifically, example AC power circuit system 104 can change one or more of voltage, frequency, signal shape, number of phases, etc. according to the type of power source 102 and the requirements of the DC power unit.

[0021] Example DC power circuit system 106 transforms the AC signal received from AC power circuit system 104 into a DC signal. Example DC power circuit system 106 includes a rectifier circuit system and a filter circuit system to convert the AC signal into a DC signal. Example DC power circuit system 106 is configured to provide a DC signal at a voltage that can be operated by example buck regulator circuit system 108. In some instances, DC power circuit system 106 is referred to as a voltage source.

[0022] Example buck regulator circuit system 108 is a voltage regulator circuit that transforms the first DC voltage provided by example DC power circuit system 106 into a second DC voltage that can be used by load 110. In combinationFigure 2 Further describe the example buck regulator circuit system 108. In the examples described herein, the first DC voltage provided by the example DC power supply circuit system 106 may be referred to as the input voltage (V_IN), and the second DC voltage available to the load 110 may be referred to as the output voltage (V_OUT).

[0023] In Figure 1 this context, the example load 110 refers to any device capable of using the power from the second DC voltage to perform operations. In some examples, the load 110 may require a specific amount of power at a specific time to perform various operations. Such requirements may generally be referred to as the performance requirements of the load 110. The load receiving the second DC voltage may be implemented by any type of circuit system, including but not limited to transceivers, volatile memories, etc. In some examples, the load 110 may be implemented by a programmable circuit system. Examples of programmable circuit systems include programmable microprocessors, field programmable gate arrays (FPGAs) that can instantiate instructions, central processing unit (CPU), graphics processing unit (GPU), digital signal processor (DSP), XPU, or microcontrollers and integrated circuits such as application specific integrated circuits (ASICs).

[0024] Figure 2 is for providing voltage to the load 110 Figure 1 The example block diagram of the buck regulator circuit system 108. Figure 2 The buck regulator circuit system 108 of Figure 2 can be instantiated (e.g., created, exist for any length of time, implemented, executed, etc.) by a programmable circuit system such as a central processing unit (CPU) that executes the first instruction. In some examples, Figure 2 the buck regulator circuit system 108 of Figure 2 can be instantiated (e.g., created, exist for any length of time, implemented, executed, etc.) by (i) an application specific integrated circuit (ASIC) and / or (ii) a field programmable gate array (FPGA) that is structured and / or configured to perform operations corresponding to the first instruction in response to the execution of the second instruction. Thus, Figure 2 some or all of the circuit systems of

[0025] In Figure 2In an example, the buck regulator circuit system 108 includes a main control circuit system 202, driver circuit systems 204 and 206, a high-side transistor 208 (which may be referred to herein as M_H 208), a switching terminal 209 (which may be referred to herein as the V_SW terminal 209), a low-side transistor 210 (which may be referred to herein as M_L 210), an example inductor 211, a capacitor 212, a short-circuit detection (SCD) circuit system 216, a zero-volt detection (ZVD) circuit system 218, and a monitoring circuit system 220. In some examples, the main control circuit system 202, the SCD circuit system 216, and the ZVD circuit system 218 may be collectively referred to as the control circuit system.

[0026] The example main control circuit system 202 generates clock signals provided to the driver circuit systems 204 and 206. In Figure 2 an example, the main control circuit system 202 generates clock signals to include a low supply voltage (e.g., ground, 0V, etc.) and pulses (e.g., a rectangular waveform including transitions from the low supply voltage to a high supply voltage and back to the low supply voltage). The main control circuit system 202 determines when to emit pulses in the clock signals such that the buck regulator circuit system 108 supports the performance requirements of the load 110. In some examples, the main control circuit system 202 adjusts the timing of pulses in one or more of the clock signals based on inputs from the SCD circuit system 216 and / or the ZVD circuit system 218. In some examples, the main control circuit system 202 is instantiated by a programmable circuit system that executes main control instructions and / or is configured to execute operations such as those represented as Figure 7 the operations of a flowchart. In some examples, one or more of the clock signals may be referred to as a control voltage.

[0027] The driver circuit systems 204 and 206 increase the gain of the clock signals. The driver circuit system 204 is coupled to the gate of M_H 208, and the driver circuit system 206 is coupled to the gate of M_L 210. In some examples, correspondingly, the gate of M_H 208 may be referred to as the voltage gate high (V_GH) terminal 205, and the gate of M_L 210 may be referred to as the voltage gate low (V_GL) terminal 207. In some examples, the driver circuit systems 204 and 206 may also adjust the width of pulses in the clock signals (e.g., the amount of time a pulse remains at a high voltage) based on instructions from the main control circuit system 202.

[0028] The transistors M_H 208 and M_L 210 are both transistors rated for high-power applications. M_H 208 and M_L 210 are coupled to each other through the V_SW terminal 209 and are coupled to the inductor 211. When the voltage at the V_GH terminal 205 crosses the threshold, M_H 208 turns on, causing current to flow from the DC power circuitry 106 and through the inductor 211 via the V_SW terminal 209. Alternatively, when the voltage of the V_GL terminal 210 crosses the threshold, M_L 210 turns on and the current from the V_SW terminal 209 flows to ground. Subsequently, when M_L 210 turns on, the current flowing through the inductor 211 decreases. The main control circuitry 202 provides the voltage in the clock signal such that only one of M_H 208 and M_L 210 is on at any given point in time. In some instances, the voltage at the V_SW terminal 209 is referred to as the drain voltage of M_L 210 (e.g., the voltage at the drain of M_L 210).

[0029] The transistors M_H 208, M_L 210, and the inductor 211 may be collectively referred to as a power stage circuit or a phase circuit. Although Figure 2 an example of contains one phase circuit, the teachings described herein can be used to implement a buck regulator circuitry containing any number of phase circuits.

[0030] In Figure 2 an example of, M_H 208 and M_L 210 are enhancement-mode GaN power transistors. Alternatively, the transistors M_H 208 and / or M_L 210 may be implemented as p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), p-channel FETs, p-channel IGBTs, p-channel JFETs, NPN BJTs, and / or N-type equivalent devices with minor modifications. The transistors M_H 208 and / or M_L 210 may be depletion-mode devices, drain-extension devices, enhancement-mode devices, natural transistors, or other types of device-structure transistors.

[0031] When M_L 210 turns on, the capacitor 212 charges the V_OUT terminal, and the current through the inductor 212 has decreased. Thus, the capacitor 212 regulates the current at the V_OUT terminal such that the value of V_OUT meets the power requirements of the load 110.

[0032] The SCD circuit system 216 is configured to detect the simultaneous turn-on of M_H 208 and M_L 210, which causes saturation. In such cases, current flows from the DC power supply circuit system 106 through M_H 208, the V_SW terminal 209, through M_L 210, and to ground. Such a configuration forms a short circuit that can damage the buck regulator circuit system 108 and / or the load 110. The SCD circuit system 216 notifies the main control circuit system 202 in the event of a short circuit, so that the main control circuit system 202 can attempt to take actions to mitigate the damage (e.g., stop transmitting pulses to the driver circuit systems 204 and 206, power off the buck regulator circuit system 108, etc.). The SCD circuit system 216 can be implemented by any type of programmable circuit system. In some instances, when the voltage at the V_SW terminal crosses the saturation threshold, the SCD circuit system 216 determines that a short circuit has occurred. Further in combination with Figure 3 Describe the short-circuit saturation threshold. In some instances, the SCD circuit system 216 is instantiated by a programmable circuit system that executes SCD instructions and / or is configured to perform operations such as those represented by Figure 7 The flowchart of.

[0033] The ZVD circuit system 218 detects when the voltage at the V_SW terminal 209 crosses zero volts (0V). During normal operation of the examples described herein, the value of V_SW can be anywhere between approximately +400V and -7V. In other instances, the value of V_SW can switch between different ranges of values. When M_H 208 turns off, the value of V_SW drops until it crosses 0V, and M_L 210 conducts current in the third operating quadrant (e.g., where both the current and voltage between the drain and source of M_L 210 are less than zero). The SCD circuit system 216 can be implemented by any type of programmable circuit system. In some instances, the ZVD circuit system 218 is instantiated by a programmable circuit system that executes ZVD instructions and / or is configured to perform operations such as those represented by Figure 7 The flowchart of.

[0034] As used above and herein, a transistor being "on" refers to the ability of current to flow from the drain to the source or from the source to the drain with a low voltage drop (thereby causing the transistor to act like a closed switch). A transistor being "off" refers to the ability of the transistor to operate in any state other than the "on" state described above. Thus, when a transistor is "off", no current can flow through the transistor, or when a transistor is "off", current can flow from the source to the drain with a large voltage drop (e.g., third quadrant operation of M_L 210).

[0035] Although M_L 210 can conduct current in the third operating quadrant, doing so can cause power loss to load 110 and degrade the performance of buck regulator circuitry 108. Accordingly, the ZVD circuitry 218 reports to the main control circuitry 202 when the V_SW terminal 209 has crossed 0V. Subsequently, the main control circuitry 202 can perform a zero-voltage switching operation to mitigate the negative performance effects of the third quadrant operation of M_L 210. Generally speaking, zero-voltage switching refers to the main control circuitry 202 that adjusts the duty cycles of M_H 208 and M_L 210 (by adjusting the timing of one or more pulses in the clock signal) to regulate the value of V_OUT. In some instances, the zero-voltage switching operation performed by the main control circuitry 202 includes energizing M_L 210 in response to a notification that the voltage at the V_SW terminal 209 has crossed 0V.

[0036] Both the SCD circuitry 216 and the ZVD circuitry 218 send notifications to the main control circuitry 202 based on the voltage at the V_SW terminal 209. The SCD circuitry 216 and the ZVD circuitry 318 can notify the main control circuitry 202 by any suitable technique, including but not limited to setting an interrupt, changing the value of a flag bit in a register, changing the voltage on a pin, etc. In some instances, directly providing the highest voltage supported by M_H 208 and M_L 210 (which is +400V in the examples described herein) to the SCD circuitry 216 and / or the ZVD circuitry 218 via the V_SW terminal 209 can damage one or both of the circuits. Additionally, in some instances, some of the voltages supported by M_H 208 and M_L 210 may be too small in magnitude to detect, and / or more generally, may not be operable for use by the SCD circuitry 216 and / or the ZVD circuitry.

[0037] The monitoring circuitry 220 is coupled to both M_H 208 and M_L 210 via the V_SW terminal 209. The monitoring circuitry 220 is also coupled to the SCD circuitry 216 and the ZVD circuitry 218. In the teachings described herein, the monitoring circuitry 220 provides a voltage to the SCD circuitry 216 and the ZVD circuitry 218 that describes the voltage at the V_SW terminal 209 when it is kept safe and operable. To this end, based on whether the V_SW terminal 209 is currently at a safe and operable voltage, the monitoring circuitry 220 provides a voltage equal to or representative of the voltage at the V_SW terminal 209.

[0038] The teachings described herein include Figure 2 multiple implementations of an example monitoring circuitry 220. An implementation referred to herein as monitoring circuitry 220A is further described below in connection with Figures 4 - 7 Further described below in connection withFigure 8 A further embodiment, referred to herein as monitoring circuit system 220B, is described. A device manufacturer or designer implementing the buck regulator circuit system 108 described herein may select one of monitoring circuit systems 220A or 220B and connect the selected circuit to the V_SW terminal 209, the SCD circuit system 216, and the ZVD circuit system 218, as described above.

[0039] Other buck regulator devices may also attempt to monitor and change the voltage of a switching terminal before providing the voltage to a programmable circuit system. Some devices do this by connecting a discrete high-voltage diode between the switching terminal and the programmable circuit system. When the diode causes a voltage drop that enables the programmable circuit system to safely detect a short circuit, such buck regulator devices must provide a relatively large amount of current (e.g., hundreds of microamperes (μA)) to charge the diode, as well as a relatively high input voltage (e.g., +15V). Thus, such buck regulator devices are limited by power consumption that is proportional to speed (e.g., detection of a short circuit may take hundreds of nanoseconds (ns)).

[0040] In addition, variations in the manufacture of the discrete high-voltage diode and the supporting resistor elements may inadvertently change the value of the desaturation threshold that defines the conditions under which such a device will classify as a short circuit. A buck regulator device using a discrete high-voltage diode as mentioned above cannot support ZVD operation with the accuracy required by the main control circuit system 202 because the diode causes a large voltage difference between the switching node and the programmable circuit system when one or more of the high-power transistors turn off. Thus, with such a buck regulator device, the voltage of the switching node cannot be known with high accuracy.

[0041] Advantageously, the example monitoring circuit system 220A described herein provides voltage to both the SCD circuit system 216 and the ZVD circuit system 218 with high accuracy. The monitoring circuit system 220A also provides such voltage in a manner that enables faster short-circuit detection (e.g., tens of nanoseconds compared to the hundreds of ns described above), uses less current (e.g., tens of μA compared to the hundreds of μA described above), and uses less voltage (e.g., +9V compared to the +15V described above) than other buck regulator devices. In other instances, the monitoring circuit system 220A uses different amounts of voltage and / or current.

[0042] In many electronic devices, transistors are implemented by forming terminals (e.g., gates, bases, drains, sources, emitters, collectors, etc.) with silicon (Si). Silicon is widely used throughout the industry because the material is abundant, has high electrical conductivity, and is thermally stable. As an alternative to silicon, some electronic devices (e.g., some buck regulator devices) use gallium nitride (GaN) to implement high-power transistors (e.g., M_H 208 and M_L 210). Implementing high-power transistors with GaN enables improved performance and supports more stringent performance requirements from load 110 because GaN can conduct a higher voltage than Si before electrical breakdown and because GaN can generally conduct electricity faster than Si. However, transistors implemented in GaN are generally more expensive and less robust (e.g., less predictable) compared to transistors implemented in Si, so the industry has not yet widely replaced Si transistors with GaN transistors. In fact, the material used to implement a particular transistor is specific.

[0043] In the examples described herein, transistors M_H 208 and M_L 210 are implemented using GaN to achieve improved performance of buck regulator circuit system 108 relative to Si-based buck regulator devices, as described above. More generally, in conjunction with Figure 4 The materials used to implement the buck regulator circuit system are further described.

[0044] Although the following examples refer to monitoring circuit system 220 in the context of buck regulator circuit system 108, in the teachings described herein, monitoring circuit system 220 can be implemented in any device that implements high-side and low-side power FETs with GaN. Other devices in which example monitoring circuit system 220 can be implemented include, but are not limited to, totem-pole power factor correction (PFC) devices, inverters, inductance-inductance-capacitance (LLC) networks within high-speed CMOS (AHC) logic, capacitance-inductance-inductance-capacitance (CLLC) networks within dual-active bridges (DAB), etc.

[0045] Figure 3 is a chart showing the characteristics of GaN power transistors in the Figure 2 buck regulator circuit system. Example chart 302 includes example operating curve 304, example overcurrent threshold 306, example short-circuit (SC) desaturation threshold 308, and example boundary curve 310. Example chart 302 also includes an x-axis showing the voltage across the drain and source of the transistor in volts (V) and a y-axis showing the current flowing through the drain and source of the transistor in amperes (A). Although Figure 3 the examples provide numerical values on the x and y axes, other examples can implement operating curve 304, overcurrent threshold 306, SC desaturation threshold 308, and / or boundary curve 310 at different voltages and / or amperages.

[0046] The operating curve 304 represents the characteristic current-voltage (IV) curve of the FET implemented on the GaN die. For example, Figure 4 , 8 An embodiment is shown in which the monitoring circuitry 220 is configured to report when M_L 210 has crossed a short-circuit desaturation threshold. Thus, Figure 3 the following description and the examples herein may refer to the characteristics of M_L 210. In other examples, the monitoring circuitry 220 is configured to report when M_H 208 has crossed a short-circuit desaturation threshold. In such examples, Figure 3 the FET characteristics described in the following description and the examples herein may equally apply to M_H 210.

[0047] When the operating curve 304 is in the linear region, M_L 210 generally follows Ohm's law (V = IR). Thus, during the linear region, the current, voltage, and resistance of M_L 210 are approximately proportional to each other. In Figure 3 the example, the operating curve 304 is in the linear region between approximately <0.0V, 0.0A> and approximately <9.0V, 50.0A>.

[0048] The overcurrent threshold 306 represents the number of amperes of current flowing through M_L 210 that can be directly measured. In Figure 3 the example, the overcurrent threshold 306 is about 42.0A, but in other examples it can be set at different amperages. During normal operation, the current through M_L210 can exceed the overcurrent threshold 306, thereby causing the main control circuitry 202 to perform operations to support various use cases. In Figure 3 such normal operation is represented by the operating signal region between the data points labeled <V_OC, I_OC_TH> and <V_SCD_TH, I_SC_TH>. In Figure 3 the example, the overcurrent voltage (V_OC) of the GaN power FET is about 5.0V, the overcurrent threshold 306 (I_OC_TH) is about 42.0A, the short-circuit desaturation threshold voltage V_SCD_TH is about 9.0V, and I_SC_TH is about 50.0A. In other examples, one or more of V_OC, I_OC_TH, V_SC_TH, and / or I_SC_TH may have different values.

[0049] The SC desaturation threshold 308 represents the number of amperes (labeled I_SC_TH above) at which M_L 210 transitions from linear behavior to saturation. When M_L 210 becomes saturated, M_L 210 forms a short circuit between its drain and source. Under such conditions, the voltage across M_L 210 can continue to increase with relatively little increase in current, thereby heating and potentially damaging the device. Thus, when throughFigure 2 When the amperage of the V_SW terminal 209 crosses the SC desaturation threshold 308, the SCD circuitry 216 uses any suitable notification technique discussed above to notify the main control circuitry 202 that a short circuit has occurred. The main control circuitry 202 processes the notification as a fault condition and turns off M_H 208 and / or M_L 210 to mitigate the safety hazard.

[0050] The transition from linear behavior to saturation is represented in Figure 3 by the operating curve 304 crossing the SC desaturation threshold 308 at <V_SC_TH, I_SC_TH> and the boundary curve 310. More generally, the boundary curve 310 illustrates the current-voltage relationship such that in the Figure 3 example of, M_L 210 behaves linearly when operating to the left of the boundary curve 310 and saturates when operating to the right of the boundary curve 310.

[0051] Notably, the overcurrent threshold 306 (which M_L 210 crosses during normal operation) is similar in magnitude to the SC desaturation threshold 308 (which M_L 210 ideally does not cross). Accordingly, the SCD circuitry 216 and the ZVD circuitry 218 need to know the value of the V_SW terminal 209 quickly and accurately so that a) M_H and / or M_L 210 are prevented from saturating after normal operation, and b) if M_H and / or M_L 210 inadvertently saturate, preventive action is taken as quickly as possible to mitigate the safety hazard. Advantageously, the monitoring circuitry 220A includes some components implemented in GaN and some components implemented in Si such that the value of the V_SW terminal 209 can be reported to the SCD circuitry 216 and the ZVD circuitry 218 quickly and accurately. Additionally, the components are implemented within the monitoring circuitry 220A such that the cost of the implementation is reduced and the circuit performance is reliable.

[0052] Figure 4 is Figure 2 a first example implementation of the monitoring circuitry 220, described herein as the monitoring circuitry 220A. Figure 4 includes Figure 2 the main control circuitry 202, the transistors M_H 208 and M_L 210, the V_SW terminal 209, the SCD circuitry 216, the ZVD circuitry 218, and the monitoring circuitry 220A. Figure 4 also includes the GaN die 401, the GaN die 402, and the Si die 404. Accordingly, the circuit elements within the GaN dies 401 and 402 can be implemented on a continuous block of gallium nitride, and the circuit elements within the Si die 404 can be implemented on a continuous block of silicon.

[0053] Example monitoring circuit system 220A includes components on both the GaN die 402 and the Si die 404 described above. The example monitoring circuit system 220A includes an example sense transistor 406 (which may be referred to herein as M_SNS 406), an example V_G_SNS terminal 407, example clamp resistors 408, 410, 412 (which may be referred to herein as M_CLMP 408, 410, and 412), an example Zener diode 414, an example current source 416, an example charge pump 418, an example V_S_Si terminal 419, an example voltage divider circuit system 420, and an example capacitor 422. The voltage divider circuit system 420 includes example resistors 424 and 430, an example V_SNS terminal 431, example transistors 426 and 432, and an example diode 428.

[0054] In Figure 4 an instance, M_SNS 406, M_CLMP 408 - 412 are GaN transistors, and transistors 426 and 432 are n-channel MOSFETs. Alternatively, transistor M_H 208 and / or M_L 210 may be implemented as GaN transistors, and / or N-type equivalent devices with minor modifications, p-channel FETs, p-channel IGBTs, p-channel JFETs, NPN BJTs. Transistor M_H 208 and / or M_L 210 may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors.

[0055] Within the GaN die 402, the example M_SNS 406 includes a drain coupled to the V_SW terminal 209, a gate coupled to the current source 416, and a source coupled to the resistor 424. In Figure 4 an instance, the gate of M_SNS 406 is referred to as the V_G_SNS terminal 407. Figure 4 The instance of

[0056] The exemplary GaN die 402 also includes clamping transistors 408-412. M_CLMP 408 includes a drain coupled to the V_S_Si terminal 419, a gate coupled to the V_S_Si terminal 419, and a source coupled to the V_G_SNS terminal 407. M_CLMP 410 includes a drain coupled to the V_G_SNS terminal 407, a gate coupled to the V_G_SNS terminal 407, and a source. M_CLMP 412 includes a drain coupled to the source of M_CLMP 410, a gate coupled to the source of M_CLMP 410, and a source coupled to the V_S_Si terminal 419.

[0057] The Si die 404 includes a Zener diode 414, a current source 416, a charge pump 418, a voltage divider circuitry 420, and a capacitor 422. The Zener diode 414 includes a positive terminal coupled to ground and a negative terminal coupled to the V_G_SNS terminal 407. The current source 416 includes an output terminal coupled to the V_G_SNS terminal 407 and an input terminal. The charge pump 418 includes an input terminal configured to receive a first reference voltage (V_REF1) and an output terminal coupled to the input terminal of the current source. The capacitor includes a positive terminal coupled to the V_S_Si terminal 419 and a negative terminal coupled to ground.

[0058] Within the Si die 404 and the voltage divider circuitry 420, a resistor 424 includes a first terminal coupled to the V_S_Si terminal 419 and a second terminal. A transistor 426 includes a drain coupled to the second terminal of the resistor 424, a gate configured to receive a second reference voltage (V_REF2), and a source coupled to both the SCD circuitry 216 and the ZVD circuitry 218. In Figure 4 the example, the terminal coupled to both the SCD circuitry 216 and the ZVD circuitry 218 is labeled V_SNS. A diode 428 includes a positive terminal coupled to the V_SNS terminal 431 and a negative terminal configured to receive V_REF2. A resistor 430 includes a first terminal coupled to the V_SNS terminal 431 and a second terminal. A transistor 432 includes a drain coupled to the second terminal of the resistor 430, a gate coupled to the gate of M_L 210, and a source coupled to ground.

[0059] Monitoring circuit system 220A implements M_SNS 406 on GaN die 402 to sense the voltage of V_SW terminal 209. That is, M_SNS 406 is configured to receive the voltage of V_SW terminal 209 as an input. M_SNS 406 also generates an output voltage indicative of the voltage of V_SW terminal 209 at V_S_Si terminal 419. For example, the voltage at V_S_Si terminal 419 may be equal to the voltage at V_SW terminal 209, or may indicate that the voltage of V_SW 209 is high enough such that a short circuit has formed between M_H 208 and M_L 210. In addition to M_SNS 406, the voltage of V_S_Si terminal 419 may be additionally regulated by transistors M_CLMP 408-412, voltage divider circuit system 420, and / or capacitor 422 to generate a voltage at V_SNS terminal 431 that is safe and operable for SCD circuit system 216 and ZVD circuit system 218.

[0060] To generate V_S_Si, M_SNS 406 is configured to block high voltage and turn off when the switching terminal (e.g., V_SW terminal 209) between high-power FETs crosses a voltage threshold. When the switching terminal crosses the voltage threshold, M_SNS 406 turns back on, thereby providing the voltage to SCD circuit system 216 and ZVD circuit system 218 when the voltage at the switching terminal is in an operable state. In combination Figure 5 and 6 Example empirical values of the voltage threshold, V_SW terminal 209, V_S_Si terminal 419, and V_SNS terminal 431 are further described. In some instances, the connection of M_SNS 406 that causes the aforementioned behavior is referred to as a cascode architecture.

[0061] The value of the voltage threshold described above is limited by the inherent threshold voltage of M_SNS 406. For example, assume that +10V is provided as a control signal to M_SNS 406 via V_G_SNS terminal 407, and M_SNS 406 has an inherent voltage threshold of +2V. In such instances, if the voltage of V_SW terminal 209 is less than or equal to +8V (since 10 - 2 = 8), then M_SNS406 may only turn on and transfer the voltage of V_SW terminal 209 to V_S_Si terminal 419.

[0062] Other buck regulator devices that use silicon to implement high-power FETs may also attempt to provide an operable voltage to a programmable circuit system by using a cascode architecture with a sense transistor between the high-power FETs. In such other devices, the transistors implemented in silicon have a relatively high inherent voltage and can thus support a relatively large voltage swing at the gate of the sense transistor without biasing. However, such buck regulator devices suffer from relatively poor performance because the high-power FETs are implemented in silicon rather than GaN as described above.

[0063] In the teachings described herein, the exemplary buck regulator circuit system 108 uses GaN to implement M_H 208 and M_L 210 to improve performance and support more stringent power requirements from the load 110. In the examples described herein, M_H 208 is implemented in the GaN die 401, while M_L 210, M_SNS 406, and M_CLMP 408 - 412 are implemented in the GaN die 402. In other examples, M_H 208 and M_L 210 may be implemented on the same GaN die.

[0064] Because M_SNS 406 is implemented in GaN, it has a relatively low inherent threshold compared to a sense transistor implemented in silicon. Advantageously, the exemplary monitoring circuit system 220A includes a current source 416 and a charge pump 418 to dynamically bias the V_G_SNS terminal 407 such that, although M_SNS 406 is implemented in GaN, the gate of M_SNS 406 can still support a large voltage swing. The large voltage swing at the V_G_SNS terminal 407 allows M_SNS 406 to transfer the voltage of the V_SW terminal 209 to the V_S_Si terminal 419 to achieve a larger range of voltages than would otherwise be possible without biasing. Thus, the dynamic biasing allows the monitoring circuit system 220A to provide information to the SCD circuit system 216 and the ZVD circuit system 218 in a fast manner while also supporting improved performance from the buck regulator circuit system 108 because M_H 208, M_L 210, and M_SNS 406 are implemented in GaN.

[0065] The V_G_SNS terminal 407 is dynamically biased because the current source 416 and the charge pump 418 enable the voltage of the V_G_SNS terminal 407 to change as the voltage at the V_SW terminal 209 changes. For example, the voltage of the V_G_SNS terminal 407 increases in response to an increase in the V_SW terminal 209, and the voltage of the V_G_SNS terminal 407 decreases in response to a decrease in the V_SW terminal 209. In some examples, the current source 416 is referred to as a variable current source because it produces an output that changes based on the value of the V_SW terminal 209.

[0066] In the absence of current source 416, if the low leakage current of M_SNS 406 charges the V_G_SNS terminal 407 for a sufficient period of time through M_CLMP 408, the voltage of the V_G_SNS terminal 407 will be approximately equal to the voltage of the V_SW terminal 209. However, example charge pump 418 uses V_REF1 to generate a voltage at the input of current source 416. In Figure 4 the example, the output of charge pump 418 is +13V and labeled as V_PMP. In other examples, charge pump 418 can be a different voltage.

[0067] Current source 416 then uses the voltage from charge pump 418 to generate current pulses that increase the voltage at the V_G_SNS terminal 407. Thus, the voltage of the V_G_SNS terminal 407 still follows the voltage of the V_SW terminal 209, but the difference between the V_G_SNS terminal 407 and the V_SW terminal 209 remains at a constant voltage (e.g., +2V). It is noted that the magnitude of the aforementioned voltage difference is greater than the inherent threshold voltage of M_SNS 406. Therefore, the increased voltage of the V_G_SNS terminal 407 and the dynamic biasing break the dependence between the inherent threshold voltage of M_SNS 406 and the voltage threshold when M_SNS turns on / off. Thus, M_SNS 406 can transfer any voltage of the V_SW terminal 209 to the V_S_Si terminal 419, provided that the magnitude of the voltage of the V_SW terminal 209 is within a safe range.

[0068] Monitoring circuitry 220A includes zener diode 414 within Si die 404 and transistors M_CLMP 408 - 412 within GaN die 402 to ensure that M_SNS 406 transfers the voltage of the V_SW terminal 209 to the V_S_Si terminal 419 only when the voltage is within a safe range. For example, although the voltage of the V_G_SNS terminal 407 and the voltage of the V_SW terminal 209 can approximately follow each other due to the low leakage current of M_SNS 406 described above, the configuration of zener diode 414 between the V_G_SNS terminal 407 and ground effectively sets a maximum threshold voltage. More generally, zener diode 414 ensures that the voltage at the V_G_SNS terminal 407 cannot rise above the maximum threshold voltage. Thus, the maximum possible voltage threshold when M_SNS 406 turns on or off is the maximum threshold voltage resulting from subtracting the inherent threshold voltage of M_SNS 406 from the zener diode 414.

[0069] The M_CLMP transistors 408-412 protect the Si die 404 by preventing it from being inadvertently biased to the connected M_SNS 406. For example, if the voltage of the V_SW terminal 209 increases to a value greater than the maximum operable voltage of the M_SNS 406, the value of the V_G_SNS terminal 407 can drop below the voltage of the V_SW terminal 209. In such instances, the M_CLMP 408 will prevent reverse current flow (e.g., from the GaN die 402 to the Si die 404 via the V_G_SNS terminal 407). Such behavior protects the gate of the M_SNS 406 from improper negative biasing. Similarly, if the voltage of the V_SW terminal 209 decreases to a voltage less than the minimum operable voltage of the M_SNS 406, the M_CLMP 410 and M_CLMP 412 protect the gate of the M_SNS 406 from improper positive biasing. By preventing improper biasing of the gate of the M_SNS 406, the transistors M_CLMP 408-412 ensure that the M_SNS 406 can transfer the voltage to the V_S_Si terminal 419 for further regulation only when the voltage of the V_SW terminal 209 is within a safe range.

[0070] Other buck regulator devices may implement high-power FETs and use a sense transistor to provide the voltage of a sense terminal to a programmable circuitry, but do not include the example current source 416 or the clamp transistors 408-412. Thus, the operation of the sense transistor in such other devices is limited by its inherent threshold voltage. For example, the current source 416 and the clamp transistors 408-412 independently increase the voltage of the V_G_SNS terminal 407 with respect to the V_SW terminal 209 such that the M_SNS 406 can remain on until the voltage at the V_SW terminal increases up to about +11V. Accordingly, the V_SNS is provided such that the SCD circuitry 216 identifies a short circuit when the voltage between the drain and source of the M_L 210 crosses V_SCD_TH (e.g., about +9V as shown Figure 3 in). In contrast, when the voltage of the terminal is about +6V, the sense transistor in other buck regulators with GaN power FETs can only remain on because the voltage at the gate of the sense transistor does not increase independently. Thus, such buck regulator devices can only set the desaturation threshold up to about +4.3V because the voltage at the gate of the sense transistor must be higher than the drain for the sense transistor to turn on. The increase in the desaturation threshold voltage provided by the example monitoring circuitry 220A enables the SCD circuitry 216 to report short circuit events more accurately than other buck regulator devices.

[0071] The maximum value of the V_S_Si terminal 419 is set at the voltage threshold of the M_SNS 406 because if the voltage of the V_SW terminal 209 exceeds the voltage threshold, the M_SNS 406 turns off. Although the magnitude of the voltage threshold is safe for the silicon die 404, the SCD circuitry 216 typically uses a low voltage reference and thus requires an input voltage less than the voltage threshold to perform SCD operations. In Figure 4 the example of, the operation of the SCD circuitry 216 involves a comparison of the voltage at the V_SNS terminal 431 with a reference voltage SCD_REF, and the operation of the ZVD circuitry 218 involves a comparison of the voltage at the V_SNS terminal 431 with a reference voltage ZVD_REF.

[0072] The voltage divider circuitry 420 includes resistors 424 and 430 that form a voltage divider, thereby generating a voltage at the V_SNS terminal 431 that is less than the V_S_Si terminal 419 and thus can be used by the SCD circuitry 216. The designer and / or manufacturer of the monitoring circuitry 220A can select specific values for the resistors 424 and / or 430 to precisely determine the voltage at the V_SNS terminal 431 based on the requirements of the SCD circuitry 216 and / or the ZVD circuitry 218.

[0073] If the resistors 424 and 430 are the only components in the voltage divider circuitry 420, then whenever the voltage of the V_SW terminal 209 is high enough, the current from the resistors can flow through the M_SNS 406 and onto the V_SW terminal 209. The flow of such current would be considered leakage current and could cause a degradation in the performance of the buck regulator circuitry 108. Advantageously, the voltage divider circuitry 420 includes transistors 426 and 432 to enable or disable the resistors 424 and 430 based on the behavior of the M_L 210, such that leakage current is avoided while also providing a scaled-down voltage to the SCD circuitry 216 to protect against short circuits. In conjunction with Figure 5 and 6 further describes the conditions for enabling or disabling the resistors 424 and 430.

[0074] Other buck regulator devices may include discrete programmable logic components dedicated to regulating the terminals of the sense transistor such that the voltage of the switch terminal can be interpreted for SCD or ZVD operations. Advantageously, the monitoring circuitry 220A does not include any discrete or programmable logic components. Thus, compared to other buck regulator devices, the example buck regulator circuitry 108 described herein can be implemented in an integrated circuit with lower complexity, area, and cost.

[0075] Figure 5 is an illustrative example of the operation performed by the monitoring circuitry 220A when the M_L 210 is turned on.Figure 5 Includes example graphs 500, example graph 502, and example table 512. Example graph 500 includes example V_SW signal 504 and example V_SNS signal 505. Example graph 502 includes example V_GL signal 506, example V_GH signal 508, and example V_SCD signal 510.

[0076] In example graph 500, V_SW signal 504 represents the voltage of V_SW terminal 209, and V_SNS signal 505 represents the voltage of V_SNS terminal 431. Similarly, in example graph 502, V_GL signal 506 represents the voltage at V_GL terminal 207, V_GH signal 508 depicts the voltage at V_GH terminal 205, and V_SCD signal depicts the output of SCD circuitry 216. The x-axes of example graphs 500 and 502 are vertically aligned such that time stamps T1 - T4 represent the same points in time on both graphs.

[0077] When M_L 210 is powered on, there is a possibility that the buck regulator circuitry 108 may inadvertently enter the saturation operating region and form a short circuit. Thus, when M_L 210 is first powered on at T1, transistors 426 and 432 enable resistors 424 and 430 to make the voltage at V_SNS terminal 431 proportionally less than the voltage of V_S_Si terminal 419 and available for use by SCD circuitry 216 (e.g., comparable to the SCD_REF voltage).

[0078] From T1 to T2, V_GL signal 506 shows M_L 210 powered on, while V_GH signal 508 shows M_H 208 powered off. Thus, from T1 to T2, the voltage at V_SW terminal 209 may decrease or remain at 0V during the initialization period, as shown in graph 500. More generally, during T1 and T2, the voltage at V_SW terminal 209 < 11V, as described in table 512. Current source 416 also generates a current flowing through M_CLMP 410 and M_CLMP 412 between T1 and T2, thereby keeping M_SNS 406 powered on. Thus, table 512 shows that when V_SW < 11V and M_L 210 is conducting, the voltage of V_S_Si terminal 419 is equal to the voltage of V_SW terminal 209.

[0079] Since a high supply voltage (e.g., +6V) at the V_GL terminal is provided to both M_L 210 and transistor 432, the voltage divider circuit system 420 is enabled after T1. Thus, Table 512 shows that when V_SW < 11V and M_L 210 is on, the voltage of the V_SNS terminal 431 is (V_SW)[R_430 / (R_424 + R_430)], where R_430 is the value of resistor 430 and R_424 is the value of resistor 424. In such a state, the value of the V_SNS terminal 431 is proportional to V_SW while still being low enough such that the SCD circuit system 216 can monitor for short circuit events.

[0080] The V_GH signal 508 shows that M_H 208 turns on at T2 with M_L 210 not turning off. The change at T2 inadvertently allows current to flow from the DC power circuit system 106 to ground because M_H 208 and M_L 210 together form a short circuit. Thus, the V_SW signal 504 shows that the voltage of the V_SW terminal 209 starts to rise at T2. At T3, the voltage of the V_SW terminal 209 crosses V_SCD_TH. More generally, M_H 208 and M_L 210 cross the SC desaturation threshold 308 at T3. Crossing the SC desaturation threshold 308 causes the SCD circuit system 216 to notify the main control circuit system 202 that a short circuit has occurred at T3, as shown in the V_SCD signal 510.

[0081] In Figure 5 the example of Figure 4 the main control circuit system 202 responds to the V_SCD signal 510 after some amount of time after

[0082] In the example described herein, current source 416 charges the gate of the terminal such that the above voltage threshold is 11V. Thus, Table 512 shows that at T4 when V_SW > 11V, M_SNS 406 turns off to block the high voltage, and the V_S_Si terminal 419 experiences 11V. Advantageously, the voltage divider circuitry 420 remains enabled until the main control circuitry 202 responds to the short circuit and reduces the V_GL signal 506 (thereby turning off M_L 210 and transistor 432). Thus, when V_SW > 11V and M_L 210 is still powered on, the V_SNS terminal 431 is 11[R_430 / (R_424 + R_430)]. Graph 500 depicts an exemplary embodiment where the values of resistors 424 and 430 are such that 11[R_430 / (R_424 + R_430)] = V_CLMP. Such a voltage is small enough for the SCD circuitry 216 to perform operations and identify that the short circuit has not been resolved by the main control circuitry 202. In other examples, resistors 424 and 430 may have different values that result in different voltages at the V_SNS terminal 431.

[0083] Figure 6 is an illustrative example of the operation performed by the Figure 2 monitoring circuitry when M_L 210 is turned off. Figure 6 Includes example graph 600, example graph 602, and example table 614. Example graph 600 includes example V_SW signal 604 and example V_SNS signal 606. Example graph 602 includes example V_GL signal 608, example V_GH signal 610, and example V_ZVD signal 612. Figure 6 The timestamp of Figure 5 is separated from the timestamp of

[0084] In example graph 600, V_SW signal 604 represents the voltage of the V_SW terminal 209, and V_SNS signal 606 represents the voltage of the V_SNS terminal 431. Similarly, in example graph 602, V_GL signal 608 represents the voltage at the V_GL terminal 207, V_GH signal 610 depicts the voltage at the V_GH terminal 205, and the V_ZVD signal describes the output of the ZVD circuitry 218. The x-axes of example graphs 600 and 602 are vertically aligned such that the timestamps T1 - T5 represent the same time points on both graphs.

[0085] Powering off M_L 210 eliminates the risk of forming a short circuit between the DC power circuit system 106 and ground. Thus, the connection between the V_GL terminal 207 and the transistor 432 causes the resistors 424 and 430 to be deactivated whenever M_L 210 is turned off because: a) short circuit detection is not required in this case, and b) deactivating the resistors prevents leakage current, as described above. Thus, Table 614 shows that the voltage of the V_S_Si terminal 419 matches the voltage of the V_SNS terminal 431 whenever the resistors 424 and 430 are deactivated.

[0086] The V_GH signal 610 shows that M_H 208 is powered on before T1, enabling power to be supplied to the load 110 during such times. The V_SW signal 604 shows that supplying power to the load 110 causes the V_SW terminal 209 to experience up to +400V. During such times, M_SNS is turned off to prevent the high voltage at the V_SW terminal 209 from reaching the Si die 404 and causing damage. Thus, the V_SNS signal 606 shows that the voltage of the V_SNS terminal 431 remains constant between T1 and T2.

[0087] The V_GH signal 610 shows that M_H 208 is turned off at T1. Thus, the V_SW signal 604 shows that the voltage of the V_SW terminal 209 begins to drop. At T2, the signal V_SW signal 604 decreases to V_CLAMP, which is the Figure 6 voltage threshold in the example. Thus, Example Table 614 shows that when V_SW is between +400V and V_CLAMP, both V_S_Si and V_SNS exhibit V_CLAMP.

[0088] The voltage threshold of M_SNS 406 when M_L 210 is off (e.g., Figure 6 V_CLAMP in ) is lower than the voltage threshold of M_SNS 406 when M_L 210 is on (e.g., Figure 5 V_SCD_TH in ) because the current source 416 only increases the voltage at the gate of M_SNS 406 when M_L210 is on and there is a possibility of a short circuit. When M_L 210 is powered off, the possibility of a short circuit is eliminated, so a relatively high value of V_SCD_TH is not required. In fact, when M_H 208 and M_L 210 are configured such that the ZVD circuit system 218 can notify the main control circuit system 202, the monitoring circuit system 220A saves power by reducing the voltage threshold (e.g., to V_CLAMP). In some examples, the value of V_CLAMP is approximately +3.5V, and the value of V_SCD_TH is approximately +9.0V. In other examples, the values of V_CLMP and / or V_SCD_TH may be different.

[0089] At T3, the V_SW signal 604 shows that the voltage at the V_SW terminal 209 reaches the ZVD threshold voltage (V_ZVD_TH). The voltage at the V_SW terminal 209 is negative because M_L 210 starts operating in the third quadrant state between T1 and T2. The third quadrant mode of M_L 210 also enables the voltage divider circuit system 420 because the V_GL terminal 207 is coupled to the gate of the transistor 432. Thus, after T3, the voltage at the V_SNS terminal 431 is proportionally less than the voltage at the V_SW terminal. For example, Table 614 shows that when the voltage at the V_SW terminal 209 is between approximately V_CLAMP and V_ZVD_TH, the voltages of the V_S_Si terminal 419 and the V_SNS terminal 431 match the V_SW. However, when the voltage at the V_SW terminal 209 is between approximately V_ZVD_TH and V_3Qmin and M_L 210 is off, the voltage of the V_S_Si terminal 419 matches the V_SW, but the voltage at the V_SNS terminal 431 is [(V_SW - V_ZVD_TH)R_430] / [(R_424 + R_430) - V_Diode)], where R_430 is the value of the resistor 430, R_424 is the value of the resistor 424, and V_Diode is the voltage drop caused by the diode 428. In some instances, the value of V_ZVD_TH is approximately -0.6V, and the value of V_Diode is approximately +0.7V. In other instances, the values of V_ZVD_TH and / or V_Diode may be different.

[0090] It is noted that the example voltage divider circuit system 420 avoids causing inaccuracies in the ZVD circuit system 218 because the resistors 424 and 430 are only enabled when below V_ZVD_TH (when M_SNS 406 is off). Thus, when the voltage at the V_SW terminal crosses 0V, the voltage at the V_SNS terminal 431 matches the voltage at the V_SW terminal without modification. In Figure 6 the instance of, the resistors 424 and 430 remain enabled between T3 and T5.

[0091] The V_SNS signal 606 crossing V_ZVD_TH indicates that the ZVD circuit system 218 is sufficiently confident that the voltage at the V_SW terminal 209 has crossed below 0V. Thus, the ZVD circuit system 218 notifies the main control circuit system 202. The notification is shown in Figure 6 as the V_ZVD signal 612 transitioning to a high voltage at T3.

[0092] In Figure 6At T4, both the V_SW signal 604 and the V_SNS signal 606 reach and remain at V_3Qmin, which is the minimum possible voltage presented during the third operating quadrant of the GaN power FET considering various process and temperature variations. At T5, the main control circuitry 202 responds to the V_ZVD signal 612 and enables ZVS by turning on M_L 210. To this end, the main control circuitry 202 increases the voltage at the V_GL terminal 207, as shown by the V_GL signal 608 at T5. Subsequently, the V_SW signal 604 and the V_SNS signal 606 return to V_ZVD_TH after T5. In some instances, V_3Qmin is approximately -7.0V. In other instances, the value of V_3Qmin is different.

[0093] Although the Figure 2 and 4 illustrate the Figure 1 step-down regulator circuitry 108 and / or Figure 2 monitoring circuitry 220 in an example manner, the elements, processes, and / or devices illustrated in Figure 2 and 4 can be combined, partitioned, rearranged, omitted, eliminated, and / or implemented in any other manner. Additionally, the main control circuitry 202, driver circuitry 204 and 206, M_H 208, V_SW terminal 209, M_L 210, inductor 211, capacitor 212, SCD circuitry 216, ZVD circuitry 218, and monitoring circuitry 220, GaN die 401 and 402, Si die 404, M_SNS 406, V_G_SNS terminal 407, M_CLMP 408 - 412, zener diode 414, current source 416, charge pump 418, V_S_Si terminal 419, voltage divider circuitry 420, example capacitor 422, and / or more generally, Figure 1 the example step-down regulator circuitry 108 and Figure 2 monitoring circuitry 220 ofFigure 1 Example buck regulator circuit system 108 and / or Figure 2 monitoring circuit system 220 can be implemented by a programmable circuit system in combination with machine-readable instructions (e.g., firmware or software), processor circuit system, analog circuit, digital circuit, logic circuit, programmable processor, programmable microcontroller, graphics processing unit (GPU), digital signal processor (DSP), ASIC, programmable logic device (PLD), and / or field programmable logic device (FPLD) such as FPGA. Further, Figure 2 example buck regulator circuit system 108 and / or monitoring circuit system 220 can include one or more elements, processes, and / or devices to supplement or replace those elements, processes, and / or devices described in Figure 2 and / or can include more than one of any or all of the described elements, processes, and devices.

[0094] Figure 7 The flowchart shown in Figure 2 represents example machine-readable instructions that can be executed by a programmable circuit system to implement and / or instantiate Figure 2 buck regulator circuit system 108 and / or monitoring circuit system 220, and / or represents example operations that can be executed by a programmable circuit system to implement and / or instantiate Figure 9 buck regulator circuit system 108 and / or monitoring circuit system 220. The machine-readable instructions can be one or more executable programs or portions of one or more executable programs for execution by a programmable circuit system, such as the programmable circuit system 912 shown in the example programmable circuit system platform 900 described below in connection with

[0095] The program can be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or discs (e.g., Blu-ray discs, compact discs (CDs), digital versatile discs (DVDs), etc.), redundant arrays of independent disks (RAID), registers, ROMs, solid state drives (SSDs), SSD memories, non-volatile memories (e.g., electrically erasable programmable read-only memories (EEPROMs), flash memories, etc.), volatile memories (e.g., any type of random access memory (RAM), etc.) and / or any other storage device or storage disk. The instructions of the non-transitory computer-readable and / or machine-readable media can be programmed and / or executed by programmable circuitry located in one or more hardware devices, but the entire program and / or parts thereof can alternatively be executed and / or instantiated and / or embodied in dedicated hardware other than programmable circuitry. The machine-readable instructions can be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., server and client hardware devices). For example, the client hardware device can be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that can facilitate communication between the server and the endpoint client hardware device. Similarly, the non-transitory computer-readable storage media can include one or more media. Additionally, although reference is made to Figure 7The illustrated flowcharts depict example programs, but many other methods may alternatively be used to implement example buck regulator circuitry 108 and / or monitoring circuitry 220. For example, the order of execution of the blocks of the flowcharts may be changed, and / or some of the blocks described may be changed, eliminated, or combined. In some instances, any or all of the blocks of the flowcharts may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGA, ASIC, comparator, operational amplifier (op-amp), logic circuitry, etc.), the one or more hardware circuits being structured to perform the corresponding operations without executing software or firmware. The programmable circuitry may be distributed at different network locations and / or local to one or more hardware devices (e.g., a single-core processor (e.g., a single-core CPU), a multi-core processor (e.g., a multi-core CPU, XPU, etc.)). For example, the programmable circuitry may be a CPU and / or FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, etc., and / or any combination thereof.

[0096] The machine-readable instructions described herein may be stored in one or more formats such as a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.)) or a data structure (e.g., a portion of an instruction, code, a representation of code, etc.), the data being usable to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices, disks, and / or computing devices (e.g., servers) located at the same or different locations of a network or network collection (e.g., in the cloud, at an edge device, etc.). The machine-readable instructions may need to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, unpackaged, distributed, redistributed, compiled, etc. in order for them to be directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, the machine-readable instructions may be stored in multiple parts, the parts being individually compressed, encrypted, and / or stored on separate computing devices, where the parts form a set of computer-executable and / or machine-executable instructions when decrypted, decompressed, and / or combined, the instructions implementing one or more functions and / or operations that may together form, for example, a program as described herein.

[0097] In another example, the machine-readable instructions may be stored in a state in which they are readable by a programmable circuitry, but libraries (e.g., Dynamic Link Libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc. need to be added in order to execute the machine-readable instructions on a particular computing device or another device. In another example, it may be necessary to configure the machine-readable instructions (e.g., store settings, data inputs, record network addresses, etc.) before they can be fully or partially executed and / or the corresponding program. Thus, the machine-readable, computer-readable, and / or machine-readable media used herein may include instructions and / or programs, regardless of the particular format or state of the machine-readable instructions and / or programs.

[0098] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0099] As mentioned above, Figure 7Example operations may be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media. As used herein, the terms non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media are expressly defined to include any type of computer-readable storage device and / or storage disk, and to exclude propagated signals and to exclude transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memories, read-only memories (ROMs), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage device or storage disk in which information is stored for any duration (e.g., an extended period of time, permanently, briefly, temporarily buffered, and / or cached). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined to include any physical (mechanical, magnetic, and / or electrical) hardware for maintaining information over a period of time, and to exclude propagated signals and to exclude transmission media. Examples of non-transitory computer-readable storage devices and / or non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid state memories, flash memories, optical disks, magnetic disks, disk drives, and / or redundant array of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure that may or may not be configured by and / or fabricated to execute computer-readable instructions, machine-readable instructions, etc., such as a mechanical and / or electrical device, hardware, and / or circuitry.

[0100] Figure 7 is a flowchart depicting example machine-readable instructions and / or example operations 700 that may be executed, instantiated, and / or performed by components including programmable circuitry to implement the buck regulator circuitry 108. Figure 7 The example machine-readable instructions and / or example operations 700 begin by monitoring the switching voltage received by the monitoring circuitry 220A at a second transistor integrated on the same die as the power FET. (Block 702). In Figure 7 an example, the switching voltage is the voltage at the V_SW terminal 209, the second transistor is M_SNS 406, the die is the GaN die 402, and the power FETs are M_H 208 and M_L 210. In other examples, the power FET and the second transistor may be implemented on dies made of different materials.

[0101] The second transistor determines whether the switching voltage is higher than a threshold. (Block 704). In the example described herein, the voltage threshold of block 704 refers to the voltage at which M_SNS 406 allows current to flow from its drain terminal to its source terminal. Thus, the voltage threshold of block 704 is the voltage at V_G_SNS terminal 407 minus the inherent threshold voltage of M_SNS 406.

[0102] Advantageously, the monitoring circuitry 220A includes a current source 416 and a charge pump 418 that jointly increase the voltage at V_G_SNS terminal 407, as described above. Thus, the exemplary voltage threshold of block 704 is greater than the voltage thresholds of other buck regulator devices, and the exemplary SC desaturation threshold 308 more accurately represents when a short circuit occurs than the desaturation thresholds in other buck regulator devices.

[0103] If the switching voltage is higher than the threshold (block 704: yes), the second transistor turns off (or remains off) to block the switching voltage. By de-energizing and blocking the high voltage presented at V_SW terminal 209, M_SNS 406 prevents potential damage to one or more components implemented on Si die 404. After block 706, control proceeds to block 712.

[0104] If the switching voltage is at or below the threshold (block 704: no), the second transistor turns on (or remains on). (Block 708). When energized, M_SNS 406 allows current to flow between its drain and source terminals with a low voltage drop. Thus, at block 708, the voltage at V_S_Si terminal 419 (coupled to the source of M_SNS 406) matches the voltage at V_SW terminal 209 (coupled to the drain of M_SNS 406).

[0105] The clamping transistors prevent improper biasing of the second transistor. (Block 710). For example, M_CLMP 408 prevents current from flowing in reverse from GaN die 402 to Si die 404 via V_G_SNS terminal 407, and such reverse flow would be an improper negative bias at the gate of M_SNS 406. Similarly, M_CLMP 410 and M_CLMP 412 prevent improper positive biasing at the gate of M_SNS 406. Thus, M_SNS 406 transfers the voltage at V_SW terminal 209 to V_S_Si terminal 419 only when the voltage at V_SW terminal 209 is within a safe range.

[0106] The programmable circuit system determines whether the low-side power FET is turned on (block 712). In the example described herein, if the voltage at the V_GL terminal 207 increases beyond a threshold, the M_L 210 is powered on. The programmable circuit system (e.g., the main control circuit system 202) determines the voltage of the V_GL terminal 207 and can thus also determine whether the low-side power FET is on or off.

[0107] If the low-side power FET is powered on (block 712: yes), the programmable circuit system turns on the voltage divider circuit to scale the output voltage of the second transistor (block 714). By enabling the resistors 424 and 430 using the transistors 426 and 432 within the voltage divider circuit system 420, the monitoring circuit system 220A generates a voltage at the V_SNS terminal 431 that is proportionally less than the voltage of the V_S_Si terminal 419 (e.g., the output voltage of the second transistor). After block 714, control proceeds to block 718.

[0108] If the low-side power FET is powered off (block 716: no), the programmable circuit system deactivates the voltage divider circuit (block 716). When the M_L 210 is powered off, the resistors 424 and 430 are deactivated because the voltage at the V_GL terminal 207 is provided to both the gate of the M_L 210 and the gate of the transistor 432.

[0109] The monitoring circuit system 220A provides a voltage to the SCD circuit system 216 and the ZVD circuit system 218 (block 718). In the example described herein, the voltage of block 718 is the voltage of the V_SNS terminal 431. Advantageously, the main control circuit system 202 and the monitoring circuit system 220A change the voltage at the V_SNS terminal 431 based on the operating conditions of the M_H 208 and the M_L 210. For example, if the M_L 210 is powered on (block 712: yes), the voltage at the V_SNS terminal 431 is scaled by the voltage divider and can be used, for example, by the SCD circuit system 216 to determine that the value of the switching voltage indicates a short circuit. When the M_L 210 is powered off (block 712: no), the voltage of the V_SNS terminal 431 can directly match the voltage of the V_SW terminal 209 (without any scaling), and thus enables the ZVD circuit system 218 to accurately determine when the switching voltage crosses 0V.

[0110] Figure 8 Yes Figure 2 A second exemplary embodiment of the monitoring circuit system 220, herein referred to as the monitoring circuit system 220B. Figure 8 Includes the main control circuit system 202, the transistors M_H 208 and M_L 210, the V_SW terminal 209, the SCD circuit system 216, the ZVD circuit system 218, and the monitoring circuit system 220B. Figure 4It also includes GaN dies 401 and 402 and Si die 404. Thus, the circuit elements within GaN dies 401 and 402 can be implemented on a continuous block of gallium nitride, and the circuit elements within Si die 404 can be implemented on a continuous block of silicon.

[0111] Similar to Figure 4 monitoring circuit system 220A, Figure 8 example monitoring circuit system 220B of Figure 4 includes M_SNS 406, Zener diode 414, current source 416, capacitor 422, and transistor 426. The connection of the foregoing components and the composite material were described above in connection with Figure 8 monitoring circuit system 220A and also apply to

[0112] In contrast to Figure 4 monitoring circuit system 220A, Figure 8 example monitoring circuit system 220B of Figure 4 does not include clamping transistors 408 - 412, charge pump 418, resistors 424 and 430, and transistor 432. Within Si die 404, monitoring circuit system 220B also includes example resistor 802 having a first terminal coupled to V_G_SNS terminal 407 and a second terminal coupled to V_S_Si terminal 419. Figure 8 Resistor 802 is not included in

[0113] Generally, monitoring circuit system 220A and monitoring circuit system 220B perform the same functions described above in connection with Figure 2 However, monitoring circuit system 220A can be used in applications where Si die 404 receives a relatively low voltage (e.g., +9.0V) as V_REF1, while monitoring circuit system 220B can be used in low - power motor applications where Si die 404 receives a relatively high voltage (e.g., +15.0V) as V_REF3. Thus, current source 416 in monitoring circuit system 220B can increase the voltage of the gate of M_SNS 406 to be greater than the voltage at V_SW terminal 209 without the help of charge pump 418.

[0114] In Figure 4In [the example], the monitoring circuit system 220A uses clamping transistors 408 - 412 to protect the gate of M_SNS 406 from improper biasing because the example monitoring circuit system 220A can be implemented in a wide range of application fields. In some such application fields, the transition speed of the voltage at V_SW can be relatively high. The high transition speed can cause the gate - source voltage of M_SNS 406 to rise to a large positive value or drop to a large negative value. The clamping transistors 408 - 412 counteract a wide range of potential voltages and effectively keep the gate - source voltage of M_SNS 406 within a predetermined and safe value range. The monitoring circuit system 220B also protects the gate of M_SNS 406 from improper biasing, but does so using resistor 802 instead of the gate of M_SNS 406 because the example monitoring circuit system 220B can be implemented in applications where the transition speed of the voltage at V_SW (compared to the transition speed of some applications supported by the monitoring circuit system 220A) is relatively low. Thus, compared to the gate - source voltage of M_SNS 406 for the monitoring circuit system 220A, the gate - source voltage of M_SNS 406 for the monitoring circuit system 220B can operate between relatively small value ranges. Due to the relatively small voltage range, the value of resistor 802 is sufficient to keep the gate - source voltage of M_SNS 406 of the monitoring circuit system 220B within a predetermined and safe value range.

[0115] The monitoring circuit system 220B does not include the voltage divider circuit system 420 because in Figure 8 the example, the SCD circuit system 216 uses an SCD reference voltage large enough to perform different comparison operations without scaling compared to the voltage at the V_S_Si terminal 419. However, the monitoring circuit system 220B includes transistor 426, which turns on when the voltage at its drain terminal is greater than the voltage at its gate terminal (labeled V_REF4). Thus, transistor 426 prevents any voltage greater than [V_REF4 - the inherent threshold voltage of transistor 426] on the V_S_Si terminal 419 from reaching the V_SNS terminal 431. Such high - voltage blocking further protects the SCD circuit system 216 and the ZVD circuit system 218 from potentially harmful voltages.

[0116] In the example described above, Figure 4 the monitoring circuit system 220A shown in Figure 8 and the monitoring circuit system 220B shown in

[0117] In other embodiments of the monitoring circuit system 220, the drain of M_SNS 406 is alternatively coupled to the drain of M_H 208. In such embodiments, the corresponding components (e.g., M_CLMP 408 - 412 for the monitoring circuit system 220A and the resistors 802 in the corresponding components) will still be connected to M_SNS 406, as Figure 4 and 7 shown. Such an instance where M_SNS 406 is coupled to the drain of M_H 408 also couples the drain terminal, gate terminal, and source terminal of M_SNS 406 to a Si die having a ground plane connected to the V_SW terminal 209. In such embodiments, following the teachings described herein, the example monitoring circuit system 220 reports when M_H 208 crosses V_SCD_TH or V_ZVD_TH.

[0118] Figure 9 is a block diagram of an example programmable circuit system platform 900 that includes circuitry configured to execute and / or instantiate example machine - readable instructions and / or Figure 7 example operations to implement Figure 2 the buck regulator circuit system 108 and / or the monitoring circuit system 220. The programmable circuit system platform 900 can be, for example, a server, a personal computer, a workstation, a self - learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smartphone, a tablet computer such as an iPad TM ), a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu - ray player, a game console, a personal video recorder, a set - top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.) or other wearable device, or any other type of computing and / or electronic device.

[0119] The illustrated example of the programmable circuit system platform 900 includes a programmable circuit system 912. The illustrated example of the programmable circuit system 912 is hardware. For example, the programmable circuit system 912 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The programmable circuit system 912 can be implemented by one or more semiconductor (e.g., silicon - based) devices. In this example, the programmable circuit system 912 implements the main control circuit system 202, the SCD circuit system 216, and the ZVD circuit system 218.

[0120] The programmable circuit system 912 of the illustrated example includes a local memory 913 (e.g., cache, registers, etc.). The programmable circuit system 912 of the illustrated example communicates with main memories 914, 916 via a bus 918, and the main memories include a volatile memory 914 and a non-volatile memory 916. The volatile memory 914 can be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), dynamic random access memory and / or any other type of RAM device. The non-volatile memory 916 can be implemented by flash memory and / or any other desired type of memory device. Access to the main memories 914, 916 of the illustrated example is controlled by a memory controller 917. In some instances, the memory controller 917 can be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuitry to manage the data stream to and from the main memories 914, 916.

[0121] The programmable circuit system platform 900 of the illustrated example further includes interface circuitry 920. The interface circuitry 920 can be implemented in hardware using any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface.

[0122] In the illustrated example, one or more input devices 922 are connected to the interface circuitry 920. The input devices 922 allow a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the programmable circuit system 912. The input devices 922 can be implemented by, for example, audio sensors, microphones, cameras (still or video), keyboards, buttons, mice, touchscreens, trackpads, trackballs, and / or other pointing devices and / or a voice recognition system.

[0123] One or more output devices 924 are also connected to the interface circuitry 920 of the illustrated example. The output devices 924 can be implemented by, for example, display devices (e.g., light-emitting diodes (LEDs), organic light-emitting diodes (OLEDs), liquid crystal displays (LCDs), cathode ray tube (CRT) displays, in-plane switching (IPS) displays, touchscreens, etc.), haptic output devices, printers, and / or speakers. Thus, the interface circuitry 920 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuitry such as a GPU.

[0124] The interface circuitry 920 of the illustrated example also includes a communication device, such as a transmitter, receiver, transceiver, modem, residential gateway, wireless access point, and / or network interface, to facilitate the exchange of data with an external machine (e.g., any type of computing device) via a network 926. The communication can occur via, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-sight wireless system, a line-of-sight wireless system, a cellular phone system, an optical connection, etc.

[0125] The programmable circuitry platform 900 of the illustrated example also includes one or more mass storage disks or devices 928 to store firmware, software, and / or data. Examples of such mass storage disks or devices 928 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices, such as flash memory devices and / or SSDs.

[0126] Machine-readable instructions 932 executable by Figure 7 the machine can be stored in the mass storage device 928, the volatile memory 914, the non-volatile memory 916, and / or on at least one non-transitory computer-readable storage medium, such as a removable CD or DVD.

[0127] "Comprising" and "including" (and all forms and tenses thereof) are used herein as open - ended terms. Thus, whenever a claim uses any form of "comprising" or "including" (e.g., comprises, includes, comprising, including, having, etc.) as a lead - in term or is employed within any type of claim recitation, additional elements, items, etc. may exist without exceeding the scope of the corresponding claim or recitation. As used herein, when the phrase "at least" is used as a transitional term in, for example, the preamble of a claim, it is open - ended in the same manner as the terms "including" and "comprising". The term "and / or", when used, for example, in the form of A, B, and / or C, means any combination or subset of A, B, C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing a structure, component, item, object, and / or thing, the phrase "at least one of A and B" refers to an embodiment that includes (1) at least one A, (2) at least one B, or (3) any one of at least one A and at least one B. Similarly, the phrase "at least one of A or B" as used herein in the context of describing a structure, component, item, object, and / or thing is intended to refer to an embodiment that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of a process, instruction, action, activity, etc., the phrase "at least one of A and B" is intended to refer to an embodiment that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of a process, instruction, action, activity, etc., the phrase "at least one of A or B" is intended to refer to an embodiment that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0128] As used herein, singular references (e.g., "a", "an", "first", "second", etc.) do not exclude a plurality. As used herein, the term "a" or "an" object means one or more of the objects. The terms "a" (or "an"), "one or more", and "at least one" may be used interchangeably herein. Further, although listed separately, multiple components, elements, or acts may be performed by, for example, the same entity or object. Additionally, while individual features may be included in different instances or claims, these features may be combinable, and inclusion in different instances or claims does not imply that a combination of the features is not feasible and / or not advantageous.

[0129] As used herein, unless otherwise stated, the term "above" describes the relationship of two parts relative to the earth. If there is at least one part of the second part between the earth and the first part, the first part is above the second part. Similarly, as used herein, when the first part is closer to the earth than the second part, the first part is "below" the second part. As mentioned above, the first part can be above or below the second part, with one or more of the following cases: there are other parts therebetween, there are no other parts therebetween, the first and second parts are in contact, or the first and second parts do not directly contact each other.

[0130] As used herein, in this patent, stating that any part (such as a layer, film, region, zone or plate) is located on another part in any way (such as on it, on top of it, disposed on it or formed on it, etc.) indicates that the part referred to is in contact with the other part, or the part referred to is above the other part, with one or more intermediate parts located therebetween.

[0131] As used herein, unless otherwise specified, connection references (such as attach, couple, connect and join) can include intermediate members between the elements referred to by the connection reference and / or relative movement between those elements. Thus, a connection reference does not necessarily imply that two elements are directly connected and / or in a fixed relationship with each other. As used herein, stating that any part is "in contact with" another part is defined to mean that there is no intermediate part between the two parts.

[0132] Unless otherwise specifically stated, descriptive terms such as "first", "second", "third", etc. are used herein without imputing or otherwise indicating a priority in a list, a physical order, the meaning of an arrangement, and / or sorting in any way, but are only used as labels and / or arbitrary names to distinguish elements, in order to facilitate understanding of the described examples. In some examples, the descriptive term "first" can be used to refer to an element in a specific embodiment, while the same element can be referred to by different descriptive terms such as "second", "third", "fourth", "fifth", "sixth", etc. in the claims. In such cases, such descriptive terms are only used to clearly identify those elements within the context of the discussion (such as within a technical solution), where the elements may, for example, otherwise share the same name.

[0133] As used herein, "substantially" and "about" modify their subject / value to identify the potential presence of variations that occur in real-world applications. For example, "substantially" and "about" can modify dimensions that may be imprecise due to manufacturing tolerances and / or other real-world defects. For example, unless otherwise specified herein, "substantially" and "about" can indicate that such dimensions can be within a tolerance range of + / - 10%.

[0134] As used herein, the phrase "communicating," including variants thereof, encompasses direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but also includes selective communication at periodic intervals, predetermined intervals, aperiodic intervals, and / or one-time events.

[0135] As used herein, "programmable circuitry" is defined to include the following: (i) one or more dedicated circuits (e.g., application specific integrated circuits (ASICs)), which are structured to perform specific operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors); and / or (ii) one or more general-purpose semiconductor-based circuits, which can be programmed with instructions to perform specific functions and / or operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors such as: a central processing unit (CPU) that can execute a first instruction to perform one or more operations and / or functions; a field programmable gate array (FPGA) that can be programmed with a second instruction to configure and / or structure the FPGA to instantiate one or more operations and / or functions corresponding to the first instruction; a graphics processing unit (GPU) that can execute a first instruction to perform one or more operations and / or functions; a digital signal processor (DSP) that can execute a first instruction to perform one or more operations and / or functions; an XPU; a network processing unit (NPU); one or more microcontrollers that can execute a first instruction to perform one or more operations and / or functions; and / or integrated circuits such as application specific integrated circuits (ASICs). For example, an XPU can be implemented by a heterogeneous computing system that includes multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination thereof) and an orchestration technique (e.g., an application programming interface (API)) that can allocate computing tasks to any programmable circuitry within the multiple types of programmable circuitry that is suitable and available to execute the computing task.

[0136] As used herein, an integrated circuit / circuit system is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on a chip (SoC), etc.

[0137] In this description, the term "coupled" can encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B by a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.

[0138] A device "configured to" perform a task or function can be configured (e.g., programmed and / or hardwired) by the manufacturer to perform the function when manufactured, and / or can be configured (or reconfigured) by the user after manufacture to perform the function and / or other additional or alternative functions. The configuration can be performed through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0139] As used herein, the terms "terminal", "node", "interconnect", "pin", and "lead" can be used interchangeably. Unless explicitly stated to the contrary, these terms are generally used to denote the interconnection between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components, or their ends.

[0140] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may actually include only semiconductor elements (e.g., semiconductor die and / or integrated circuit (IC) packages) within a single physical device, and may be adapted to be coupled to at least some of the passive elements and / or sources, e.g., by an end user and / or a third party, during or after manufacture to form the described structure.

[0141] The circuits described herein can be reconfigured to include replacement components to provide functionality that is at least partially similar to the functionality available prior to component replacement. Unless otherwise stated, a component shown as a resistor generally represents any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component can alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor. While some elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features can be incorporated into the integrated circuit. Additionally, some or all of the features described as external to the integrated circuit can be included in the integrated circuit, and / or some of the features described as internal to the integrated circuit can be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in a semiconductor substrate / above; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0142] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification.

[0143] Modifications may be made to the described embodiments, and other embodiments are possible within the scope of the claims.

[0144] From the foregoing, it can be understood that example systems, devices, articles, and methods have been described that are capable of rapid and accurate short-circuit desaturation / detection, zero-volt detection, and zero-volt switching of high-power FETs implemented in gallium nitride. The described systems, devices, articles, and methods improve the efficiency of using a computing device by: including a sense transistor in the GaN between the high-side FET and the low-side FET; dynamically biasing the gate of a second transistor with a low-magnitude current source to support a higher desaturation threshold; protecting the logic in the silicon die from potentially hazardous voltages supported in the GaN; and optionally scaling down the output voltage of the GaN die to support SC detection operations. The described systems, devices, articles, and methods thus relate to one or more improvements in the operation of machines such as computers or other electronic and / or mechanical devices.

Claims

1. A device comprising: A first transistor implemented using gallium nitride (GaN), the first transistor having: a drain configured to receive an input voltage from a power source; a gate configured to receive a voltage from the control circuitry; and source; A second transistor implemented using GaN, the second transistor having: a drain coupled to the source of the first transistor; a gate coupled to a current source; and a source configured to provide an output voltage based on a voltage at the source of the first transistor; as well as A third transistor is implemented using GaN, the third transistor having: a drain coupled to the source of the first transistor and the drain of the second transistor; a gate; and A source configured to be coupled to ground.

2. The apparatus of claim 1, wherein the output voltage is used by the control circuitry to detect whether the third transistor has crossed a short circuit desaturation threshold.

3. The apparatus according to claim 1, wherein: The output voltage is used by the control circuitry to detect whether the voltage at the drain of the third transistor crosses below zero volts.

4. The apparatus of claim 1, further comprising: A fourth transistor having: a drain coupled to the source of the second transistor; a gate coupled to the source of the second transistor; a source coupled to the current source and the gate of the second transistor; A fifth transistor having: a drain coupled to the current source and the gate of the second transistor; a gate coupled to the current source and the gate of the second transistor; and source; as well as A sixth transistor having: a drain coupled to the source of the fifth transistor; a gate coupled to the source of the fifth transistor; and A source is coupled to the source of the second transistor, the drain of the fourth transistor, and the gate of the fourth transistor. 5 . The apparatus of claim 4 , wherein the fourth transistor, the fifth transistor, and the sixth transistor are implemented using GaN.

6. The apparatus of claim 4, wherein: The fifth transistor and the sixth transistor are configured to prevent a positive bias between the gate and the source of the second transistor; and The fourth transistor is configured to prevent negative bias between the gate and the source of the second transistor.

7. The apparatus of claim 4, wherein: The voltage at the drain of the third transistor is a drain voltage; and In response to the drain voltage falling below a voltage threshold: The apparatus is configured to keep the second transistor powered on; and The second transistor is configured to generate an output voltage proportional to the drain voltage.

8. The apparatus of claim 7, wherein: The control circuitry is implemented in a silicon die; and The apparatus is configured to, in response to the drain voltage being above a voltage threshold, prevent the output voltage from being proportional to the drain voltage to protect the silicon die from receiving a voltage that could damage the control circuitry.

9. The apparatus of claim 8, wherein to prevent the output voltage from being proportional to the drain voltage, the apparatus is configured to turn off the second transistor in response to the drain voltage being greater than a voltage threshold.

10. A system comprising: control circuitry configured to generate a first control voltage and a second control voltage; A first transistor having: a drain configured to receive an input voltage from a power source; a gate configured to receive the first control voltage; and source; a current source configured to generate a current based on a reference voltage; A second transistor having: a drain coupled to the source of the first transistor; a gate coupled to the current source; and a source configured to provide an output voltage based on a voltage at the source of the first transistor; as well as A third transistor having: a drain coupled to the source of the first transistor and the drain of the second transistor; Gate; and A source configured to be coupled to ground.

11. The system of claim 10, wherein: The control circuitry and the current source are implemented using silicon; and The first transistor, the second transistor, and the third transistor are implemented using gallium nitride.

12. The system of claim 10, wherein: The voltage at the drain of the third transistor is a drain voltage; and In response to the drain voltage falling below a voltage threshold: The system is configured to keep the second transistor powered on; and The second transistor is configured to generate an output voltage proportional to the drain voltage.

13. The system of claim 12, wherein to keep the second transistor powered on, the current source is configured to provide the current to the source of the second transistor.

14. The system of claim 10, wherein: The system additionally includes a charge pump configured to receive a reference voltage and coupled to the current source; and The current source is used to generate the current using the output of the charge pump.

15. The system of claim 10, further comprising voltage divider circuitry, the voltage divider circuitry comprising: A first resistor having: a first terminal coupled to the source of the second transistor; and Second terminal; A fourth transistor having: a drain coupled to the second terminal of the first resistor; a gate configured to receive a reference voltage; and source; A diode having: a positive terminal coupled to the source of the fourth transistor; and a negative terminal configured to receive a reference voltage; A second resistor having: a first terminal coupled to the source of the fourth transistor; and Second terminal; as well as A fifth transistor having: a drain coupled to the second terminal of the second resistor; a gate coupled to the gate of the third transistor; and A source configured to be coupled to ground.

16. The system of claim 15, wherein in response to the third transistor being energized: the control circuitry being configured to provide the second control voltage such that the voltage divider circuitry is enabled; the source of the fourth transistor coupled to the control circuitry; A voltage at the source of the fourth transistor is less than a voltage at the drain of the third transistor; and The control circuitry is configured to use the voltage at the source of the fourth transistor to detect whether a third transistor has crossed a short circuit desaturation threshold.

17. The system of claim 15, wherein: The voltage at the drain of the third transistor is a drain voltage; In response to the third transistor being de-energized: the control circuitry being configured to provide the second control voltage such that the voltage divider circuitry is disabled; the source of the fourth transistor coupled to the control circuitry; the voltage at the source of the fourth transistor matches the drain voltage; and The control circuitry is configured to use the voltage at the source of the fourth transistor to detect whether the drain voltage crosses zero volts.

18. The system of claim 15, further comprising a resistor having a first terminal connected to the gate of the second transistor and a second terminal connected to the source of the second transistor.

19. A non-transitory computer-readable storage medium comprising instructions that cause programmable circuitry on a first integrated circuit die to perform at least the following operations: receiving an input voltage at a sense transistor integrated between a high-side transistor and a low-side transistor, the sense transistor, the high-side transistor, and the low-side transistor being implemented on second and third integrated circuit dies separate from the first integrated circuit die, the low-side transistor including a drain configured to receive a drain voltage; turning on the sense transistor when the drain voltage is below a voltage threshold, the voltage threshold being based on the drain voltage dynamically biasing a voltage at a gate of the sense transistor and a current source independently increasing the voltage at the gate; as well as The sense transistor is turned off when the drain voltage is above the voltage threshold to prevent the first integrated circuit die from receiving a voltage that could damage the programmable circuitry.

20. The non-transitory computer-readable storage medium of claim 19, wherein the instructions cause the programmable circuitry to use the output of the sense transistor to: determining when the high-side transistor and the low-side transistor have formed a short circuit; and A determination is made as to when a switch terminal coupled to the high-side transistor and the low-side transistor crosses zero volts.

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