Chip aging test device and chip aging test method

Abstract

The present disclosure provides a chip aging test device and a chip aging test method, which relate to the field of semiconductor testing technology. The device includes: multiple test cavities and multiple buffer cavities; each test cavity is equipped with a first temperature control component for independently regulating the temperature in the corresponding test cavity so that the test cavity has a constant test temperature, and the test cavity is used to perform aging tests on the chipset; the buffer cavity and the test cavity are alternately arranged and form a closed cavity structure, the closed cavity structure is used to accommodate at least one test core component, the test core component is configured to be able to rotate in the closed cavity structure, and the test core component provides a test signal for each chip in the chipset; each buffer cavity includes at least two partitions, the partitions are used to block the airflow exchange between the buffer cavity and the adjacent test cavity; the multiple partitions are configured to open and close alternately so that the chipset can enter and exit the buffer cavity. The efficiency of chip aging testing can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor testing technology, and in particular to a chip aging test device and a chip aging test method. Background Art

[0002] Burn-in testing (BIT) is a testing process that involves accelerated aging screening of semiconductor chips after chip packaging by applying electrical stress, temperature stress, or a combination of both that exceeds normal operating conditions. This is one of the key quality assurance links in the semiconductor manufacturing process.

[0003] At present, aging test furnace equipment is often used to perform aging tests on semiconductor chips. However, most aging test furnace equipment can only test a single chip at a specific temperature. It is necessary to frequently switch the equipment temperature to obtain the aging performance of the chip at different temperatures. The temperature adjustment of the equipment occupies most of the test time, resulting in low chip testing efficiency.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] In view of this, a chip aging test device and a chip aging test method are provided. The device includes multiple alternately arranged test chambers and buffer chambers, and is equipped with a rotatable test core component. It can perform multi-temperature aging tests on multiple groups of chipsets at the same time, shortening the temperature adjustment time of the device and greatly improving the chip aging test efficiency.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a chip aging test device is provided, the device comprising:

[0008] Multiple test cavities, each of which is equipped with a first temperature control component, which independently regulates the temperature within the corresponding test cavity to maintain a constant test temperature within the test cavity, and the test cavity is used to perform burn-in testing on a chipset;

[0009] a plurality of buffer cavities, the buffer cavities and the test cavities being alternately arranged to form a closed cavity structure, the closed cavity structure being used to accommodate at least one test core component, the test core component being configured to be capable of rotating within the closed cavity structure, the test core component providing a test signal to each chip in the chipset;

[0010] Each of the buffer cavities includes at least two partitions, which are used to block the airflow exchange between the buffer cavity and the adjacent test cavity; wherein the multiple partitions are configured to open and close alternately to allow the chipset to enter and exit the buffer cavity.

[0011] In an exemplary embodiment of the present disclosure, the test temperatures of at least two of the test cavities are different.

[0012] In an exemplary embodiment of the present disclosure, the test temperatures of two adjacent test cavities are different, and each buffer cavity is equipped with a second temperature control component, which adjusts the temperature inside the buffer cavity so that the temperature inside the buffer cavity is between the test temperatures of the two adjacent test cavities.

[0013] In an exemplary embodiment of the present disclosure, before the chipset enters the buffer cavity, the second temperature control component is used to control the temperature in the buffer cavity to adjust to the current test temperature of the chipset; the temperature of the buffer cavity is between the test temperatures of two adjacent test cavities.

[0014] In an exemplary embodiment of the present disclosure, the number of the test core components and the number of the chipset are both one, and the test core component rotates according to the test cavity where the chipset is located so that the test core component is docked with the chipset.

[0015] In an exemplary embodiment of the present disclosure, the number of the test core components and the number of the chipsets are both plural, the test core components are arranged in a one-to-one correspondence with the chipsets, and the test core components rotate synchronously with the corresponding chipsets.

[0016] In an exemplary embodiment of the present disclosure, the device also includes a first driving mechanism arranged in the closed cavity structure, and the test core assembly is connected to the first driving mechanism. The first driving mechanism is used to drive the test core assembly to rotate along the circumferential direction of the closed cavity structure according to the position of the chipset, so that the chipset is docked with the test core assembly.

[0017] In an exemplary embodiment of the present disclosure, there are multiple test core components and one chipset. The test core components are arranged in a one-to-one correspondence with the test cavities. When one chipset is tested and the chipset moves between different test cavities, the test core component does not rotate relative to the test cavity.

[0018] In an exemplary embodiment of the present disclosure, each of the partition pieces is provided with an air curtain isolation assembly, and the air curtain isolation assembly is used to generate an air curtain when the partition piece is opened to isolate the air flow exchange between the buffer cavity and the test cavity; wherein, the projection of the air curtain on the surface of the partition piece at least partially overlaps with the surface of the partition piece.

[0019] In an exemplary embodiment of the present disclosure, the time during which the air curtain isolation assembly generates the air curtain is greater than or equal to the opening time of the partition member.

[0020] In an exemplary embodiment of the present disclosure, a connector is provided on a surface of each test cavity facing the test core component, and each connector is located in the closed cavity structure. One end of the connector is docked with each chip in the chipset, and the other end of the connector is docked with the test core component.

[0021] According to another aspect of the present disclosure, a chip aging test method is provided, the method comprising:

[0022] In response to a test condition, controlling the chipset to move into the test chamber;

[0023] Controlling the chipset to remain stationary in the test chamber for a preset period of time to obtain an aging status of each chip in the chipset under the test conditions;

[0024] The test conditions include a test temperature, different test temperatures correspond to different test cavities, each test cavity has a constant test temperature, a buffer cavity is provided between two adjacent test cavities, and the buffer cavity and the test cavity form a closed cavity structure;

[0025] Before controlling the chipset to move to the test cavity, the method includes controlling the chipset to move to the buffer cavity for pre-processing to reduce the temperature difference between each chip in the chipset and the test temperature of the test cavity.

[0026] In an exemplary embodiment of the present disclosure, controlling the chipset to move into the buffer chamber for pre-processing includes:

[0027] The temperature in the buffer cavity is adjusted so that the temperature in the buffer cavity is between the test temperatures of two adjacent test cavities.

[0028] The present disclosure provides a chip aging test device, which includes multiple test cavities and multiple buffer cavities that are alternately arranged and form a closed cavity structure. Each test cavity is independently temperature-controlled by a first temperature control component to ensure that the test temperature in each test cavity is constant. The test temperatures between the test cavities do not affect each other, so that each test cavity can independently perform chip aging tests. Multiple groups of different chipsets can be aged simultaneously to improve test efficiency. A buffer cavity is provided between two adjacent test cavities in this device. A chipset can move between different test cavities to perform aging tests on the same chipset at different test temperatures. When the same chipset moves between different test cavities, the buffer cavity can pre-treat the chipset to shorten the temperature conversion time of the chipset, further improving test efficiency. In addition, because the buffer cavity includes at least two partitions that open and close alternately to block airflow exchange between the buffer cavity and the test cavity, the test temperature in each test cavity can be kept constant when the chipset moves between different test cavities, thereby ensuring the reliability of the chip aging test.

[0029] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0031] Figure 1 Schematic diagram of the structure of a chip aging test device in an exemplary embodiment of the present disclosure.

[0032] Figure 2 Schematic diagram of the position of the air curtain isolation component in the chip aging test device in the exemplary embodiment of the present disclosure.

[0033] Figure 3 Schematic diagram of the positional relationship between the air curtain and the surface of the partition member in an exemplary embodiment of the present disclosure.

[0034] Figure 4 Schematic diagram of the positional relationship among the test core components, connectors, and chipset in an exemplary embodiment of the present disclosure.

[0035] Figure 5 Schematic diagram of the corresponding connection relationship among the test core components, connectors and chipset in the exemplary embodiment of the present disclosure.

[0036] Figure 6 This is a diagram showing the correspondence between a test core component and a chipset in an exemplary embodiment of the present disclosure.

[0037] Figure 7 FIG. 4 is a diagram showing another correspondence between a test core component and a chipset in an exemplary embodiment of the present disclosure.

[0038] Figure 8 FIG. 4 is a diagram showing another correspondence between a test core component and a chipset in an exemplary embodiment of the present disclosure.

[0039] Figure 9 FIG. 4 is a diagram showing another correspondence between a test core component and a chipset in an exemplary embodiment of the present disclosure.

[0040] Figure 10 The figure is a flow chart of a chip aging test method in an exemplary embodiment of the present disclosure.

[0041] The description of the accompanying drawings is as follows:

[0042] 100. Test cavity; 200. Buffer cavity; 300. Chip set; 301. Test core component; 302. Connector; 400. Closed cavity structure; 500. Partition; 501. Air curtain isolation component; 502. Air curtain; 503. Surface of partition; 601. First drive mechanism; 700. Control center. DETAILED DESCRIPTION

[0043] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0044] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0045] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0046] In related technologies, semiconductor back-end aging testing is one of the key quality assurance links in the semiconductor manufacturing process. Aging testing uses high and low temperature and high voltage tests to enable semiconductor chips to pass through the early failure stage of the bathtub curve and enter a period of stable performance.

[0047] Since aging tests need to be completed at multiple different temperatures, common test temperatures include -10°C, 25°C, 88°C, and 125°C. Currently, the most commonly used chip aging test device is a high-temperature aging furnace, which is mostly a single-chamber structure. Frequent temperature changes within the furnace chamber are required to complete the entire aging test cycle with different test temperatures. The heating and cooling time within the chamber accounts for a large proportion of the entire test time, affecting the efficiency of the aging test. Furthermore, high-temperature aging furnaces can only perform aging tests on a single chip or a single chipset at the same temperature at a time, resulting in low test efficiency and high test costs.

[0048] Based on this, the embodiment of the present disclosure provides a chip aging test device, such as Figure 1 As shown, the device includes: a plurality of test chambers 100 and a plurality of buffer chambers 200 .

[0049] Each test cavity 100 is equipped with a first temperature control component that independently regulates the temperature within the corresponding test cavity 100 to maintain a constant test temperature within the test cavity 100. The test cavity 100 is used to perform burn-in tests on the chipset 300. Each test cavity 100 provided by the present disclosure maintains a constant test temperature, and the test temperatures of the test cavities 100 do not affect each other. This allows each test cavity 100 to independently perform chip burn-in tests, allowing burn-in tests to be performed on multiple different chipsets 300 simultaneously, thereby improving test efficiency.

[0050] The buffer chamber 200 and the test chamber 100 are alternately arranged to form a closed cavity structure 400. The closed cavity structure 400 is used to accommodate at least one test core component 301. The test core component 301 is configured to rotate within the closed cavity structure 400. The test core component 301 provides test signals to the chips in the chipset 300. By coordinating the positions of the test core component 301 with the buffer chamber 200 and the test chamber 100, the chipset 300 can be moved between different test chambers 100 to perform aging tests at different test temperatures on the same chipset 300. When the same chipset 300 moves between different test chambers 100, the buffer chamber 200 can pre-treat the chipset 300 to shorten the temperature conversion time of the chipset 300 and further improve test efficiency.

[0051] Each buffer chamber 200 includes at least two partitions 500, which are used to block airflow between the buffer chamber 200 and the adjacent test chamber 100. The partitions 500 are configured to open and close alternately to allow the test chipset 300 to enter and exit the buffer chamber 200. As the chipset 300 moves between different test chambers 100, the partitions 500 installed on the buffer chamber 200 ensure that the test temperature within each test chamber 100 remains constant, thus ensuring the reliability of chip burn-in testing.

[0052] The following is a detailed description of the various parts of the chip aging test device provided by the embodiment of the present disclosure with reference to the accompanying drawings:

[0053] In the embodiments provided in the present disclosure, Figure 1 As shown, combined Figures 5 to 9 The chip aging test device includes a plurality of test chambers 100 , each test chamber 100 is used to perform an aging test on a chipset 300 .

[0054] The number of test cavities 100 is at least two. For example, the number of test cavities 100 can be two, three, four, or more. The number of test cavities 100 can be selected based on different test temperatures and the number of chipsets 300. For example, if there are four chipsets 300 undergoing aging tests at the same temperature, the test apparatus can be adaptively configured with four test cavities 100, each corresponding to one chipset 300. Alternatively, if the test temperatures include -10°C, 25°C, 88°C, and 125°C, the test apparatus can be adaptively configured with four test cavities 100, each corresponding to one test temperature. Of course, the number of test cavities 100 can also be combined with different test temperatures and different numbers of chipsets 300, which will not be further described in detail here.

[0055] Each test cavity 100 is equipped with a first temperature control component, which independently regulates the temperature within the corresponding test cavity 100 so that the test cavity 100 has a constant test temperature. Taking the four commonly used test temperatures of -10°C, 25°C, 88°C, and 125°C as an example, the device has four test cavities 100, each with a test temperature of -10°C, 25°C, 88°C, and 125°C, and each test cavity 100 maintains its own test temperature constant. Of course, the test temperature of each test cavity can be a constant temperature value within the range of -20°C to 200°C. The specific test temperature of each test cavity can be determined according to actual test requirements.

[0056] In some embodiments, the first temperature control component may include a temperature sensor and a cooling and heating system arranged in the test cavity 100. The device may monitor the temperature in the test cavity 100 in real time through the temperature sensor, and adjust the test temperature in the test cavity 100 in real time through the cooling and heating system according to the temperature information obtained by the temperature sensor, and keep the test temperature in the test cavity 100 constant.

[0057] Taking the test temperature of the test cavity 100 as 25°C as an example, when the chipset 300 enters and exits the test cavity 100, the airflow causes the temperature of the test cavity 100 to change. The temperature sensor in the first temperature control component senses the temperature variation range of the test cavity 100, and controls the cooling and heating system to increase or decrease the temperature of the test cavity 100 according to the temperature variation range of the test cavity 100, so as to maintain the test cavity 100 at a test temperature of 25°C. The above embodiment is described using the test temperature of the test cavity 100 as an example. When the test cavities 100 have different test temperatures, the first temperature control component can be adaptively adjusted according to the test temperature in the test cavity 100 to maintain a constant test temperature in each test cavity 100.

[0058] It should be noted that the constant test temperature in the test chamber 100 is not strictly limited. The test temperature may have a deviation of ±1° C. Within this deviation range, the test temperature can be considered constant.

[0059] In some embodiments, when multiple test cavities 100 have the same test temperature, when aging tests are performed on multiple groups of chipsets 300 at the same temperature through multiple test cavities 100, a first temperature control component can be provided in each test cavity 100 to ensure precise control of the test temperature of each test cavity 100; or multiple test cavities 100 with the same temperature can be equipped with a first temperature control component, and multiple test cavities 100 can be simultaneously controlled by a first temperature control component so that the multiple test cavities 100 are at the same test temperature, so as to further simplify the structure of the device and improve the compactness of the device.

[0060] Among them, the adjustment time of the first temperature control component to the test temperature can be 5s~30s, for example, it can be 5s, 10s, 15s, 20s, 25s or 30s, etc. In addition, the adjustment time of the first temperature control component to the test temperature needs to be less than or equal to the residence time of the chipset 300 in the buffer cavity 200, so as to ensure that the chipset 300 can be subjected to aging testing at a precise and constant test temperature, thereby improving test reliability. It should be noted that the adjustment time of the first temperature control component to the test temperature includes the response time of the first temperature control component to the test temperature, so as to improve the detection efficiency and adjustment efficiency of the first temperature control component to the test temperature, thereby shortening the entire aging test time and improving the aging test efficiency.

[0061] In some specific embodiments, the cooling and heating system in the first temperature control component may include a circulating air duct, which is arranged on the bottom wall and / or two side walls and / or top wall of the test cavity 100. When the test cavity 100 needs to be heated up, hot air is input into the test cavity 100 through the circulating air duct to achieve the purpose of heating; when the test cavity 100 needs to be cooled down, cold air can be input into the test cavity 100 through the circulating air duct to achieve the purpose of cooling.

[0062] In some specific embodiments, the temperature sensor in the first temperature control assembly may include a first temperature sensor and a second temperature sensor. The first temperature sensor may be disposed on the sidewall and / or bottom wall of the test chamber 100 and / or suspended within the cavity of the test chamber 100, and is configured to obtain a test temperature within the test chamber 100 in real time. The first temperature sensor transmits the obtained real-time test temperature within the test chamber 100 to a control center. By comparing the preset constant test temperature of the test chamber 100 with the real-time test temperature, the cooling and heating system is used to adjust the temperature within the test chamber 100 to always maintain the preset constant test temperature.

[0063] A second temperature sensor can be disposed within the chipset 300, for example, on a chip within the chipset 300 or on a connecting board used to carry the chips. The second temperature sensor can be used to obtain the actual test temperature of the chipset 300. Because the test chamber 100 may have uneven temperature distribution within the space, this can lead to a difference between the actual test temperature of the chipset 300 and the preset constant test temperature within the test chamber 100, which can cause errors in the aging test. Therefore, the second temperature sensor can transmit the actual test temperature of the chipset 300 to the control center. By comparing the actual test temperature with the preset constant test temperature, the actual test temperature of the chipset 300 is adjusted to the preset constant test temperature to improve test accuracy.

[0064] The actual test temperature of the chipset 300 can be adjusted by a cooling and heating system, or by setting a separate temperature control system on the chipset 300 to achieve independent, rapid and precise control of the temperature of the chipset 300. Specifically, the temperature control system can be a heater and a cooler set on the chipset 300 or in the area near the chipset 300 to achieve rapid heating or cooling of the chipset 300, and at the same time, the heater is combined with the cooler to achieve two-way precise temperature control. The heater can be a resistance wire heater or an oil bath heater, etc.; the cooler can be a compressor, a radiator or a cooling pipe, etc. When using a separate temperature control system to adjust the actual temperature of the chipset 300, the temperature control system needs to be combined with a cooling and heating system to avoid large fluctuations in temperature and airflow near the chipset 300, which may affect the accuracy of the aging test.

[0065] In order to further improve the applicable scenarios and applicability of the device, in some embodiments, the multiple test cavities 100 in the device can have the same test temperature, so that the device can be used to perform aging tests on multiple groups of chipsets 300 at the same test temperature; in some embodiments, the multiple test cavities 100 of the device can partially have the same test temperature and another portion have different test temperatures, so that the device can perform aging tests on multiple groups of chipsets 300 at the same test temperature, and can also perform aging tests on the same chipset 300 at multiple different test temperatures; in some embodiments, the test temperatures of the multiple test cavities 100 of the device can all be different, so that the device can perform aging tests on the same chipset 300 at different test temperatures.

[0066] In some specific embodiments, the test temperatures of at least two test cavities 100 are different. When performing aging tests at different test temperatures on the same group of chipset 300, among the multiple test cavities 100 in the device provided by the present disclosure, at least two test cavities 100 have different test temperatures, so as to implement aging tests at multiple different test temperatures on the same group of chipset 300 in this device.

[0067] In the embodiments provided in the present disclosure, Figure 1 As shown, combined Figures 5 to 9 The chip aging test device includes a plurality of buffer cavities 200 , wherein the buffer cavities 200 and the test cavities 100 are alternately arranged to form a closed cavity structure 400 .

[0068] The number of buffer cavities 200 is at least two. For example, the number of buffer cavities 200 can be two, three, four, or more. The number of buffer cavities 200 can be set according to the number of different test cavities 100. In order to ensure that the buffer cavity 200 can provide temperature pretreatment for each test cavity 100, and the test cavity 100 and the buffer cavity 200 can be enclosed to form a closed cavity structure 400, the number of buffer cavities 200 is usually consistent with the number of test cavities 100. For example, when the number of test cavities 100 is four, the number of buffer cavities 200 can also be four, and the four buffer cavities 200 and the four test cavities 100 are alternately arranged, with a buffer cavity 200 arranged between two adjacent test cavities 100.

[0069] like Figure 1 As shown, in order to allow the chipset 300 to move into the test chamber 100 via the buffer chamber 200, each buffer chamber 200 includes at least two partitions 500. The multiple partitions 500 can be opened and closed to allow the test chipset 300 to enter and exit the buffer chamber 200. In the present disclosure, the partitions 500 are used to isolate the test chamber 100 from the buffer chamber 200 to ensure that the test temperature in the test chamber 100 is not affected by the temperature of the buffer chamber 200 or the external temperature, thereby ensuring the consistency of the test temperature in each test chamber 100. Furthermore, in order to prevent the airflow exchange generated by the opening and closing of the partition piece 500 from affecting the test temperature in the test chamber 100, multiple partition pieces 500 are configured to open and close alternately. When the chipset 300 is about to move into or out of the buffer chamber 200, the partition piece 500 is opened, and after the chipset 300 moves to a position where there is no intersection with the partition piece 500, the partition piece 500 is immediately closed to achieve the purpose of minimizing airflow exchange.

[0070] The opening and closing time of each partition member 500 can be adjusted according to the movement time of the chipset 300 at the corresponding position. In order to ensure that the chipset 300 can move smoothly between the buffer cavity 200 and the test cavity 100 and reduce the airflow exchange between the buffer cavity 200 and the test cavity 100, the opening and closing time of the partition member 500 can usually be less than or equal to 1.5s. For example, it can be 1.5s, 1.0s, 0.5s, 0.3s, 0.1s, etc. The shorter the opening and closing time of each partition member 500, the better its airflow isolation effect. Among them, the opening and closing times of multiple partition members 500 can be the same or different. The opening and closing time of each partition member 500 can also be determined according to the specific movement time of the chipset 300 to ensure the smooth movement of the chipset 300.

[0071] In the present disclosure, each partition 500 may be provided in a double-layer structure or a multi-layer structure to further improve the thermal insulation performance of the partition 500. When the partition 500 is provided in a double-layer structure, the inner layer structure of the partition 500 may be a vacuum insulation layer, and the pressure leakage rate of the inner layer structure is less than 1×10 -5 Pa·m³ / s, so as to maintain the pressure in the buffer cavity 200 through the inner layer structure, thereby ensuring that the buffer cavity 200 minimizes the impact of the test temperature in the adjacent test cavity 100; the outer layer structure of the partition piece 500 can adopt a high-temperature alloy honeycomb sealing structure, and the temperature resistance range of the outer layer structure is -50°C~300°C, thereby ensuring the heat resistance strength of the partition piece 500 and reducing the heat transfer of the partition piece 500, preventing the partition piece 500 from transferring temperature and causing the temperature of the test cavity 100 to be unstable.

[0072] The inner layer structure of the partition member 500 refers to the side of the partition member 500 close to the cavity structure of the buffer cavity 200, and the outer layer structure of the partition member 500 refers to the side of the partition member 500 away from the cavity structure of the buffer cavity 200. Of course, the partition member 500 may also adopt a three-layer structure, a four-layer structure, or even a multi-layer structure. The specific structure of each layer within the partition member 500 can be selected and adaptively adjusted according to the actual structural design requirements of the device, and will not be described in detail here.

[0073] like Figure 2 As shown, combined Figure 1 Since airflow exchange occurs between the buffer cavity 200 and the test cavity 100 when the partition 500 is opened, thereby affecting the constancy of the test temperature in the test cavity 100, in order to further reduce the impact of airflow exchange on the test temperature in the test cavity 100, each partition 500 is equipped with an air curtain isolation assembly 501. The air curtain isolation assembly 501 is used to generate an air curtain 502 when the partition 500 is opened to isolate the airflow exchange between the buffer cavity 200 and the test cavity 100.

[0074] The wind curtain isolation assembly 501 can be set at the junction of the buffer cavity 200 and the test cavity 100. When the partition 500 is opened, the wind curtain isolation assembly 501 can generate a gradient wind curtain 502 with an air curtain structure, and the buffer cavity 200 and the test cavity 100 are isolated through the airflow isolation effect of this wind curtain 502.

[0075] Among them, such as Figure 3 As shown, combined Figure 2To ensure the isolation effect of the air curtain 502, the projection of the air curtain 502 on the partition surface 503 at least partially overlaps with the partition surface 503. Furthermore, to improve the isolation effect of the air curtain 502, the projection of the air curtain 502 on the partition surface 503 covers the partition surface 503.

[0076] To improve the isolation effect of the air curtain 502, the time for the air curtain isolation assembly 501 to generate the air curtain 502 is greater than or equal to the opening time of the partition member 500. Before the partition member 500 is opened, the air curtain isolation assembly 501 generates the air curtain 502 to prevent the airflow exchange generated by the instantaneous opening of the partition member 500. After the partition member 500 is closed, the air curtain isolation assembly 501 stops generating the air curtain 502. The air curtain 502 forms a partition during the closing process of the partition member 500, further preventing the airflow exchange between the buffer chamber 200 and the test chamber 100. The time for the air curtain isolation assembly 501 to generate the air curtain 502 can be greater than 1.5 seconds, for example, it can be 1.5 seconds, 1.8 seconds, 2.0 seconds, 2.5 seconds, etc. The time for the air curtain 502 to generate the air curtain 502 should not be too long to prevent excessive power consumption of the device, thereby reducing the aging test cost while ensuring the isolation effect of the air curtain 502.

[0077] Among them, each buffer cavity 200 is also equipped with a second temperature control component, which adjusts the temperature inside the buffer cavity 200 through the second temperature control component to pre-heat or pre-cool the chipset 300 before the chipset 300 enters the test cavity 100, thereby shortening the test time of the chipset 300 and improving the test efficiency.

[0078] The second temperature control component may include a temperature sensor and a temperature adjustment system, wherein the temperature sensor detects the temperature inside the buffer cavity 200, and according to the temperature information obtained by the temperature sensor, adjusts the temperature inside the buffer cavity 200 through the temperature adjustment system to be between the test temperatures of the two adjacent test cavities 100, so as to pre-heat or pre-cool the chipset 300, reduce the temperature difference generated by the chipset 300 after entering the test cavity 100, so that the chipset 300 can be quickly adjusted to the test temperature for aging testing, thereby shortening the aging test time and improving the aging test efficiency.

[0079] In addition, before the chipset 300 enters the buffer cavity 200, the second temperature control component is used to control the temperature inside the buffer cavity 200 to adjust to the current test temperature of the chipset 300, thereby avoiding damage to the chipset 300 due to the large temperature difference between the test temperature and the temperature inside the buffer cavity 200, thereby improving the overall test reliability of the device.

[0080] Among them, the temperature control system in the second temperature control component can be arranged on the side wall and / or bottom wall and / or top wall of the buffer cavity 200, or it can be suspended in the cavity of the buffer cavity 200. The temperature control system can be a heating device, a cooling device or a combined heating and cooling device. For example, it can be a PTC heater, a heat pump heater, a heat sink, a heat pipe cooler, etc. The specific type of the temperature control system can be selected according to the actual design requirements of the buffer cavity 200, and this disclosure does not make specific limitations.

[0081] In the embodiment provided in the present disclosure, the chip aging test device includes at least one test core component 301, which is configured to be able to rotate within a closed cavity structure 400, and provides test signals for the chips in the chipset 300.

[0082] Among them, the closed cavity structure 400 is in a room temperature environment. For example, the test core component 301 can be in a temperature environment of 20°C~30°C to prevent the test core component 301 from being damaged in a high temperature environment, thereby improving the service life of the test core component 301 and thus improving the overall service life and test reliability of the device.

[0083] Each test core component 301 may include a test core board, which may integrate a power module, a signal input and output module, and other functions, as well as test algorithms, data analysis, and timing control logic. The test core board is responsible for generating test patterns and controlling test processes, such as power sequence and signal timing. The test core board within the test core component 301 provided in the present disclosure has the functions and hardware structure required for aging testing. The specific structure and functions of the test core board are not described in detail here.

[0084] like Figure 4 and Figure 5 As shown, combined Figure 1 In order to achieve the connection between the test core component 301 and the chipset 300, a connector 302 is provided between each test core component 301 and the chipset 300. Since the chipset 300 moves inside the test cavity 100 and the buffer cavity 200, and the test core component 301 rotates in the closed cavity structure 400, there is a cavity isolation between the chipset 300 and the test core component 301, and the chipset 300 and the test core component 301 also have the phenomenon of asynchronous movement. In order to ensure the effective connection between the test core component 301 and the chipset 300, a connector 302 is provided on the side of each test cavity 100 facing the test core component 301. Each connector 302 is located in the closed cavity structure 400. One end of the connector 302 is connected to each test chip in the test chipset 300, and the other end of the connector 302 is connected to the test core component 301.

[0085] Connector 302 can be a site board. It provides an adaptive physical interface and can also perform functions such as power distribution and signal conditioning, serving as a bridge between chipset 300 and test core component 301. Of course, connector 302 can also be a connection structure other than a site board. As chip burn-in test equipment evolves, the structure of connector 302 can also be updated accordingly.

[0086] like Figure 1 As shown, combined Figures 5 to 9 In order to realize the rotation of the test core component 301 in the closed cavity structure 400, the device also includes a first driving mechanism 601 arranged in the closed cavity structure 400. The test core component 301 is connected to the first driving mechanism 601. The first driving mechanism 601 is used to drive the test core component 301 to rotate along the circumferential direction of the closed cavity structure 400 according to the position of the chipset 300, so that the chipset 300 is docked with the test core component 301.

[0087] The first driving mechanism 601 may include a driving motor and a stage connected to the driving motor. The test core assembly 301 is disposed on the stage. The driving motor within the first driving mechanism 601 may be integrated into the bottom of the device. The driving motor may drive the stage to rotate, thereby driving the test core assembly 301 to rotate to a position corresponding to the chipset 300. In addition, the driving motor within the first driving mechanism 601 may also drive the stage to swing. After the test core assembly 301 rotates to a position corresponding to the chipset 300, the driving motor drives the test core assembly 301 to swing, thereby enabling the test core assembly 301 to be plugged in and out of the connector 302, thereby enabling the test core assembly 301 to be connected and disconnected from the connector 302.

[0088] In order to enable the chipset 300 to move within the buffer cavity 200 and the test cavity 100, the device also includes a second drive mechanism (not shown in the figure). The second drive mechanism may include a track and a drive motor provided at the bottom of the buffer cavity 200 and the test cavity 100. The drive motor can drive the chipset 300 located on the track to move, so as to enable the chipset 300 to move within the buffer cavity 200 and the test cavity 100. It should be noted that the setting of the track in the second drive mechanism does not affect the sealing of the test cavity 100 and the buffer cavity 200. In addition, the track may not be provided, and the chipset 300 may be directly driven to move by the drive motor. In addition, the drive motor in the second drive mechanism can also drive the chipset 300 to swing. After the test core component 301 rotates to a position corresponding to the chipset 300, the chipset 300 is driven to swing by the drive motor to achieve plugging and unplugging between the chipset 300 and the connector 302, thereby achieving connection and disconnection between the chipset 300 and the connector 302.

[0089] It should be understood that both the first drive mechanism 601 and the second drive mechanism can be designed and adjusted according to the actual structural requirements of the device. For example, the first drive mechanism 601 and the second drive mechanism can be related, and both can use the same drive motor to provide driving force to improve the integration of the device; of course, the first drive mechanism 601 and the second drive mechanism can also be two different mechanisms set up independently.

[0090] Among them, such as Figure 4 As shown, the device may also include a control center 700. The control center 700 has overall control functions such as controlling the motion trajectory of each mechanism and collecting and processing data. The control center 700 can be a central processing unit (CPU), microcontroller (MCU), programmable logic controller (PLC), system-on-chip (SoC), etc., which is connected to the test device signal. It is responsible for coordinating, managing, and scheduling the various components within the device to complete the entire device aging test process. Of course, the device also includes other auxiliary components or conventional connection components available in the art that are not listed here and will not be described in detail here.

[0091] Based on the above-mentioned burn-in test device structure provided by the present disclosure, the device can be used for burn-in testing of at least one chipset 300 at at least one test temperature. The relationship between the test core component 301 and the chipset 300 in the chip burn-in test device provided by the present disclosure is described below with reference to specific embodiments.

[0092] In some embodiments, as Figure 6As shown, the number of test core components 301 and the number of chipsets 300 are both one. The test core component 301 rotates according to the test chamber 100 where the chipset 300 is located so that the test core component 301 docks with the chips in the chipset 300. In this embodiment, the test core component 301 and the chipset 300 can rotate synchronously. After the chipset 300 determines the position of the test chamber 100 in which it is located, the test core component 301 docks with the chipset 300, thereby shortening the docking time between the test core component 301 and the chipset 300, further shortening the test time, and improving the test efficiency. In this embodiment, a chipset 300 can move between multiple test chambers 100, and multiple test chambers 100 can have different test temperatures to enable aging tests on the same chipset 300 at different test temperatures.

[0093] In some embodiments, as Figure 7 As shown, the number of test core components 301 and the number of chipsets 300 are both multiple, and the test core components 301 are arranged in a one-to-one correspondence with the chipsets 300. The test core components 301 and the corresponding chipsets 300 rotate synchronously. In this embodiment, the test core components 301 and the corresponding chipsets 300 can perform synchronous rotation. After the corresponding chipset 300 determines the position of the test chamber 100 in which it is located, the test core component 301 immediately docks with the corresponding chipset 300, thereby shortening the docking time between the test core component 301 and the corresponding chipset 300, further shortening the test time and improving the test efficiency. In this embodiment, multiple chipsets 300 can be moved between multiple test chambers 100, and the multiple test chambers 100 can have different test temperatures to enable burn-in tests to be performed on multiple different chipsets 300 at different test temperatures simultaneously. Of course, in this embodiment, the test temperatures of multiple test chambers 100 can also be the same or partially the same, so that multiple chipsets 300 or some chipsets 300 can be burned-in at the same test temperature.

[0094] In some embodiments, as Figure 8As shown, there are multiple test core components 301 and one chipset 300. The test core components 301 are arranged in a one-to-one correspondence with the test chamber 100. When testing a chipset 300 and the chipset 300 moves between different test chambers 100, the test core component 301 does not rotate relative to the test chamber 100. In this embodiment, the test core component 301 and the corresponding test chamber 100 are relatively stationary. After the chipset 300 determines the position of the test chamber 100 in which it is located, the test core component 301 and the chipset 300 are docked, avoiding the power consumption caused by the first drive mechanism 601 driving the test core component 301 to rotate, thereby achieving the purpose of reducing the overall power consumption of the device. In this embodiment, a chipset 300 can move between multiple test chambers 100, and multiple test chambers 100 can have different test temperatures to achieve aging testing of the same chipset 300 at different test temperatures.

[0095] In some embodiments, as Figure 9 As shown, there is one test core assembly 301 and multiple chipsets 300, with the number of chipsets 300 being less than the number of test chambers 100. The test core assembly 301 can be used to connect to one of the multiple chipsets 300. The test core assembly 301 rotates according to the test chamber 100 where the chipset 300 to be connected is located, so that the test core assembly 301 can dock with the chip in the corresponding chipset 300. In this embodiment, the test core assembly 301 and the chipset 300 do not have a specific correspondence. The test core assembly 301 can be rotated according to the chipset 300 to be burn-in tested. After the test core assembly 301 rotates to a preset position, it docks with the chipset 300, allowing targeted burn-in testing of the chipset 300. In this embodiment, multiple chipsets 300 can be moved between multiple test chambers 100, and the multiple test chambers 100 can have different test temperatures to enable burn-in testing of a single chipset 300 at different test temperatures. Of course, in this embodiment, the test temperatures of the multiple test chambers 100 may also be the same or partially the same, and the position of the test core component 301 may be adjusted according to actual test requirements.

[0096] According to experiments, the chip aging test device provided by the present invention can shorten the test time by at least 2 hours per test compared to a single test chamber aging furnace. For multiple chip groups 300, the cumulative reduction in the shortened test time is large, which can improve the utilization rate of the device itself, shorten the test time, and improve the test efficiency.

[0097] The buffer chamber 200 provided in the present disclosure can also serve as a backup chamber for the test chamber 100. If the test chamber 100 fails or the number of chipsets 300 under test changes, the temperature of the buffer chamber 200 can be adjusted to a preset test temperature, thereby meeting the various testing requirements of the burn-in test device and increasing the device's reusability. When the buffer chamber 200 serves as a backup chamber, spare connectors and other components can be adaptively installed on the buffer chamber 200 to meet testing conditions.

[0098] In the present disclosure, the chipset 300 includes at least one chip, which can be one of DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), NAND Flash (NOT AND Flash Memory), NOR Flash (NOT OR Flash Memory), MRAM (Magnetoresistive RAM), ReRAM (Resistive RAM), PCRAM (Phase Change RAM), etc. The chips in each chipset 300 can be of the same type or different types. The specific settings of the chipset 300 can be selected or adaptively adjusted according to specific test requirements. In addition, the structure and configuration of the test core component 301 can also be adaptively adjusted according to the number of chipsets 300 and the type of chips in the chipset 300 to meet the chip testing requirements.

[0099] The present disclosure provides a chip aging test method, such as Figure 10 As shown, combined Figure 1 The method includes: step S10 to step S20.

[0100] Wherein, step S10: in response to the test conditions, controlling the chipset to move into the test chamber;

[0101] Step S20: controlling the chipset to remain in the test chamber for a preset time period to obtain the aging status of each chip in the chipset under the test conditions.

[0102] The test conditions include a test temperature. Different test temperatures correspond to different test cavities 100. Each test cavity 100 has a constant test temperature. A buffer cavity 200 is provided between two adjacent test cavities 100. The buffer cavity 200 and the test cavity 100 form a closed cavity structure 400.

[0103] Before controlling the chipset 300 to move to the test chamber 100, the process includes: controlling the chipset 300 to move to the buffer chamber 200 for pre-processing to reduce the temperature difference between the test temperature of each chip in the chipset 300 and the test temperature of the test chamber 100, thereby shortening the temperature conversion time of the chipset 300 at different test temperatures, thereby shortening the test time and improving the test efficiency.

[0104] Among them, controlling the chipset 300 to move into the buffer chamber 200 for pre-processing includes: adjusting the temperature in the buffer chamber 200 so that the temperature in the buffer chamber 200 is between the test temperatures of two adjacent test chambers 100. Specifically, before the chipset 300 enters the buffer chamber 200, the temperature of the buffer chamber 200 can be controlled to adjust to the test temperature of the test chamber 100 where the chipset 300 is currently located, so as to avoid damage to the chips in the chipset 300 due to a large temperature difference between the buffer chamber 200 and the test chamber 100. Before the chipset 300 is about to move from the buffer chamber 200 to the test chamber 100, the temperature of the buffer chamber 200 can be controlled to adjust to the test temperature of the test chamber 100 to which the chipset 300 is pre-moved, thereby pre-heating or pre-cooling the chipset 300, thereby shortening the test time of the chipset 300 and improving the test efficiency.

[0105] The chip aging test method provided by the present disclosure can use the chip aging test device provided in the above embodiment to perform aging test on the chipset 300, and the specific test method can be adaptively adjusted according to the change of the specific structure of the device.

[0106] The following uses an example of a device performing an aging test on a group of chipsets at four different test temperatures to illustrate the test method provided by the present disclosure. Figure 1 The chip aging test device has four test cavities 100 and four buffer cavities 200 that are alternately arranged. The test temperatures of the four test cavities 100 are -10°C (low-temperature stress test), 25°C (normal temperature reference), 88°C (accelerated aging), and 125°C (high-temperature limit test), respectively. The test cavities 100 corresponding to the above four test temperatures are arranged and enclosed in sequence. Each test cavity 100 maintains a constant test temperature. A test core component 301 is provided in the closed cavity structure 400 formed by the buffer cavity 200 and the test cavity 100.

[0107] At the beginning of the test, the chipset 300 can be directly placed in the test chamber 100 corresponding to the initial test temperature required by the chipset 300. For example, before the test begins, the chipset 300 can be placed in the test chamber 100 at 25°C.

[0108] When the test begins, the device controls the chipset 300 to move into the corresponding test chamber 100 in response to the test conditions. For example, the device may respond to the test condition of an accelerated chip aging test temperature of 88°C by: controlling the chipset 300 to disconnect from the test core component 301 in the 25°C test chamber 100; controlling the chipset 300 to enter the 88°C test chamber 100 from the 25°C test chamber 100 through the buffer chamber 200, and simultaneously controlling the test core component 301 to rotate synchronously from the 25°C test chamber 100 to the 88°C test chamber 100; and connecting the chipset 300 and the test core component 301 via a connector 302 provided on the 88°C test chamber 100, so that the chipset 300 is kept at the test temperature of 88°C for a preset period of time to obtain an accelerated aging test curve of the chip at 88°C.

[0109] Among them, before the chipset 300 enters the buffer cavity 200, the buffer cavity 200 is controlled to adjust the temperature to 25°C; during the movement of the chipset 300 from the 25°C test cavity 100 to the buffer cavity 200, the temperature in the buffer cavity 200 is continued to be adjusted so that the temperature in the buffer cavity 200 is between 25°C and 88°C, so as to reduce the impact of the temperature difference on the chip aging test, and at the same time, the chip is preheated before entering the 88°C test cavity 100 to shorten the chip heating time.

[0110] In the process of transferring the chipset 300 from the 25°C test chamber 100 to the 88°C test chamber 100, when the chipset 300 moves to the position where the 25°C test chamber 100 and the buffer chamber 200 are adjacent, the air curtain isolation component of the buffer chamber 200 is opened to form an air curtain, and the air flow of the 25°C test chamber 100 and the buffer chamber 200 is isolated. Then, the partition piece 500 corresponding to the adjacent position is opened, and the chipset 300 is transferred from the 25°C test chamber 100 to the 88°C test chamber 100. 100 moves into the buffer cavity 200 and turns off the isolation piece; when the chip moves to the position where the buffer cavity 200 and the 88°C test cavity 100 are adjacent, the wind curtain isolation component of the buffer cavity 200 is opened to form an air curtain, and after the airflow of the 88°C test cavity 100 and the buffer cavity 200 is isolated, the partition piece 500 corresponding to the adjacent position is opened, and the chipset 300 moves from the buffer cavity 200 to the 88°C test cavity 100, and the isolation piece is turned off.

[0111] The above embodiment illustrates the movement of the chipset 300 from a 25°C test chamber 100 to an 88°C test chamber 100. When the chipset 300 is moved from an 88°C test chamber 100 to a 125°C test chamber 100 for high-temperature extreme testing, the movement process, temperature control process, and component control process of the chipset 300 are the same or substantially the same as those in the above embodiment and will not be repeated here. After the chipset 300 undergoes a low-temperature stress test at -10°C, a room-temperature test at 25°C, an accelerated aging test at 88°C, and a high-temperature extreme test at 125°C, the chipset passes through the early failure stage of the bathtub curve and enters a period of performance stabilization, completing the entire aging test cycle. This method can shorten the entire test cycle time and significantly improve test efficiency.

[0112] It should be noted that although the various steps of the chip burn-in test method disclosed herein are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into a single step, and / or a single step may be broken down into multiple steps.

[0113] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A chip aging test device, characterized in that: include: Multiple test cavities, each equipped with a first temperature control component that independently regulates the temperature within the corresponding test cavity to maintain a constant test temperature within the test cavity. Adjacent test cavities have different test temperatures. The test cavities are used to perform burn-in tests on chipsets. a plurality of buffer cavities, the buffer cavities and the test cavities being alternately arranged to form a closed cavity structure, the closed cavity structure being used to accommodate at least one test core component, the test core component being configured to be capable of rotating within the closed cavity structure, the test core component providing a test signal to each chip in the chipset; Each of the buffer cavities includes at least two partitions, which are used to block airflow exchange between the buffer cavity and the adjacent test cavity; wherein the plurality of partitions are configured to open and close alternately to allow the chipset to enter and exit the buffer cavity; Each of the buffer cavities is equipped with a second temperature control component, and the temperature inside the buffer cavity is adjusted by the second temperature control component so that the temperature inside the buffer cavity is between the test temperatures of two adjacent test cavities; Before the chipset enters the buffer cavity, the second temperature control component is used to control the temperature in the buffer cavity to be adjusted to the current test temperature of the chipset.

2. The chip aging test device according to claim 1, characterized in that: The number of the test core components and the number of the chipset are both one, and the test core component rotates according to the test cavity where the chipset is located, so that the test core component is docked with the chip.

3. The chip aging test device according to claim 1, characterized in that: The number of the test core components and the number of the chipsets are both plural, the test core components are arranged in a one-to-one correspondence with the chipsets, and the test core components rotate synchronously with the corresponding chipsets.

4. The chip aging test device according to claim 2 or 3, characterized in that: The device also includes a first driving mechanism arranged in the closed cavity structure, and the test core assembly is connected to the first driving mechanism. The first driving mechanism is used to drive the test core assembly to rotate along the circumferential direction of the closed cavity structure according to the position of the chipset, so that the chipset is docked with the test core assembly.

5. The chip aging test device according to claim 1, characterized in that: There are multiple test core components and one chipset. The test core components are arranged in a one-to-one correspondence with the test cavities. When one chipset is tested and the chipset moves between different test cavities, the test core component does not rotate relative to the test cavity.

6. The chip aging test device according to claim 1, characterized in that: Each of the partition pieces is equipped with an air curtain isolation assembly, which is used to generate an air curtain when the partition piece is opened to isolate the air flow exchange between the buffer cavity and the test cavity; wherein the projection of the air curtain on the surface of the partition piece at least partially overlaps with the surface of the partition piece.

7. The chip aging test device according to claim 6, characterized in that: The time for the air curtain isolation assembly to generate the air curtain is greater than or equal to the opening time of the partition member.

8. The chip aging test device according to any one of claims 1-3 and 5-7, characterized in that: A connector is provided on the side of each test cavity facing the test core component. Each connector is located in the closed cavity structure. One end of the connector is connected to each chip in the chipset, and the other end of the connector is connected to the test core component.

9. A chip aging test method, used in the device according to any one of claims 1 to 8, characterized in that: include: In response to a test condition, controlling the chipset to move into the test chamber; Controlling the chipset to remain stationary in the test chamber for a preset period of time to obtain an aging status of each chip in the chipset under the test conditions; The test conditions include a test temperature, different test temperatures correspond to different test cavities, each test cavity has a constant test temperature, a buffer cavity is provided between two adjacent test cavities, and the buffer cavity and the test cavity form a closed cavity structure; Before controlling the chipset to move to the test cavity, the method includes controlling the chipset to move to the buffer cavity for pre-processing to reduce the temperature difference between each chip in the chipset and the test temperature of the test cavity.

10. The chip aging test method according to claim 9, characterized in that: The step of moving the chipset into the buffer chamber for pre-processing includes: The temperature in the buffer cavity is adjusted so that the temperature in the buffer cavity is between the test temperatures of two adjacent test cavities.

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