Band-gap reference source circuit

Abstract

The invention discloses a band-gap reference source circuit, which relates to the technical field of integrated circuits, is used for reducing the power consumption and complexity of a traditional band-gap reference source circuit, and comprises an NMOS (N-channel Metal Oxide Semiconductor) tube, a first PMOS (P-channel Metal Oxide Semiconductor) tube, a second PMOS tube, a first resistor, a second resistor and a triode network, the source electrode of the NMOS tube is connected with a power supply and is used for keeping a conducting state in the process of electrifying and starting the band-gap reference power supply circuit; the drain electrode of the NMOS tube is connected with the output end of the band-gap reference source circuit, and is connected with the triode network based on the first resistor and the second resistor; the two ends of the triode network are connected with the drain electrode of the first PMOS tube and the drain electrode of the second PMOS tube respectively, and the triode network is used for enabling a current mirror composed of the first PMOS tube and the second PMOS tube to work normally.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular, to a bandgap reference circuit. Background Art

[0002] As a common circuit structure in a chip, a bandgap reference circuit is used to provide a reference voltage V that does not change with the power supply voltage and temperature REF (usually 1.2V). Please refer to Figure 1 , Figure 1 which is the structural diagram of the bandgap reference circuit provided for the background art of this application.

[0003] Existing bandgap reference circuits require a startup circuit ( Figure 1 not shown in DD ). During the power-on process of the power supply voltage V E , when the gate voltage (V DD ) of PM1 is equal to V Figure 1 not shown in Summary of the Invention

[0004] In view of the above technical status quo, the present invention provides a bandgap reference circuit to reduce the power consumption of the bandgap reference circuit.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A bandgap reference circuit includes: an NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first resistor, a second resistor, and a triode network;

[0007] The source of the NMOS transistor is connected to the power supply, and is used to keep conducting during the power-on startup process of the bandgap reference power supply circuit; the drain of the NMOS transistor is connected to the output end of the bandgap reference circuit, and is connected to the triode network based on the first resistor and the second resistor;

[0008] Both ends of the triode network are respectively connected to the drains of the first PMOS transistor and the second PMOS transistor, and are used to make the current mirror formed by the first PMOS transistor and the second PMOS transistor work normally.

[0009] In an alternative embodiment of the present application, the NMOS transistor is a depletion-type NMOS transistor, and the threshold voltage of the NMOS transistor is less than zero.

[0010] In an alternative embodiment of the present application, it further includes: a capacitor;

[0011] One end of the capacitor is connected to the gate of the NMOS transistor and the drain of the second PMOS transistor, and the other end is grounded.

[0012] In an alternative embodiment of the present application, the triode network includes: a first triode, a second triode, a third triode, and a fourth triode;

[0013] The ratio of the emitter areas of the first triode and the second triode is 1:N; the ratio of the emitter areas of the third triode and the fourth triode is 1:1;

[0014] Wherein, the collector of the fourth triode is connected to the drain of the second PMOS transistor, the emitter of the fourth triode is grounded, and the base of the fourth triode is respectively connected to the second resistor and the collector of the second triode;

[0015] The emitter of the second triode is grounded, and the base of the second triode is connected to the collector of the first triode, one end of the second resistor, and the collector of the third triode;

[0016] The emitter of the first triode is grounded, and the base of the first triode is connected to the other end of the first resistor;

[0017] The emitter of the third triode is grounded, and the collector of the third triode is connected to the drain of the first PMOS transistor.

[0018] In an alternative embodiment of the present application, it further includes: a third resistor;

[0019] One end of the third resistor is respectively connected to the first resistor and the second resistor, and the other end of the third resistor is respectively connected to the drain of the NMOS transistor and the output terminal of the bandgap reference source circuit.

[0020] In an alternative embodiment of the present application, the resistance values of the first resistor and the second resistor are equal.

[0021] In an alternative embodiment of the present application, the first PMOS transistor and the second PMOS transistor form a 1:1 current mirror.

[0022] In an alternative embodiment of the present application, the bandgap reference voltage output by the output terminal of the bandgap reference source circuit is represented by the following formula:

[0023]

[0024] Among them, V REF represents the bandgap reference voltage; T represents temperature; k and q are constants; N represents the area ratio of the emitters of the second triode and the first triode; R1 represents the resistance value of the first resistor; R3 represents the resistance value of the third resistor; V BE,Q2 represents the voltage between the base and the emitter of the second triode.

[0025] Compared with the prior art, a bandgap reference source circuit provided by the present invention has its source of the NMOS transistor connected to the power supply, so as to start the bandgap reference source circuit through the NMOS transistor, reduce the complexity of the circuit structure, and maintain the conducting state during the power-on startup process of the bandgap reference source circuit, so as to solve the problem of incorrect stable states existing in the traditional bandgap reference source circuit. At the same time, a current mirror composed of a first PMOS transistor and a second PMOS transistor is constructed through the first PMOS transistor, the second PMOS transistor and the triode network to clamp the voltage of the node where the first resistor and the second resistor are connected to the triode network, saving an additional bias circuit and reducing the overall power consumption of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0027] Figure 1 is a structural diagram of the bandgap reference source circuit provided in the background art of the present application;

[0028] Figure 2 is a schematic structural diagram of the bandgap reference source circuit provided in the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0030] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0031] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0032] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0033] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and may be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0034] The bandgap reference circuit, as a common circuit structure in a chip, is used to provide a reference voltage V that does not change with the power supply voltage and temperature REF (usually 1.2V). Please refer to Figure 1 , Figure 1 which is the structural diagram of the bandgap reference circuit provided in the background art of this application.

[0035] Figure 1 In [reference], the ratio of the emitter areas of transistor Q1 and transistor Q2 is 1:N, and the resistance values of resistor R2 and resistor R3 are equal (R2 = R3).

[0036] In the actual application process, the input virtual short characteristic of the auxiliary operational amplifier A1 makes the voltage V at node A A equal to the voltage V at node B B . Since R2 = R3, the currents flowing through resistor R2 and resistor R3 are also equal, that is:

[0037]

[0038] where I R2 represents the current flowing through resistor R2; VD represents the voltage of node D; V B represents the voltage of node B; V A represents the voltage of node A; I R3 represents the current flowing through resistor R3; R2 represents the resistance value of resistor R2; R3 represents the resistance value of resistor R3.

[0039] Furthermore, since transistor Q1 and resistor R3 are in series, and transistor Q2 and resistor R2 are in series, therefore, the currents flowing through transistor Q1 and transistor Q2 are also equal. At this time, the voltage of node A is the voltage V between the base and emitter of transistor Q1 BE,Q1 , and the voltage of node C is equal to the voltage V between the base and emitter of transistor Q2 BE,Q2 , therefore, the voltage drop across resistor R1 can be expressed by the following formula (1):

[0040]

[0041] where, V R1 represents the voltage drop across resistor R1; T represents temperature; K and q are both constants; N represents the ratio of the emitter area of transistor Q2 to that of transistor Q1.

[0042] The current flowing through resistor R1 can be expressed by the following formula (2):

[0043]

[0044] where, I R1 represents the current flowing through resistor R1.

[0045] Based on the above formula (2), it can be known that the current flowing through resistor R1 is a current with a positive temperature coefficient, and its positive temperature coefficient is related to N and the resistance value of resistor R1. Therefore, the final bandgap reference voltage can be expressed by the following formula (3):

[0046]

[0047] where, V REF represents the bandgap reference voltage.

[0048] Since the voltage V between the base and emitter of transistor Q1 BE,Q1 has a negative temperature coefficient, therefore, by adjusting the proportional relationship among N, R1, R3, and R4 in the above formula, the positive temperature coefficient of can be made the opposite of the negative temperature coefficient of voltage V BE,Q1 , so that the temperature coefficient of V REF is approximately 0 and hardly changes with temperature, so as to output a stable bandgap reference voltage.

[0049] The existing bandgap reference circuit requires a startup circuit ( Figure 1 not shown in DD During the power-on process, when the gate voltage (V E ) of PM1 is equal to V DD , the circuit will enter and lock into an incorrect stable state, resulting in the circuit being unable to operate normally. At this time, an additional startup circuit is required to return the circuit to the normal stable state, but this will increase the complexity and power consumption of the circuit; at the same time, the auxiliary operational amplifier A1 and its bias circuit ( Figure 1 not shown in

[0050] in the existing bandgap reference circuit) will further increase the overall power consumption of the circuit and is not suitable for some low-power applications.

[0051] In view of the above technical status quo, the present invention provides a bandgap reference circuit to reduce the power consumption of the bandgap reference circuit. Figure 2 , Figure 2 For the bandgap reference voltage provided by the embodiment of the present application, please refer to

[0052] As Figure 2 shown, the bandgap reference circuit includes: an NMOS transistor (i.e., NMOS), a first PMOS transistor (i.e., PMOS1), a second PMOS transistor (i.e., PMOS2), a first resistor R1, a second resistor R2, and a triode network.

[0053] Among them, the source of the NMOS transistor is connected to the power supply VDD and is used to maintain a conducting state during the power-on startup process of the bandgap reference power supply circuit.

[0054] The drain of the NMOS transistor is connected to the output terminal of the bandgap reference circuit, and the drain of the NMOS transistor is connected to the triode network based on the first resistor R1 and the second resistor R2.

[0055] Both ends of the triode network are respectively connected to the drains of PMOS1 and PMOS2 and are used to make the current mirror formed by PMOS1 and PMOS2 work normally. Among them, PMOS1 and PMOS2 are a 1:1 current mirror.

[0056] The triode network includes: a first triode Q1, a second triode Q2, a third triode Q3, and a fourth triode Q4.

[0057] Among them, the ratio of the emitter areas of the first triode Q1 and the second triode Q2 is 1:N, and the ratio of the emitter areas of the third triode Q3 and the fourth triode Q4 is 1:1.

[0058] The collector of the fourth triode Q4 is connected to the drain of PMOS2, the emitter of the fourth triode Q4 is grounded, and the base of the fourth triode Q4 is respectively connected to the second resistor R1 and the collector of the second triode Q2;

[0059] The emitter of the second triode Q2 is grounded, and the base of the second triode Q2 is connected to the collector of the first triode Q1, one end of the second resistor R2, and the collector of the third triode Q3;

[0060] The emitter of the first triode Q1 is grounded, and the base of the first triode Q1 is connected to the other end of the first resistor R1;

[0061] The emitter of the third triode Q3 is grounded, and the collector of the third triode Q3 is connected to the drain of PMOS1.

[0062] The bandgap reference source circuit further includes: a third resistor R3, one end of the third resistor R3 is respectively connected to the first resistor R1 and the second resistor R2, and the other end of the third resistor R3 is respectively connected to the drain of the NMOS transistor and the output terminal of the bandgap reference source circuit.

[0063] The resistance values of the first resistor R1 and the second resistor R2 are equal.

[0064] In an alternative embodiment of the present application, the bandgap reference source circuit further includes: a capacitor C1;

[0065] One end of the capacitor C1 is connected to the gate of the NMOS and the drain of the PMOS2, and the other end is grounded, so that the rising rate of the gate voltage of the NMOS is smoother during the power-on startup process, preventing obvious voltage overshoot from occurring in the bandgap reference voltage V output by the bandgap reference source circuit REF during the power-on startup process.

[0066] In the actual application process, the NMOS transistor is a depletion-type NMOS transistor, and its threshold voltage is less than zero. During the process of the power supply voltage gradually rising from 0 to the power supply voltage VDD, the gate voltage V of the NMOS transistor A gradually rises from 0. Since the threshold voltage V of the NMOS transistor TH,NM1 is less than 0. Therefore, the gate voltage V of the NMOS transistor GS,NM1 is always greater than the threshold voltage V of the NMOS transistor TH,NM1 , and the NMOS transistor always remains in the conducting state, and there is no incorrect stable state.

[0067] During the process of powering on the power supply voltage, the node voltages V of nodes C, D, and E C , V D , V E also gradually start to rise. When the node voltages V D , V EWhen the threshold voltages of the third transistor Q3 and the fourth transistor Q4 are reached, the current mirror formed by PMOS1 and PMOS2 starts to work properly, so that a negative feedback loop composed of node E - node D - node F - node A - node B - node C - node E is formed in the circuit, thereby enabling the bandgap reference circuit to maintain a normal working state.

[0068] Further, after the bandgap reference circuit works properly, since PMOS1 and PMOS2 form a 1:1 current mirror, the currents flowing through the third transistor Q3 and the fourth transistor Q4 are equal. Also, because the ratio of the emitter areas of the third transistor Q3 and the fourth transistor Q4 is 1:1, therefore, the voltage V D at node D and the voltage V E at node E are the same, and the currents flowing through the first resistor R1 and the second resistor R2 are also the same.

[0069] That is,

[0070] Further, since the first transistor Q1 is connected in series with the first resistor R1, and the second transistor Q2 is connected in series with the second resistor R2, and the currents flowing through the first transistor Q1 and the second transistor Q2 are also equal. At this time, the voltage V C at node C is equal to the voltage V BE,Q1 between the base and the emitter of the first transistor Q1. Therefore, the voltage drop across the resistor R1 can be expressed by the following formula (4):

[0071]

[0072] where, V R1 represents the voltage drop across the resistor R1; V C represents the voltage at node C; V D represents the voltage at node D; V BE,Q1 represents the voltage between the base and the emitter of the first transistor Q1; V BE,Q2 represents the voltage between the base and the emitter of the second transistor Q2; T represents temperature; k, q are constants; N represents the ratio of the emitter areas of the second transistor Q2 and the first transistor Q1.

[0073] Further, the current flowing through the resistor R1 can be expressed by the following formula (5):

[0074]

[0075] where, I R1 represents the current flowing through the resistor R1; R1 represents the resistance value of the first resistor R1.

[0076] It can be seen that the current flowing through the resistor R1 is a current with a positive temperature coefficient, and its positive temperature coefficient is related to N and the resistance value of the first resistor R1.

[0077] The bandgap reference voltage finally output by the bandgap reference source circuit can be expressed by the following formula (6):

[0078]

[0079] Furthermore, since the voltage V between the base and the emitter of the second transistor Q2 has a negative temperature coefficient, therefore, by adjusting the proportional relationship of N, R1, and R3 in the above formula (6), the positive temperature coefficient of the part in the formula can be made BE,Q2 opposite to the negative temperature coefficient of V, so that the temperature coefficient of the bandgap reference voltage V is approximately zero, and further the bandgap reference voltage V is almost not affected by temperature changes. BE,Q2 not affected by temperature changes. REF not affected by temperature changes. REF not affected by temperature changes.

[0080] In the process of practical application, the bandgap reference source circuit shown in Figure 2 has the same order of magnitude of temperature coefficient (less than 10 ppm) as the bandgap reference circuit shown in Figure 1

[0081] In summary, for the described bandgap reference circuit, the source of the NMOS transistor is connected to the power supply to start the bandgap reference source circuit through the NMOS transistor, reducing the complexity of the circuit structure, and remaining in the conducting state during the power-on startup process of the bandgap reference source circuit to solve the problem of incorrect stable states existing in the traditional bandgap reference source circuit. At the same time, a current mirror composed of the first PMOS transistor and the second PMOS transistor is constructed through the first PMOS transistor, the second PMOS transistor, and the transistor network to clamp the voltage of the node where the first resistor and the second resistor are connected to the transistor network, saving the additional bias circuit and reducing the overall power consumption of the circuit.

[0082] The above describes the embodiments of the present disclosure. However, these embodiments are only for illustrative purposes and not for limiting the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims

1. A bandgap reference source circuit, characterized in that: include: An NMOS tube, a first PMOS tube, a second PMOS tube, a first resistor, a second resistor and a triode network; The source of the NMOS tube is connected to a power supply, and is used to maintain a conducting state during the power-on startup of the bandgap reference power supply circuit; the drain of the NMOS tube is connected to the output end of the bandgap reference source circuit, and is connected to the triode network based on the first resistor and the second resistor; Two ends of the triode network are respectively connected to the drains of the first PMOS tube and the second PMOS tube, so as to enable the current mirror formed by the first PMOS tube and the second PMOS tube to work normally.

2. The bandgap reference source circuit according to claim 1, characterized in that: The NMOS tube is a depletion-type NMOS tube, and a threshold voltage of the NMOS tube is less than zero.

3. The bandgap reference source circuit according to claim 1, characterized in that: Also includes: capacitance; One end of the capacitor is connected to the gate of the NMOS tube and the drain of the second PMOS tube, and the other end is grounded.

4. The bandgap reference source circuit according to claim 1, characterized in that: The triode network includes: a first triode, a second triode, a third triode and a fourth triode; The ratio of the emitter areas of the first triode to the second triode is 1:N; the ratio of the emitter areas of the third triode to the fourth triode is 1:1; The collector of the fourth transistor is connected to the drain of the second PMOS transistor, the emitter of the fourth transistor is grounded, and the base of the fourth transistor is connected to the second resistor and the collector of the second transistor respectively; The emitter of the second transistor is grounded, and the base of the second transistor is connected to the collector of the first transistor, one end of the second resistor, and the collector of the third transistor; The emitter of the first transistor is grounded, and the base of the first transistor is connected to the other end of the first resistor; The emitter of the third transistor is grounded, and the collector of the third transistor is connected to the drain of the first PMOS transistor.

5. The bandgap reference source circuit according to claim 4, characterized in that: Also includes: The third resistor; One end of the third resistor is connected to the first resistor and the second resistor respectively, and the other end of the third resistor is connected to the drain of the NMOS tube and the output end of the bandgap reference source circuit respectively.

6. The bandgap reference source circuit according to claim 1, characterized in that: The resistance values ​​of the first resistor and the second resistor are equal.

7. The bandgap reference source circuit according to claim 1, characterized in that: The first PMOS tube and the second PMOS tube form a 1:1 current mirror.

8. The bandgap reference source circuit according to claim 5, characterized in that: The bandgap reference voltage outputted from the output end of the bandgap reference source circuit is expressed by the following formula: Among them, V REF represents the bandgap reference voltage; T represents temperature; k and q are constants; N represents the ratio of the area of ​​the emitter of the second transistor to that of the first transistor; R1 represents the resistance value of the first resistor; R3 represents the resistance value of the third resistor; V BE,Q2 Represents the voltage between the base and emitter of the second transistor.

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